935312727528 [NXP]
Microcontroller;
| 型号： | 935312727528 |
| 厂家： | 
NXP |
| 描述： | Microcontroller 微控制器 外围集成电路 |
| 文件： | 总136页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5643L
Rev. 9, 6/2013
MPC5643L
144 LQFP
Qorivva MPC5643L
Microcontroller Data Sheet
257 MAPBGA
(20 x 20 x 1.4 mm)
(14 x 14 x 0.8 mm)
—
Cyclic redundancy check (CRC) unit
•
High-performance e200z4d dual core
•
Decoupled Parallel mode for high-performance use of
replicated cores
Nexus Class 3+ interface
Interrupts
—
—
GPIOs individually programmable as input, output or
special function
Three 6-channel general-purpose eTimer units
2 FlexPWM units
—
—
—
—
—
—
—
32-bit Power Architecture® technology CPU
Core frequency as high as 120 MHz
Dual issue five-stage pipeline core
Variable Length Encoding (VLE)
Memory Management Unit (MMU)
4 KB instruction cache with error detection code
Signal processing engine (SPE)
•
•
Replicated 16-priority controller
Replicated 16-channel eDMA controller
•
•
•
Memory available
•
•
—
—
—
1 MB flash memory with ECC
128 KB on-chip SRAM with ECC
Built-in RWW capabilities for EEPROM emulation
—
Four 16-bit channels per module
•
Communications interfaces
—
—
SIL3/ASILD innovative safety concept: LockStep mode and
Fail-safe protection
2 LINFlexD channels
3 DSPI channels with automatic chip select
generation
2 FlexCAN interfaces (2.0B Active) with 32
message objects
FlexRay module (V2.1 Rev. A) with 2 channels,
64 message buffers and data rates up to 10 Mbit/s
—
Sphere of replication (SoR) for key components (such as
CPU core, eDMA, crossbar switch)
—
—
—
—
Fault collection and control unit (FCCU)
Redundancy control and checker unit (RCCU) on outputs
of the SoR connected to FCCU
—
—
Boot-time Built-In Self-Test for Memory (MBIST) and
Logic (LBIST) triggered by hardware
Boot-time Built-In Self-Test for ADC and flash memory
triggered by software
•
Two 12-bit analog-to-digital converters (ADCs)
—
—
16 input channels
Programmable cross triggering unit (CTU) to
synchronize ADCs conversion with timer and
PWM
—
—
—
—
—
—
Replicated safety enhanced watchdog
Replicated junction temperature sensor
Non-maskable interrupt (NMI)
16-region memory protection unit (MPU)
Clock monitoring units (CMU)
•
•
•
Sine wave generator (D/A with low pass filter)
On-chip CAN/UART bootstrap loader
Single 3.0 V to 3.6 V voltage supply
•
•
Ambient temperature range –40 °C to 125 °C
Junction temperature range –40 °C to 150 °C
Power management unit (PMU)
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009–2013. All rights reserved.
Table of Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1
1.5.40 Voltage regulator / Power Management Unit
(PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.41 Built-In Self-Test (BIST) capability . . . . . . . . . . 22
Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 76
3.3 Recommended operating conditions. . . . . . . . . . . . . . 77
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78
3.4.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.5 Electromagnetic Interference (EMI) characteristics. . . 81
3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 82
3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.8 Voltage regulator electrical characteristics . . . . . . . . . 83
3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 86
3.10 Supply current characteristics . . . . . . . . . . . . . . . . . . . 87
3.11 Temperature sensor electrical characteristics . . . . . . . 90
3.12 Main oscillator electrical characteristics . . . . . . . . . . . 90
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 92
3.14 16 MHz RC oscillator electrical characteristics . . . . . . 94
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 94
3.15.1 Input Impedance and ADC Accuracy. . . . . . . . 94
3.16 Flash memory electrical characteristics. . . . . . . . . . . . 99
3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . 100
3.18 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.18.1 Pad AC specifications . . . . . . . . . . . . . . . . . . 101
3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . 102
3.19.2 Reset sequence description. . . . . . . . . . . . . . 102
3.19.3 Reset sequence trigger mapping . . . . . . . . . . 105
3.19.4 Reset sequence — start condition . . . . . . . . . 106
3.19.5 External watchdog window. . . . . . . . . . . . . . . 107
3.20 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . 107
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 108
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 109
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 109
3.20.4 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . .111
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 114
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 120
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 126
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High-performance e200z4d core. . . . . . . . . . . . .7
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8
1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .8
1.5.5 On-chip flash memory with ECC . . . . . . . . . . . . .9
1.5.6 On-chip SRAM with ECC. . . . . . . . . . . . . . . . . . .9
1.5.7 Platform flash memory controller. . . . . . . . . . . . .9
1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10
1.5.9 Memory subsystem access time . . . . . . . . . . . .10
1.5.10 Error Correction Status Module (ECSM) . . . . . .11
1.5.11 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .11
1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11
1.5.13 System clocks and clock generation . . . . . . . . .12
1.5.14 Frequency-Modulated Phase-Locked Loop
2
3
(FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.16 Internal Reference Clock (RC) oscillator . . . . . .13
1.5.17 Clock, reset, power, mode and test control
modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)
13
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13
1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .13
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14
1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14
1.5.22 System Integration Unit Lite (SIUL) . . . . . . . . . .14
1.5.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . .14
1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .14
1.5.25 System Status and Configuration Module
(SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.28 Serial communication interface module
(LINFlexD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.29 Deserial Serial Peripheral Interface (DSPI) . . . .17
1.5.30 FlexPWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5.31 eTimer module. . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19
1.5.33 Analog-to-Digital Converter module (ADC) . . . .19
1.5.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .19
1.5.35 Cyclic Redundancy Checker (CRC) Unit. . . . . .20
1.5.36 Redundancy Control and Checker Unit (RCCU)20
1.5.37 Junction temperature sensor. . . . . . . . . . . . . . .20
1.5.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . .20
1.5.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . .21
4
5
6
MPC5643L Microcontroller Data Sheet, Rev. 9
2
Freescale Semiconductor
Introduction
1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of
microcontroller units (MCUs). For functional characteristics, see the MPC5643L Microcontroller Reference Manual. For use
of the MPC5643Lin a fail-safe system according to safety standard ISO26262, see the Safety Application Guide for MPC5643L.
1.2
Description
The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS),
electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643L
automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as
120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users’ implementations.
1.3
Device comparison
Table 1. MPC5643L device summary
Feature
MPC5643L
CPU
Type
2 × e200z4
(in lock-step or decoupled operation)
Architecture
Harvard
Execution speed
DMIPS intrinsic performance
SIMD (DSP + FPU)
MMU
0–120 MHz (+2% FM)
>240 MIPS
Yes
16 entry
Instruction set PPC
Instruction set VLE
Instruction cache
MPU-16 regions
Yes
Yes
4 KB, EDC
Yes, replicated module
Yes
Semaphore unit (SEMA4)
Core bus
Buses
AHB, 32-bit address, 64-bit data
32-bit address, 32-bit data
Internal periphery bus
Master × slave ports
Crossbar
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
3
Introduction
Table 1. MPC5643L device summary (continued)
Feature
MPC5643L
Memory
Modules
Flash
1 MB, ECC, RWW
128 KB, ECC
Static RAM (SRAM)
Interrupt Controller (INTC)
Periodic Interrupt Timer (PIT)
System Timer Module (STM)
Software Watchdog Timer (SWT)
eDMA
16 interrupt levels, replicated module
1 × 4 channels
1 × 4 channels, replicated module
Yes, replicated module
16 channels, replicated module
1 × 64 message buffers, dual channel
2 × 32 message buffers
2
FlexRay
FlexCAN
LINFlexD (UART and LIN with DMA support)
Clock out
Yes
Fault Collection and Control Unit (FCCU)
Cross Triggering Unit (CTU)
eTimer
Yes
Yes
3 × 6 channels1
FlexPWM
2 Module 4 × (2 + 1) channels2
Analog-to-Digital Converter (ADC)
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
Sine Wave Generator (SWG)
32 point
Modules
(cont.)
Deserial Serial Peripheral Interface (DSPI)
3 × DSPI
as many as 8 chip selects
Cyclic Redundancy Checker (CRC) unit
Junction temperature sensor (TSENS)
Digital I/Os
Yes
Yes, replicated module
16
Supply
Device power supply
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
Analog reference voltage
Frequency-modulated phase-locked loop (FMPLL)
Internal RC oscillator
3.0 V – 3.6 V and 4.5 V – 5.5 V
Clocking
2
16 MHz
External crystal oscillator
Nexus
4 – 40 MHz
Level 3+
Debug
MPC5643L Microcontroller Data Sheet, Rev. 9
4
Freescale Semiconductor
Introduction
Table 1. MPC5643L device summary (continued)
Feature
MPC5643L
Packages
LQFP
144 pins
MAPBGA
257 MAPBGA
–40 to 150 °C
–40 to 125 °C
Temperature
Temperature range (junction)
Ambient temperature range using external ballast
transistor (LQFP)
Ambient temperature range using external ballast
transistor (BGA)
–40 to 125 °C
1
The third eTimer (eTimer_2) is available with external I/O access only in the BGA package, on the LQFP package
eTimer_2 is available internally only without any external I/O access.
2
The second FlexPWM module is available only in the BGA package.
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5643L device.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
5
Introduction
PMU
JTAG
Nexus
e200z4
e200z4
SWT
ECSM
STM
SWT
ECSM
STM
SPE
VLE
SPE
VLE
INTC
INTC
MMU
MMU
FlexRay
RC
SEMA4
eDMA
SEMA4
eDMA
I-CACHE
I-CACHE
Crossbar Switch
Memory Protection Unit
ECC logic for SRAM
Crossbar Switch
Memory Protection Unit
ECC logic for SRAM
PBRIDGE
PBRIDGE
RC
RC
TSENS
Flash memory
SRAM
TSENS
ECC bits + logic
ECC bits
RC
ADC
– Analog-to-Digital Converter
– Boot Assist Module
– Clock Monitoring Unit
– Cyclic Redundancy Check unit
– Cross Triggering Unit
– Serial Peripherals Interface
– Error Correction Code
LINFlexD – LIN controller with DMA support
MC – Mode Entry, Clock, Reset, & Power
PBRIDGE – Peripheral bridge
BAM
CMU
CRC
CTU
DSPI
ECC
PIT
– Periodic Interrupt Timer
– Power Management Unit
– Redundancy Checker
– Real Time Clock
PMU
RC
RTC
ECSM
eDMA
FCCU
– Error Correction Status Module
– Enhanced Direct Memory Access controller
– Fault Collection and Control Unit
SEMA4
SIUL
SSCM
STM
SWG
SWT
– Semaphore Unit
– System Integration Unit Lite
– System Status and Configuration Module
– System Timer Module
– Sine Wave Generator
– Software Watchdog Timer
– Temperature Sensor
FlexCAN – Controller Area Network controller
FMPLL
INTC
IRCOSC – Internal RC Oscillator
JTAG – Joint Test Action Group interface
– Frequency Modulated Phase Locked Loop
– Interrupt Controller
TSENS
XOSC
– Crystal Oscillator
Figure 1. MPC5643L block diagram
MPC5643L Microcontroller Data Sheet, Rev. 9
6
Freescale Semiconductor
Introduction
1.5
Feature details
1.5.1
High-performance e200z4d core
®
The e200z4d Power Architecture core provides the following features:
•
•
2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
•
•
•
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
•
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
No data cache
•
•
•
•
•
•
•
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
— Misaligned access support
— Single stall cycle on load to use
•
•
•
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
Single precision floating-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
•
— Support for vectorized mode: as many as two floating-point instructions per clock
Vectored interrupt support
•
•
•
Reservation instruction to support read-modify-write constructs
Extensive system development and tracing support via Nexus debug port
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
7
Introduction
1.5.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting
that slave port are stalled until the higher priority master completes its transactions.
The crossbar provides the following features:
•
4 masters and 3 slaves supported per each replicated crossbar
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D
access (2 masters), one eDMA, one FlexRay
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum
flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1
redundant peripheral bus bridge
•
•
32-bit address bus and 64-bit data bus
Programmable arbitration priority
— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,
based upon the ID of the last master to be granted access or a priority order can be assigned by software at
application run time
•
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processing channel.
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be
assigned different access rights to each region.
•
•
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
The memory protection unit is replicated for each processing channel.
1.5.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is used to minimize the overall block size.
The eDMA module provides the following features:
•
•
•
•
•
•
•
•
16 channels supporting 8-, 16-, and 32-bit value single or block transfers
Support variable sized queues and circular buffered queue
Source and destination address registers independently configured to post-increment or stay constant
Support major and minor loop offset
Support minor and major loop done signals
DMA task initiated either by hardware requestor or by software
Each DMA task can optionally generate an interrupt at completion and retirement of the task
Signal to indicate closure of last minor loop
MPC5643L Microcontroller Data Sheet, Rev. 9
8
Freescale Semiconductor
Introduction
•
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.5.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction
storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory
array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait
state response at 120 MHz.
The flash memory module provides the following features
•
•
•
•
•
1 MB of flash memory in unique multi-partitioned hard macro
Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow block for test, censorship device and user option bits
Wait states:
— 3 wait states for frequencies =< 120 MHz
— 2 wait states for frequencies =< 80 MHz
— 1 wait state for frequencies =< 60 MHz
•
•
•
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
1.5.6
On-chip SRAM with ECC
The MPC5643L SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic
coverage including the array internal address decoder.
The SRAM module provides the following features:
•
•
System SRAM: 128 KB
ECC on 32-bit word (syndrome of 7 bits)
— ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
•
•
— 1 wait state for frequencies =< 120 MHz
— 0 wait states for frequencies =< 80 MHz
1.5.7
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
•
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container
are supported. Only aligned word writes are supported.
•
•
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch support.
— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized
flash access.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
9
Introduction
•
•
•
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a
least-recently-used replacement algorithm to maximize performance.
Programmable response for read-while-write sequences including support for stall-while-write, optional stall
notification interrupt, optional flash operation abort , and optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
•
•
•
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
•
•
•
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
The following functions are implemented:
•
•
•
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
1.5.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform memory access time summary
Data phase
wait states
AHB transfer
Description
e200z4d instruction fetch
e200z4d instruction fetch
0
3
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read
e200z4d data write
0–1
0
SRAM read
SRAM 32-bit write
MPC5643L Microcontroller Data Sheet, Rev. 9
10
Freescale Semiconductor
Introduction
Table 2. Platform memory access time summary (continued)
Data phase
AHB transfer
Description
wait states
e200z4d data write
e200z4d data write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read
e200z4d flash memory read
0
3
Flash memory prefetch buffer hit (page hit)
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.5.10 Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).
It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported
to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:
•
•
•
•
ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
1.5.11 Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
•
•
•
•
Duplicated periphery
Master access privilege level per peripheral (per master: read access enable; write access enable)
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.12 Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
•
•
•
•
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resource
The INTC is replicated for each processor.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
11
Introduction
1.5.13 System clocks and clock generation
The following list summarizes the system clock and clock generation on this device:
•
•
•
•
•
Lock status continuously monitored by lock detect circuitry
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
Programmable output clock divider of system clock (1, 2, 4, 8)
FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
•
•
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
— Supports automated frequency trimming by hardware during device startup and by user application
Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)
•
1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio are all software configurable. The FMPLLs have the following major features:
•
•
•
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
Option to switch modulation on and off via software interface
Output divider (ODF) for reduced frequency operation without re-lock
3 modes of operation
•
•
•
— Bypass mode
— Normal FMPLL mode with crystal reference (default)
— Normal FMPLL mode with external reference
Lock monitor circuitry with lock status
•
•
•
•
•
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
On-chip loop filter
Auxiliary FMPLL
— Used for FlexRay due to precise symbol rate requirement by the protocol
— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies
of operation for PWM and timers and jitter-free control
— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in
electric motor control loop
— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than
the system to ensure higher resolution
MPC5643L Microcontroller Data Sheet, Rev. 9
12
Freescale Semiconductor
Introduction
1.5.15 Main oscillator
The main oscillator provides these features:
•
•
•
•
Input frequency range 4–40 MHz
Crystal input mode
External reference clock (3.3 V) input mode
FMPLL reference
1.5.16 Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap
reference voltage. The RC oscillator is the device safe clock.
The RC oscillator provides these features:
•
•
•
Nominal frequency 16 MHz
±5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
FMPLL
•
RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)
in case XOSC fails
1.5.17 Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
•
•
•
•
Clock gating and clock distribution control
Halt, stop mode control
Flexible configurable system and auxiliary clock dividers
Various execution modes
— HALT and STOP mode as reduced activity low power mode
— Reset, Idle, Test, Safe
— Various RUN modes with software selectable powered modules
— No stand-by mode implemented (no internal switchable power domains)
1.5.18 Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
•
•
•
4 general purpose interrupt timers
32-bit counter resolution
Can be used for software tick or DMA trigger operation
1.5.19 System Timer Module (STM)
The STM implements the following features:
•
•
Up-counter with 4 output compare registers
OS task protection and hardware tick implementation per AUTOSAR requirement
1
1.Automotive Open System Architecture
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
13
Introduction
The STM is replicated for each processor.
1.5.20 Software Watchdog Timer (SWT)
This module implements the following features:
•
•
•
•
•
Fault tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21 Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
•
•
•
•
Redundant collection of hardware checker results
Redundant collection of error information and latch of faults from critical modules on the device
Collection of self-test results
Configurable and graded fault control
— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered)
— External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.5.22 System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal
peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration
logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform
and discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
•
Centralized pad control on a per-pin basis
— Pin function selection
— Configurable weak pull-up/down
— Configurable slew rate control (slow/medium/fast)
— Hysteresis on GPIO pins
— Configurable automatic safe mode pad control
Input filtering for external interrupts
•
1.5.23 Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.5.24 Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode
is selected via boot configuration pins.
MPC5643L Microcontroller Data Sheet, Rev. 9
14
Freescale Semiconductor
Introduction
The BAM provides the following features:
•
•
•
•
Enables booting via serial mode (FlexCAN or LINFlex-UART)
Supports programmable 64-bit password protection for serial boot mode
Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code
Automatic switch to serial boot mode if internal flash memory is blank or invalid
1.5.25 System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
•
•
•
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half
Word
•
•
Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE
code out of flash memory
Triggering of device self-tests during reset phase of device boot
1.5.26 FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version
2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of
this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required
bandwidth.
The FlexCAN module provides the following features:
•
Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate as fast as 1Mbit/s
•
•
•
•
•
•
•
•
•
•
•
•
32 message buffers of 0 to 8 bytes data length
Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
•
Receive features
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
15
Introduction
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
•
— System clock
— Direct oscillator clock to avoid FMPLL jitter
1.5.27 FlexRay
The FlexRay module provides the following features:
•
•
•
•
•
•
•
•
•
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
64 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as transmit or receive
Message buffer size configurable
Message filtering for all message buffers based on Frame ID, cycle count, and message ID
Programmable acceptance filters for receive FIFO
Message buffer header, status, and payload data stored in system memory (SRAM)
Internal FlexRay memories have error detection and correction
1.5.28 Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following:
•
•
•
•
Supports LIN Master mode, LIN Slave mode and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Manages LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— Message buffer to store as many as 8 data bytes
— Supports messages as long as 64 bytes
— Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and Time-out errors)
— Classic or extended checksum calculation
— Configurable break duration of up to 50-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features (Loop back, LIN bus stuck dominant detection)
— Interrupt driven operation with 16 interrupt sources
LIN slave mode features
•
•
— Autonomous LIN header handling
— Autonomous LIN response handling
UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words)
— Configurable parity scheme: none, odd, even, always 0
— Speed as fast as 2 Mbit/s
MPC5643L Microcontroller Data Sheet, Rev. 9
16
Freescale Semiconductor
Introduction
— Error detection and flagging (Parity, Noise and Framing errors)
— Interrupt driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— Two receiver wake-up methods
•
Support for DMA enabled transfers
1.5.29 Deserial Serial Peripheral Interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the MPC5643L and external devices.
A DSPI module provides these features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
As many as 8 chip select lines available, depending on package and pin multiplexing
4 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-glitching
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
1.5.30 FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single
half-bridge power stage. Two modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is
present. Additionally, four fault input channels are provided per FlexPWM module.
This PWM is capable of controlling most motor types, including:
•
•
•
•
•
AC induction motors (ACIM)
Permanent Magnet AC motors (PMAC)
Brushless (BLDC) and brush DC motors (BDC)
Switched (SRM) and variable reluctance motors (VRM)
Stepper motors
A FlexPWM module implements the following features:
•
•
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
Maximum operating frequency as high as 120 MHz
— Clock source not modulated and independent from system clock (generated via secondary FMPLL)
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
•
•
•
•
•
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
17
Introduction
•
Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
•
•
•
•
•
•
•
•
•
•
•
•
•
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime values
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
— External ADC input, taking into account values set in ADC high- and low-limit registers
DMA support
•
1.5.31 eTimer module
The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is available internally only without any
external I/O access). Six 16-bit general purpose up/down timer/counters per module are implemented with the following
features:
•
•
Maximum clock frequency of 120 MHz
Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
•
— Equals peripheral clock divided by 2 for external event counting
— Equals peripheral clock for internal clock counting
Cascadeable counters
•
•
•
•
•
•
•
•
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
MPC5643L Microcontroller Data Sheet, Rev. 9
18
Freescale Semiconductor
Introduction
1.5.32 Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).
1.5.33 Analog-to-Digital Converter module (ADC)
The ADC module features include:
Analog part:
•
2 on-chip ADCs
— 12-bit resolution SAR architecture
— Same digital interface as in the MPC5604P family
— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)
— One channel dedicated to each T-sensor to enable temperature reading during application
— Separated reference for each ADC
— Shared analog supply voltage for both ADCs
— One sample and hold unit per ADC
— Adjustable sampling and conversion time
Digital part:
•
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
•
•
2 modes of operation: CPU Mode or CTU Mode
CPU mode features
— Register based interface with the CPU: one result register per channel
— ADC state machine managing three request flows: regular command, hardware injected command, software
injected command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
•
•
CTU mode features
— Triggered mode only
— 4 independent result queues (1 16 entries, 2 8 entries, 1 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit parts
— DMA compatible interfaces
Built-in self-test features triggered by software
1.5.34 Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without
CPU load during the PWM period and with minimized CPU load for dynamic configuration.
The CTU implements the following features:
•
•
•
•
•
Cross triggering between ADC, FlexPWM, eTimer, and external pins
Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers
Maximum operating frequency less than or equal to 120 MHz
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low pass filter
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
19
Introduction
•
•
•
•
•
Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger capable of generating consecutive commands
ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
•
DMA support with safety features
1.5.35 Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register.
The CRC unit has the following features:
•
3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable
polynomial and seed
•
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.
The following standard CRC polynomials are implemented:
8
4
3
2
—
—
x + x + x + x + 1 [8-bit CRC]
16
12
5
x
+ x + x + 1 [16-bit CRC-CCITT]
32
26
23
22
16
12
11
10
8
7
5
4
2
— x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
[32-bit CRC-ethernet(32)]
•
•
Key engine to be coupled with communication periphery where CRC application is added to allow implementation of
safe communication protocol
Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic
procedures
•
•
CRC unit connected as peripheral bus on internal peripheral bus
DMA support
1.5.36 Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:
•
•
Duplicated module to guarantee highest possible diagnostic coverage (check of checker)
Multiple times replicated IPs are used as checkers on the SoR outputs
1.5.37 Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device
junction temperature.
The key parameters of the junction temperature sensor include:
•
•
Nominal temperature range from –40 to 150 °C
Software temperature alarm via analog ADC comparator possible
1.5.38 Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO
5001-2003. This development support is supplied for MCUs without requiring external address and data pins for internal
visibility.
MPC5643L Microcontroller Data Sheet, Rev. 9
20
Freescale Semiconductor
Introduction
The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO
5001-2003 Class 3+, including selected features from Class 4 standard.
The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the
MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also
supports a JTAG only mode using only the JTAG pins. The following features are implemented:
•
•
•
•
•
Full and reduced port modes
MCKO (message clock out) pin
4 or 12 MDO (message data out) pins
2 MSEO (message start/end out) pins
EVTO (event out) pin
1
— Auxiliary input port
•
•
EVTI (event in) pin
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Supports JTAG mode
•
Host processor (e200) development support features
— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool
to trace reads or writes, or both, to selected internal memory resources.
— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility
of which process ID or operating system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership flow.
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what
transpires between the discontinuities. Thus, static code may be traced.
— Watchpoint messaging (WPM) via the auxiliary port
— Watchpoint trigger enable of program and/or data trace messaging
— Data tracing of instruction fetches via private opcodes
1.5.39 IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic
when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block
is compliant with the IEEE standard.
The JTAG controller provides the following features:
•
IEEE Test Access Port (TAP) interface with 5 pins:
— TDI
— TMS
— TCK
— TDO
— JCOMP
•
•
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS
— IDCODE
1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
21
Introduction
— EXTEST
— SAMPLE
— SAMPLE/PRELOAD
•
•
3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the
boundary scan register is parameterized to support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
1.5.40 Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features:
•
•
Single external rail required
Single high supply required: nominal 3.3 V both for packaged and Known Good Die option
— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but
can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower
frequency of operation)
— Known Good Die option uses embedded ballast transistor as dissipation capacity is increased to reduce system
cost
•
•
All I/Os are at same voltage as external supply (3.3 V nominal)
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal
operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing
feature)
1.5.41 Built-In Self-Test (BIST) capability
This device includes the following protection against latent faults:
•
•
•
•
Boot-time Memory Built-In Self-Test (MBIST)
Boot-time scan-based Logic Built-In Self-Test (LBIST)
Run-time ADC Built-In Self-Test (BIST)
Run-time Built-In Self Test of LVDs
MPC5643L Microcontroller Data Sheet, Rev. 9
22
Freescale Semiconductor
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
Figure 2 shows the MPC5643L in the 144 LQFP package.
NMI
A[6]
D[1]
F[4]
1
2
3
4
5
6
7
8
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
108
107
106
105
104
103
102
101
100
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
9
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
99
D[12]
G[6]
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
144 LQFP package
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[10]
G[11]
A[1]
A[0]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
Figure 2. MPC5643L 144 LQFP pinout (top view)
Figure 3 shows the MPC5643L in the 257 MAPBGA package.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
23
Package pinouts and signal descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V
V
V
V
V
H[2]
V
V
V
V
SS_HV
_IO
SS_HV
_IO
DD_HV
_IO
DD_HV
_IO
SS_HV
_IO
SS_HV
_IO
A
B
C
D
E
F
H[0]
G[14]
D[3]
C[15]
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
A[14]
V
V
SS_HV
_IO
SS_HV
_IO
SS_HV
_IO
DD_HV
_IO
SS_HV
_IO
B[6]
F[3]
D[2]
A[9]
D[4]
D[0]
H[12]
E[15]
E[14]
I[1]
B[3]
F[14]
F[15]
F[13]
B[1]
B[0]
V
V
FCCU_
F[1]
V
V
V
DD_HV
_IO
1
SS_HV
_IO
DD_HV
DD_HV
SS_HV
_IO
NC
A[13]
I[0]
JCOMP H[11]
A[4]
F[12]
G[3]
I[3]
_REG_2
_REG_2
V
V
V
V
V
V
PP
SS_LV_
COR
DD_LV_
COR
DD_HV
_IO
SS_HV
_IO
DD_HV
_IO
F[5]
F[4]
F[6]
A[15]
D[1]
A[7]
C[5]
C[4]
C[6]
NMI
A[8]
A[6]
A[5]
F[0]
A[11]
NC
E[13]
D[14]
G[2]
I[2]
_TEST
MDO0
H[1]
NC
NC
C[14]
V
V
V
V
V
V
V
V
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
DD_LV_
COR
G[12]
C[13]
H[13]
G[4]
G[6]
H[6]
H[15]
A[3]
B[4]
H[5]
G[5]
G[7]
G[9]
V
V
V
V
V
V
V
DD_HV
_IO
DD_LV_
COR
SS_LV_
COR
SS_LV_
COR
SS_LV_
COR
SS_LV_
COR
SS_LV_
COR
DD_LV_
COR
G
H
J
H[3]
D[12]
H[9]
V
V
V
SS_HV
_IO
DD_HV
DD_HV
_FLA
G[13]
F[7]
V
V
V
V
V
V
V
V
SS_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
SS_LV
SS_LV
SS_LV
SS_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
DD_LV
_REG_1
V
V
V
V
DD_HV
DD_HV
DD_HV
SS_HV
_FLA
G[15]
F[8]
V
V
V
V
V
V
V
V
V
V
DD_LV
NC
_REG_0
_REG_0
_REG_1
K
L
F[9]
C[7]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
H[8]
H[7]
H[4]
TMS
A[2]
F[10]
F[11]
D[9]
D[8]
D[5]
D[6]
NC
NC
NC
TCK
B[5]
V
V
DD_HV
_OSC
DD_HV
_IO
M
N
P
R
T
V
V
V
V
V
C[11]
NC
V
V
SS_HV
_IO
SS_LV_
PLL
XTAL
C[12]
G[10]
V
V
V
V
V
V
V
V
V
SS_HV
_OSC
DD_LV_
PLL
DD_LV_
COR
SS_LV_
COR
SS_HV
_IO
DD_HV
_IO
DD_LV_
COR
SS_LV_
COR
DD_HV
_IO
RESET
B[8]
NC
B[14]
B[15]
E[10]
G[8]
D[11]
FCCU
_F[0]
V
V
V
V
SS_HV
_IO
DD_HV
DD_HV
SS_HV
_IO
EXTAL
D[7]
C[1]
B[7]
E[5]
E[6]
E[7]
B[10]
B[11]
B[13]
E[9]
C[0]
BCTRL
E[0]
A[1]
_ADR0
_ADR1
V
V
V
V
V
V
V
SS_HV
_IO
DD_HV
_IO
SS_HV
_ADR0
SS_HV
_ADR1
DD_HV
_IO
SS_HV
_IO
NC
E[12]
A[0]
D[10]
V
V
V
V
V
V
SS_HV
_IO
SS_HV
_IO
DD_HV
_ADV
SS_HV
_ADV
DD_HV
SS_HV
_IO
SS_HV
_IO
U
E[4]
4
C[2]
5
E[2]
6
B[9]
B[12]
8
E[11]
11
NC
12
NC
13
G[11]
15
NC
3
_PMU
1
2
7
9
10
14
16
17
1
NC = Not connected (the pin is physically not connected to anything on the device)
Figure 3. MPC5643L 257 MAPBGA pinout (top view)
Table 3 and Table 4 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
MPC5643L Microcontroller Data Sheet, Rev. 9
24
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary
Pin #
Port/function
Peripheral
Output function
Input function
1
2
NMI
A[6]
—
GPIO[6]
SCK
SIUL
DSPI_1
SIUL
GPIO[6]
SCK
—
EIRQ[6]
GPIO[49]
ETC[2]
—
3
D[1]
SIUL
GPIO[49]
ETC[2]
EXT_TGR
—
eTimer_1
CTU_0
FlexRay
SIUL
CA_RX
GPIO[84]
—
4
5
F[4]
F[5]
GPIO[84]
MDO[3]
GPIO[85]
MDO[2]
—
NPC
SIUL
GPIO[85]
—
NPC
6
7
8
VDD_HV_IO
VSS_HV_IO
F[6]
—
SIUL
NPC
GPIO[86]
MDO[1]
—
GPIO[86]
—
9
MDO0
A[7]
10
SIUL
DSPI_1
SIUL
GPIO[7]
SOUT
—
GPIO[7]
—
EIRQ[7]
GPIO[36]
CS0
11
C[4]
SIUL
GPIO[36]
CS0
DSPI_0
FlexPWM_0
SSCM
SIUL
X[1]
X[1]
DEBUG[4]
—
—
EIRQ[22]
GPIO[8]
SIN
12
13
A[8]
C[5]
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
GPIO[37]
SCK
SIUL
GPIO[37]
SCK
DSPI_0
SSCM
FlexPWM_0
SIUL
DEBUG[5]
—
—
FAULT[3]
EIRQ[23]
—
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
25
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
14
A[5]
SIUL
DSPI_1
eTimer_1
DSPI_0
SIUL
GPIO[5]
CS0
GPIO[5]
CS0
ETC[5]
CS7
ETC[5]
—
—
EIRQ[5]
GPIO[39]
A[1]
15
C[7]
SIUL
GPIO[39]
A[1]
FlexPWM_0
SSCM
DEBUG[7]
—
—
DSPI_0
SIN
16
17
18
19
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
—
—
—
SIUL
NPC
SIUL
NPC
GPIO[87]
MCKO
GPIO[88]
MSEO[1]
—
GPIO[87]
—
20
F[8]
GPIO[88]
—
21
22
23
VDD_HV_IO
VSS_HV_IO
F[9]
—
SIUL
NPC
GPIO[89]
MSEO[0]
GPIO[90]
EVTO
GPIO[91]
—
GPIO[89]
—
24
25
26
F[10]
F[11]
D[9]
SIUL
GPIO[90]
—
NPC
SIUL
GPIO[91]
EVTI
NPC
SIUL
GPIO[57]
X[0]
GPIO[57]
X[0]
FlexPWM_0
LINFlexD_1
TXD
—
27
28
29
30
31
VDD_HV_OSC
VSS_HV_OSC
XTAL
—
—
—
EXTAL
—
RESET
—
MPC5643L Microcontroller Data Sheet, Rev. 9
26
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
32
D[8]
SIUL
DSPI_1
GPIO[56]
GPIO[56]
—
CS2
eTimer_1
DSPI_0
ETC[4]
ETC[4]
—
CS5
FlexPWM_0
SIUL
—
FAULT[3]
GPIO[53]
—
33
34
D[5]
D[6]
GPIO[53]
DSPI_0
CS3
FlexPWM_0
SIUL
—
FAULT[2]
GPIO[54]
—
GPIO[54]
DSPI_0
CS2
FlexPWM_0
FlexPWM_0
X[3]
X[3]
—
FAULT[1]
35
36
37
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
D[7]
—
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
GPIO[55]
CS3
—
—
CS4
analog output
—
38
39
40
41
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
FCCU
F[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F[0]
SIUL
ADC_0
SIUL
GPIO[33]
AN[2]
42
43
E[4]
B[7]
GPIO[68]
AN[7]
ADC_0
SIUL
GPIO[23]
RXD
LINFlexD_0
ADC_0
SIUL
AN[0]
44
45
46
E[5]
C[2]
E[6]
GPIO[69]
AN[8]
ADC_0
SIUL
GPIO[34]
AN[3]
ADC_0
SIUL
GPIO[70]
AN[4]
ADC_0
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
27
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
47
B[8]
SIUL
eTimer_0
ADC_0
SIUL
—
—
—
—
—
—
—
—
—
—
—
GPIO[24]
ETC[5]
AN[1]
48
49
E[7]
E[2]
GPIO[71]
AN[6]
ADC_0
SIUL
GPIO[66]
AN[5]
ADC_0
50
51
52
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
SIUL
GPIO[25]
AN[11]
ADC_0
ADC_1
53
54
55
B[10]
B[11]
B[12]
SIUL
—
—
GPIO[26]
AN[12]
ADC_0
ADC_1
SIUL
—
—
GPIO[27]
AN[13]
ADC_0
ADC_1
SIUL
—
—
GPIO[28]
AN[14]
ADC_0
ADC_1
56
57
58
59
60
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
AN[0]
61
62
E[9]
GPIO[73]
AN[7]
ADC_1
SIUL
B[15]
GPIO[31]
EIRQ[20]
AN[2]
SIUL
ADC_1
SIUL
63
E[10]
GPIO[74]
AN[8]
ADC_1
MPC5643L Microcontroller Data Sheet, Rev. 9
28
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
64
B[14]
SIUL
eTimer_0
SIUL
—
—
GPIO[30]
ETC[4]
EIRQ[19]
AN[1]
—
ADC_1
SIUL
—
65
66
67
68
E[11]
C[0]
—
GPIO[75]
AN[4]
ADC_1
SIUL
—
—
GPIO[32]
AN[3]
ADC_1
SIUL
—
E[12]
E[0]
—
GPIO[76]
AN[6]
ADC_1
SIUL
—
—
GPIO[64]
AN[5]
ADC_1
—
69
70
71
72
73
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
A[0]
—
—
—
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[0]
ETC[0]
SCK
—
GPIO[0]
ETC[0]
SCK
EIRQ[0]
GPIO[1]
ETC[1]
—
74
A[1]
SIUL
GPIO[1]
ETC[1]
SOUT
—
eTimer_0
DSPI_2
SIUL
EIRQ[1]
GPIO[107]
—
75
76
77
G[11]
D[10]
G[10]
SIUL
GPIO[107]
DBG3
—
FlexRay
FlexPWM_0
SIUL
FAULT[3]
GPIO[58]
A[0]
GPIO[58]
A[0]
—
FlexPWM_0
eTimer_0
SIUL
ETC[0]
GPIO[106]
—
GPIO[106]
DBG2
CS3
—
FlexRay
DSPI_2
FlexPWM_0
—
FAULT[2]
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
29
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
78
D[11]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[59]
B[0]
GPIO[59]
B[0]
—
ETC[1]
GPIO[105]
—
79
G[9]
GPIO[105]
DBG1
CS1
FlexRay
DSPI_1
FlexPWM_0
SIUL
—
—
FAULT[1]
EIRQ[29]
GPIO[43]
ETC[4]
—
—
80
81
C[11]
G[8]
SIUL
GPIO[43]
ETC[4]
CS2
eTimer_0
DSPI_2
SIUL
GPIO[104]
DBG0
CS1
GPIO[104]
—
FlexRay
DSPI_0
FlexPWM_0
SIUL
—
—
FAULT[0]
EIRQ[21]
GPIO[44]
ETC[5]
—
—
82
C[12]
SIUL
GPIO[44]
ETC[5]
CS3
eTimer_0
DSPI_2
SIUL
83
84
G[7]
A[2]
GPIO[103]
B[3]
GPIO[103]
B[3]
FlexPWM_0
SIUL
GPIO[2]
ETC[2]
A[3]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
—
SIN
—
ABS[0]
EIRQ[2]
GPIO[101]
X[3]
—
85
86
G[5]
B[5]
SIUL
GPIO[101]
X[3]
FlexPWM_0
DSPI_2
SIUL
CS3
—
GPIO[21]
—
GPIO[21]
TDI
JTAGC
87
88
TMS
TCK
—
—
MPC5643L Microcontroller Data Sheet, Rev. 9
30
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
89
B[4]
SIUL
GPIO[20]
TDO
—
GPIO[20]
—
JTAGC
90
91
92
VSS_HV_IO
VDD_HV_IO
A[3]
—
SIUL
eTimer_0
DSPI_2
GPIO[3]
ETC[3]
CS0
GPIO[3]
ETC[3]
CS0
FlexPWM_0
MC_RGM
SIUL
B[3]
B[3]
—
ABS[2]
EIRQ[3]
—
93
94
95
96
97
98
VDD_LV_COR
VSS_LV_COR
VDD_HV_REG_1
VSS_HV_FLA
VDD_HV_FLA
G[6]
—
—
—
—
—
SIUL
FlexPWM_0
SIUL
GPIO[102]
A[3]
GPIO[102]
A[3]
99
D[12]
G[4]
GPIO[60]
X[1]
GPIO[60]
X[1]
FlexPWM_0
LINFlexD_1
SIUL
—
RXD
100
101
GPIO[100]
B[2]
GPIO[100]
B[2]
FlexPWM_0
eTimer_0
SIUL
—
ETC[5]
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[98]
X[2]
C[13]
GPIO[45]
ETC[1]
—
eTimer_1
CTU_0
FlexPWM_0
SIUL
—
102
103
G[2]
GPIO[98]
X[2]
FlexPWM_0
DSPI_1
CS1
—
C[14]
SIUL
GPIO[46]
ETC[2]
EXT_TGR
GPIO[46]
ETC[2]
—
eTimer_1
CTU_0
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
31
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
104
G[3]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[99]
A[2]
GPIO[99]
A[2]
—
ETC[4]
GPIO[62]
B[1]
105
106
D[14]
F[12]
GPIO[62]
B[1]
FlexPWM_0
eTimer_0
SIUL
—
ETC[3]
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[92]
ETC[3]
—
eTimer_1
SIUL
1
107
108
VPP_TEST
—
A[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
GPIO[16]
—
109
110
B[0]
B[1]
SIUL
GPIO[16]
TXD
FlexCAN_0
eTimer_1
SSCM
ETC[2]
DEBUG[0]
—
ETC[2]
—
SIUL
EIRQ[15]
GPIO[17]
ETC[3]
—
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
eTimer_1
SSCM
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
GPIO[42]
—
111
112
C[10]
F[13]
SIUL
GPIO[42]
CS2
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[3]
A[3]
—
FAULT[1]
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[93]
ETC[4]
—
eTimer_1
SIUL
MPC5643L Microcontroller Data Sheet, Rev. 9
32
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
113
F[15]
SIUL
LINFlexD_1
SIUL
GPIO[95]
—
GPIO[95]
RXD
114
B[2]
GPIO[18]
TXD
GPIO[18]
—
LINFlexD_0
SSCM
DEBUG[2]
—
—
SIUL
EIRQ[17]
GPIO[94]
—
115
116
F[14]
B[3]
SIUL
GPIO[94]
TXD
LINFlexD_1
SIUL
GPIO[19]
DEBUG[3]
—
GPIO[19]
—
SSCM
LINFlexD_0
SIUL
RXD
117
118
E[13]
A[10]
GPIO[77]
ETC[5]
CS3
GPIO[77]
ETC[5]
—
eTimer_0
DSPI_2
SIUL
—
EIRQ[25]
GPIO[10]
CS0
SIUL
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[78]
ETC[5]
EIRQ[26]
GPIO[11]
SCK
119
120
E[14]
A[11]
SIUL
GPIO[78]
ETC[5]
—
eTimer_1
SIUL
SIUL
GPIO[11]
SCK
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
A[0]
A[0]
A[2]
A[2]
—
EIRQ[10]
GPIO[79]
—
121
E[15]
SIUL
GPIO[79]
CS1
DSPI_0
SIUL
—
EIRQ[27]
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
33
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
122
A[12]
SIUL
DSPI_2
GPIO[12]
SOUT
A[2]
GPIO[12]
—
FlexPWM_0
FlexPWM_0
SIUL
A[2]
B[2]
B[2]
—
EIRQ[11]
JCOMP
GPIO[47]
—
123
124
JCOMP
C[15]
—
—
SIUL
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
FlexRay
eTimer_1
FlexPWM_0
CTU_0
ETC[0]
A[1]
—
EXT_IN
EXT_SYNC
GPIO[48]
—
FlexPWM_0
SIUL
—
125
D[0]
GPIO[48]
CA_TX
ETC[1]
B[1]
FlexRay
eTimer_1
FlexPWM_0
ETC[1]
B[1]
126
127
128
VDD_HV_IO
VSS_HV_IO
D[3]
—
—
SIUL
FlexRay
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[51]
—
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
129
D[4]
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
GPIO[52]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[5]
B[3]
130
131
132
133
VDD_HV_REG_2
VDD_LV_COR
VSS_LV_COR
F[0]
—
—
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
GPIO[80]
A[1]
—
ETC[2]
EIRQ[28]
—
MPC5643L Microcontroller Data Sheet, Rev. 9
34
Freescale Semiconductor
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
134
A[9]
SIUL
GPIO[9]
CS1
GPIO[9]
—
DSPI_2
FlexPWM_0
FlexPWM_0
B[3]
B[3]
—
FAULT[0]
135
136
VDD_LV_COR
A[13]
—
SIUL
FlexPWM_0
DSPI_2
GPIO[13]
B[2]
GPIO[13]
B[2]
—
SIN
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[12]
—
137
138
VSS_LV_COR
B[6]
—
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
GPIO[22]
—
—
—
EIRQ[18]
GPIO[83]
—
139
140
F[3]
D[2]
SIUL
GPIO[83]
CS6
DSPI_0
SIUL
GPIO[50]
ETC[3]
X[3]
GPIO[50]
ETC[3]
X[3]
eTimer_1
FlexPWM_0
FlexRay
FCCU
—
CB_RX
F[1]
141
142
FCCU_F[1]
C[6]
F[1]
SIUL
GPIO[38]
SOUT
B[1]
GPIO[38]
—
DSPI_0
FlexPWM_0
SSCM
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
GPIO[14]
—
143
A[14]
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
ETC[4]
—
ETC[4]
EIRQ[13]
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
35
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
144
A[15]
SIUL
GPIO[15]
ETC[5]
—
GPIO[15]
ETC[5]
RXD
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
—
RXD
—
EIRQ[14]
1
VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary
Pin #
Port/function
Peripheral
Output function
Input function
A1
A2
A3
A4
VSS_HV_IO_RING
VSS_HV_IO_RING
VDD_HV_IO_RING
H[2]
—
—
—
SIUL
NPC
GPIO[114]
MDO[5]
GPIO[112]
MDO[7]
GPIO[110]
MDO[9]
GPIO[51]
CB_TX
ETC[4]
A[3]
GPIO[114]
—
A5
A6
A7
H[0]
G[14]
D[3]
SIUL
GPIO[112]
—
NPC
SIUL
GPIO[110]
—
NPC
SIUL
GPIO[51]
—
FlexRay
eTimer_1
FlexPWM_0
SIUL
ETC[4]
A[3]
A8
C[15]
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
GPIO[47]
—
FlexRay
eTimer_1
FlexPWM_0
CTU_0
FlexPWM_0
ETC[0]
A[1]
—
EXT_IN
EXT_SYNC
—
A9
VDD_HV_IO_RING
A[12]
—
A10
SIUL
DSPI_2
GPIO[12]
SOUT
A[2]
GPIO[12]
—
FlexPWM_0
FlexPWM_0
SIUL
A[2]
B[2]
B[2]
—
EIRQ[11]
MPC5643L Microcontroller Data Sheet, Rev. 9
36
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
A11
H[10]
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[122]
X[2]
GPIO[122]
X[2]
ETC[2]
GPIO[126]
A[3]
ETC[2]
GPIO[126]
A[3]
A12
A13
H[14]
A[10]
FlexPWM_1
eTimer_2
SIUL
ETC[4]
GPIO[10]
CS0
ETC[4]
GPIO[10]
CS0
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
B[0]
B[0]
X[2]
X[2]
—
EIRQ[9]
GPIO[18]
—
A14
A15
B[2]
SIUL
GPIO[18]
TXD
LINFlexD_0
SSCM
DEBUG[2]
—
—
SIUL
EIRQ[17]
GPIO[42]
—
C[10]
SIUL
GPIO[42]
CS2
DSPI_2
FlexPWM_0
FlexPWM_0
A[3]
A[3]
—
FAULT[1]
A16
A17
B1
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
B[6]
—
—
—
B2
—
B3
SIUL
MC_CGM
DSPI_2
SIUL
GPIO[22]
clk_out
CS2
GPIO[22]
—
—
—
EIRQ[18]
GPIO[14]
—
B4
B5
A[14]
F[3]
SIUL
GPIO[14]
TXD
FlexCAN_1
eTimer_1
SIUL
ETC[4]
—
ETC[4]
EIRQ[13]
GPIO[83]
—
SIUL
GPIO[83]
CS6
DSPI_0
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
37
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
B6
A[9]
SIUL
DSPI_2
GPIO[9]
CS1
GPIO[9]
—
FlexPWM_0
FlexPWM_0
SIUL
B[3]
B[3]
—
FAULT[0]
GPIO[52]
—
B7
B8
D[4]
D[0]
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
FlexRay
eTimer_1
FlexPWM_0
SIUL
ETC[5]
B[3]
GPIO[48]
CA_TX
ETC[1]
B[1]
GPIO[48]
—
FlexRay
eTimer_1
FlexPWM_0
ETC[1]
B[1]
B9
VSS_HV_IO_RING
H[12]
—
B10
SIUL
FlexPWM_1
SIUL
GPIO[124]
B[2]
GPIO[124]
B[2]
B11
B12
B13
B14
B15
E[15]
E[14]
B[3]
GPIO[79]
CS1
GPIO[79]
—
DSPI_0
SIUL
—
EIRQ[27]
GPIO[78]
ETC[5]
EIRQ[26]
GPIO[19]
—
SIUL
GPIO[78]
ETC[5]
—
eTimer_1
SIUL
SIUL
GPIO[19]
DEBUG[3]
—
SSCM
LINFlexD_0
SIUL
RXD
F[13]
B[0]
GPIO[93]
ETC[4]
—
GPIO[93]
ETC[4]
EIRQ[31]
GPIO[16]
—
eTimer_1
SIUL
SIUL
GPIO[16]
TXD
FlexCAN_0
eTimer_1
SSCM
ETC[2]
DEBUG[0]
—
ETC[2]
—
SIUL
EIRQ[15]
B16
B17
C1
VDD_HV_IO_RING
VSS_HV_IO_RING
VDD_HV_IO_RING
—
—
—
MPC5643L Microcontroller Data Sheet, Rev. 9
38
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
C2
C3
C4
C5
Not connected
VSS_HV_IO_RING
FCCU_F[1]
D[2]
—
—
FCCU
SIUL
F[1]
F[1]
GPIO[50]
ETC[3]
X[3]
GPIO[50]
ETC[3]
X[3]
eTimer_1
FlexPWM_0
FlexRay
SIUL
—
CB_RX
GPIO[13]
B[2]
C6
A[13]
GPIO[13]
B[2]
FlexPWM_0
DSPI_2
—
SIN
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[12]
—
C7
C8
C9
VDD_HV_REG_2
VDD_HV_REG_2
I[0]
—
—
SIUL
eTimer_2
DSPI_0
FlexPWM_1
—
GPIO[128]
ETC[0]
CS4
GPIO[128]
ETC[0]
—
—
FAULT[0]
JCOMP
GPIO[123]
A[2]
C10
C11
JCOMP
H[11]
—
SIUL
GPIO[123]
A[2]
FlexPWM_1
SIUL
C12
I[1]
GPIO[129]
ETC[1]
CS5
GPIO[129]
ETC[1]
—
eTimer_2
DSPI_0
FlexPWM_1
SIUL
—
FAULT[1]
GPIO[94]
—
C13
C14
F[14]
B[1]
GPIO[94]
TXD
LINFlexD_1
SIUL
GPIO[17]
ETC[3]
DEBUG[1]
—
GPIO[17]
ETC[3]
—
eTimer_1
SSCM
FlexCAN_0
FlexCAN_1
SIUL
RXD
—
RXD
—
EIRQ[16]
C15
VSS_HV_IO_RING
—
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
39
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
C16
A[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
GPIO[4]
ETC[0]
CS1
GPIO[4]
ETC[0]
—
ETC[4]
—
ETC[4]
FAB
—
EIRQ[4]
GPIO[92]
ETC[3]
EIRQ[30]
GPIO[85]
—
C17
F[12]
SIUL
GPIO[92]
ETC[3]
—
eTimer_1
SIUL
D1
D2
D3
F[5]
F[4]
SIUL
GPIO[85]
MDO[2]
GPIO[84]
MDO[3]
GPIO[15]
ETC[5]
—
NPC
SIUL
GPIO[84]
—
NPC
A[15]
SIUL
GPIO[15]
ETC[5]
RXD
eTimer_1
FlexCAN_1
FlexCAN_0
SIUL
—
RXD
—
EIRQ[14]
GPIO[38]
—
D4
C[6]
SIUL
GPIO[38]
SOUT
B[1]
DSPI_0
FlexPWM_0
SSCM
B[1]
DEBUG[6]
—
—
SIUL
EIRQ[24]
D5
D6
D7
VSS_LV_CORE_RING
VDD_LV_CORE_RING
F[0]
—
—
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[80]
A[1]
GPIO[80]
A[1]
—
ETC[2]
EIRQ[28]
—
D8
D9
VDD_HV_IO_RING
VSS_HV_IO_RING
Not connected
—
—
D10
—
MPC5643L Microcontroller Data Sheet, Rev. 9
40
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
D11
A[11]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
GPIO[11]
SCK
GPIO[11]
SCK
A[0]
A[0]
A[2]
A[2]
—
EIRQ[10]
GPIO[77]
ETC[5]
—
D12
D13
E[13]
SIUL
GPIO[77]
ETC[5]
CS3
eTimer_0
DSPI_2
SIUL
—
EIRQ[25]
GPIO[95]
RXD
F[15]
SIUL
GPIO[95]
—
LINFlexD_1
D14
D15
D16
VDD_HV_IO_RING
—
1
VPP_TEST
—
D[14]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[62]
B[1]
GPIO[62]
B[1]
—
ETC[3]
GPIO[99]
A[2]
D17
G[3]
GPIO[99]
A[2]
FlexPWM_0
eTimer_0
—
ETC[4]
E1
E2
MDO0
F[6]
—
SIUL
NPC
GPIO[86]
MDO[1]
GPIO[49]
ETC[2]
EXT_TGR
—
GPIO[86]
—
E3
D[1]
SIUL
GPIO[49]
ETC[2]
—
eTimer_1
CTU_0
FlexRay
CA_RX
E4
NMI
Not connected
C[14]
—
E14
E15
—
SIUL
eTimer_1
CTU_0
GPIO[46]
ETC[2]
EXT_TGR
GPIO[98]
X[2]
GPIO[46]
ETC[2]
—
E16
G[2]
SIUL
GPIO[98]
X[2]
FlexPWM_0
DSPI_1
CS1
—
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
41
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
E17
I[3]
SIUL
eTimer_2
DSPI_0
CTU_0
FlexPWM_1
SIUL
GPIO[131]
ETC[3]
CS7
GPIO[131]
ETC[3]
—
EXT_TGR
—
—
FAULT[3]
GPIO[113]
—
F1
F2
F3
H[1]
G[12]
A[7]
GPIO[113]
MDO[6]
GPIO[108]
MDO[11]
GPIO[7]
SOUT
—
NPC
SIUL
GPIO[108]
—
NPC
SIUL
GPIO[7]
—
DSPI_1
SIUL
EIRQ[7]
GPIO[8]
SIN
F4
A[8]
SIUL
GPIO[8]
—
DSPI_1
SIUL
—
EIRQ[8]
F6
F7
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
VDD_LV_CORE_RING
Not connected
—
—
F8
—
F9
—
F10
F11
F12
F14
F15
—
—
—
—
C[13]
SIUL
eTimer_1
CTU_0
GPIO[45]
ETC[1]
—
GPIO[45]
ETC[1]
EXT_IN
EXT_SYNC
GPIO[130]
ETC[2]
FlexPWM_0
SIUL
—
F16
F17
I[2]
GPIO[130]
ETC[2]
CS6
eTimer_2
DSPI_0
—
FlexPWM_1
SIUL
—
FAULT[2]
GPIO[100]
B[2]
G[4]
GPIO[100]
B[2]
FlexPWM_0
eTimer_0
—
ETC[5]
MPC5643L Microcontroller Data Sheet, Rev. 9
42
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
G1
H[3]
SIUL
NPC
GPIO[115]
MDO[4]
—
GPIO[115]
—
G2
G3
VDD_HV_IO_RING
C[5]
SIUL
DSPI_0
SSCM
GPIO[37]
SCK
GPIO[37]
SCK
DEBUG[5]
—
—
FlexPWM_0
SIUL
FAULT[3]
EIRQ[23]
GPIO[6]
SCK
—
G4
A[6]
SIUL
GPIO[6]
SCK
DSPI_1
SIUL
—
EIRQ[6]
G6
G7
VDD_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VSS_LV_CORE_RING
VDD_LV_CORE_RING
D[12]
—
—
G8
—
G9
—
G10
G11
G12
G14
—
—
—
SIUL
FlexPWM_0
LINFlexD_1
SIUL
GPIO[60]
X[1]
GPIO[60]
X[1]
—
RXD
G15
G16
H[13]
H[9]
GPIO[125]
X[3]
GPIO[125]
X[3]
FlexPWM_1
eTimer_2
SIUL
ETC[3]
GPIO[121]
B[1]
ETC[3]
GPIO[121]
B[1]
FlexPWM_1
DSPI_0
CS7
—
G17
H1
G[6]
G[13]
SIUL
GPIO[102]
A[3]
GPIO[102]
A[3]
FlexPWM_0
SIUL
GPIO[109]
MDO[10]
—
GPIO[109]
—
NPC
H2
VSS_HV_IO_RING
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
43
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
H3
C[4]
SIUL
DSPI_0
FlexPWM_0
SSCM
GPIO[36]
GPIO[36]
CS0
CS0
X[1]
X[1]
DEBUG[4]
—
SIUL
—
EIRQ[22]
GPIO[5]
CS0
H4
A[5]
SIUL
GPIO[5]
DSPI_1
eTimer_1
DSPI_0
SIUL
CS0
ETC[5]
ETC[5]
—
CS7
—
EIRQ[5]
H6
H7
VDD_LV
VSS_LV
—
—
H8
VSS_LV
—
H9
VSS_LV
—
H10
H11
H12
H14
H15
H16
H17
VSS_LV
—
VSS_LV
—
VDD_LV
—
VSS_LV
—
VDD_HV_REG_1
VDD_HV_FLA
H[6]
—
—
SIUL
FlexPWM_1
DSPI_0
SIUL
GPIO[118]
B[0]
GPIO[118]
B[0]
CS5
GPIO[87]
MCKO
GPIO[111]
MDO[8]
—
—
J1
J2
F[7]
GPIO[87]
—
NPC
G[15]
SIUL
GPIO[111]
—
NPC
J3
J4
VDD_HV_REG_0
VDD_HV_REG_0
VDD_LV
—
J6
—
J7
VSS_LV
—
J8
VSS_LV
—
J9
VSS_LV
—
J10
J11
VSS_LV
—
VSS_LV
—
MPC5643L Microcontroller Data Sheet, Rev. 9
44
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
J12
J14
J15
J16
J17
VDD_LV
VDD_LV
—
—
VDD_HV_REG_1
VSS_HV_FLA
H[15]
—
—
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[127]
B[3]
GPIO[127]
B[3]
ETC[5]
GPIO[89]
MSEO[0]
GPIO[88]
MSEO[1]
RDY
ETC[5]
GPIO[89]
—
K1
K2
K3
K4
F[9]
F[8]
NPC
SIUL
GPIO[88]
—
NPC
RDY
C[7]
NPC
—
SIUL
GPIO[132]
GPIO[39]
A[1]
GPIO[132]
GPIO[39]
A[1]
SIUL
FlexPWM_0
SSCM
DSPI_0
DEBUG[7]
—
—
SIN
K6
K7
VDD_LV
VSS_LV
—
—
K8
VSS_LV
—
K9
VSS_LV
—
K10
K11
K12
K14
K15
VSS_LV
—
VSS_LV
—
VDD_LV
—
Not connected
H[8]
—
SIUL
FlexPWM_1
DSPI_0
GPIO[120]
A[1]
GPIO[120]
A[1]
CS6
—
K16
H[7]
SIUL
GPIO[119]
X[1]
GPIO[119]
X[1]
FlexPWM_1
eTimer_2
ETC[1]
ETC[1]
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
45
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
K17
A[3]
SIUL
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
GPIO[3]
ETC[3]
CS0
B[3]
GPIO[3]
ETC[3]
CS0
B[3]
—
ABS[2]
EIRQ[3]
GPIO[90]
—
—
L1
L2
L3
F[10]
F[11]
D[9]
SIUL
GPIO[90]
EVTO
GPIO[91]
—
NPC
SIUL
GPIO[91]
EVTI
NPC
SIUL
GPIO[57]
X[0]
GPIO[57]
X[0]
FlexPWM_0
LINFlexD_1
TXD
—
—
L4
L6
Not connected
VDD_LV
—
L7
VSS_LV
—
L8
VSS_LV
—
L9
VSS_LV
—
L10
L11
L12
L14
L15
L16
VSS_LV
—
VSS_LV
—
VDD_LV
—
Not connected
TCK
—
—
H[4]
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[116]
X[0]
GPIO[116]
X[0]
ETC[0]
GPIO[20]
TDO
—
ETC[0]
GPIO[20]
—
L17
B[4]
JTAGC
M1
M2
M3
VDD_HV_OSC
VDD_HV_IO_RING
D[8]
—
SIUL
DSPI_1
GPIO[56]
CS2
ETC[4]
CS5
—
GPIO[56]
—
eTimer_1
DSPI_0
ETC[4]
—
FlexPWM_0
FAULT[3]
MPC5643L Microcontroller Data Sheet, Rev. 9
46
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
M4
M6
Not connected
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
C[11]
—
—
M7
—
M8
—
M9
—
M10
M11
M12
M14
—
—
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[43]
ETC[4]
CS2
GPIO[21]
—
GPIO[43]
ETC[4]
—
M15
B[5]
GPIO[21]
TDI
JTAGC
M16
M17
TMS
H[5]
—
SIUL
GPIO[117]
A[0]
GPIO[117]
A[0]
FlexPWM_1
DSPI_0
CS4
—
—
N1
N2
N3
XTAL
VSS_HV_IO_RING
D[5]
—
SIUL
GPIO[53]
CS3
—
GPIO[53]
—
DSPI_0
FlexPWM_0
FAULT[2]
N4
VSS_LV_PLL0_PLL1
Not connected
C[12]
—
N14
N15
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[44]
ETC[5]
CS3
GPIO[2]
ETC[2]
A[3]
GPIO[44]
ETC[5]
—
N16
A[2]
GPIO[2]
ETC[2]
A[3]
eTimer_0
FlexPWM_0
DSPI_2
MC_RGM
SIUL
—
SIN
—
ABS[0]
EIRQ[2]
—
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
47
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
N17
G[5]
SIUL
GPIO[101]
GPIO[101]
X[3]
FlexPWM_0
DSPI_2
X[3]
CS3
—
P1
P2
P3
VSS_HV_OSC
RESET
D[6]
—
—
SIUL
GPIO[54]
GPIO[54]
—
DSPI_0
CS2
FlexPWM_0
FlexPWM_0
X[3]
X[3]
—
FAULT[1]
P4
P5
P6
P7
VDD_LV_PLL0_PLL1
VDD_LV_CORE_RING
VSS_LV_CORE_RING
B[8]
—
—
—
SIUL
—
GPIO[24]
ETC[5]
AN[1]
eTimer_0
ADC_0
—
—
P8
P9
Not connected
VSS_HV_IO_RING
VDD_HV_IO_RING
B[14]
—
—
P10
P11
—
SIUL
eTimer_0
SIUL
—
GPIO[30]
ETC[4]
—
—
EIRQ[19]
AN[1]
ADC_1
—
P12
P13
P14
P15
VDD_LV_CORE_RING
VSS_LV_CORE_RING
VDD_HV_IO_RING
G[10]
—
—
—
SIUL
FlexRay
DSPI_2
FlexPWM_0
SIUL
GPIO[106]
DBG2
CS3
—
GPIO[106]
—
—
FAULT[2]
GPIO[104]
—
P16
G[8]
GPIO[104]
DBG0
CS1
—
FlexRay
DSPI_0
FlexPWM_0
SIUL
—
FAULT[0]
EIRQ[21]
—
MPC5643L Microcontroller Data Sheet, Rev. 9
48
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
P17
G[7]
SIUL
GPIO[103]
GPIO[103]
B[3]
FlexPWM_0
B[3]
R1
R2
R3
R4
EXTAL
FCCU_F[0]
VSS_HV_IO_RING
D[7]
—
FCCU
F[0]
F[0]
—
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
GPIO[55]
—
CS3
CS4
—
analog output
—
R5
R6
B[7]
E[6]
SIUL
—
—
—
—
—
—
—
—
GPIO[23]
RXD
LINFlexD_0
ADC_0
SIUL
AN[0]
GPIO[70]
AN[4]
ADC_0
R7
R8
VDD_HV_ADR0
B[10]
SIUL
GPIO[26]
AN[12]
ADC_0
ADC_1
R9
VDD_HV_ADR1
B[13]
—
—
R10
SIUL
LINFlexD_1
ADC_1
SIUL
GPIO[29]
RXD
—
—
AN[0]
R11
R12
B[15]
C[0]
—
GPIO[31]
EIRQ[20]
AN[2]
SIUL
—
ADC_1
SIUL
—
—
GPIO[32]
AN[3]
ADC_1
—
R13
R14
BCTRL
A[1]
—
SIUL
eTimer_0
DSPI_2
SIUL
GPIO[1]
ETC[1]
SOUT
—
GPIO[1]
ETC[1]
—
EIRQ[1]
R15
VSS_HV_IO_RING
—
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
49
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
R16
D[11]
SIUL
FlexPWM_0
eTimer_0
SIUL
GPIO[59]
GPIO[59]
B[0]
B[0]
—
ETC[1]
GPIO[105]
—
R17
G[9]
GPIO[105]
FlexRay
DSPI_1
DBG1
CS1
—
—
FlexPWM_0
SIUL
FAULT[1]
EIRQ[29]
—
T1
T2
T3
T4
VSS_HV_IO_RING
VDD_HV_IO_RING
Not connected
C[1]
—
—
—
SIUL
ADC_0
SIUL
—
GPIO[33]
AN[2]
—
T5
T6
E[5]
E[7]
—
GPIO[69]
AN[8]
ADC_0
SIUL
—
—
GPIO[71]
AN[6]
ADC_0
—
T7
T8
VSS_HV_ADR0
B[11]
—
SIUL
—
GPIO[27]
AN[13]
ADC_0
ADC_1
—
T9
VSS_HV_ADR1
E[9]
—
—
T10
SIUL
ADC_1
SIUL
GPIO[73]
AN[7]
—
T11
T12
T13
T14
E[10]
E[12]
E[0]
—
GPIO[74]
AN[8]
ADC_1
SIUL
—
—
GPIO[76]
AN[6]
ADC_1
SIUL
—
—
GPIO[64]
AN[5]
ADC_1
SIUL
—
A[0]
GPIO[0]
ETC[0]
SCK
—
GPIO[0]
ETC[0]
SCK
eTimer_0
DSPI_2
SIUL
EIRQ[0]
MPC5643L Microcontroller Data Sheet, Rev. 9
50
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
T15
D[10]
SIUL
GPIO[58]
A[0]
—
GPIO[58]
A[0]
FlexPWM_0
eTimer_0
ETC[0]
T16
T17
U1
VDD_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
VSS_HV_IO_RING
Not connected
E[4]
—
—
—
U2
—
U3
—
U4
SIUL
ADC_0
SIUL
—
GPIO[68]
AN[7]
—
U5
U6
U7
C[2]
E[2]
B[9]
—
GPIO[34]
AN[3]
ADC_0
SIUL
—
—
GPIO[66]
AN[5]
ADC_0
SIUL
—
—
GPIO[25]
AN[11]
ADC_0
ADC_1
—
U8
B[12]
SIUL
—
—
GPIO[28]
AN[14]
ADC_0
ADC_1
U9
VDD_HV_ADV
VSS_HV_ADV
E[11]
—
U10
U11
—
SIUL
—
GPIO[75]
AN[4]
ADC_1
—
U12
U13
U14
U15
Not connected
Not connected
VDD_HV_PMU
G[11]
—
—
—
GPIO[107]
DBG3
—
SIUL
GPIO[107]
—
FlexRay
FlexPWM_0
FAULT[3]
U16
U17
VSS_HV_IO_RING
VSS_HV_IO_RING
—
—
1
VPP_TEST should always be tied to ground (VSS) for normal operations.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
51
Package pinouts and signal descriptions
2.2
Supply pins
Table 5. Supply pins
Supply
Pin #
144
257
pkg
Symbol
Description
pkg
VREG control and power supply pins
BCTRL
Voltage regulator external NPN ballast base control pin
69
70
71
72
R13
VDD_LV1
VSS_LV2
U14
VDD_LV_COR Core logic supply
VSS_LV_COR Core regulator ground
VDD_HV_PMU Voltage regulator supply
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0 ADC_0 high reference voltage
VSS_HV_ADR0 ADC_0 low reference voltage
VDD_HV_ADR1 ADC_1 high reference voltage
VSS_HV_ADR1 ADC_1 low reference voltage
VDD_HV_ADV ADC voltage supply for ADC_0 and ADC_1
VSS_HV_ADV ADC ground for ADC_0 and ADC_1
Power supply pins (3.3 V)
50
51
56
57
58
59
R7
T7
R9
T9
U9
U10
VDD_HV_IO
VSS_HV_IO
3.3 V Input/Output supply voltage
3.3 V Input/Output ground
6
7
VDD_HV3
VSS_HV4
J3
VDD_HV_REG_0 VDD_HV_REG_0
VDD_HV_IO 3.3 V Input/Output supply voltage
VSS_HV_IO 3.3 V Input/Output ground
16
21 VDD_HV3
22 VSS_HV4
VDD_HV_OSC Crystal oscillator amplifier supply voltage
VSS_HV_OSC Crystal oscillator amplifier ground
27
28
M1
P1
VSS_HV_IO
VDD_HV_IO
3.3 V Input/Output ground
90 VSS_HV4
91 VDD_HV3
3.3 V Input/Output supply voltage
VDD_HV_REG_1 VDD_HV_REG_1
VSS_HV_FLA VSS_HV_FLA
VDD_HV_FLA VDD_HV_FLA
95
96
97
H15
J16
H16
VDD_HV_IO
VSS_HV_IO
VDD_HV_IO
VSS_HV_IO
126 VDD_HV3
127 VSS_HV4
VDD_HV_REG_2 VDD_HV_REG_2
130
C7
Power supply pins (1.2 V)
MPC5643L Microcontroller Data Sheet, Rev. 9
52
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply
Pin #
144
pkg
257
pkg
Symbol
Description
VSS_LV_COR VSS_LV_COR
17 VSS_HV2
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR VDD_LV_COR
18
35
36
39
40
70
71
93
94
VDD_LV1
N4
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
VSS 1V2
VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor
must be connected between this pin and VDD_LV_PLL.
VDD 1V2
VDD_LV_PLL0_PLL1
P4
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and VSS_LV_PLL.
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
VDD_LV1
VSS_LV2
VDD_LV1
VSS_LV2
VDD_LV1
VSS_LV2
VSS_LV_COR VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
VSS_LV_COR VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
VDD_LV_COR VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
VSS_LV_COR VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
VDD 1V2
VSS 1V2
VDD 1V2
VSS 1V2
VDD_LV_COR
131 VDD_LV1
132 VSS_LV2
135 VDD_LV1
137 VSS_LV2
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
1
VDD_LV balls are tied together on the 257 MAPBGA substrate.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
53
Package pinouts and signal descriptions
2
VSS_LV balls are tied together on the 257 MAPBGA substrate.
3
VDD_HV balls are tied together on the 257 MAPBGA substrate.
4
VSS_HV balls are tied together on the 257 MAPBGA substrate.
2.3
System pins
Table 6. System pins
Pin #
Symbol
Description
Direction
144 257
pkg pkg
Dedicated pins
MDO01
NMI2
Nexus Message Data Output — line
Non Maskable Interrupt
Output only
Input only
Input only
Input/Output4
Input only
Input only
Input only
9
1
E1
E4
N1
R1
XTAL
Input for oscillator amplifier circuit and internal clock generator
Oscillator amplifier output
JTAG state machine control
JTAG clock
29
30
3
EXTAL
TMS2
TCK2
87 M16
88 L15
123 C10
JCOMP5
JTAG compliance select
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Bidirectional
This pin has medium drive strength. Output drive is open drain and
must be terminated by an external resistor of value 1KOhm.
31
P2
6
Test pin
VPP TEST
Pin for testing purpose only. To be tied to ground in normal
operating mode.
107 D15
1
2
3
4
This pad is configured for Fast (F) pad speed.
This pad contains a weak pull-up.
EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied
at EXTAL as an input. In XOSC Normal Mode, EXTAL is an output
5
6
This pad contains a weak pull-down.
RESET output shall be considered valid only after the 3.3V supply reaches its stable value.
NOTE
None of system pins (except RESET) provides an open drain output.
MPC5643L Microcontroller Data Sheet, Rev. 9
54
Freescale Semiconductor
2.4
Pin muxing
Table 7 defines the pin list and muxing for this device.
Each entry of Table 7 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is
indicated by ALT0.
NOTE
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable
device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable device behavior.
Table 7. Pin muxing
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
Port A
A[0]
A[1]
PCR[0]
SIUL
GPIO[0]
ETC[0]
ALT0
ALT1
GPIO[0]
ETC[0]
—
—
M
S
73 T14
eTimer_0
PSMI[35];
PADSEL=0
DSPI_2
SCK
ALT2
SCK
PSMI[1];
PADSEL=0
SIUL
SIUL
—
—
EIRQ[0]
GPIO[1]
ETC[1]
—
—
PCR[1]
GPIO[1]
ETC[1]
ALT0
ALT1
—
M
S
74 R14
eTimer_0
PSMI[36];
PADSEL=0
DSPI_2
SIUL
SOUT
—
ALT2
—
—
—
—
EIRQ[1]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
A[2]
A[3]
A[4]
PCR[2]
SIUL
GPIO[2]
ETC[2]
ALT0
ALT1
GPIO[2]
ETC[2]
—
Pull down
Pull down
Pull down
M
S
84 N16
92 K17
108 C16
eTimer_0
PSMI[37];
PADSEL=0
FlexPWM_0
DSPI_2
A[3]
—
ALT3
—
A[3]
SIN
PSMI[23];
PADSEL=0
PSMI[2];
PADSEL=0
MC_RGM
SIUL
—
—
—
—
ABS[0]
EIRQ[2]
GPIO[3]
ETC[3]
—
—
—
PCR[3]
SIUL
GPIO[3]
ETC[3]
ALT0
ALT1
M
S
eTimer_0
PSMI[38];
PADSEL=0
DSPI_2
CS0
B[3]
ALT2
ALT3
CS0
B[3]
PSMI[3];
PADSEL=0
FlexPWM_0
PSMI[27];
PADSEL=0
MC_RGM
SIUL
—
—
—
—
ABS[2]
EIRQ[3]
GPIO[4]
ETC[0]
—
—
—
PCR[4]
SIUL
GPIO[4]
ETC[0]
ALT0
ALT1
M
S
eTimer_1
PSMI[9];
PADSEL=0
DSPI_2
CS1
ALT2
ALT3
—
—
eTimer_0
ETC[4]
ETC[4]
PSMI[7];
PADSEL=0
MC_RGM
SIUL
—
—
—
—
FAB
—
—
EIRQ[4]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
A[5]
PCR[5]
SIUL
GPIO[5]
CS0
ALT0
ALT1
ALT2
GPIO[5]
CS0
—
—
—
M
S
14
H4
DSPI_1
eTimer_1
ETC[5]
ETC[5]
PSMI[14];
PADSEL=0
DSPI_0
SIUL
CS7
—
ALT3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EIRQ[5]
GPIO[6]
SCK
A[6]
A[7]
A[8]
A[9]
PCR[6]
PCR[7]
PCR[8]
PCR[9]
SIUL
GPIO[6]
SCK
—
ALT0
ALT1
—
—
—
—
—
M
M
M
M
S
S
S
S
2
G4
F3
F4
DSPI_1
SIUL
EIRQ[6]
GPIO[7]
—
SIUL
GPIO[7]
SOUT
—
ALT0
ALT1
—
10
12
DSPI_1
SIUL
EIRQ[7]
GPIO[8]
SIN
SIUL
GPIO[8]
—
ALT0
—
DSPI_1
SIUL
—
—
EIRQ[8]
GPIO[9]
—
SIUL
GPIO[9]
CS1
ALT0
ALT1
ALT3
134 B6
DSPI_2
FlexPWM_0
B[3]
B[3]
PSMI[27];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=0
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
A[10]
A[11]
A[12]
PCR[10]
SIUL
GPIO[10]
CS0
ALT0
ALT1
GPIO[10]
CS0
—
—
—
—
M
S
118 A13
120 D11
122 A10
DSPI_2
PSMI[3];
PADSEL=1
FlexPWM_0
FlexPWM_0
B[0]
X[2]
ALT2
ALT3
B[0]
X[2]
PSMI[24];
PADSEL=0
PSMI[29];
PADSEL=0
SIUL
SIUL
—
—
EIRQ[9]
GPIO[11]
SCK
—
—
PCR[11]
GPIO[11]
SCK
ALT0
ALT1
M
S
DSPI_2
PSMI[1];
PADSEL=1
FlexPWM_0
FlexPWM_0
A[0]
A[2]
ALT2
ALT3
A[0]
A[2]
PSMI[20];
PADSEL=0
PSMI[22];
PADSEL=0
SIUL
SIUL
—
GPIO[12]
SOUT
A[2]
—
EIRQ[10]
GPIO[12]
—
—
—
—
PCR[12]
ALT0
ALT1
ALT2
M
S
DSPI_2
FlexPWM_0
A[2]
PSMI[22];
PADSEL=1
FlexPWM_0
SIUL
B[2]
—
ALT3
—
B[2]
PSMI[26];
PADSEL=0
EIRQ[11]
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
A[13]
PCR[13]
SIUL
GPIO[13]
B[2]
ALT0
ALT2
GPIO[13]
B[2]
—
—
M
S
136 C6
FlexPWM_0
PSMI[26];
PADSEL=1
DSPI_2
—
—
—
—
SIN
PSMI[2];
PADSEL=1
FlexPWM_0
FAULT[0]
PSMI[16];
PADSEL=1
SIUL
SIUL
—
—
EIRQ[12]
GPIO[14]
—
—
—
—
A[14]
A[15]
PCR[14]
PCR[15]
GPIO[14]
TXD
ALT0
ALT1
ALT2
—
—
M
M
S
S
143 B4
FlexCAN_1
eTimer_1
ETC[4]
ETC[4]
PSMI[13];
PADSEL=0
SIUL
SIUL
—
—
EIRQ[13]
GPIO[15]
ETC[5]
—
—
GPIO[15]
ETC[5]
ALT0
ALT2
144 D3
eTimer_1
PSMI[14];
PADSEL=1
FlexCAN_1
FlexCAN_0
SIUL
—
—
—
—
—
—
RXD
RXD
PSMI[34];
PADSEL=0
PSMI[33];
PADSEL=0
EIRQ[14]
Port B
—
B[0]
PCR[16]
SIUL
GPIO[16]
TXD
ALT0
ALT1
ALT2
GPIO[16]
—
—
—
—
M
S
109 B15
FlexCAN_0
eTimer_1
ETC[2]
ETC[2]
PSMI[11];
PADSEL=0
SSCM
SIUL
DEBUG[0]
—
ALT3
—
—
—
—
EIRQ[15]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
B[1]
PCR[17]
SIUL
GPIO[17]
ETC[3]
ALT0
ALT2
GPIO[17]
ETC[3]
—
—
M
S
110 C14
eTimer_1
PSMI[12];
PADSEL=0
SSCM
DEBUG[1]
—
ALT3
—
—
—
FlexCAN_0
RXD
PSMI[33];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=1
SIUL
SIUL
—
GPIO[18]
TXD
—
EIRQ[16]
GPIO[18]
—
—
—
—
—
—
—
—
B[2]
B[3]
PCR[18]
PCR[19]
ALT0
ALT1
ALT3
—
—
—
M
M
S
S
114 A14
LINFlexD_0
SSCM
DEBUG[2]
—
—
SIUL
EIRQ[17]
GPIO[19]
—
SIUL
GPIO[19]
DEBUG[3]
—
ALT0
ALT3
—
116 B13
SSCM
LINFlexD_0
RXD
PSMI[31];
PADSEL=0
B[4]2
B[5]
B[6]
PCR[20]
PCR[21]
PCR[22]
SIUL
JTAGC
SIUL
GPIO[20]
TDO
ALT0
ALT1
ALT0
—
GPIO[20]
—
—
—
—
—
—
—
—
—
—
Pull up
—
F
M
F
S
S
S
89
L17
GPIO[21]
—
GPIO[21]
TDI
86 M15
138 B3
JTAGC
SIUL
GPIO[22]
clk_out
CS2
ALT0
ALT1
ALT2
GPIO[22]
—
MC_CGM
DSPI_2
SIUL
—
—
EIRQ[18]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
B[7]
PCR[23]
SIUL
—
—
ALT0
—
GPI[23]
RXD
—
—
—
—
43
R5
LINFlexD_0
PSMI[31];
PADSEL=1
ADC_0
SIUL
—
—
—
—
ALT0
—
AN[0]3
GPI[24]
ETC[5]
—
—
B[8]
PCR[24]
—
—
—
47
P7
eTimer_0
PSMI[8];
PADSEL=2
ADC_0
SIUL
—
—
—
—
ALT0
—
AN[1]3
GPI[25]
AN[11]3
—
—
—
B[9]
PCR[25]
PCR[26]
PCR[27]
PCR[28]
PCR[29]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
52
53
54
55
U7
R8
T8
U8
ADC_0
ADC_1
B[10]
B[11]
B[12]
B[13]
SIUL
—
—
ALT0
—
GPI[26]
AN[12]3
—
—
ADC_0
ADC_1
SIUL
—
—
ALT0
—
GPI[27]
AN[13]3
—
—
ADC_0
ADC_1
SIUL
—
—
ALT0
—
GPI[28]
AN[14]3
—
—
ADC_0
ADC_1
SIUL
—
—
ALT0
—
GPI[29]
RXD
—
60 R10
LINFlexD_1
PSMI[32];
PADSEL=0
ADC_1
—
—
AN[0]3
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
B[14]
PCR[30]
SIUL
—
—
ALT0
—
GPI[30]
ETC[4]
—
—
—
—
64
P11
eTimer_0
PSMI[7];
PADSEL=2
SIUL
ADC_1
SIUL
—
—
—
—
—
—
—
EIRQ[19]
AN[1]3
GPI[31]
EIRQ[20]
AN[2]3
Port C
—
—
—
—
—
B[15]
PCR[31]
ALT0
—
—
—
—
62 R11
SIUL
ADC_1
—
C[0]
C[1]
C[2]
C[4]
PCR[32]
PCR[33]
PCR[34]
PCR[36]
SIUL
ADC_1
SIUL
—
—
ALT0
—
GPI[32]
AN[3]3
GPI[33]
AN[2]3
GPI[34]
AN[3]3
GPIO[36]
CS0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
M
—
—
—
S
66 R12
—
ALT0
—
41
45
11
T4
U5
H3
ADC_0
SIUL
—
—
ALT0
—
ADC_0
SIUL
—
GPIO[36]
CS0
X[1]
ALT0
ALT1
ALT2
DSPI_0
FlexPWM_0
X[1]
PSMI[28];
PADSEL=0
SSCM
SIUL
DEBUG[4]
—
ALT3
—
—
—
—
EIRQ[22]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
C[5]
PCR[37]
SIUL
DSPI_0
GPIO[37]
SCK
ALT0
ALT1
ALT3
—
GPIO[37]
SCK
—
—
—
—
M
S
13
G3
SSCM
DEBUG[5]
—
—
FlexPWM_0
FAULT[3]
PSMI[19];
PADSEL=0
SIUL
SIUL
—
GPIO[38]
SOUT
B[1]
—
EIRQ[23]
GPIO[38]
—
—
—
—
C[6]
PCR[38]
ALT0
ALT1
ALT2
—
M
S
142 D4
DSPI_0
FlexPWM_0
B[1]
PSMI[25];
PADSEL=0
SSCM
SIUL
DEBUG[6]
—
ALT3
—
—
—
—
—
EIRQ[24]
GPIO[39]
A[1]
C[7]
PCR[39]
PCR[42]
SIUL
GPIO[39]
A[1]
ALT0
ALT2
—
—
M
M
S
S
15
K4
FlexPWM_0
PSMI[21];
PADSEL=0
SSCM
DSPI_0
SIUL
DEBUG[7]
—
ALT3
—
—
SIN
—
—
—
—
C[10]
GPIO[42]
CS2
ALT0
ALT1
ALT3
GPIO[42]
—
111 A15
DSPI_2
FlexPWM_0
A[3]
A[3]
PSMI[23];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=0
C[11]
PCR[43]
SIUL
GPIO[43]
ETC[4]
ALT0
ALT1
GPIO[43]
ETC[4]
—
—
M
S
80 M14
eTimer_0
PSMI[7];
PADSEL=1
DSPI_2
CS2
ALT2
—
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
C[12]
PCR[44]
SIUL
GPIO[44]
ETC[5]
ALT0
ALT1
GPIO[44]
ETC[5]
—
—
M
S
82 N15
eTimer_0
PSMI[8];
PADSEL=0
DSPI_2
SIUL
CS3
ALT2
ALT0
ALT1
—
—
—
C[13]
PCR[45]
GPIO[45]
ETC[1]
GPIO[45]
ETC[1]
—
M
S
101 F15
eTimer_1
PSMI[10];
PADSEL=0
CTU_0
—
—
—
—
EXT_IN
PSMI[0];
PADSEL=0
FlexPWM_0
EXT_SYNC
PSMI[15];
PADSEL=0
C[14]
C[15]
PCR[46]
PCR[47]
SIUL
GPIO[46]
ETC[2]
ALT0
ALT1
GPIO[46]
ETC[2]
—
—
—
M
S
S
103 E15
eTimer_1
PSMI[11];
PADSEL=1
CTU_0
SIUL
EXT_TGR
GPIO[47]
CA_TR_EN
ETC[0]
ALT2
ALT0
ALT1
ALT2
—
GPIO[47]
—
—
—
—
SYM
124 A8
FlexRay
eTimer_1
ETC[0]
PSMI[9];
PADSEL=1
FlexPWM_0
CTU_0
A[1]
—
ALT3
—
A[1]
PSMI[21];
PADSEL=1
EXT_IN
PSMI[0];
PADSEL=1
FlexPWM_0
—
—
EXT_SYNC
PSMI[15];
PADSEL=1
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
Port D
GPIO[48]
—
D[0]
PCR[48]
SIUL
GPIO[48]
CA_TX
ETC[1]
ALT0
ALT1
ALT2
—
—
—
SYM
S
125 B8
FlexRay
eTimer_1
ETC[1]
PSMI[10];
PADSEL=1
FlexPWM_0
B[1]
ALT3
B[1]
PSMI[25];
PADSEL=1
D[1]
D[2]
PCR[49]
PCR[50]
SIUL
GPIO[49]
ETC[2]
ALT0
ALT2
GPIO[49]
ETC[2]
—
—
—
M
M
S
S
3
E3
eTimer_1
PSMI[11];
PADSEL=2
CTU_0
FlexRay
SIUL
EXT_TGR
—
ALT3
—
—
—
—
—
CA_RX
GPIO[50]
ETC[3]
GPIO[50]
ETC[3]
ALT0
ALT2
140 C5
eTimer_1
PSMI[12];
PADSEL=1
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=0
FlexRay
SIUL
—
—
CB_RX
GPIO[51]
—
—
—
—
D[3]
PCR[51]
GPIO[51]
CB_TX
ETC[4]
ALT0
ALT1
ALT2
—
SYM
S
128 A7
FlexRay
eTimer_1
ETC[4]
PSMI[13];
PADSEL=1
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=2
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
D[4]
PCR[52]
SIUL
GPIO[52]
CB_TR_EN
ETC[5]
ALT0
ALT1
ALT2
GPIO[52]
—
—
—
—
SYM
S
129 B7
FlexRay
eTimer_1
ETC[5]
PSMI[14];
PADSEL=2
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=2
D[5]
D[6]
PCR[53]
PCR[54]
SIUL
GPIO[53]
CS3
ALT0
ALT1
—
GPIO[53]
—
—
—
—
—
M
M
S
S
33
34
N3
P3
DSPI_0
FlexPWM_0
—
FAULT[2]
PSMI[18];
PADSEL=0
SIUL
GPIO[54]
CS2
ALT0
ALT1
ALT3
GPIO[54]
—
—
—
DSPI_0
FlexPWM_0
X[3]
X[3]
PSMI[30];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=1
D[7]
D[8]
PCR[55]
PCR[56]
SIUL
DSPI_1
DSPI_0
SWG
GPIO[55]
CS3
ALT0
ALT1
ALT3
—
GPIO[55]
—
—
—
—
—
—
—
—
—
M
M
S
S
37
32
R4
M3
CS4
—
analog output
GPIO[56]
CS2
—
SIUL
ALT0
ALT1
ALT2
GPIO[56]
—
DSPI_1
eTimer_1
ETC[4]
ETC[4]
PSMI[13];
PADSEL=2
DSPI_0
CS5
—
ALT3
—
—
—
FlexPWM_0
FAULT[3]
PSMI[19];
PADSEL=1
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
D[9]
PCR[57]
SIUL
GPIO[57]
X[0]
ALT0
ALT1
ALT2
ALT0
ALT1
GPIO[57]
X[0]
—
—
—
—
—
M
S
26
L3
FlexPWM_0
LINFlexD_1
SIUL
TXD
—
D[10]
PCR[58]
PCR[59]
PCR[60]
PCR[62]
GPIO[58]
A[0]
GPIO[58]
A[0]
—
M
M
M
M
S
S
S
S
76 T15
78 R16
99 G14
105 D16
FlexPWM_0
PSMI[20];
PADSEL=1
eTimer_0
—
—
ETC[0]
PSMI[35];
PADSEL=1
D[11]
D[12]
D[14]
SIUL
GPIO[59]
B[0]
ALT0
ALT1
GPIO[59]
B[0]
—
—
—
—
FlexPWM_0
PSMI[24];
PADSEL=1
eTimer_0
—
—
ETC[1]
PSMI[36];
PADSEL=1
SIUL
GPIO[60]
X[1]
ALT0
ALT1
GPIO[60]
X[1]
FlexPWM_0
PSMI[28];
PADSEL=1
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=1
SIUL
GPIO[62]
B[1]
ALT0
ALT1
GPIO[62]
B[1]
—
FlexPWM_0
PSMI[25];
PADSEL=2
eTimer_0
—
—
ETC[3]
PSMI[38];
PADSEL=1
Port E
E[0]
E[2]
PCR[64]
PCR[66]
SIUL
ADC_1
SIUL
—
—
—
—
ALT0
—
GPI[64]
AN[5]3
GPI[66]
AN[5]3
—
—
—
—
—
—
—
—
—
—
68 T13
ALT0
—
49
U6
ADC_0
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
E[4]
E[5]
PCR[68]
PCR[69]
PCR[70]
PCR[71]
PCR[73]
PCR[74]
PCR[75]
PCR[76]
PCR[77]
SIUL
ADC_0
SIUL
—
—
ALT0
—
GPI[68]
AN[7]3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
42
44
46
48
U4
T5
R6
T6
—
ALT0
—
GPI[69]
AN[8]3
—
—
—
—
—
—
—
M
—
—
—
—
—
—
—
S
ADC_0
SIUL
—
E[6]
—
ALT0
—
GPI[70]
AN[4]3
ADC_0
SIUL
—
E[7]
—
ALT0
—
GPI[71]
AN[6]3
ADC_0
SIUL
—
E[9]
—
ALT0
—
GPI[73]
AN[7]3
61 T10
ADC_1
SIUL
—
E[10]
E[11]
E[12]
E[13]
—
ALT0
—
GPI[74]
AN[8]3
63
T11
ADC_1
SIUL
—
—
ALT0
—
GPI[75]
AN[4]3
65 U11
67 T12
117 D12
ADC_1
SIUL
—
—
ALT0
—
GPI[76]
AN[6]3
ADC_1
SIUL
—
GPIO[77]
ETC[5]
ALT0
ALT1
GPIO[77]
ETC[5]
eTimer_0
PSMI[8];
PADSEL=1
DSPI_2
SIUL
CS3
—
ALT2
—
—
—
—
—
EIRQ[25]
GPIO[78]
ETC[5]
E[14]
PCR[78]
SIUL
GPIO[78]
ETC[5]
ALT0
ALT1
—
M
S
119 B12
eTimer_1
PSMI[14];
PADSEL=3
SIUL
—
—
EIRQ[26]
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
E[15]
PCR[79]
SIUL
DSPI_0
SIUL
GPIO[79]
CS1
ALT0
ALT1
—
GPIO[79]
—
—
—
—
—
M
S
121 B11
—
EIRQ[27]
Port F
F[0]
PCR[80]
SIUL
GPIO[80]
A[1]
ALT0
ALT1
GPIO[80]
A[1]
—
—
M
S
133 D7
FlexPWM_0
PSMI[21];
PADSEL=2
eTimer_0
—
—
ETC[2]
PSMI[37];
PADSEL=1
SIUL
SIUL
DSPI_0
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
—
—
EIRQ[28]
GPIO[83]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F[3]
F[4]
F[5]
F[6]
F[7]
F[8]
F[9]
F[10]
PCR[83]
PCR[84]
PCR[85]
PCR[86]
PCR[87]
PCR[88]
PCR[89]
PCR[90]
GPIO[83]
CS6
ALT0
ALT1
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
—
—
—
—
—
—
—
—
M
F
F
F
F
F
F
F
S
S
S
S
S
S
S
S
139 B5
GPIO[84]
MDO[3]
GPIO[85]
MDO[2]
GPIO[86]
MDO[1]
GPIO[87]
MCKO
GPIO[84]
—
4
5
D2
D1
E2
J1
GPIO[85]
—
GPIO[86]
—
8
GPIO[87]
—
19
20
23
24
GPIO[88]
MSEO[1]
GPIO[89]
MSEO[0]
GPIO[90]
EVTO
GPIO[88]
—
K2
K1
L1
GPIO[89]
—
GPIO[90]
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
F[11]
F[12]
PCR[91]
PCR[92]
SIUL
NPC
GPIO[91]
—
ALT0
ALT2
ALT0
ALT1
GPIO[91]
EVTI
—
—
—
—
—
M
S
25
L2
SIUL
GPIO[92]
ETC[3]
GPIO[92]
ETC[3]
M
M
S
S
106 C17
112 B14
eTimer_1
PSMI[12];
PADSEL=2
SIUL
SIUL
—
—
EIRQ[30]
GPIO[93]
ETC[4]
—
—
F[13]
PCR[93]
GPIO[93]
ETC[4]
ALT0
ALT1
—
eTimer_1
PSMI[13];
PADSEL=3
SIUL
SIUL
—
GPIO[94]
TXD
—
EIRQ[31]
GPIO[94]
—
—
—
—
—
F[14]
F[15]
PCR[94]
PCR[95]
ALT0
ALT1
ALT0
—
—
—
M
M
S
S
115 C13
113 D13
LINFlexD_1
SIUL
GPIO[95]
—
GPIO[95]
RXD
LINFlexD_1
PSMI[32];
PADSEL=2
FCCU
F[0]
FCCU_
F[0]
—
—
FCCU
FCCU
F[0]
F[1]
ALT0
ALT0
—
—
—
—
S
S
S
S
38
R2
FCCU_
F[1]
F[1]
141 C4
102 E16
Port G
GPIO[98]
X[2]
G[2]
PCR[98]
SIUL
GPIO[98]
X[2]
ALT0
ALT1
—
—
M
S
FlexPWM_0
PSMI[29];
PADSEL=1
DSPI_1
CS1
ALT2
—
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
G[3]
G[4]
G[5]
PCR[99]
SIUL
GPIO[99]
A[2]
ALT0
ALT1
GPIO[99]
A[2]
—
—
—
—
M
S
104 D17
100 F17
85 N17
FlexPWM_0
PSMI[22];
PADSEL=2
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=3
PCR[100]
PCR[101]
SIUL
GPIO[100]
B[2]
ALT0
ALT1
GPIO[100]
B[2]
—
M
M
S
S
FlexPWM_0
PSMI[26];
PADSEL=2
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=3
SIUL
GPIO[101]
X[3]
ALT0
ALT1
GPIO[101]
X[3]
—
FlexPWM_0
PSMI[30];
PADSEL=2
DSPI_2
SIUL
CS3
GPIO[102]
A[3]
ALT2
ALT0
ALT1
—
GPIO[102]
A[3]
—
—
G[6]
G[7]
G[8]
PCR[102]
PCR[103]
PCR[104]
—
—
—
M
M
M
S
S
S
98 G17
83 P17
81 P16
FlexPWM_0
PSMI[23];
PADSEL=3
SIUL
GPIO[103]
B[3]
ALT0
ALT1
GPIO[103]
B[3]
FlexPWM_0
PSMI[27];
PADSEL=3
SIUL
FlexRay
GPIO[104]
DBG0
CS1
ALT0
ALT1
ALT2
—
GPIO[104]
—
—
—
—
DSPI_0
—
FlexPWM_0
—
FAULT[0]
PSMI[16];
PADSEL=2
SIUL
—
—
EIRQ[21]
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
G[9]
PCR[105]
SIUL
FlexRay
GPIO[105]
DBG1
CS1
ALT0
ALT1
ALT2
—
GPIO[105]
—
—
—
—
—
M
S
79 R17
DSPI_1
—
FlexPWM_0
—
FAULT[1]
PSMI[17];
PADSEL=2
SIUL
SIUL
—
GPIO[106]
DBG2
CS3
—
EIRQ[29]
GPIO[106]
—
—
—
—
—
G[10] PCR[106]
ALT0
ALT1
ALT2
—
—
—
M
M
S
S
77 P15
FlexRay
DSPI_2
FlexPWM_0
—
—
FAULT[2]
PSMI[18];
PADSEL=1
G[11] PCR[107]
SIUL
GPIO[107]
DBG3
—
ALT0
ALT1
—
GPIO[107]
—
—
—
75 U15
FlexRay
FlexPWM_0
FAULT[3]
PSMI[19];
PADSEL=2
G[12] PCR[108]
G[13] PCR[109]
G[14] PCR[110]
G[15] PCR[111]
SIUL
NPC
SIUL
NPC
SIUL
NPC
SIUL
NPC
GPIO[108]
MDO[11]
GPIO[109]
MDO[10]
GPIO[110]
MDO[9]
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
GPIO[108]
—
—
—
—
—
—
—
—
—
—
—
—
—
F
F
F
F
S
S
S
S
—
—
—
—
F2
H1
A6
J2
GPIO[109]
—
GPIO[110]
—
GPIO[111]
MDO[8]
GPIO[111]
—
Port H
GPIO[112]
—
H[0]
PCR[112]
SIUL
NPC
GPIO[112]
MDO[7]
ALT0
ALT2
—
—
—
F
S
—
A5
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
H[1]
H[2]
H[3]
H[4]
PCR[113]
PCR[114]
PCR[115]
PCR[116]
SIUL
NPC
GPIO[113]
MDO[6]
GPIO[114]
MDO[5]
GPIO[115]
MDO[4]
GPIO[116]
X[0]
ALT0
ALT2
ALT0
ALT2
ALT0
ALT2
ALT0
ALT1
ALT2
GPIO[113]
—
—
—
—
—
—
—
—
—
—
—
—
—
F
S
—
—
—
—
F1
SIUL
GPIO[114]
—
F
F
S
S
S
A4
NPC
SIUL
GPIO[115]
—
G1
L16
NPC
SIUL
GPIO[116]
X[0]
M
FlexPWM_1
eTimer_2
ETC[0]
ETC[0]
PSMI[39];
PADSEL=0
H[5]
H[6]
H[7]
PCR[117]
PCR[118]
PCR[119]
SIUL
FlexPWM_1
DSPI_0
GPIO[117]
A[0]
ALT0
ALT1
ALT3
ALT0
ALT1
ALT3
ALT0
ALT1
ALT2
GPIO[117]
A[0]
—
—
—
—
—
—
—
—
—
—
—
M
M
M
S
S
S
—
—
—
M17
H17
K16
CS4
—
SIUL
GPIO[118]
B[0]
GPIO[118]
B[0]
FlexPWM_1
DSPI_0
CS5
—
SIUL
GPIO[119]
X[1]
GPIO[119]
X[1]
FlexPWM_1
eTimer_2
ETC[1]
ETC[1]
PSMI[40];
PADSEL=0
H[8]
H[9]
PCR[120]
PCR[121]
SIUL
FlexPWM_1
DSPI_0
GPIO[120]
A[1]
ALT0
ALT1
ALT3
ALT0
ALT1
ALT3
GPIO[120]
A[1]
—
—
—
—
—
—
—
—
M
M
S
S
—
—
K15
G16
CS6
—
SIUL
GPIO[121]
B[1]
GPIO[121]
B[1]
FlexPWM_1
DSPI_0
CS7
—
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
H[10] PCR[122]
SIUL
FlexPWM_1
eTimer_2
SIUL
GPIO[122]
X[2]
ALT0
ALT1
ALT2
ALT0
ALT1
ALT0
ALT1
ALT0
ALT1
ALT2
GPIO[122]
X[2]
—
—
—
—
—
—
—
—
—
—
M
S
—
A11
ETC[2]
GPIO[123]
A[2]
ETC[2]
GPIO[123]
A[2]
H[11] PCR[123]
H[12] PCR[124]
H[13] PCR[125]
—
—
—
M
M
M
S
S
S
—
—
—
C11
B10
G15
FlexPWM_1
SIUL
GPIO[124]
B[2]
GPIO[124]
B[2]
FlexPWM_1
SIUL
GPIO[125]
X[3]
GPIO[125]
X[3]
FlexPWM_1
eTimer_2
ETC[3]
ETC[3]
PSMI[42];
PADSEL=0
H[14] PCR[126]
H[15] PCR[127]
SIUL
GPIO[126]
A[3]
ALT0
ALT1
ALT2
ALT0
ALT1
ALT2
GPIO[126]
A[3]
—
—
—
—
—
—
—
—
M
M
S
S
—
—
A12
J17
FlexPWM_1
eTimer_2
SIUL
ETC[4]
GPIO[127]
B[3]
ETC[4]
GPIO[127]
B[3]
FlexPWM_1
eTimer_2
ETC[5]
ETC[5]
Port I
I[0]
PCR[128]
SIUL
GPIO[128]
ETC[0]
ALT0
ALT1
GPIO[128]
ETC[0]
—
—
M
S
—
C9
eTimer_2
PSMI[39];
PADSEL=1
DSPI_0
CS4
—
ALT2
—
—
—
—
FlexPWM_1
FAULT[0]
Table 7. Pin muxing (continued)
Pad speed1
SRC SRC
Pin #
Alternate
output
function
Weak pull
config during
reset
Port
name
Output
mux sel
Input
functions
Input mux
select
PCR
Peripheral
144 257
pkg pkg
= 1
= 0
I[1]
I[2]
I[3]
PCR[129]
SIUL
GPIO[129]
ETC[1]
ALT0
ALT1
GPIO[129]
ETC[1]
—
—
—
—
M
S
—
—
—
C12
F16
E17
eTimer_2
PSMI[40];
PADSEL=1
DSPI_0
FlexPWM_1
SIUL
CS5
—
ALT2
—
—
—
—
—
FAULT[1]
GPIO[130]
ETC[2]
PCR[130]
PCR[131]
GPIO[130]
ETC[2]
ALT0
ALT1
M
M
S
S
eTimer_2
PSMI[41];
PADSEL=1
DSPI_0
FlexPWM_1
SIUL
CS6
—
ALT2
—
—
—
—
—
FAULT[2]
GPIO[131]
ETC[3]
GPIO[131]
ETC[3]
ALT0
ALT1
eTimer_2
PSMI[42];
PADSEL=1
DSPI_0
CTU_0
FlexPWM_1
SIUL
CS7
EXT_TGR
—
ALT2
ALT3
—
—
—
—
—
—
—
—
FAULT[3]
GPIO[132]
—
RDY
PCR[132]
GPIO[132]
RDY
ALT0
ALT2
—
F
S
—
K3
NPC
1
Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM =
Symmetric (for FlexRay)
2
3
The default function of this pin out of reset is ALT1 (TDO).
Analog
NOTE
Open Drain can be configured by the PCRn for all pins used as output (except FCCU_F[0] and FCCU_F[1] ).
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs,
design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the
product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”,
“C”, “T”, or “D”.
•
•
•
“SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An
example is the input voltage of a voltage regulator.
“CC” identifies controller characteristics—indicating the characteristics and timing of the signals that the chip
provides.
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define normal device operation.
They specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant
sample size across process variations.
— T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical
conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category.
— D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
1
Table 8. Absolute maximum ratings
Symbol
Parameter
Conditions
Min
Max
Unit
VDD_HV_REG SR 3.3 V voltage regulator supply voltage
—
—
—
—
—
—
–0.3
–0.3
–0.1
–0.3
–0.1
–0.3
3.632, 3
3.632, 3
0.1
V
V
V
V
V
V
VDD_HV_IOx
VSS_HV_IOx
SR 3.3 V input/output supply voltage
SR Input/output ground voltage
VDD_HV_FLA SR 3.3 V flash supply voltage
VSS_HV_FLA SR Flash memory ground
3.632, 3
0.1
VDD_HV_OSC SR 3.3 V crystal oscillator amplifier supply
voltage
3.632, 3
VSS_HV_OSC SR 3.3 V crystal oscillator amplifier reference
voltage
—
—
—
–0.1
–0.3
–0.1
0.1
6.0
0.1
V
V
V
3,4
VDD_HV_ADR0
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
VDD_HV_ADR1
VSS_HV_ADR0 SR ADC_0 ground and low reference voltage
VSS_HV_ADR1 ADC_1 ground and low reference voltage
VDD_HV_ADV SR 3.3 V ADC supply voltage
VSS_HV_ADV SR 3.3 V ADC supply ground
—
—
–0.3
–0.1
3.632, 3
0.1
V
V
MPC5643L Microcontroller Data Sheet, Rev. 9
76
Freescale Semiconductor
Electrical characteristics
1
Table 8. Absolute maximum ratings (continued)
Symbol
TVDD
Parameter
SR Supply ramp rate
Conditions
Min
Max
Unit
—
0.5 V/s
V/s
3.0 × 10-6
(3.0 V/sec)
VIN
SR Voltage on any pin with respect to ground
(VSS_HV_IOx
—
Relative to VDD
—
–0.3
–0.3
–10
6.05
VDD + 0.35,6
10
V
)
IINJPAD
IINJSUM
TSTG
SR Injected input current on any pin during
overload condition
mA
mA
°C
SR Absolute sum of all injected input currents
during overload condition
—
—
–50
–55
50
SR Storage temperature
150
1
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
3
4
5
5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
6.4 V for 10 hours cumulative time, 6.0 V for time remaining.
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met and VDDE is within the operating voltage specifications.
6
Only when VDD < 5.2 V.
3.3
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Min1
Max
Unit
VDD_HV_REG
VDD_HV_IOx
VSS_HV_IOx
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_OSC
VSS_HV_OSC
SR 3.3 V voltage regulator supply voltage
SR 3.3 V input/output supply voltage
SR Input/output ground voltage
—
—
—
—
—
—
—
—
3.0
3.0
0
3.63
3.63
0
V
V
V
V
V
V
V
V
SR 3.3 V flash supply voltage
3.0
0
3.63
0
SR Flash memory ground
SR 3.3 V crystal oscillator amplifier supply voltage
SR 3.3 V crystal oscillator amplifier reference voltage
3.0
0
3.63
0
2 3
VDD_HV_ADR0
,
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
4.5 to 5.5 or
3.0 to 3.63
VDD_HV_ADR1
VDD_HV_ADV
VSS_HV_AD0
SR 3.3 V ADC supply voltage
—
—
3.0
3.63
0
V
V
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
0
VSS_HV_AD1
VSS_HV_ADV
SR 3.3 V ADC supply ground
—
—
—
—
0
—
0
0
—
0
V
V
V
V
4
VDD_LV_REGCOR SR Internal supply voltage
5
VSS_LV_REGCOR SR Internal reference voltage
2
VDD_LV_CORx
SR Internal supply voltage
—
—
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
77
Electrical characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
SR Internal reference voltage
Conditions
Min1
Max
Unit
3
VSS_LV_CORx
—
—
—
0
—
0
—
V
V
2
VDD_LV_PLL
SR Internal supply voltage
3
VSS_LV_PLL
SR Internal reference voltage
SR Ambient temperature under bias
SR Junction temperature under bias
0
0
V
TA
TJ
f
120 MHz
—
–40
–40
125
150
°C
°C
CPU
1
2
3
4
5
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same
voltage source.
VDD_HV_ADRx must always be applied and should be stable before LBIST starts. If this supply is not above its
absolute minimum level, LBIST operations can fail.
Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced
by an on-chip voltage regulator.
For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one
is used.
3.4
Thermal characteristics
1
Table 10. Thermal characteristics for 100 LQFP package
Symbol
Parameter
Conditions
Value Unit
RJA
D
Thermal resistance, junction-to-ambient natural Single layer board – 1s
46 °C/W
34
convection2
Four layer board – 2s2p
RJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
36 °C/W
28
convection at 200 ft/min
Four layer board – 2s2p
RJB
RJC
JT
D
D
D
Thermal resistance junction-to-board3
Thermal resistance junction-to-case4
Junction-to-package-top natural convection5
—
—
—
19 °C/W
8
2
°C/W
°C/W
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2
3
4
5
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5643L Microcontroller Data Sheet, Rev. 9
78
Freescale Semiconductor
Electrical characteristics
Value Unit
1
Table 11. Thermal characteristics for 144 LQFP package
Symbol
Parameter Conditions
RJA
D
Thermal resistance, junction-to-ambient natural Single layer board – 1s
44 °C/W
36
convection2
Four layer board – 2s2p
RJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
35 °C/W
30
convection at 200 ft/min
Four layer board – 2s2p
RJB
RJC
JT
D
D
D
Thermal resistance junction-to-board3
Thermal resistance junction-to-case4
Junction-to-package-top natural convection5
—
—
—
24 °C/W
8
2
°C/W
°C/W
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2
3
4
5
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
1
Table 12. Thermal characteristics for 257 MAPBGA package
Symbol
Parameter
Conditions
Value Unit
RJA
D
Thermal resistance junction-to-ambient natural Single layer board – 1s
46 °C/W
26
convection2
Four layer board – 2s2p
RJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
37 °C/W
22
convection at 200 ft/min
Four layer board – 2s2p
RJB
RJC
JT
D
D
D
Thermal resistance junction-to-board3
Thermal resistance junction-to-case4
Junction-to-package-top natural convection5
—
—
—
13 °C/W
8
2
°C/W
°C/W
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2
3
4
5
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
79
Electrical characteristics
3.4.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from Equation 1:
J
T = T + (R
× P )
Eqn. 1
J
A
JA
D
where:
o
T
= ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
= power dissipation in the package (W)
JA
P
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
R
= R
+ R
CA
Eqn. 2
JA
JC
where:
R
R
R
= junction to ambient thermal resistance (°C/W)
= junction to case thermal resistance (°C/W)
= case to ambient thermal resistance (°C/W)
JA
JC
CA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
JC
ambient thermal resistance, R
. For instance, the user can change the size of the heat sink, the air flow around the device, the
CA
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at
JT
the top center of the package case using Equation 3:
T = T + ( × P )
Eqn. 3
J
T
JT
D
where:
T
= thermocouple temperature on top of the package (°C)
= thermal characterization parameter (°C/W)
= power dissipation in the package (W)
T
JT
P
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
3.4.1.1
References
Semiconductor Equipment and Materials International
3081 Zanker Road
MPC5643L Microcontroller Data Sheet, Rev. 9
80
Freescale Semiconductor
Electrical characteristics
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.5
Electromagnetic Interference (EMI) characteristics
The characteristics in Table 14 were measured using:
•
•
•
Device configuration, tet conditions, and EM testing per standard IEC61967-2
Supply voltage of 3.3 V DC
Ambient temperature of 25 C
The configuration information referenced in Table 14 is explained in Table 13.
Table 13. EMI configuration summary
Configuration name
Description
Configuration A
• High emission = all pads have max slew rate, LVDS pads running at 40 MHz
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• No PLL frequency modulation
• IEC level I ( 36 dBV)
Configuration B
• Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• 2% PLL frequency modulation
• IEC level K( 30 dBV)
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
81
Electrical characteristics
Symbol
Table 14. EMI emission testing specifications
Parameter
Conditions
Min
Typ
Max
Unit
VEME
CC Radiated emissions
Configuration A; frequency range
150 kHz–50 MHz
—
—
—
—
—
—
—
—
16
—
dBV
Configuration A; frequency range
50–150 MHz
16
32
25
15
21
30
24
—
—
—
—
—
—
—
Configuration A; frequency range
150–500 MHz
Configuration A; frequency range
500–1000 MHz
Configuration B; frequency range
50–150 MHz
Configuration B; frequency range
50–150 MHz
Configuration B; frequency range
150–500 MHz
Configuration B; frequency range
500–1000 MHz
EMC testing was performed and documented according to these standards: [IEC61508-2-7.4.5.1.b, IEC61508-2-7.2.3.2.e,
IEC61508-2-Table-A.17 (partially), IEC61508-2-Table-B.5(partially),SRS2110]
EME testing was performed and documented according to these standards: [IEC 61967-2 & -4]
EMS testing was performed and documented according to these standards: [IEC 62132-2 & -4]
Refer MPC5643L for detailed information pertaining to the EMC, EME, and EMS testing and results.
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
1, 2
Table 15. ESD ratings
No.
Symbol
Parameter
Conditions
Class Max value3
Unit
1
VESD(HBM)
SR Electrostatic discharge TA = 25 °C
H1C
M2
2000
200
V
(Human Body Model)
conforming to AEC-Q100-002
2
3
VESD(MM)
SR Electrostatic discharge TA = 25 °C
V
V
(Machine Model)
conforming to AEC-Q100-003
VESD(CDM)
SR Electrostatic discharge TA = 25 °C
C3A
500
(Charged Device Model) conforming to AEC-Q100-011
750 (corners)
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
MPC5643L Microcontroller Data Sheet, Rev. 9
82
Freescale Semiconductor
Electrical characteristics
3
Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 16. Latch-up results
No.
Symbol
LU
Parameter
SR Static latch-up class
Conditions
TA = 125 °C conforming to JESD 78
Class
II level A
1
3.8
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
•
•
•
•
•
•
•
•
•
•
High power regulator HPREG1 (internal ballast to support core current)
High power regulator HPREG2 (external NPN to support core current)
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (V
)
DDIO
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (V
)
DDREG
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (V
)
DDFLASH
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPV
)
DD
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPV
)
DD
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on
board to supply core current. The MPC5643L always powers up using HPREG1 if an external NPN transistor is present. Then
the MPC5643L makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational,
the controller part of HPREG1 is switched off.
The following bipolar transistors are supported:
•
•
BCP68 from ON Semiconductor
BCX68 from Infineon
Table 17. Recommended operating characteristics
Symbol
Parameter
Value
Unit
hFE( )
DC current gain (Beta)
85 - 375
1.5
—
W
PD
Maximum power dissipation @
TA=25°C1
ICMaxDC
VCESAT
Maximum peak collector current
1.0
A
Collector-to-emitter saturation
voltage(Max)
6002
mV
VBE
Base-to-emitter voltage (Max)
1.0
V
1
derating factor 12mW/degC
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
83
Electrical characteristics
2
Adjust resistor at bipolar transistor collector for 3.3V to avoid VCE<VCESAT
The recommended external ballast transistor is the bipolar transistor BCP68 with the gain range of 85 up to 375 (for IC=500mA,
VCE=1V) provided by several suppliers. This includes the gain variations BCP68-10, BCP68-16 and BCP68-25.The most
important parameters for the interoperability with the integrated voltage regulator are the DC current gain (hFE) and the
temperature coefficient of the gain (XTB). While the specified gain range of most BCP68 vendors is the same, there are slight
variations in the temperature coefficient parameter. MPC5643L Voltage regulator operation was simulated against the typical
variation on temperature coefficient and against the specified gain range to have a robust design.
Table 18. Voltage regulator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
C
External decoupling/
stability capacitor
Min, max values shall be
granted with respect to
tolerance, voltage,
temperature, and aging
variations.
12
—
40
µF
ext
SR Combined ESR of
external capacitor
—
1
5
—
—
100
—
m
SR Number of pins for
external decoupling/
stability capacitor
—
—
C
SR Total capacitance on
1.2 V pins
Ceramic capacitors,
taking into account
300
—
900
nF
V1V2
tolerance, aging, voltage
and temperature variation
tSU
—
Start-up time after main
supply stabilization
Cload = 10 µF × 4
—
—
—
—
2.5
ms
V
Main High Voltage Power -
Low Voltage Detection,
upper threshold
—
2.93
—
—
D
D
Main supply low voltage
detector, lower threshold
—
2.6
—
—
—
V
V
Digitalsupplyhighvoltage Before a destructive reset
1.355
1.495
detector upper threshold
initialization phase
completion
After a destructive reset
initialization phase
completion
1.39
1.315
1.35
—
—
—
1.47
1.455
1.38
—
D
Digitalsupplyhighvoltage Before a destructive reset
V
detector lower threshold
initialization phase
completion
After a destructive reset
initialization phase
completion
MPC5643L Microcontroller Data Sheet, Rev. 9
84
Freescale Semiconductor
Electrical characteristics
Table 18. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
D
Digital supply low voltage After a destructive reset
1.080
—
1.140
V
detector lower threshold
initialization phase
completion
—
D
Digital supply low voltage After a destructive reset
1.16
—
1.22
V
detector upper threshold
initialization phase
completion
—
—
—
D
D
D
Digital supply low voltage Before a destructive
detector lower threshold reset initialization phase
1.080
1.160
1.6
—
—
—
1.226
1.306
2.6
V
V
V
Digital supply low voltage Before a destructive
detector upper threshold
reset initialization phase
POR rising/ falling supply
threshold voltage
—
—
—
SR Supply ramp rate
—
3 V/s
1.1
—
—
0.5 V/µs
—
—
µs
D
D
D
LVD_MAIN: Time
constant of RC filter at
LVD input
3.3V noise rejection at the
input of
LVD comparator
—
—
HVD_DIG: Time constant 1.2V noise rejection at the
of RC filter at LVD input
0.1
0.1
—
—
—
—
µs
µs
input of
LVD comparator
LVD_DIG: Time constant
of RC filter at LVD input
1.2V noise rejection at the
input of
LVD comparator
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
85
Electrical characteristics
VDD
BCP68
BCRTL
V1V2 ring on board
Lb
Rb
ESR
Rs
C
v1v2
Cext
Cint
V1V2 pin
MPC5643L
Figure 4. BCP68 board schematic example
NOTE
The minimum value of the ESR is constrained by the resonance caused by the external
components, bonding inductance, and internal decoupling. The minimum ESR is required
to avoid the resonance and make the regulator stable.
3.9
DC electrical characteristics
Table 19 gives the DC electrical characteristics at 3.3 V (3.0 V < V
< 3.6 V).
DD_HV_IOx
1
Table 19. DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIL
D Minimum low level input voltage
P Maximum level input voltage
P Minimum high level input voltage
D Maximum high level input voltage
T Schmitt trigger hysteresis
—
–0.12
—
—
—
—
—
—
—
—
—
0.35 VDD_HV_IOx
—
V
V
V
V
V
V
V
V
—
—
VIH
—
0.65 VDD_HV_IOx
2 3
VIH
—
—
—
0.1 VDD_HV_IOx
—
V
+ 0.1 ,
DD_HV_IOx
VHYS
—
VOL_S
VOH_S
VOL_M
P Slow, low level output voltage
P Slow, high level output voltage
P Medium, low level output voltage
IOL = 1.5 mA
0.5
—
IOH = –1.5 mA VDD_HV_IOx – 0.8
IOL = 2 mA
—
0.5
MPC5643L Microcontroller Data Sheet, Rev. 9
86
Freescale Semiconductor
Electrical characteristics
1
Table 19. DC electrical characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH_M
VOL_F
VOH_F
P Medium, high level output voltage IOH = –2 mA VDD_HV_IOx – 0.8
—
—
—
—
—
0.5
—
V
V
V
V
P Fast, high level output voltage
P Fast, high level output voltage
IOL = 11 mA
IOH = –11 mA VDD_HV_IOx – 0.8
IOL = 1.5 mA
—
VOL_SYM P Symmetric, high level output
voltage
—
0.5
VOH_SYM P Symmetric, high level output
voltage
IOH = –1.5 mA VDD_HV_IOx – 0.8
—
—
—
1
V
IINJ
T DC injection current per pin
(all bi-directional ports)
—
–1
mA
µA
IPU
P Equivalent pull-up current
VIN = VIL
–130
—
—
—
—
—
—
—
–10
—
VIN = VIH
IPD
P Equivalent pull-down current
VIN = VIL
VIN = VIH
10
µA
—
130
1
IIL
P Input leakage current
(all bidirectional ports)
TJ = –40 to
+150 °C
-1
A
Input leakage current
-0.25
-0.3
—
—
0.25
0.3
(all ADC input-only ports)4
Input leakage current
(shared ADC input-only ports)
VILR
VIHR
VHYSR
VOLR
IPD
P RESET, low level input voltage
P RESET, high level input voltage
D RESET, Schmitt trigger hysteresis
D RESET, low level output voltage
—
—
–0.12
—
—
—
—
—
—
0.35 VDD_HV_IOx
V
V
0.65 VDD_HV_IOx
VDD_HV_IOx+0.12
—
0.1 VDD_HV_IOx
—
0.5
—
V
IOL = 2 mA
VIN = VIL
VIN = VIH
—
10
—
V
D RESET, equivalent pull-down
current
µA
130
1
2
3
4
These specifications are design targets and subject to change per device characterization.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 8.
The max input voltage on the ADC pins is the ADC reference voltage VDD_HV_ADRx.
Measured values are applicable to all modes of the pad i.e. IBE = 0/1 and / or APC= 0/1.
3.10 Supply current characteristics
Current consumption data is given in Table 20. These specifications are design targets and are subject to change per device
characterization.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
87
Electrical characteristics
Symbol
Table 20. Current consumption characteristics
Parameter
Conditions1
Min
Typ
Max
Unit
IDD_LV_FULL
+ IDD_LV_PLL
T Operating current
T Operating current
T Operating current
1.2 V supplies
—
—
50 mA+
2.18 mA*fCPU[MHz]
mA
TJ = 25 C
DD_LV_COR = 1.32 V
V
1.2 V supplies
TJ = 150 C
—
—
—
—
—
—
—
—
80 mA+
2.50 mA*fCPU[MHz]
VDD_LV_COR = 1.32 V
IDD_LV_TYP
+ IDD_LV_PLL
1.2 V supplies
TJ = 25 C
26 +
mA
mA
2
2.10 mA*fCPU[MHz]
VDD_LV_COR = 1.32 V
1.2 V supplies
TJ = 150 C
41 mA+
2.30 mA*fCPU[MHz]
VDD_LV_COR = 1.32 V
IDD_LV_BIST
+ IDD_LV_PLL
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ = 25 C
VDD_LV_COR = 1.32 V
250
290
279
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
—
—
IDD_LV_TYP
+ IDD_LV_PLL
P Operating current
1.2 V supplies
TJ = 25 C
mA
2
VDD_LV_COR = 1.32 V
LSM mode
TJ = 150 C
VDD_LV_COR = 1.32 V
LSM mode
—
—
—
—
318
275
mA
mA
IDD_LV_TYP
IDD_LV_PLL
+
T Operating current
1.2V supplies
Tj=105C
2
VDD_LV_COR = 1.2V
LSM mode
1.2V supplies
—
—
299
mA
Tj=125C
VDD_LV_COR = 1.2V
LSM mode
MPC5643L Microcontroller Data Sheet, Rev. 9
88
Freescale Semiconductor
Electrical characteristics
Table 20. Current consumption characteristics (continued)
Symbol
IDD_LV_TYP
Parameter
Conditions1
Min
Typ
Max
Unit
+
T Operating current
1.2V supplies
Tj=105C
—
—
189
mA
2
IDD_LV_PLL
VDD_LV_COR = 1.2V
DPM Mode
1.2V supplies
Tj=125C
—
—
—
—
214
235
mA
mA
mA
VDD_LV_COR = 1.2V
DPM Mode
1.2V supplies
Tj=150C
VDD_LV_COR = 1.2V
DPM Mode
IDD_LV_STOP
T Operating current in TJ = 25 C
VDD STOP mode VDD_LV_COR = 1.32 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
57
T
TJ = 55 C
VDD_LV_COR = 1.32 V
P
TJ = 150 C
VDD_LV_COR = 1.32 V
105
25
IDD_LV_HALT
T Operating current in TJ = 25 C
VDD HALT mode VDD_LV_COR = 1.32 V
mA
T
TJ = 55 C
VDD_LV_COR = 1.32 V
64
P
TJ = 150 C
VDD_LV_COR = 1.32 V
115
10
3,4
IDD_HV_ADC
T Operating current
T Operating current
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_ADC = 3.6 V
mA
mA
4
IDD_HV_AREF
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF = 3.6 V
—
—
—
—
3
5
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF = 5.5 V
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
89
Electrical characteristics
Symbol
Table 20. Current consumption characteristics (continued)
Parameter
Conditions1
Min
Typ
Max
Unit
IDD_HV_OSC
(oscillator
bypass mode)
T Operating current
D Operating current
T Operating current
T Operating current
TJ = 150 C
3.3 V supplies
120 MHz
—
—
900
A
IDD_HV_OSC
(crystaloscillator
mode)
TJ = 150 C
3.3 V supplies
120 MHz
—
—
—
—
—
—
3.5
4
mA
mA
mA
5
IDD_HV_FLASH
TJ = 150 C
3.3 V supplies
120 MHz
IDD_HV_PMU
TJ = 150 C
3.3 V supplies
120 MHz
10
1
2
3
Devices configured for DPM mode, single core only with Core 0 executing typical code at 120 MHz from SRAM and Core 1 in
reset. If core execution mode not specified, the device is configured for LSM mode with both cores executing typical code at
120 MHz from SRAM.
Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1, PIT,
CRC, PLL0/1, I/O supply current excluded. If DPM mode is configured, Core_0 is active while Core_1 is in reset during the
measurements.
Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum
injection current specification is met and VDDA is within the operating voltage specifications.
4
5
This value is the total current for both ADCs.
VFLASH is only available in the calibration package.
3.11 Temperature sensor electrical characteristics
Table 21. Temperature sensor electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
—
P
D
Accuracy
Minimum sampling period
TJ = –40 °C to 150 °C
—
–10
4
10
—
°C
µs
TS
3.12 Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 5 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
MPC5643L Microcontroller Data Sheet, Rev. 9
90
Freescale Semiconductor
Electrical characteristics
EXTAL
C
L
R
EXTAL
P
XTAL
C
L
DEVICE
V
DD
I
EXTAL
R
XTAL
DEVICE
XTAL
DEVICE
Figure 5. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MTRANS
1
0
V
XTAL
1/f
XOSCHS
V
XOSCHS
90%
10%
V
XOSCHSOP
T
valid internal clock
XOSCHSSU
Figure 6. Main oscillator electrical characteristics
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
91
Electrical characteristics
×
Table 22. Main oscillator electrical characteristics
Value
Typ
Symbol
Parameter
Conditions1
Unit
Min
Max
fXOSCHS
SR Oscillator frequency
—
4.0
4.5
—
—
40.0
MHz
gmXOSCHS P Oscillator
VDD = 3.3 V ±10%
13.25
mA/V
transconductance
D Oscillation amplitude
VXOSCHS
fOSC = 4, 8, 10, 12, 16 MHz
1.3
1.1
—
—
—
—
—
—
V
fOSC = 40 MHz
—
VXOSCHSOP D Oscillation operating
point
0.82
V
TXOSCHSSU
T
Oscillator start-up time
fOSC = 4, 8, 10, 12 MHz2
fOSC = 16, 40 MHz2
—
—
—
—
—
6
2
ms
VIH
VIL
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode
0.65 × VDD
VDD + 0.4
V
V
SR Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
–0.4
—
0.35 × VDD
1
2
VDD = 3.3 V ±10%, TJ = –40 to +150 °C, unless otherwise specified.
The recommended configuration for maximizing the oscillator margin are:
XOSC_MARGIN = 0 for 4 MHz quartz
XOSC_MARGIN = 1 for 8/16/40 MHz quartz
3.13 FMPLL electrical characteristics
Table 23. FMPLL electrical characteristics
Symbol
Parameter Conditions Min
Typ
Max
Unit
f
D FMPLL reference frequency Crystal reference
range1
4
4
—
40
MHz
REF_CRYSTAL
fREF_EXT
fPLL_IN
D Phase detector input
frequency range (after
pre-divider)
—
—
16
MHz
fFMPLLOUT D Clock frequency range in
normal mode
—
4
—
—
1202
150
MHz
MHz
fFREE
P Free running frequency
Measured using clock division
20
(typically 16)
fsys
D On-chip FMPLL frequency2
D System clock period
—
—
16
—
—
—
—
—
—
120
1 / fsys
3.7
MHz
ns
tCYC
fLORL
fLORH
D Loss of reference frequency Lower limit
1.6
24
20
MHz
window3
Upper limit
56
fSCM
D Self-clocked mode
frequency4,5
—
150
MHz
µs
tLOCK
P Lock time
Stable oscillator (fPLLIN = 4 MHz),
stable VDD
—
—
200
MPC5643L Microcontroller Data Sheet, Rev. 9
92
Freescale Semiconductor
Electrical characteristics
Table 23. FMPLL electrical characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tlpll
tdc
D FMPLL lock time 6, 7
—
—
—
40
–6
—
—
—
200
60
6
s
%
D Duty cycle of reference
CJITTER T CLKOUT period jitter8,9,10,11 Long-term jitter (avg. over 2 ms
interval), fFMPLLOUT maximum
ns
tPKJIT T Single period jitter (peak to PHI @ 120 MHz,
—
—
—
—
—
—
—
—
175
185
200
±6
ps
ps
ps
ns
peak)
Input clock @ 4 MHz
PHI @ 100 MHz,
Input clock @ 4 MHz
PHI @ 80 MHz,
Input clock @ 4 MHz
tLTJIT
T Long term jitter
PHI @ 16 MHz,
Input clock @ 4 MHz
fLCK
fUL
fCS
D Frequency LOCK range
D Frequency un-LOCK range
D Modulation depth
—
–6
–18
±0.25
–0.5
—
—
—
—
—
—
6
% fFMPLLOUT
% fFMPLLOUT
—
Center spread
Down spread
—
18
±2.0
-8.0
100
%
fDS
fFMPLLOUT
fMOD
D Modulation frequency12
kHz
1
2
3
Considering operation with FMPLL not bypassed.
With FM; the value does not include a possible +2% modulation
“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked
mode.
4
5
Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside
the fLOR window.
fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.
fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
fSYS = fVCOODF
This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
FMPLL, load capacitors should not exceed these limits.
6
7
This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
8
9
This value is determined by the crystal manufacturer and board design.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the
CJITTER percentage for a given interval.
10 Proper PC board layout procedures must be followed to achieve specifications.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
93
Electrical characteristics
3.14 16 MHz RC oscillator electrical characteristics
Table 24. 16 MHz RC oscillator electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions
Unit
Min
Max
fRC
P RC oscillator frequency
TA = 25 °C
—
—
16
—
—
6
MHz
%
RCMVAR P Fast internal RC oscillator variation over
temperature and supply with respect to fRC at
TA = 25 °C in high-frequency configuration
6
3.15 ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 7. ADC characteristics and error definitions
3.15.1 Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
MPC5643L Microcontroller Data Sheet, Rev. 9
94
Freescale Semiconductor
Electrical characteristics
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C and C being
S
p2
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C + CS equal to 7.5 pF, a resistance of 133 k is obtained
p2
(R = 1 / (fS*(C +C )), where fS represents the conversion rate at the considered channel). To minimize the error induced
EQ
p2
S
by the voltage partitioning between this resistance (sampled voltage on C ) and the sum of R + R , the external circuit must be
s
S
F
designed to respect the Equation 4:
R + R
S
F
1
2
--------------------
V
-- LSB
Eqn. 4
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
C
S
V
C
C
C
P2
A
F
P1
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 8. Input Equivalent Circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 8): A charge sharing phenomenon is
A
installed when the sampling phase is started (A/D switch close).
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
95
Electrical characteristics
Voltage Transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << TS
V
A1
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 9. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
C C
P
S
--------------------
= R
+ R
Eqn. 5
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
R
+ R
C « T
Eqn. 6
1
SW
AD
S
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
V
C + C + C = V C + C
Eqn. 7
A1
S
P1
P2
A
P1
P2
•
A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
R C + C + C
P1 P2
Eqn. 8
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
10 = 10 R C + C + C T
P1 P2 S
Eqn. 9
2
L
S
MPC5643L Microcontroller Data Sheet, Rev. 9
96
Freescale Semiconductor
Electrical characteristics
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
Eqn. 10
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.
S
Analog Source Bandwidth (V )
A
T
f
2 R C (Conversion Rate vs. Filter Pole)
F F
C
Noise
f (Anti-aliasing Filtering Condition)
F
0
2 f f (Nyquist)
0
C
f
0
f
Anti-Aliasing Filter (f = RC Filter pole)
Sampled Signal Spectrum (f = conversion Rate)
C
F
f
f
f
C
F
0
f
f
Figure 10. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,
C
C
S
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the
S
S
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A2
P1
F
V
C
+ C + C + C
A
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 12
C
8192 C
F
S
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
97
Electrical characteristics
Symbol
Table 25. ADC conversion characteristics
Parameter
Conditions1
Min Typ Max
Unit
fCK
SR ADC Clock frequency (depends on ADC
configuration)
—
3
—
60
MHz
(The duty cycle depends on AD_CK2
frequency)
fs
SR Sampling frequency
—
—
—
983.6 KHz
3
tsample
teval
D Sample time4
60 MHz
383
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
D Evaluation time5
60 MHz
6
CS
D ADC input sampling capacitance
D ADC input pin capacitance 1
D ADC input pin capacitance 2
D Internal resistance of analog source
—
7.32
5(7)
0.8
0.3
875
825
3
pF
6
CP1
—
—
pF
6
CP2
—
—
pF
6
RSW1
VREF range = 4.5 to 5.5 V
—
k
VREF range = 3.0 to 3.6 V
—
6
RAD
D Internal resistance of analog source
P Integral non linearity
P Differential non linearity8
T Offset error
—
—
INL
DNL
—
–3
–1
–6
–6
LSB
LSB
LSB
LSB
—
2
OFS
—
6
GNE
T Gain error
—
6
IS1WINJ
(single ADC channel)
C Max positive/negative injection
C Max positive/negative injection
–3
—
—
3
mA
mA
IS1WWINJ
(double ADC channel)
|Vref_ad0 - Vref_ad1| <
150mV
–3.6
3.6
SNR
SNR
T Signal-to-noise ratio
Vref = 3.3V
Vref = 5.0V
67
69
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
dB
dB
T Signal-to-noise ratio
THD
T Total harmonic distortion
T Signal-to-noise and distortion
T Effective number of bits
—
-65
65
dB
SINAD
ENOB
—
dB
—
10.5
–6
bits
LSB
LSB
LSB
LSB
TUEIS1WINJ T Total unadjusted error for IS1WINJ (single ADC
channels)
Without current injection
With current injection
Without current injection
With current injection
–8
8
TUEIS1WWINJ P Total unadjusted error for IS1WWINJ (double
–8
8
ADC channels)
T
–10
10
1
2
3
TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF
.
AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is not
possible.
MPC5643L Microcontroller Data Sheet, Rev. 9
98
Freescale Semiconductor
Electrical characteristics
4
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance
of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time
tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend
on programming.
5
6
7
8
This parameter does not include the sample time Tsample, but only the time for determining the digital result.
See Figure 8.
For the 144-pin package
No missing codes
3.16 Flash memory electrical characteristics
Table 26. Flash memory program and erase electrical specifications
Initial Lifetime
No.
Symbol
Parameter
Typ1
Unit
Max2 Max3
4
1
2
3
4
5
6
7
TDWPROGRAM
TPPROGRAM
*
Double word (64 bits) program time4
30
40
—
500
500
µs
µs
*4 Page(128 bits) program time4
160
T16KPPERASE *4 16 KB block pre-program and erase time
T48KPPERASE *4 48 KB block pre-program and erase time
T64KPPERASE *4 64 KB block pre-program and erase time
T128KPPERASE *4 128 KB block pre-program and erase time
T256KPPERASE *4 256 KB block pre-program and erase time
250 1000 5000
400 1500 5000
450 1800 5000
800 2600 7500
ms
ms
ms
ms
1400 5200 15000 ms
1
2
Typical program and erase times represent the median performance and assume nominal supply values
and operation at 25C. These values are characterized, but not tested.I
Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for
<100 program/erase cycles, nominal supply values and operation at 25C. These values are verified at
production test.
3
4
Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product
life. These values are characterized, but not tested.
Program times are actual hardware programming times and do not include software overhead.
Table 27. Flash memory timing
Value
Symbol
Parameter
Unit
Min
Typ
Max
TRES
D Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
—
—
100
ns
ns
TDONE D Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
—
100
10
—
—
5
TPSRT D Time between program suspend resume and the next program
suspend request.1
—
s
ms
TESRT D Time between erase suspend resume and the next erase
suspend request.2
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
99
Electrical characteristics
1
Repeated suspends at a high frequency may result in the operation timing out, and the flash module will
respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish
(MCR[DONE] = 1 during Program operation). The minimum time between suspends to ensure this does not
occur is TPSRT
.
2
If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs
during erase pulse. This improves erase time but reduces cycling figure due to
overstress
Table 28. Flash memory module life
Value
No. Symbol
Parameter
Unit
Minimu
m
Typical Maximum
1
2
3
P/E
P/E
C Number of program/erase cycles per block for 16 KB, 48 KB, 100000
and 64 KB blocks over the operating temperature range1
—
—
—
cycles
cycles
C Number of program/erase cycles per block for 128 KB and
256 KB blocks over the operating temperature range1
1000
1000002
3
Retention C Minimum data retention at 85 °C average ambient temperature
Blocks with 0–1,000 P/E cycles
years
20
10
5
—
—
—
—
—
—
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
1
Operating temperature range is TJ from –40 °C to 150 °C. Typical endurance is evaluated at 25 C. Product qualification
is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance,
please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
2
3
Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks. For additional information on the Freescale
definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
3.17 SWG electrical characteristics
Table 29. MPC5643L SWG Specifications
Value
Symbol
Parameter
Minimum
Typical
Maximum
T
T
T
T
T
T
Input clock
12 MHz
1kHz
0.4 V
-6%
16 MHz
—
20 MHz
50 kHz
2.0V
6%
Frequency Range
Peak to Peak1
—
Peak to Peak variation2
Common Mode3
Common Mode variation
—
—
1.3 V
—
—
-6%
6%
MPC5643L Microcontroller Data Sheet, Rev. 9
100
Freescale Semiconductor
Electrical characteristics
Table 29. MPC5643L SWG Specifications
Value
Symbol
Parameter
Minimum
Typical
Maximum
T
T
T
T
SiNAD4
Load C
Load I
45 dB
25 pF
0 A
—
—
—
—
—
100 pF
100 A
360
ESD Pad Resistance5
230
1
2
3
4
5
Peak to Peak value is measured with no R or I load.
Peak to Peak excludes noise, SiNAD must be considered.
Common mode value is measured with no R or I load.
SiNAD is measured at Max Peak to Peak voltage.
Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak to Peak
voltages, depending on application I load and/or R load.
3.18 AC specifications
3.18.1 Pad AC specifications
1
Table 30. Pad AC specifications (3.3 V , IPP_HVE = 0 )
Tswitchon1
(ns)
Rise/Fall2
(ns)
Frequency
(MHz)
Current slew3
(mA/ns)
Load drive
(pF)
No.
Pad
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
1
Slow
T
T
T
T
3
3
3
3
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
40
40
40
40
15
15
15
15
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
50
75
100
12
25
40
70
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
2
0.01
0.01
0.01
0.01
2.5
2.5
2.5
2.5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
25
50
2
2
100
200
25
2
2
2
3
4
Medium
40
20
13
7
7
7
50
7
100
200
25
7
Fast
72
55
40
25
50
40
40
40
40
25
6
7
7
50
6
12
18
5
7
100
200
25
6
7
Symmetric
8
3
1
2
3
Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
Slope at rising/falling edge.
Data based on characterization results, not tested in production.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
101
Electrical characteristics
VDDE/2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
Pad
Output
VOL
Figure 11. Pad output delay
3.19 Reset sequence
This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start
conditions and the end indication for the reset sequences.
3.19.1 Reset sequence duration
Table 31 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in
Section 3.19.2, Reset sequence description.
Table 31. RESET sequences
TReset
No.
Symbol
Parameter
Conditions
Unit
Min
Typ
Max1
1
2
3
4
5
TDRB
CC
CC
CC
CC
CC
Destructive Reset Sequence, BIST enabled
Destructive Reset Sequence, BIST disabled
External Reset Sequence Long, BIST enabled
Functional Reset Sequence Long
28
500
28
35
1
34
4200
32
39
5000
37
ms
s
ms
s
s
TDR
—
TERLB
TFRL
TFRS
—
—
150
4
400
10
Functional Reset Sequence Short
1
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
3.19.2 Reset sequence description
The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the
figures indicate the starting point and the end point for which the duration is specified in Table 31. The start point and end point
MPC5643L Microcontroller Data Sheet, Rev. 9
102
Freescale Semiconductor
Electrical characteristics
conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3, Reset sequence
trigger mapping.
With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and
the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the
signal pin RESET.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is strong enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the following figures
indicates the time when the device stops driving it low. The reset sequence durations given
in table Table 31 are applicable only if the internal reset sequence is not prolonged by an
external reset generator keeping RESET asserted low beyond the last PHASE3.
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Establish IRC
and PWR
Device
Config
Self Test
Setup
Device
Config
Application
Execution
Flash init
MBIST
LBIST
Flash init
TDRB, min < TReset < TDRB, max
Figure 12. Destructive Reset Sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
DRUN
Establish IRC
and PWR
Device
Config
Application
Execution
Flash init
TDR, min < TReset < TDR, max
Figure 13. Destructive Reset Sequence, BIST disabled
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
103
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Device
Config
Self Test
Setup
Device
Config
Application
Execution
Flash init
MBIST
LBIST
Flash init
TERLB, min < TReset < TERLB, max
Figure 14. External Reset Sequence Long, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
DRUN
Device
Config
Application
Execution
Flash init
TFRL, min < TReset < TFRL, max
Figure 15. Functional Reset Sequence Long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE3
DRUN
Application
Execution
TFRS, min < TReset < TFRS, max
Figure 16. Functional Reset Sequence Short
MPC5643L Microcontroller Data Sheet, Rev. 9
104
Freescale Semiconductor
Electrical characteristics
The reset sequences shown in Figure 15 and Figure 16 are triggered by functional reset events. RESET is driven low during
these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to
1
drive RESET low for the duration of the internal reset sequence .
3.19.3 Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start
conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 31.
Table 32. Reset sequence trigger — reset sequence
Reset Sequence
Reset
Sequence
Start
Reset
Sequence
End
Destructiv
e Reset
Sequence, Sequence, Sequenc
Destructiv
e Reset
External
Reset
Functiona Functiona
Reset
Sequence
Trigger
l Reset
Sequenc
e Long
l Reset
Sequenc
e Short
Condition
Indication
BIST
BIST
e Long,
BIST
enabled1
disabled1
enabled
All internal
destructivereset
sources
(LVDsorinternal
HVD during
power-up and
during
Section 3.1
9.4.1,
Destructive
reset
Release of
RESET2
triggers
cannot
trigger
cannot
trigger
cannot
trigger
operation)
Assertion of
RESET3
Section 3.1
9.4.2,
External
reset via
RESET
cannot trigger
cannot trigger
cannot trigger
triggers4
triggers5
triggers
triggers6
All internal
functional reset
sources
configured for
long reset
Sequence
starts with
internal
reset
Release of
RESET7
cannot
trigger
cannot
trigger
trigger
All internal
functional reset
sources
cannot
trigger
cannot
trigger
triggers
configured for
short reset
1
2
Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.
End of the internal reset sequence (as specified in Table 31) can only be observed by release of RESET if it is not
held low externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till
RESET is released externally.
3
The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
1.See RGM_FBRE register for more details.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
105
Electrical characteristics
4
If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the
shadow sector of the NVM.
5
If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the
shadow sector of the NVM.
6
7
If RESET is configured for short reset
Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for
the functional reset source which triggered the reset sequence.
3.19.4 Reset sequence — start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage
rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.
3.19.4.1 Destructive reset
Figure 17 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start
for the Destructive Reset Sequence, BIST disabled.
V
Supply Rail
Vmax
Vmin
t
TReset, max starts here
TReset, min starts here
Figure 17. Reset sequence start for Destructive Resets
Table 33. Voltage Thresholds
Variable name
Value
Vmin
Refer to Table 18
Vmax
Refer to Table 18
VDD_HV_PMU
Supply Rail
3.19.4.2 External reset via RESET
Figure 18 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as
specified in Table 32.
MPC5643L Microcontroller Data Sheet, Rev. 9
106
Freescale Semiconductor
Electrical characteristics
V
RESET
0.65 * VDD_HV_IO
0.35 * VDD_HV_IO
t
TReset, max starts here
TReset, min starts here
Figure 18. Reset sequence start via RESET assertion
3.19.5 External watchdog window
If the application design requires the use of an external watchdog the data provided in Section 3.19, Reset sequence can be used
to determine the correct positioning of the trigger window for the external watchdog. Figure 19 shows the relationships between
the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window.
Watchdog needs to be triggered within this window
TWDStart, min
External Watchdog Window Closed
TWDStart, max
External Watchdog Window Open
External Watchdog Window Closed
External Watchdog Window Open
Watchdog trigger
Basic Application Init
TReset, min
Application Running
Basic Application Init
TReset, max
Application Running
Application time required to
prepare watchdog trigger
Earliest
Application
Start
Latest
Application
Start
Internal Reset Sequence
Start condition (signal or voltage rail)
Figure 19. Reset sequence - External watchdog trigger window position
3.20 AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows:
• TJ = –40 to 150 C
• Supply voltages as specified in Table 9
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
107
Electrical characteristics
• Input conditions: All Inputs: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF
3.20.1 RESET pin characteristics
The MPC5643L implements a dedicated bidirectional RESET pin.
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 20. Start-up reset requirements
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 21. Noise filtering on reset signal
MPC5643L Microcontroller Data Sheet, Rev. 9
108
Freescale Semiconductor
Electrical characteristics
Table 34. RESET electrical characteristics
No. Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
1
Ttr
D Output transition time output pin2
CL = 25pF
CL = 50pF
CL = 100pF
—
—
—
—
—
—
—
—
12
25
40
40
—
ns
—
2
3
WFRST P nRESET input filtered pulse
—
ns
ns
WNFRST P nRESET input not filtered pulse
—
500
1
2
VDD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified
CL includes device and package capacitance (CPKG < 5 pF).
3.20.2 WKUP/NMI timing
Table 35. WKUP/NMI glitch filter
No. Symbol
Parameter
Min
Typ
Max
Unit
1
2
WFNMI D NMI pulse width that is rejected
WNFNMI D NMI pulse width that is passed
—
—
—
45
—
ns
ns
205
3.20.3 IEEE 1149.1 JTAG interface timing
Table 36. JTAG pin AC electrical characteristics
No.
Symbol
Parameter
Conditions
Min Max Unit
1
2
tJCYC
tJDC
D
D
D
D
D
D
D
D
D
D
D
D
D
TCK cycle time
—
—
—
—
—
—
—
—
—
—
—
—
—
62.5
—
ns
%
TCK clock pulse width (measured at VDDE/2)
TCK rise and fall times (40%–70%)
TMS, TDI data setup time
40 60
3
tTCKRISE
—
5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
tTDOHZ
tBSDV
t
—
—
20
—
20
50
50
50
—
—
5
t
TMS, TDI data hold time
25
—
0
6
TCK low to TDO data valid
7
TCK low to TDO data invalid
8
TCK low to TDO high impedance
—
—
—
—
50
50
11
12
13
14
15
TCK falling edge to output valid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
109
Electrical characteristics
TCK
2
3
3
2
1
Figure 22. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 23. JTAG test access port timing
MPC5643L Microcontroller Data Sheet, Rev. 9
110
Freescale Semiconductor
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 24. JTAG boundary scan timing
3.20.4 Nexus timing
1
Table 37. Nexus debug port timing
No.
Symbol
Parameter
Conditions Min Max Unit
1
2
tMCYC
tMDC
D MCKO Cycle Time
—
—
—
—
—
—
—
—
15.6
40
—
ns
%
D MCKO Duty Cycle
60
3
tMDOV
tEVTIPW
tEVTOPW
tTCYC
D MCKO Low to MDO, MSEO, EVTO Data Valid2
–0.1 0.25 tMCYC
4
D EVTI Pulse Width
4.0
1
—
tTCYC
tMCYC
ns
5
D EVTO Pulse Width
6
D TCK Cycle Time3
62.5
40
8
—
60
—
—
25
7
tTDC
D TCK Duty Cycle
%
8
t
NTDIS, tNTMSS D TDI, TMS Data Setup Time
ns
9
t
t
D TDI, TMS Data Hold Time
5
ns
NTDIH, NTMSH
10
tJOV
D TCK Low to TDO/RDY Data Valid
0
ns
1
2
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal.
For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
111
Electrical characteristics
3
The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
Figure 25. Nexus output timing
4
EVTI
Figure 26. Nexus EVTI Input Pulse Width
MPC5643L Microcontroller Data Sheet, Rev. 9
112
Freescale Semiconductor
Electrical characteristics
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
Figure 27. Nexus Double Data Rate (DDR) Mode output timing
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
113
Electrical characteristics
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 28. Nexus TDI, TMS, TDO timing
3.20.5 External interrupt timing (IRQ pin)
Table 38. External interrupt timing
No.
Symbol
Parameter
IRQ pulse width low
Conditions
Min Max Unit
1
2
3
tIPWL
tIPWH
tICYC
D
D
D
—
—
—
3
3
6
—
—
—
tCYC
tCYC
tCYC
IRQ pulse width high
IRQ edge to edge time1
1
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
MPC5643L Microcontroller Data Sheet, Rev. 9
114
Freescale Semiconductor
Electrical characteristics
IRQ
1
2
3
Figure 29. External interrupt timing
3.20.6 DSPI timing
Table 39. DSPI timing
No. Symbol
Parameter
Conditions
Master (MTFE = 0)
Min
Max
Unit
1
tSCK
D
D
D
D
D
D
D
D
D
D
D
DSPI cycle time
62
62
16
16
16
—
—
—
—
—
ns
Slave (MTFE = 0)
Slave Receive Only Mode1
2
3
4
5
6
7
8
9
tCSC
tASC
tSDC
tA
PCS to SCK delay
After SCK delay
—
ns
ns
—
—
SCK duty cycle
tSCK/2 - 10 tSCK/2 + 10 ns
Slave access time
Slave SOUT disable time
PCSx to PCSS time
PCSS to PCSx time
Data setup time for inputs
SS active to SOUT valid
SS inactive to SOUT High-Z or invalid
—
—
—
13
13
20
2
40
10
—
—
—
—
—
—
—
—
—
—
4
ns
ns
ns
ns
ns
tDIS
tPCSC
tPASC
tSUI
—
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
5
20
–5
4
10
tHI
D
D
Data hold time for inputs
ns
ns
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
11
–5
—
—
—
—
11 tSUO
Data valid (after SCK edge)
23
12
4
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
115
Electrical characteristics
No. Symbol
Table 39. DSPI timing (continued)
Conditions
Parameter
Data hold time for outputs
Min
Max
Unit
12 tHO
D
Master (MTFE = 0)
–2
6
—
—
—
—
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
6
–2
1
Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data
on SIN, but no valid data is transmitted on SOUT.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Note: The numbers shown are referenced in Table 39.
Figure 30. DSPI classic SPI timing — master, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 9
116
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: The numbers shown are referenced in Table 39.
Figure 31. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: The numbers shown are referenced in Table 39.
Figure 32. DSPI classic SPI timing — slave, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
117
Electrical characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: The numbers shown are referenced in Table 39.
Figure 33. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Note: The numbers shown are referenced in Table 39.
Figure 34. DSPI modified transfer format timing — master, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 9
118
Freescale Semiconductor
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: The numbers shown are referenced in Table 39.
Figure 35. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: The numbers shown are referenced in Table 39.
Figure 36. DSPI modified transfer format timing – slave, CPHA = 0
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
119
Package characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: The numbers shown are referenced in Table 39.
Figure 37. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Note: The numbers shown are referenced in Table 39.
Figure 38. DSPI PCS strobe (PCSS) timing
4
Package characteristics
4.1
Package mechanical data
MPC5643L Microcontroller Data Sheet, Rev. 9
120
Freescale Semiconductor
Package characteristics
Figure 39. 144 LQFP package mechanical drawing (1 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
121
Package characteristics
Figure 40. 144 LQFP package mechanical drawing (2 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 9
122
Freescale Semiconductor
Package characteristics
Figure 41. 257 MAPBGA package mechanical drawing (1 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
123
Package characteristics
Figure 42. 257 MAPBGA package mechanical drawing (2 of 2)
MPC5643L Microcontroller Data Sheet, Rev. 9
124
Freescale Semiconductor
Ordering information
5
Ordering information
M PC 5643L F F2 M LQ
1
R
Qualification status
Core code (Power Architecture)
Device number
F = FlexRay
(blank) = No FlexRay
Fab and mask identifier
Temperature range
Package identifier
Operating frequency
Tape and reel status
Temperature range
Package identifier
Operating frequency
Tape and reel status
R = Tape and reel
(blank) = Trays
M = –40 °C to 125 °C
V = –40 °C to 105 °C
LQ = 144 LQFP
MM = 257 MAPBGA
1 = 120 MHz
8 = 80 MHz
Qualification status
P = Pre-qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Note: Not all options are available on all devices. See Table 40.
Figure 43. Commercial product code structure
Table 40. Orderable part number summary
Speed
(MHz)2
Part number1
Flash/SRAM
Package
Other features
SPC5643LFF2MLQ1
1 MB/128 KB
144 LQFP (Pb free)
120
120
120
120
120
120
120
120
80
FlexRay
–40–125 C
SPC5643LFF2MMM1
SPC5643LF2MLQ1
SPC5643LF2MMM1
SPC5643LFF2VLQ1
SPC5643LFF2VMM1
SPC5643LF2VLQ1
SPC5643LF2VMM1
SPC5643LFF2MLQ8
SPC5643LFF2MMM8
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
257 MAPBGA (Pb free)
144 LQFP (Pb free)
FlexRay
–40–125 C
No FlexRay
–40–125 C
257 MAPBGA (Pb free)
144 LQFP (Pb free)
No FlexRay
–40–125 C
FlexRay
–40–105 C
257 MAPBGA (Pb free)
144 LQFP (Pb free)
FlexRay
–40–105 C
No FlexRay
–40–105 C
257 MAPBGA (Pb free)
144 LQFP (Pb free)
No FlexRay
–40–105 C
FlexRay
–40–125 C
257 MAPBGA (Pb free)
80
FlexRay
–40–125 C
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
125
Document revision history
Table 40. Orderable part number summary (continued)
Speed
(MHz)2
Part number1
Flash/SRAM
Package
Other features
SPC5643LF2MLQ8
1 MB/128 KB
144 LQFP (Pb free)
80
80
80
80
80
80
No FlexRay
–40–125 C
SPC5643LF2MMM8
SPC5643LFF2VLQ8
SPC5643LFF2VMM8
SPC5643LF2VLQ8
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
1 MB/128 KB
257 MAPBGA (Pb free)
144 LQFP (Pb free)
No FlexRay
–40–125 C
FlexRay
–40–105 C
257 MAPBGA (Pb free)
144 LQFP (Pb free)
FlexRay
–40–105 C
No FlexRay
–40–105 C
SPC5643LF2VMM8
257 MAPBGA (Pb free)
No FlexRay
–40–105 C
1
All packaged devices are SPC, rather than MPC or SPC, until product qualifications are complete.
The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
Not all configurations are available in the SPC parts.
2
This speed rating does not include the ±2% for frequency modulation.
6
Document revision history
Table 41 summarizes revisions to this document.
Table 41. Revision history
Description of changes
Revision
Date
1
2
2 Mar 2009 Initial release.
5 May 2009 Updated, Advance Information.
—Revised SINAD/SNR specifications.
— Updated pinout and pin multiplexing information.
3
5 Oct 2009 Updated, Advance Information, Public release.
— Throughout this document, added information for 257 MAPBGA package.
— Updated Table 1, MPC5643L device summary.
— Updated Section 1.3, Feature Details.
— Updated pin-out and pin multiplexing tables.
— In Section 3, Electrical characteristics, added symbols for signal characterization
methods.
— In Table 8, updated maximum ratings.
— In Table 10 and Table 11, removed moving-air thermal characteristics.
— Updated Section 3.8, Voltage regulator electrical characteristics.
— Updated Section 3.14, ADC electrical characteristics.
— Updated Section 3.15, Flash memory electrical characteristics.
— Updated Section 3.17.1, RESET pin characteristics.
— Removed External interrupt timing (IRQ pin) timing specifications.
— Updated Section 3.17.6, DSPI timing.
— Updated Section 5, Ordering information.
MPC5643L Microcontroller Data Sheet, Rev. 9
126
Freescale Semiconductor
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
4
2 Mar 2010 Editorial changes and improvements.
Revised the 257-pin package pin pitch (was 1.4 mm, is 0.8 mm).
In the Overview section:
• Renamed the peripheral bridge to “PBRIDGE”.
• Revised the information for FlexRay.
• Revised the “Clock, reset, power, mode and test control module” section.
• Revised the “Platform memory access time summary” table and replaced TBDs by
meaningful values.
Extensive revisions to signal descriptions and pin muxing information.
In the “ conditions (3.3 V)” table, changed the specification for VDD_HV_ADR0 and
VDD_HV_ADR1 (was “...3.3 V”, is “...3.6 V”).
Revised the “EMI testing specifications” table.
In the “HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical
specifications” table, added a specification for the digital low voltage detector upper
threshold.
Revised the “FMPLL electrical characteristics” table.
In the “Main oscillator electrical characteristics” table, changed the maximum specification
for gmXOSCHS (was 11 mA/V, is 11.8 mA/V).
Revised the “ADC electrical characteristics” section.
In the “ADC conversion characteristics” table:
• Changed the tADC_S specification (was TBD, is minimum of 383 ns).
• Added the footnote “No missing codes” to the DNL specification.
• Added specifications for SNR, THD, SINAD, and ENOB.
Revised the “Ordering information” section.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
127
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
5
31 Aug 2010 Editorial changes and improvements.
Revised the Overview section.
Replaced references to PowerPC with references to Power Architecture.
In the feature summary, changed “As much as 128 KB on-chip SRAM” to “128 KB on-chip
SRAM”.
In the “Feature details” section:
• In the “On-chip SRAM with ECC” section, added information about required RAM wait
states.
• In the PIT section, deleted “32-bit counter for real time interrupt, clocked from main
external oscillator” (not supported on this device).
• In the flash-memory section, changed “16 KB Test” to “16 KB test sector”, revised the
wait state information, and deleted the associated Review_Q&A content.
• In the SRAM section, revised the wait state information.
In the 144-pin pinout diagram:
• Renamed pin 58 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).
• Renamed pin 59 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).
In the “144 LQFP pin function summary” table, for pin 39, changed VSS_LV_COR to
VDD_LV_COR
.
In the “Supply pins” table:
• Changed the description for VDD_LV_COR (was “Voltage regulator supply voltage”, is
“Core logic supply”).
• Changed the description for VDD_HV_PMU (was “Core regulator supply”, is “Voltage
regulator supply”).
In the “Pin muxing” table:
• In the “Pad speed” column headings, changed “SRC = 0” to “SRC = 1” and “SRC = 1”
to “SRC = 0”
• For port B[6], changed the pad speed for SRC=0 (was M, is F).
In the “Thermal characteristics” section, added meaningful values to the
thermal-characteristics tables.
Added the “SWG electrical specifications” section.
In the “Voltage regulator electrical characteristics” section, changed the table title (was
“HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical
specifications”, is “Voltage regulator electrical characteristics”) and revised the table.
In the “BCP68 board schematic example” figure, removed the resistor at the base of the
BCP68 transistor.
In the “DC electrical characteristics” table:
• Changed the guarantee parameter for IINJ (was P, is T).
• Added a specification for input leakage current for shared ADC input-only ports.
Revised the “Flash memory module life” table.
In the “FMPLL electrical characteristics” table, revised the footnote defining fSCM and
fVCO
.
In the “Main oscillator electrical characteristics” table:
• Changed the max specification for gmXOSCHS (was 11.8 mA/V, is 13.25 mA/V).
• Revised the conditions for TXOSCHSSU
.
In the ‘RC oscillator electrical characteristics” table, deleted the specification for
RCMTRIM
.
Revised the “ADC conversion characteristics” table.
5
31 Aug 2010 In the “RESET pin characteristics” section, changed “nRSTIN” to “RESET”.
(cont.)
(cont.)
Added the “Reset sequence” section.
Revised the footnotes in the “Nexus debug port timing” table.
In the “Orderable part number summary” table, added a footnote about frequency
modulation to the “Speed (MHz)” column heading.
MPC5643L Microcontroller Data Sheet, Rev. 9
128
Freescale Semiconductor
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
6
11 Mar 2011 Editorial changes.
In the “Document overview” section, added information about how content specific to
silicon versions (“cut1” and “cut2”) is presented.
In the isometric miniature package drawings on the front page, removed the third
dimension.
Changed Symbol from P to D for “Conversion Time” in “ADC conversion characteristics”
table.
Added classification symbol “D” to seven entries in “Voltage regulator electrical
specifications“ table.
Removed irrelevant Flexcan specs.
Updated Table “Voltage Thresholds” to reference values specified in Table “Voltage
Regulator Electrical Specifications”.
RDY pin added for cut2.
In the “System pins” table, added a footnote about the MDO0 pad speed.
Updated Rsw1 values.
Added TUE-related spec information for single and double ADC channels.
Added AC Test Timing Conditions to the “AC timing characteristics” section.
Added a statement on the first page describing cut1 versus cut2.
Moved the first paragraph from the “Description” section to the beginning of the
“Document overview” section.
Changed pad speed from “M” to “SYM” for FlexRay pins in the “Pin Muxing” table and
added this pad type to the footnote.
Moved the newly added device current specification entries from the “DC electrical
characteristics“ table into a newly created “Supply current characteristics“ table.
Added symbol “CC” to the description in the “Introduction” section.
Updated “Input leakage current” specs in the “DC electrical characteristics” table.
Changed TADC_S to Tsample and TADC_C toTconv in the “ADC conversion characteristics”
table and footnotes.
Removed “IINJ” from the “ADC conversion characteristics” table as this is included in
IS1WIKNJ and IS1WWiNJ.
Changed RESET_B to RESET in the "Reset sequence" section.
Added the “Flash memory timing” table.
Added cut2 specs for TDRB and TERLB to the “Reset sequences” table.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
129
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
6
11 Mar 2011 Added “WKUP/NMI Timing” subsection and “WKUP/NMI Glitch Filter” table to the “AC
(cont.)
(cont.)
timing characteristics” section.
Added “Nexus DDR Mode output timing” table to the “Nexus timing” section.
Removed the “CLKOUT” diagram from the “External interrupt timing (IRQ pin)” section as
it is not relevant.
Corrected an error in the IRQ timing in the “External interrupt timing” figure.
Updated the tSDC parameters in the “DSPI timing” table.
Renamed the “Electromagnetic Interference (EMI) characteristics” section (is
“Electromagnetic Interference (EMI) characteristics (cut1)”) and revised all information
in that section.
In the “Voltage regulator electrical characteristics” section, added the BCX68 from
Infineon to the list of supported transistors.
Revised the “Voltage regulator electrical specifications” table to include cut1 and cut2
information.
Renamed the “Supply current characteristics” section (is “Supply current characteristics
(cut2)”) and revised it to show meaningful data.
In the footnotes of the “Main oscillator electrical characteristics” table, changed
SELMARGIN to XOSC_MARGIN.
In the “ADC conversion characteristics” table:
• Changed “LSB” to “Counts”.
• Created separate rows for the TUE specifications.
Added bullet regarding HALT and STOP in the “Clock, reset, power, mode and test control
modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)“ subsection of the “Features“
section.
In the “Analog-to-Digital Converter module“ subsection of the “Feature Details” section,
changed “Motor control mode“ to “CTU mode“ to be consistent with the nomenclature
used in the Reference Manual.
Updated the JCOMP entries in the “Pin function summary“ table.
Added footnotes regarding pad pull devices to NMI, TMS, TCK, and JCOMP in the
“System pins“ table.
Added “Time constant of RC filter at LVD input” parameters to the “Main supply LVD (LVD
Main) specifications“ table.
In the “Supply current characteristics (cut2)“ table:
• Changed “IDD_LV_MAX” to “IDD_LV_MAX“;
• Removed all “40-120 MHz” frequency ranges from the “Conditions” column;
• Updated the “Max” values column;
• Added parameter “IDD_LV_TYP + IDD_LV_PLL“ with “P” classification and special footnote;
• Changed all “25C“ temperature conditions to “ambient”;
• Added “TJ = 150 C“ condition to parameters IDD_HV_ADC, IDD_HV_AREF., IDD_HV_OSC
and IDD_HV_FLASH
Changed the timing diagram in the “Main oscillator electrical characteristics” section to
reference MTRANS assertion instead of VDDMIN
,
.
.
Updated the jitter specs in the “FMPLL electrical characteristics“ table.
In the “ADC conversion characteristics“ table, changed all parameters with units of
“counts” to units of “LSB” and updated Min/Max values.
Changed IDD_LV_BIST + IDD_LV_PLL operating current (for both cases) to TBD.
In the “Supply current characteristics (cut2)” section, added a footnote that IDD_HV_ADC
and IDD_HV_AREF represent the total current of both ADCs in the “Current consumption
characteristics” table.
MPC5643L Microcontroller Data Sheet, Rev. 9
130
Freescale Semiconductor
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
6
11 Mar 2011 In the “ADC conversion characteristics” table:
(cont.)
(cont.)
• Changed DNL min from -2 to -1.
• Changed OFS min from -2 to -6.
• Changed OFS max from 2 to 6.
• Changed GNE min from -2 to -6.
• Changed GNE max from 2 to 6.
• Changed SNR min from 69 to 67.
• Changed TUE min (without current injection) from -6 to -8.
• Changed TUE max (without current injection) from 6 to 8.
• Changed TUE min (with current injection) from -8 to -10.
• Changed TUE max (with current injection) from 8 to 10.
7
25 Mar 2011 In the “Description” section, changed the first paragraph and its bullets to paragraph form
only.
In the “Voltage regulator electrical specifications“ table, changed the CV1V2 Min value from
“—“ to 300 nF, and changed the Max value from 300 nF to 900 nF.
In the “Supply current characteristics (cut2)“ table, corrected the “IDD_LV_TYP
+ IDD_LV_PLL“ values as follows:
• Changed the maximum value for “TJ = ambient“ from “279 mA+
2.10 mA*fCPU“ to “279 mA”.
• Changed the maximum value for “TJ = 150 C“ from “318 mA+
2.30 mA*fCPU“ to 318 mA.
• Changed the frequency multiplier “fCPU” in the max value to read “fCPU[MHz]“ for
“IDD_LV_FULL + IDD_LV_PLL“ and “IDD_LV_TYP + IDD_LV_PLL“.
In the “JTAG pin AC electrical characteristics“ table:
• Changed tJCYC min from 100ns to 62.5ns.
• Changed tJDC units from “ns” to “%”.
In the “Nexus debug port timing“ table:
• Changed tTCYC min from 40ns to 62.5 ns.
• Changed tJOV parameter description from “TCK Low to TDO Data Valid“ to “TCK Low
to TDO/RDY Data Valid“.
Changed “DDR” to “Double Data Rate (DDR)“ in the “Nexus DDR Mode output timing“
figure.
Changed “TDO” to “TDO/RDY” in the “Nexus TDI, TMS, TDO timing“ figure.
Removed “fmax” from the “DSPI timing” table.
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
131
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
8
27 April 2012 Editorial changes.
In the “Device comparison” section, changed “Ambient temperature range using external
ballast transistor (BGA)“ from TBD to “–40 to 125 °C“.
In the “Block diagram” section, removed one PMU from the figure.
In the 257-pin pinout figure, changed cut2 to cut2/3 in Notes.
In the pin function summary table, changed cut2 to cut2/3.
In the “System pins” table:
• Added Note regarding Open Drain Enable.
• Added description to RESET pin.
In the pin-muxing table:
• Added Note about Open Drain.
• Changed cut2 to cut2/3.
• Changed all entries of column 'Weak pull config during reset’ to ' - ' , except for PCR[2],
PCR[3], PCR[4] and PCR[21].
In the “Absolute maximum ratings” table:
• Removed the “VSS_HV_REG” row.
• Added the footnote “Internal structures hold the input voltage...” to the VIN maximum
specifications.
In the “ conditions” table, removed the “VSS_HV_REG” row.
In the “Thermal characteristics” section:
• Added the “Thermal characteristics for 100 LQFP package“ table.
• Updated values and footnote 1 in the 144 package table.
• Updated footnote 1 in the 257 package table.
In the “Supply current characteristics“ table:
• Added footnote 1 to parameter “IDD_LV_TYP + IDD_LV_PLL“ (symbol “T”).
• Changed “IDD_LV_STOP” at 150C from 80mA to 72mA.
• Changed “IDD_LV_HALT” at 150C from 72mA to 80mA.
In the “FMPLL electrical characteristics” table:
• Deleted the footnote “This value is true when operating at frequencies above 60 MHz...”
from the specification for fCS and fDS
.
• Changed “fSYS” to “fFMPLLOUT” in the entries for the CJITTER, fLCK, fUL, fCS, and fDS
specifications.
In the “ADC conversion characteristics” table:
• Revised the entry for TUEIS1WINJ (was P/T and “Total unadjusted error for IS1WINJ”, is
T and “Total unadjusted error for IS1WINJ (single ADC channels)”).
• Revised the entry for TUEIS1WWINJ (was “Total unadjusted error for IS1WWINJ”, is
“Total unadjusted error for IS1WWINJ (double ADC channels)”).
In the “Temperature sensor electrical characteristics“ table, for TJ = TA to 125 °C, changed
Min/Max from values -7/+7 to -10/+10.
In the “Input Impedance and ADC Accuracy“ section:
• Changed CS in the text from 3 pF to 7.5 pF.
• Changed Req in the text from 330 k to 133 k.
• Removed RL, RSW, and RAD from the external network design constraint equation and
the sentence immediately preceding it.
• Changed the CF constraint value equation constant from 2048 to 8192.
• In the “ADC conversion characteristics“ table, changed INL Min/Max values from -2/+2
to -3/+3.
MPC5643L Microcontroller Data Sheet, Rev. 9
132
Freescale Semiconductor
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
• In Section 1.5.31, “eTimer module” changed text from “The MPC5643L provides three
eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144
LQFP package” to “The MPC5643L provides three eTimer modules (on the LQFP
package eTimer_2 is available internally only without any external I/O access)”.
• In Section 3.5, “Electromagnetic Interference (EMI) characteristics”,added additional
information at the end of this section.
• In Section 3.8, Voltage regulator electrical characteristics, added text related to
external ballast transistor.
• In Table 3 and Table 4 (257 MAPBGA pin function summary), moved EVTI from output
function to input function.
• In Table 6 (System pins), changed the direction for EXTAL from “Output Only” to
“Input/Output”.
• InTable 6, added table footnote for symbol “EXTAL”.
• Changed the row (TVdd) in Table 8 (Absolute maximum ratings).
• In Table 8, Maximum value for “VDD_HV_IOX” and “VDD_HV_FLA” changed from “3.6” to
“4.0”.
• In Table 20 (Current consumption characteristics), added max value 250 and 290 mA
for symbol IDD_LV_BIST+IDD_LV_PLL
.
• Added five additional RunIDD parameters in Table 20 (Current consumption
characteristics).
• In Table 21 (Temperature sensor electrical characteristics), changed condition for
parameter “Accuracy” from “-40°C to 25°C” to “-40°C to 150°C”
• In Table 23 (FMPLL electrical characteristics),added ‘150’ to the max value for ‘fSCM’ In
Table 24 (16 MHz RC oscillator electrical characteristics),changes done are:
fRC symbol- Added min value ‘15.04’ and max value ‘16.96’.Removed condition “TJ=25°C”
Removed row containing RCMVAR symbol.
• In Figure 8, added the name ‘CS’ to the capacitor in the internal circuit scheme.
• Removed references to Cut1 and Cut2:
Renamed Section ”Electromagnetic Interference (EMI) characteristics (cut1)” to
“Electromagnetic Interference (EMI) characteristics” .
In Table 25 (ADC conversion characteristics), removed reference to cut2 only for symbol
‘IS1WINJ’ and ‘TUEIS1WWINJ’.
In Section 1.1, Document overview, modified text to remove references to ‘Cut1’.
• In Table 25 (ADC conversion characteristics), for tCONV added ‘60 MHz’ to ‘conditions’
and ‘600’ to the ‘Min’ value.
Separated SNR into two specifications with conditions Vref 3.3 V and 5.0 V respectively.
Changed min value to ‘-72’ for symbol ‘THD’.
• In Table 25 (ADC conversion characteristics), changed ADC specification parameter
‘THD’ minimum limit from -72 to -65dB.
• In Table 26 (Flash memory program and erase electrical specifications), changes done
are as follows:
TDWPROGRAM, changed typical value from ‘39’ to ‘38’.
TPPROGRAM, changed typical value from ‘48’ to ‘45’ and intial max value from ‘100’ to ‘160’.
T16KPPERASE, inserted typical value ‘270’ and factory avg ‘1000’.
T48KPPERASE, inserted typical value ‘625’ and factory avg ‘1500’.
T64KPPERASE, inserted typical value ‘800’ and factory avg ‘1800’.
T128KPPERASE, inserted typical value ‘1500’ and factory avg ‘2600’.
T256KPPERASE, inserted typical value ‘3000’ and factory avg ‘5200’.
Updated table footnote and removed min column in Table 26 (Flash memory program and
erase electrical specifications)
• In Table 27 (Flash memory timing), added symbol TPSRT ,TESRT and added table
footnote for TPSRT ,TESRT .
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
133
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
• Added Table 29 (MPC5643L SWG Specifications)
• In Table 29 (MPC5643L SWG Specifications)
Added table footnote for Common Mode.
Changed text from “internal device pad resistance” to “internal device routing resistance”.
• Added Figure 26 in Section 3.20.4, “Nexus timing”.
• In Table 30 (Pad AC specifications (3.3 V , IPP_HVE = 0 )), removed the row of pad
“Pull Up/Downc(3.6 V max)”.
• In Table 40 (Orderable part number summary) and Figure 43, updated part numbers
(changed ‘PPC’ to ‘SPC’ and ‘F0’ to ‘F2’).
• Replaced Figure 39, Figure 40, Figure 41, Figure 42 with the new versions.
• InTable 18 (Voltage regulator electrical specifications),changed the symbol of spec
external decoupling capacitor from SR to Cext
.
In Figure 4, changed the ESR range in note text to 1 mW to 100 mW from 30 mW to
150 mW.
• In Section 1.5.32, “Sine Wave Generator (SWG)” removed the following text:
Frequency range from 1kHz to 50kHz.
Sine wave amplitude from 0.47 V to 2.26 V.
• In Table 20 (Current consumption characteristics)”,changed symbol from ‘C’ to ‘T’ ,
added “operating current” to the parameter and updated the maximum value for five
additional RunIDD parameters.
• In Table 20 (Current consumption characteristics), changed “Conditions” from ‘1.2 V
supplies’ to ‘1.2 V supplies during LBIST (full LBIST configuration)’ for all the
parameters.
• Removed Table “SWG electrical characteristics”.
• In Table 18 (Voltage regulator electrical specifications), changed the “Digital supply
high voltage detector upper threshold low limit (After a destructive reset initialization
phase completion)” from 1.43V to 1.38V.
• Added Table 17 (Recommended operating characteristics).
• Updated the IDD values in Table 20 (Current consumption characteristics). Changed
conditions text from “1.2 supplies during LBIST (full LBIST configuration)” to “1.2 V
supplies” for all the IDD parameters except IDD_LV_BIST+IDD_LV_PLL. Added footnote in
“Conditions” for the DPM mode.
• Removed Cut references from the whole document.
• In Table 25 (ADC conversion characteristics), changed the sampling frequency value
from ‘1 MHz’ to ‘983.6 KHz’.
8.1
07 May 2012 • Deleted the Footer "Preliminary-Subject to Change Without Notice" label.
MPC5643L Microcontroller Data Sheet, Rev. 9
134
Freescale Semiconductor
Document revision history
Table 41. Revision history (continued)
Description of changes
Revision
Date
9
12 June 2013 • Updated Table 18
—
added Digital supply low voltage detector lower threshold and Digital supply
low voltage detector upper threshold
—
Updated Main High Voltage Power-Low Voltage Detection value to 2.93 V
• Replaced IEC with ISO26262 in Section 1.1, “Document overview
• Table 1-removed KGD
• Table 24 modified fRC values
• Updated Table 26
• Updated Table 25-tconv to teval and associated footnote
• Updated Table 19
—
added VIH footnote
—
Updated IOL, IOH value for Fast pads
• Updated Table 31-TDRB and TELRB
• Updated Table 18-combined ESR of external capacitor values
• Updated Section 3.15.1, “Input Impedance and ADC Accuracy -replaced fc by fs
• Table 6-added footnote to RESET pin about weak pull down
• Updated Injection current information in Table 19-IINJ, Table 8-footnote 4
• Updated Table 20 for the following:
—
—
—
—
specified oscillator bypass mode and crystal oscillator mode
Updated STOP and HALT mode values
Added IDD_HV_PMU
footnote 2, footnote 3
• Added footnote VDD_HV_ADRx must always be applied and should be stable before
LBIST starts. to Table 9
• Added footnote to Section 5, “Ordering information
• Edit changes to Section 3.5, “Electromagnetic Interference (EMI) characteristics
• Updated Equation 16
MPC5643L Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
135
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Document Number: MPC5643L
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