935312823518_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5121E

Rev. 5, 02/2012

MPC5121E/MPC5123

516 TEPBGA

27 mm x 27 mm

MPC5121E/MPC5123 

Data Sheet

The MPC5121e/MPC5123 integrates a high performance

e300 CPU core based on the Power Architecture Technology

• On-chip temperature sensor

• IIM – IC Identification module

®

with a rich set of peripheral functions focused on

communications and systems integration.

Major features of the MPC5121e/MPC5123 are:

• e300 Power Architecture processor core

• Power modes include doze, nap, sleep, deep sleep, and

hibernate

• AXE – Auxiliary Execution Engine

• MBX Lite – 2D/3D graphics engine (not available in

MPC5123)

• DIU – Display interface unit

• DDR1, DDR2, and LPDDR/mobile-DDR SDRAM

memory controller

• MEM – 128 KB on-chip SRAM

• USB 2.0 OTG controller with integrated physical layer

(PHY)

• DMA subsystem

• EMB – Flexible multi-function external memory bus

interface

• NFC – NAND flash controller

• LPC – LocalPlus interface

• 10/100Base Ethernet

• PCI interface, version 2.3

• PATA – Parallel ATA integrated development environment

(IDE) controller

• SATA – Serial ATA controller with integrated physical

layer (PHY)

• SDHC – MMC/SD/SDIO card host controller

• PSC – Programmable serial controller

2

• I C – inter-integrated circuit communication interfaces

• S/PDIF – Serial audio interface

• CAN – Controller area network

• BDLC – J1850 interface

• VIU – Video Input, ITU-656 compliant

• RTC – On-Chip real-time clock

Table of Contents

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1

2

3.3.11 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.12 USB ULPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3.13 On-Chip USB PHY. . . . . . . . . . . . . . . . . . . . . . 60

3.3.14 SDHC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3.15 DIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.3.16 SPDIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.17 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.18 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.19 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.3.20 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.3.21 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 73

3.3.22 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.3.23 IEEE 1149.1 (JTAG). . . . . . . . . . . . . . . . . . . . . 74

3.3.24 VIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.1 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . . . . 76

4.2 System and CPU Core AVDD Power Supply Filtering. 76

4.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 77

4.4 Pull-Up/Pull-Down Resistor Requirements . . . . . . . . . 78

4.4.1 Pull-Down Resistor Requirements for TEST pin78

4.4.2 Pull-Up Requirements for the PCI Control Lines78

4.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.5.1 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.5.2 e300 COP/BDM Interface . . . . . . . . . . . . . . . . 79

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 83

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 516-TEPBGA Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.2 Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Electrical and Thermal Characteristics. . . . . . . . . . . . . . . . . .17

3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .17

3.1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . .17

3.1.2 Recommended Operating Conditions . . . . . . . .18

3.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .19

3.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .22

3.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .23

3.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .24

3.2 Oscillator and PLL Electrical Characteristics . . . . . . . .25

3.2.1 System Oscillator Electrical Characteristics . . .26

3.2.2 RTC Oscillator Electrical Characteristics. . . . . .26

3.2.3 System PLL Electrical Characteristics. . . . . . . .26

3.2.4 e300 Core PLL Electrical Characteristics . . . . .27

3.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .28

3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .28

3.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .32

3.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .32

3.3.6 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.7 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.3.8 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

3.3.9 PATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

3.3.10 SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3

4

5

6

MPC5121E/MPC5123 Data Sheet, Rev. 5

2

Freescale Semiconductor

Ordering Information

Figure 1 shows a simplified MPC5121e/MPC5123 block diagram.

Display DDR1/DDR2 Memory

Functionally

Multiplexed I/O

not available in MPC5123

AXE

Engine

8 KB

Instruc-

tion

MBX Lite

Graphics Engine with

Vector Processing

Multi-Port

Memory Controller

FEC

LPC

NFC

PATA

VIU DIU

USB2

+ PHY

DMA

64-Channel

Cache

128 KB

SRAM

USB2

ULPI

JTAG/COP

SATA

+ PHY

RESET/

CLOCK

e300

Power Architecture

32 KB Instruction Cache

32 KB Data Cache

PCI

Temp

Fuse

83 MHz (max) IP Bus

Figure 1. Simplified MPC5121e/MPC5123 Block Diagram

1

Ordering Information

Table 1. MPC5121e Orderable Part Numbers

Temperature

(ambient)

Freescale Part Number

Speed (MHz)

Qualification

Package

Availability

MPC5121VY400B

MPC5121VY400BR

MPC5121YVY400B

MPC5121YVY400BR

SPC5121YVY400B

SPC5121YVY400BR

400

0 ^oC to 70 ^oC

Consumer

Industrial

RoHS and Pb-free

RoHS and Pb-free Tape and Reel

RoHS and Pb-free Tray

RoHS and Pb-free Tape and Reel

Tray

Automotive—AEC RoHS and Pb-free Tape and Reel

Tray

–40 ^oC to 85 ^oC

Automotive—AEC RoHS and Pb-free

Table 2. MPC5123 Orderable Part Numbers

Temperature

Freescale Part Number

Speed (MHz)

Qualification

Package

Availability

(ambient)

MPC5123VY400B

MPC5123VY400BR

MPC5123YVY400B

400

0 ^oC to 70 ^oC

–40 ^oC to 85 ^oC

Consumer

Industrial

RoHS and Pb-free

Tray

Tape and Reel

Tray

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

3

Ordering Information

Freescale Part Number

Table 2. MPC5123 Orderable Part Numbers (continued)

Temperature

Speed (MHz)

Qualification

Package

Availability

(ambient)

MPC5123YVY400BR

SPC5123YVY400B

SPC5123YVY400BR

400

–40 ^oC to 85 ^oC

Industrial

RoHS and Pb-free

Tape and Reel

Tray

Automotive—AEC RoHS and Pb-free

Tape and Reel

MPC5121E/MPC5123 Data Sheet, Rev. 5

4

Freescale Semiconductor

Pin Assignments

2

Pin Assignments

This section details pin assignments.

2.1

516-TEPBGA Ball Map

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

SATA_

RX_VS

SA

USB2_

DRVVB

US

SATA_ SATA_

PSC7_ PSC7_ PSC6_ PSC6_ PSC6_ PSC11 PSC10 PSC2_ PSC1_ PSC1_ PSC0_ CAN1_ GPIO2 RTC_X

USB_D USB_D USB_T

A

B

VSS

RXN

RXP

4

3

4

2

0

_0

_2

3

1

TX

8

TALO

VSS

M

P

PA

USB2_

VBUS_

PWR_F

AULT

SATA_

VSS RX_VS VSS

SA

USB_V

VSS SSA_B

IAS

PSC8_

3

PSC7_ PSC6_ VDD_I PSC11

PSC10 PSC2_ VDD_I PSC0_

_1

GPIO3 CAN2_

RX

USB_X VDD_I

TALO

VSS

0

3

O

_1

1

O

4

1

O

SATA_

VSS VDDA_

1P2

AVDD_

FUSE

WR

PSC_

MCLK_

IN

SATA_ SATA_

XTALO XTALI

PSC9_ PSC8_ PSC7_

PSC6_ PSC11 PSC10 PSC10 PSC2_ PSC1_ PSC0_

GPIO3 CAN1_ RTC_X USB_V USB_V

RX TALI DDA SSA

USB_X

TALI

PCI_C

LK

C

D

VSS

0

2

1

_2

_3

_0

0

3

0

SATA_

SATA_ SATA_ SATA_

VDDA_ VSS PLL_V VDDA_ VDDA_

USB_V USB_P

DDA_B LL_PW VSS

IAS R3

PSC9_ PSC9_ PSC8_ VDD_I VDD_I PSC11

PSC2_ PSC1_ VDD_I PSC0_

HIB_M VBAT_ USB_V USB_V

PCI_R

EQ2

VSS

3

1

O

_4

4

O

0

ODE

RTC

DDA

BUS

1P2

SSA

3P3

VREG

SATA_V SATA_P

DDA_1 LL_VDD

SATA_

TXN

SATA_R SATA_A PSC9_ PSC9_ PSC8_ PSC8_ PSC7_ PSC11 PSC10 PSC2_ PSC1_ PSC0_ CAN2_ GPIO2

USB_U USB_V USB_V USB_R USB_PL PCI_G PCI_G PCI_R

E

F

VSS

ESREF NAVIZ

4

2

4

0

1

_3

_4

2

TX

9

ID

SSA

REF

L_GND

NT2

NT0

EQ1

P2

A1P2

SATA_

TXP

VDD_I

O

VDD_I VDD_I

VDD_I

O

PCI_RS VDD_I PCI_A VDD_I PCI_A

T_OUT D30 D28

VSS

O

SATA_

TX_VS

SA

NFC_R NFC_ NFC_

WE WP

PCI_G PCI_R PCI_A PCI_A PCI_C/

G

H

J

E

NT1

EQ0

D29

D26

BE3

NFC_R PATA_ NFC_C NFC_A NFC_C

VDD_I PCI_A

PCI_A

D24

PCI_A

D21

VSS

/B

DACK

E0

LE

O

D31

PATA_I

OCHR

DY

PATA_I

OR

PATA_I PATA_ VDD_I

PCI_A PCI_A PCI_A PCI_A PCI_A

D27 D25 D23 D20 D18

NTRQ DRQ

PATA_I

SOLAT

E

O

PATA_ VDD_I

VDD_I PATA_I

VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C

PCI_ID PCI_A PCI_A PCI_A PCI_IR

SEL D22 D19 D17 DY

K

VSS

CE1

O

OW

ORE

VSS

ORE

VSS

ORE

VSS

ORE

VSS

ORE

VSS

ORE

VSS

ORE

EMB_A EMB_A EMB_A EMB_A PATA_

VDD_C

ORE

VDD_C

ORE

PCI_A VDD_I PCI_C/ VDD_I PCI_D

D16 BE2 EVSEL

L

M

N

P

R

T

D03

D02

D01

D00

CE2

O

EMB_A

D06

EMB_A

D05

EMB_A

D04

VDD_C

ORE

VDD_C

ORE

PCI_T PCI_F PCI_S PCI_P PCI_S

VSS

RDY

RAME

TOP

ERR

EMB_A EMB_A EMB_A EMB_A

D10 D09 D08 D07

VDD_I

O

VDD_C

ORE

VDD_C

ORE

VDD_I PCI_P

AR

PCI_C/

BE1

PCI_A

D15

VSS

O

EMB_A EMB_A EMB_A EMB_A EMB_A VDD_I

VDD_C

ORE

VDD_C

ORE

VDD_I PCI_C/ PCI_A PCI_A PCI_A PCI_A

D15

D14

D11

D13

D12

O

BE0

D09

D13

D14

D12

EMB_A VDD_I EMB_A VDD_I EMB_A

D17 D16 D19

VDD_C

ORE

VDD_C

ORE

PCI_A PCI_A PCI_A PCI_A PCI_A

D03 D06 D10 D11 D08

O

EMB_A EMB_A EMB_A EMB_A EMB_A

VDD_C

ORE

VDD_C

ORE

SYS_PL VDD_I PCI_A VDD_I PCI_A

L_AVDD D05 D07

VSS

D22

D18

D20

D21

D23

O

EMB_A

D25

EMB_A

D24

EMB_A

D29

VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C

SYS_PL PCI_IN PCI_A PCI_A PCI_A

U

V

W

Y

VSS

ORE

L_AVSS

TA

D00

D02

D04

EMB_A EMB_A EMB_A EMB_A EMB_A

D26 D27 D28 D30 X01

SRESE

T

SYS_X

TALI

PCI_A

D01

VSS

EMB_A EMB_A EMB_A LPC_A LPC_C VDD_I

VDD_I

O

PORE HRES

SYS_X

TALO

TDO

TEST

TMS

D31

X00

X02

X03

S0

O

SET

ET

LPC_C VDD_I LPC_C VDD_I LPC_O

S2 S1

J1850_

TX

CKSTP

_OUT

TDI

VSS

O

E

VDD_

MEM_I

O

VDD_ VDD_

MEM_I MEM_I

CORE

_PLL_

AVDD

LPC_R LPC_A PSC4_ LPC_C PSC4_

I2C2_S VDD_I J1850_ VDD_I

AA

AB

AC

AD

VSS

MA1

VSS

TRST

TCK

WB

CK

1

LK

3

DA

O

RX

O

VDD_

SPDIF

PSC4_

0

PSC4_

2

PSC3_

1

MDQ1

0

MVRE MDQ1 MDQ2 MDQ2 MDQ3

I2C1_S I2C1_S

VSS

MDQ1 MVTT0 MDQ5

MA5 MEM_I MA14 MCKE _TXCL

VSS

IRQ1

F

9

1

7

1

CL

DA

O

K

VDD_

MEM_I

O

VDD_

MEM_I

O

VDD_

PSC5_ PSC4_ PSC5_ PSC3_

MDQ1

4

MDQS

2

MDQ2

5

MDQ3

0

I2C0_S SPDIF I2C2_S

MEM_I MDM0 MDQ8

O

VSS

MBA1

MBA0

VSS

MA0

VSS

MA7

MA11 MEM_I MODT

O

VSS

IRQ0

0

4

1

2

CL

_RX

CL

VDD_

MEM_I

O

CORE

MCS _PLL_

AVSS

PSC5_ PSC5_

PSC3_ MDQS

MDQ1 MDQS

MDQ1 MDQ1 MDQ2 MDQ2 MDQS MDQ2

SPDIF

_TX

I2C0_S

DA

VSS

MDQ6

MA4

MA9

MA13 MWE

VSS

2

3

0

1

6

8

0

3

9

VDD_

MEM_I MVTT2 VSS

O

VDD_

VDD_I VDD_I PSC5_

MDQ1

2

MDQ2

4

MDQ2

8

VDD_I VDD_I

AE

AF

MDQ2 MEM_I MDQ7

O

VSS

MDM1

MVTT3 MEM_I

O

MA2

MCK

MA6 MEM_I MA12 MA15

O

VSS

O

4

O

VDD_I PSC3_ PSC3_

MDQ1 MDQ1 MDQ1

3

MDQ2 MDQ2

2

VDD_I

O

MDQ0 MDQ3 MDQ4 MDQ9 MVTT1

MDM2

MDM3 MCK

MBA2

MA3

MA8

MA10 MRAS MCAS

O

0

4

5

7

6

Figure 2. Ball Map for the MPC5121e 516 TEPBGA Package

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

5

Pin Assignments

2.2

Pinout Listings

Table 3 provides the pin-out listing for the MPC5121e/MPC5123.

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 1 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

DDR Memory Interface (67 Total)

MDQ0

MDQ1

AF5

AB6

DDR

V_{DD_MEM_IO}

—

MDQ2

AE4

MDQ3

AF6

MDQ4

AF7

MDQ5

AB8

MDQ6

AD6

MDQ7

AE6

MDQ8

AC7

MDQ9

AF8

MDQ10

MDQ11

MDQ12

MDQ13

MDQ14

MDQ15

MDQ16

MDQ17

MDQ18

MDQ19

MDQ20

MDQ21

MDQ22

MDQ23

MDQ24

MDQ25

MDQ26

MDQ27

MDQ28

MDQ29

MDQ30

AB9

AD7

AE9

AF10

AC9

AF11

AD10

AF12

AD11

AB12

AD12

AB13

AF14

AD13

AE13

AC13

AF15

AB14

AE16

AD15

AC15

MPC5121E/MPC5123 Data Sheet, Rev. 5

6

Freescale Semiconductor

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 2 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

MDQ31

MDM0

MDM1

MDM2

MDM3

MDQS0

MDQS1

MDQS2

MDQS3

MBA0

MBA1

MBA2

MA0

AB15

AC6

DDR

V_{DD_MEM_IO}

—

AE8

AF13

AF16

AD5

AD8

AC11

AD14

AD16

AC16

AF19

AD17

AB16

AE18

AF20

AD18

AB17

AE19

AC18

AF21

AD19

AF22

AC19

AE21

AD20

AB19

AE22

AD21

AF23

AF24

AD22

AB20

AF17

AF18

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

MA10

MA11

MA12

MA13

MA14

MA15

MWE

MRAS

MCAS

MCS

MCKE

MCK

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

7

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 3 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

MODT

AC21

DDR

V_{DD_MEM_IO}

—

LPC Interface (8 Total)

LPC_CLK

LPC_OE

AA4

Y5

General IO

V_{DD_IO}

—

LPC_RW

LPC_CS0

LPC_CS1

LPC_CS2

LPC_ACK

LPC_AX03

AA1

W5

Y3

Y1

AA2

W4

EMB Interface (35 Total)

EMB_AX02

EMB_AX01

EMB_AX00

EMB_AD31

EMB_AD30

EMB_AD29

EMB_AD28

EMB_AD27

EMB_AD26

EMB_AD25

EMB_AD24

EMB_AD23

EMB_AD22

EMB_AD21

EMB_AD20

EMB_AD19

EMB_AD18

EMB_AD17

EMB_AD16

EMB_AD15

EMB_AD14

EMB_AD13

EMB_AD12

W3

V5

W2

W1

V4

U5

V3

V2

V1

U1

U3

T5

T1

T4

T3

R5

T2

R1

R3

P1

P2

P4

P5

General IO

V_{DD_IO}

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

8

Freescale Semiconductor

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 4 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

EMB_AD11

EMB_AD10

EMB_AD09

EMB_AD08

EMB_AD07

EMB_AD06

EMB_AD05

EMB_AD04

EMB_AD03

EMB_AD02

EMB_AD01

EMB_AD00

P3

N1

N2

N3

N4

M1

M3

M5

L1

General IO

V_{DD_IO}

—

L2

L3

L4

PATA Interface (9 Total)

PATA_CE1

PATA_CE2

K1

L5

K3

J1

K5

J2

J3

J4

H2

General IO

V_{DD_IO}

ATA name: CS0

ATA name: CS1

—

PATA_ISOLATE

PATA_IOR

ATA name: DIOR

ATA name: DIOW

ATA name: IORDY

—

PATA_IOW

PATA_IOCHRDY

PATA_INTRQ

PATA_DRQ

ATA name: DMARQ

ATA name: DMACK

PATA_DACK

NFC Interface (7 Total)

NFC_WP

NFC_R/B

NFC_WE

NFC_RE

NFC_ALE

NFC_CLE

NFC_CE0

G4

H1

G3

G2

H4

H5

H3

General IO

V_{DD_IO}

—

I2C Interface (6 Total)

I2C0_SCL

I2C0_SDA

I2C1_SCL

AC23

AD26

AB22

General IO

V_{DD_IO}

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

9

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 5 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

I2C1_SDA

I2C2_SCL

I2C2_SDA

AB23

AC25

AA22

General IO

V_{DD_IO}

—

IRQ Interface (2 Total)

IRQ0

IRQ1

AC26

AB25

General IO

V_{DD_IO}

—

CAN Interface (4 Total)

CAN1_RX

CAN1_TX

CAN2_RX

CAN2_TX

C19

A18

B19

E16

Analog Input

General IO

Analog Input

General IO

VBAT_RTC

V_{DD_IO}

—

VBAT_RTC

V_{DD_IO}

J1850 Interface (2 Total)

J1850_TX

J1850_RX

Y22

General IO

V_{DD_IO}

—

AA24

SPDIF Interface (3 Total)

SPDIF_TXCLK

SPDIF_TX

AB21

AD24

AC24

General IO

V_{DD_IO}

—

SPDIF_RX

PCI (54 Total)

PCI_INTA

PCI_RST_OUT

PCI_AD00

PCI_AD01

PCI_AD02

PCI_AD03

PCI_AD04

PCI_AD05

PCI_AD06

PCI_AD07

PCI_AD08

PCI_AD09

PCI_AD10

PCI_AD11

PCI_AD12

U23

F22

U24

V26

U25

R22

U26

T24

R23

T26

R26

P23

R24

R25

P26

PCI

V_{DD_IO}

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

10

Freescale Semiconductor

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 6 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

PCI_AD13

PCI_AD14

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

PCI_AD21

PCI_AD22

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD26

PCI_AD27

PCI_AD28

PCI_AD29

PCI_AD30

PCI_AD31

PCI_C/BE0

PCI_C/BE1

PCI_C/BE2

PCI_C/BE3

PCI_PAR

P24

P25

N26

L22

K25

J26

PCI

V_{DD_IO}

—

K24

J25

H26

K23

J24

H24

J23

G25

J22

F26

G24

F24

H22

P22

N24

L24

G26

N22

M23

M22

K26

M24

L26

K22

M26

M25

G23

E26

D26

—

1

PCI_FRAME

PCI_TRDY

PCI_IRDY

PCI_STOP

PCI_DEVSEL

PCI_IDSEL

PCI_SERR

PCI_PERR

PCI_REQ0

PCI_REQ1

PCI_REQ2

1

—

1

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

11

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 7 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

PCI_GNT0

PCI_GNT1

PCI_GNT2

PCI_CLK

E25

G22

E24

C26

PCI

V_{DD_IO}

—

PSC Interface (61 Total)

PSC_MCLK_IN

PSC0_0

PSC0_1

PSC0_2

PSC0_3

PSC0_4

PSC1_0

PSC1_1

PSC1_2

PSC1_3

PSC1_4

PSC2_0

PSC2_1

PSC2_2

PSC2_3

PSC2_4

PSC3_0

PSC3_1

PSC3_2

PSC3_3

PSC3_4

PSC4_0

PSC4_1

PSC4_2

PSC4_3

PSC4_4

PSC5_0

PSC5_1

PSC5_2

C17

D16

A17

E15

C16

B16

C15

A16

E14

A15

D14

C14

B14

E13

A14

D13

AF3

AB5

AC4

AD4

AF4

AB1

AA3

AB3

AA5

AC2

AC1

AC3

AD1

General IO

V_{DD_IO}

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

12

Freescale Semiconductor

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 8 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

PSC5_3

PSC5_4

PSC6_0

PSC6_1

PSC6_2

PSC6_3

PSC6_4

PSC7_0

PSC7_1

PSC7_2

PSC7_3

PSC7_4

PSC8_0

PSC8_1

PSC8_2

PSC8_3

PSC8_4

PSC9_0

PSC9_1

PSC9_2

PSC9_3

PSC9_4

PSC10_0

PSC10_1

PSC10_2

PSC10_3

PSC10_4

PSC11_0

PSC11_1

PSC11_2

PSC11_3

PSC11_4

AD2

AE3

A11

C10

A10

B9

General IO

V_{DD_IO}

—

A9

B8

E10

C8

A8

A7

E9

D8

C7

B6

E8

C6

D7

E7

D6

E6

C13

B13

A13

C12

E12

A12

B11

C11

E11

D11

JTAG (5 Total)

2

TCK

AB26

General IO

V_{DD_IO}

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

13

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 9 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

3

TDI

TDO

TMS

TRST

Y23

W22

Y25

General IO

V_{DD_IO}

—

3

AA26

Test / Debug (2 Total)

4

5

TEST

W25

Y26

General IO

V_{DD_IO}

,

CKSTP_OUT

—

System Control (3 Total)

6

2

HRESET

PORESET

SRESET

W24

W23

V22

General IO

V_{DD_IO}

,

4 2

,

6 2

,

System Clock (2 Total)

SYS_XTALI

SYS_XTALO

V24

Analog Input

SYS_PLL_AVDD

Oscillator Input

W26

Analog Output SYS_PLL_AVDD

RTC (3 Total)

Analog Input

Oscillator Output

RTC_XTALI

RTC_XTALO

HIB_MODE

C20

A20

D18

VBAT_RTC

Oscillator Input

Oscillator Output

—

Analog Output

GP Input Only (4 Total)

GPIO28

GPIO29

GPIO30

GPIO31

A19

E17

C18

B18

Analog Input

VBAT_RTC

—

DDR Reference Voltage

MVREF

AB11

Analog Input Voltage Reference for SSTL input pads

USB – PHY without Power and Ground Supplies (7 Total)

USB_XTALI

USB_XTALO

USB_DP

C24

B24

A23

A22

A24

Analog Input

USB_PLL_PWR3

Oscillator Input

Analog Output USB_PLL_PWR3

Oscillator Output

Analog IO

USB_VDDA

—

USB_DM

USB_TPA

Analog Output

USB PHY

debug output

USB_VBUS

D21

Analog IO

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

14

Freescale Semiconductor

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 10 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

USB_UID

E19

Analog Input

—

USB digital IOs (2 Total)

USB2_VBUS_PWR_FA

ULT

B21

A21

General IO

V_{DD_IO}

—

USB2_DRVVBUS

General IO

SATA PHY without Power and Ground Supplies (7 Total)

SATA_XTALI

SATA_XTALO

SATA_ANAVIZ

C3

C2

E5

Analog Input SATA_VDDA_3P3

Oscillator Input

Analog Output SATA_VDDA_3P3 Oscillator Output

Analog Output

—

SATA PHY debug

output

SATA_TXN

SATA_TXP

SATA_RXP

SATA_RXN

E1

F1

A5

A4

Analog Output SATA_VDDA_1P2

Analog Input SATA_VDDA_1P2

—

Power and Ground Supplies (without SATA PHY and USB PHY)

V_{DD_CORE}

K10, K11, K12, K13,

K14, K15, K16, K17,

L10, L17, M10, M17,

N10, N17, P10, P17,

R10, R17, T10, T17,

U10, U11, U12, U13,

U14, U15, U16, U17

Power

—

V_{DD_IO}

B10, B15, B25, D9,

D10, D15, F11, F13,

F14, F19, F23, F25,

H21, J5, K2, K4, L23,

L25, N6, N21, P6,

P21, R2, R4, T23,

T25, W6, W21, Y2,

Y4, AA23, AA25, AE1,

AE2, AE24, AE25,

AF2, AF25

Power

—

V_{DD_MEM_IO}

AA8, AA13, AA14,

AB18, AC5, AC10,

AC14, AC20, AD9,

AE5, AE10, AE15,

AE20

Power

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

15

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 11 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

V_SS

A2, A3, A25, B1,B2,

B3, B5, B7, B12, B17,

B20, B22, B26, C1,

C4, C23, C25, D2,

D12, D17, D24, D25,

E18, F2, F3, F4, F5,

F6, F8, F10, F16, F17,

F21, G5, H6, H23,

H25, K6, K21, L6, L11,

L12, L13, L14, L15,

L16, L21, M2, M4,

M11, M12, M13, M14,

M15, M16, N5, N11,

N12, N13, N14, N15,

N16,

Ground

—

V_SS

N23, N25, P11, P12,

P13, P14, P15, P16,

R11, R12, R13, R14,

R15, R16, T6, T11,

T12, T13, T14, T15,

T16, T21, U2, U4, U6,

U21, V23, V25, Y24,

AA6, AA10, AA11,

AA16, AA17, AA21,

AB2, AB4, AB10,

Ground

—

AB24, AC8, AC12,

AC17, AC22, AD3,

AD25, AE7, AE12,

AE17, AE23, AE26

SYS_PLL_AVDD

SYS_PLL_AVSS

CORE_PLL_AVDD

CORE_PLL_AVSS

VBAT_RTC

T22

U22

Analog Power

Analog Ground

Analog Power

Analog Ground

Power

—

AA19

AD23

D19

AVDD_FUSEWR

MVTT0

C9

Power

AB7

AF9

Analog Input SSTL(DDR2) Termination (ODT) Voltage

MVTT1

MVTT2

AE11

AE14

MVTT3

Power and Ground Supplies (USB PHY)

USB_PLL_GND

USB_PLL_PWR3

USB_RREF

E23

D23

E22

B23

Analog Ground

Analog Power

Analog Ground

—

USB_VSSA_BIAS

MPC5121E/MPC5123 Data Sheet, Rev. 5

16

Freescale Semiconductor

Pin Assignments

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 12 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

USB_VDDA_BIAS

USB_VSSA

D22

Analog Power

Analog Ground

Analog Power

—

C22, E20, E21

C21, D20

USB_VDDA

Power and Ground Supplies (SATA PHY)

SATA_RESREF

SATA_VDDA_3P3

SATA_VDDA_1P2

SATA_VDDA_VREG

SATA_PLL_VDDA1P2

SATA_PLL_VSSA

SATA_RX_VSSA

SATA_TX_VSSA

E4

D4

Analog Power

Analog Ground

—

C5, D1, E2

D5

E3

D3

A6, B4

G1

1

This pins should have an external pull-up resistor. Follow PCI specification and see System Design

Information.

2

3

4

5

6

This pin contains an enabled internal Schmitt trigger.

These JTAG pins have internal pull-up P-FETs. This pin can not be configured.

This pin is an input only. This pin can not be configured.

This test pin must be tied to V_SS

.

This pin is an input or open-drain output. This pin can not be configured. There is an internal pull-up resistor

implemented.

NOTE

This table indicates only the pins with permananently enabled internal pull-up, pull-down,

or Schmitt trigger. Most of the digital I/O pins can be configured to enable internal pull-up,

pull-down, or Schmitt trigger. See the MPC5121e Microcontroller Reference Manual, IO

Control chapter.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

17

Electrical and Thermal Characteristics

3

Electrical and Thermal Characteristics

3.1

DC Electrical Characteristics

3.1.1

Absolute Maximum Ratings

The tables in this section describe the MPC5121e/MPC5123 DC Electrical characteristics. Table 4 gives the absolute maximum

ratings.

1

Table 4. Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

SpecID

Supply voltage – e300 core and peripheral logic

Supply voltage – I/O buffers

V_{DD_CORE}

–0.3

1.47

3.6

2.6

1.47

3.6

V

D1.1

D1.2

V_{DD_IO}

,

V_{DD_MEM_IO}

Input reference voltage (DDR/DDR2)

Termination Voltage (DDR2)

MVREF

MVTT

Supply voltage – System APLL, System Oscillator

Supply voltage – e300 APLL

SYS_PLL_AVDD

CORE_PLL_AVDD

VBAT_RTC

D1.3

D1.4

Supply voltage – RTC (Hibernation)

Supply voltage – FUSE Programming

Supply voltage – SATA PHY analog

Supply voltage – SATA PHY voltage regulator

Supply voltage – SATA PHY Tx/Rx

Supply voltage – SATA PHY PLL

D1.5

AVDD_FUSEWR

SATA_VDDA_3P3

SATA_VDDA_VREG

SATA_VDDA_1P2

SATA_PLL_VDDA1P2

USB_PLL_PWR3

USB_VDDA

D1.6

D1.8

D1.9

D1.10

D1.11

D1.12

D1.13

D1.14

D1.15

D1.16

Supply voltage – USB PHY PLL and OSC

Supply voltage – USB PHY transceiver

Supply voltage – USB PHY bandgap bias

Input voltage – USB PHY cable

USB_VDDA_BIAS

USB_VBUS

Input voltage (V_{DD_IO}

)

Vin

V_{DD_IO}

+ 0.3

Input voltage (V_{DD_MEM_IO}

)

Vin

–0.3

V_{DD_MEM_IO}

+ 0.3

V

D1.17

D1.18

Input voltage (VBAT_RTC)

VBAT_RTC

+ 0.3

Input voltage overshoot

Input voltage undershoot

Storage temperature range

Vinos

Vinus

Tstg

—

1

V

D1.19

D1.20

D1.21

55

150

^oC

1

Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses

beyond those listed may affect device reliability or cause permanent damage.

MPC5121E/MPC5123 Data Sheet, Rev. 5

18

Freescale Semiconductor

Electrical and Thermal Characteristics

3.1.2

Recommended Operating Conditions

Table 5 gives the recommended operating conditions.

Table 5. Recommended Operating Conditions

3)

Characteristic

Symbol

Min¹

Typ

Max¹

Unit SpecID

Supply voltage – e300 core and peripheral

logic

V_{DD_CORE}

1.33

1.4

1.47

V

D2.1

State Retention voltage – e300 core and

peripheral logic ²

1.08

V

D2.2

—

Supply voltage – standard I/O buffers

V_{DD_IO}

3.0

2.3

1.7

3.3

2.5

1.8

3.6

2.7

1.9

V

D2.3

D2.4

D2.5

Supply voltage – memory I/O buffers (DDR)

V_{DD_MEM_IO_DDR}

Supply voltage – memory I/O buffers (DDR2,

LPDDR)

V_{DD_MEM_IO_DDR2}

V_{DD_MEM_IO_LPDDR}

Input Reference Voltage (DDR/DDR2)

MVREF

0.49 ×

V_{DD_MEM_IO}

0.50 ×

V_{DD_MEM_IO}V_{DD_MEM_IO}

0.51 ×

V

D2.6

D2.7

D2.8

Termination Voltage (DDR2)

MVTT

MVREF

– 0.04

MVREF

+ 0.04

Supply voltage – System APLL, System

Oscillator

SYS_PLL_AVDD

3.0

3.3

3.6

Supply voltage – e300 APLL

CORE_PLL_AVDD

VBAT_RTC

3.0

3.3

3.0

1.7

1.14

1.33

3.0

1.4

0

3.3

3.6

V

D2.9

Supply voltage – RTC (Hibernation)³

D2.10

D2.11

D2.13

D2.14

D2.15

D2.16

D2.17

D2.18

D2.19

D2.20

D2.21

D2.22

Supply voltage – FUSE Programming

AVDD_FUSEWR

3.6

Supply voltage – SATA PHY analog and OSC SATA_VDDA_3P3

Supply voltage – SATA PHY voltage regulator SATA_VDDA_VREG

3.3

3.6

2.6

Supply voltage – SATA PHY Tx/Rx

Supply voltage – SATA PHY PLL

SATA_VDDA_1P2

SATA_PLL_VDDA1P2

USB_PLL_PWR3

USB_VDDA

1.2

1.4

3.3

—

1.47

3.6

Supply voltage – USB PHY PLL and OSC

Supply voltage – USB PHY transceiver

Supply voltage – USB PHY bandgap bias

Input voltage – USB PHY cable

3.6

USB_VDDA_BIAS

USB_VBUS

3.6

Input voltage – standard I/O buffers

Input voltage – memory I/O buffers (DDR)

Vin

—

V_{DD_IO}

Vin_DDR

0

V_{DD_MEM_IO}

—

_DDR

Input voltage – memory I/O buffers (DDR2)

Input voltage – memory I/O buffers (LPDDR)

Vin_DDR2

0

V_{DD_MEM_I}

V

D2.23

D2.24

O_DDR2

Vin_LPDDR

V_{DD_MEM_I}

O_LPDR

Ambient operating temperature range

Junction operating temperature range

TA

TJ

–40

—

+85

^oC D2.25

^oC D2.26

+125

1

2

3

These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.

The State Retention voltage can be applied to V_{DD_CORE}after the device is placed in Deep-Sleep mode.

VBAT_RTC should not be supplied by a battery of voltage less than 3.0 V.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

19

Electrical and Thermal Characteristics

3.1.3

DC Electrical Specifications

Table 6 gives the DC Electrical characteristics for the MPC5121e/MPC5123 at recommended operating conditions.

Table 6. DC Electrical Specifications

Characteristic

Condition

Symbol

Min

Max

Unit SpecID

Input high voltage

Input type = TTL V_{DD_IO}

V_IH

0.51 × V_{DD_IO}

MVREF + 0.15

MVREF + 0.125

—

V

D3.1

D3.2

D3.3

Input type = TTL V_{DD_MEM_IO_DDR}

Input type = TTL

V_{DD_MEM_IO_DDR2}

Input high voltage

Input type =



V_IH

0.7 ×

—

V

D3.4

TTL V_{DD_MEM_IO_LPDDR}

Input type = PCI V_{DD_IO}

Input type = Schmitt V_{DD_IO}

V_{DD_MEM_IO_LPDDR}

Input high voltage

V_IH

0.5 × V_{DD_IO}

0.65 × V_{DD_IO}

—

V

D3.5

D3.6

D3.7

SYS_XTALI crystal mode¹

Bypass mode²

CV_IH

Vxtal + 0.4V

(V_{DD_IO}/2) + 0.4V

Input high voltage

SATA_XTALI crystal mode

Bypass mode

SV_IH

UV_IH

RV_IH

Vxtal + 0.4V

(V_{DD_IO}/2) + 0.4V

—

V

D3.8

D3.9

USB_XTALI crystal mode

Bypass mode

Vxtal + 0.4V

(V_{DD_IO}/2) + 0.4V

RTC_XTALI crystal mode³

(VBAT_RTC/5)

+ 0.5V

(VBAT_RTC/2)

+ 0.4V

D3.10

Bypass mode⁴

Input low voltage

Input type = TTL V_{DD_IO}

V_IL

—

0.42 × V_{DD_IO}

MVREF – 0.15

MVREF – 0.125

V

D3.11

D3.12

D3.13

Input type = TTL V_{DD_MEM_IO_DDR}

Input type = TTL

V_{DD_MEM_IO_DDR2}

Input low voltage

Input type = 

V_IL

—

0.3 ×

V

D3.14

TTL V_{DD_MEM_IO_LPDDR}

V_{DD_MEM_IO_LPDDR}

Input low voltage

Input type = PCI V_{DD_IO}

V_IL

—

0.3 × V_{DD_IO}

0.35 × V_{DD_IO}

V

D3.15

D3.16

D3.17

Input type = Schmitt V_{DD_IO}

SYS_XTALI crystal mode

Bypass mode

CV_IL

Vxtal – 0.4

(V_{DD_IO}/2) – 0.4

Input low voltage

SATA_XTALI crystal mode

Bypass mode

SV_IL

UV_IL

RV_IL

I_IN

Vxtal – 0.4 V

(V_{DD_IO}/2) – 0.4

V

D3.18

D3.19

D3.20

—

USB_XTALI crystal mode

Bypass mode

Vxtal – 0.4

(V_{DD_IO}/2) – 0.4

RTC_XTALI crystal mode

Bypass mode

(VBAT_RTC/5) – 0.5

(VBAT_RTC/2) – 0.4

—

Input leakage current Vin = 0 or

2.5

2.5

µA D3.21

µA D3.22

V_{DD_IO}/V_{DD_MEM_IO_DDR}

/2

(depending on input type)⁵

Input leakage current SYS_XTALI Vin = 0 or V_{DD_IO}

I_IN

—

20

MPC5121E/MPC5123 Data Sheet, Rev. 5

20

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 6. DC Electrical Specifications (continued)

Characteristic

Condition

Symbol

Min

Max

Unit SpecID

Input leakage current RTC_XTALI Vin = 0 or V_{DD_IO}

I_IN

—

1.0

µA D3.23

µA D3.24

Input current, pullup Pullup V_{DD_IO}Vin = VIL

resistor⁶

I_INpu

25

150

Input current,

Pulldown V_{DD_IO}Vin = VIH

I_INpd

25

150

µA D3.25

pulldown resistor ⁸

Output high voltage

IOH is driver dependent⁷V_{DD_IO}

V_OH

0.8 × V_{DD_IO}

1.90

—

V

D3.26

D3.27

IOH is driver dependent⁷

V_{DD_MEM_IO_DDR}

V_OHDDR

Output high voltage

IOH is driver dependent⁷

V_{DD_MEM_IO_DDR2}

V_OHDDR2

1.396

V

D3.28

—

IOH is driver dependent⁷

V_{DD_MEM_IO_LPDDR}

V_OHLPDDR

V_{DD_MEM_IO}

– 0.28

Output low voltage

IOL is driver dependent⁷V_{DD_IO}

V_OL

—

0.2 × V_{DD_IO}

0.36

V

D3.30

D3.31

IOL is driver dependent⁷

V_{DD_MEM_IO_DDR}

V_OLDDR

Output low voltage

IOL is driver dependent⁷

V_{DD_MEM_IO_DDR2}

V_OLDDR2

V_OLLPDDR

V_OXMCK

—

0.28

V

D3.32

D3.33

D3.34

IOL is driver dependent⁷

V_{DD_MEM_IO_LPDDR}

Differential cross point

voltage 

—

0.5 ×

V_{DD_MEM_IO}– 0.125

V_{DD_MEM_IO}+ 0.125

(DDR MCK/MCK)

DC Injection Current

Per Pin⁸

—

I_CS

C_in

1.0

—

1.0

7

mA D3.35

pF D3.36

pF D3.37

Input Capacitance

(digital pins)

Input Capacitance

(analog pins)

C_in

—

10

180

On Die Termination

(DDR2)

R_ODT

120



D3.38

1

This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,

Vextal – Vxtal - 400mV criteria has to be met for oscillator’s comparator to produce output clock.

2

This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass

mode. In that case, drive only the EXTAL pin not connecting anything to other pin for the oscillator’s comparator to produce

output clock.

3

4

This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,

drive one of the XTAL_IN or XTAL_OUT pins not connecting anything to other pin for the oscillator’s comparator to produce

output clock.

This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass

mode. In that case, drive only the xtal_in pin not connecting anything to other pin for the oscillator’s comparator to produce

output clock.

5

6

Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive.

Pullup current is measured at VIL and pulldown current is measured at VIH.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

21

Electrical and Thermal Characteristics

7

See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin

as listed in Table 3.

8

All injection current is transferred to V_{DD_IO}/V_{DD_MEM_IO}. An external load is required to dissipate this current to maintain the

power supply within the specified voltage range.

Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can

cause disruption of normal operation.

Table 7. I/O Pads—Drive Current, Slew Rate

Drive Select/Slew

Rate Control

Rise time

max (ns)

Fall time Current Current

max (ns) Ioh (mA) Iol (mA)

Pad Type

Supply Voltage

SpecID

General IO

V_{DD_IO}= 3.3V

configuration 3 (11)

configuration 2 (10)

configuration 1 (01)

configuration 0 (00)

1.4

9.8

19

140

2

1.6

12

24

183

2

35

D3.41

D3.42

D3.43

D3.44

D3.45

D3.46

D3.47

D3.48

D3.49

D3.50

D3.51

DDR

V_{DD_MEM_IO}= 2.5V (DDR) configuration 3 (011)

V_{DD_MEM_IO}= 1.8V (LPDDR) configuration 0 (000)

configuration 1 (001)

16.2

4.6

8.1

5.3

13.4

11

16.2

4.6

8.1

5.3

13.4

17

1

V_{DD_MEM_IO}= 1.8V (DDR2) configuration 2 (010)

configuration 6 (110)

1

PCI

V_{DD_IO}= 3.3V

configuration 1 (1)

configuration 0 (0)

1.4

2

1.4

2

1

Notes:

1. General IO – Rise and Fall Times at Drive load 50pF.

2. PCI – Rise and Fall Times at Drive load 10pF.

3. DDR – for LPDDR/Mobile-DDR, slew rate is measured between 20% of V_{DD_MEM_IO}and 80% of V_{DD_MEM_IO}

4. DDR – for DDR, DDR2, rising signals, slew rate is measured between V_{DD_MEM_IO}× 0.5 and ViH_AC. For falling signals, slew

rate is measured between V_{DD_MEM_IO}× 0.5 and ViL_AC

.

5. DDR – Rise and Fall Times terminated at the destination with 50 ohm to MVTT (0.5 × V_{DD_MEM_IO}), with 4 pF representing the

DDR input capacitance.

MPC5121E/MPC5123 Data Sheet, Rev. 5

22

Freescale Semiconductor

Electrical and Thermal Characteristics

3.1.4

Electrostatic Discharge

CAUTION

This device contains circuitry that protects against damage due to high-static voltage or

electrical fields. However, it is advised that normal precautions be taken to avoid

application of any voltages higher than maximum-rated voltages. Operational

reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND

or VDD). Table 10 gives package thermal characteristics for this device.

Table 8. ESD and Latch-Up Protection Characteristics

Symbol

Rating

Min

Max

Unit

SpecID

V_HBMHuman Body Model (HBM) – JEDEC JESD22-A114-B

V_MMMachine Model (MM) – JEDEC JESD22-A115

V_CDMCharge Device Model (CDM) – JEDEC JESD22-C101

2000

200

—

V

D4.1

D4.2

D4.3

500

3.1.5

Power Dissipation

Power dissipation of the MPC5121e/MPC5123 is caused by 4 different components: the dissipation of the internal or core

digital logic (supplied by V , the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and

DD_CORE)

CORE_PLL_AVDD), the dissipation of the IO logic (supplied by V

and V

) and the dissipation of the PHYs

DD_MEM_IO

DD_IO

(supplied by own supplies). Table 9 details typical measured core and analog power dissipation figures for a range of operating

modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each

application case using the following formula:

2

P

= P

+

N  C  VDD_IO  f

Eqn. 1

IO

IOint



M

where N is the number of output pins switching in a group M, C is the capacitance per pin, V

is the IO voltage swing, f

DD_IO

is the switching frequency and P

is the power consumed by the unloaded IO stage. The total power consumption of the

IOint

device must not exceed the value that would cause the maximum junction temperature to be exceeded.

P

= P

+ P

+ P + PPHYs

analog IO

Eqn. 2

total

core

Table 9. Power Dissipation

Core Power Supply (V_{DD_CORE}

)

SpecID

High-Performance

Mode

Unit

e300 = 300 MHz, CSB = 200 MHz

Operational¹

Deep-Sleep¹

Hibernation

800

1

mW

uW

D5.1

D5.2

D5.3

20

PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)

Typical 25 mW D5.4

Unloaded I/O Power Supplies (V_{DD_IO}, V_{DD_MEM_IO}

)

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

23

Electrical and Thermal Characteristics

Table 9. Power Dissipation (continued)

Core Power Supply (V_{DD_CORE}

)

SpecID

High-Performance

Mode

Unit

e300 = 300 MHz, CSB = 200 MHz

300

Typical

mW

D5.5

PHY Power Supplies (USB_VDDA, SATA_VDDA)

Typical 200 mW

D5.6

1

Typical core power is measured at V_{DD_CORE}= 1.4 V, T_j= 25 ^oC.

NOTE

The maximum power depends on the supply voltage, process corner,

junction temperature, and the concrete application and clock

configurations.

The worst case power consumption could reach a maximum of 2000 mW.

3.1.6

Thermal Characteristics

Table 10. Thermal Resistance Data

TEPBGA

Rating

Board Layers

Symbol TEPBGA

Value

Unit

SpecID

2

Junction to Ambient Natural Single layer board (1s)

Convection^1,2

R_JA

31

22

25

19

24

30

°C/W

D6.1

Junction to Ambient Natural Four layer board (2s2p)

Convection^1,3

R_JMA

17

19

14

22

24

19

°C/W

D6.2

D6.3

D6.4

Junction to Ambient (@200 Single layer board (1s)

ft/min)^1,3

Junction to Ambient (@200 Four layer board (2s2p)

ft/min)^1,3

Junction to Board⁴

—

R_JB

R_JC

_JT

14

9

7

14

8

°C/W

D6.5

D6.6

D6.7

Junction to Case⁵

Junction to Package Top⁶

Natural Convection

2

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2

3

4

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

MPC5121E/MPC5123 Data Sheet, Rev. 5

24

Freescale Semiconductor

Electrical and Thermal Characteristics

3.1.6.1

Heat Dissipation

An estimation of the chip-junction temperature, T , can be obtained from the following equation:

J

T

= T +(R

 P )

Eqn. 3

J

A

JA

D

where:

T

= ambient temperature for the package (ºC)

A

R

= junction to ambient thermal resistance (ºC/W)

JA

P

= power dissipation in package (W)

D

The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value

obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which

value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board

is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually

appropriate if the board has low power dissipation and the components are well separated.

Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case

to ambient thermal resistance:

R

= R

+R

CA

Eqn. 4

JA

JC

where:

R

= junction to ambient thermal resistance (ºC/W)

= junction to case thermal resistance (ºC/W)

= case to ambient thermal resistance (ºC/W)

JA

JC

CA

R

is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient

JC

thermal resistance, R

. For instance, you can change the air flow around the device, add a heat sink, change the mounting

CA

arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This

description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat

sink to ambient. For most packages, a better model is required.

A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal

resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated

from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat

is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics

(CFD) thermal model.

To determine the junction temperature of the device in the application after prototypes are available, the Thermal

Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at

JT

the top center of the package case using the following equation:

T

= T +(  P )

Eqn. 5

J

T

JT

D

where:

T



= thermocouple temperature on top of package (ºC)

= thermal characterization parameter (ºC/W)

T

JT

P

= power dissipation in package (W)

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

25

Electrical and Thermal Characteristics

from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling

effects of the thermocouple wire.

3.2

Oscillator and PLL Electrical Characteristics

The MPC5121e/MPC5123 System requires a system-level clock input SYS_XTALI. This clock input may be driven directly

from an external oscillator or with a crystal using the internal oscillator.

There is a separate oscillator for the independent Real Time Clock (RTC) system.

The MPC5121e/MPC5123 clock generation uses two phase locked loop (PLL) blocks.

•

The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The

system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL

configuration.

•

The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency

is determined by the system clock frequency and the settings of the CORE_PLL configuration.

The USB PHY contains its own oscillator with the input USB_XTALI and an embedded PLL.

The SATA PHY contains its own oscillator with the input SATA_XTALI and an embedded PLL.

3.2.1

System Oscillator Electrical Characteristics

Table 11. System Oscillator Electrical Characteristics

Characteristic

SYS_XTALI frequency

Symbol

Min

Typical

Max

Unit

SpecID

f_{sys_xtal}

15.6

33.3

35.0

MHz

O1.1

The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference.

t_CYCLE

t_DUTY

t_FALL

t_RISE

CV_IH

CV_IL

V_M

SYS_XTALI CLK

Figure 3. Timing Diagram—SYS_XTALI

Table 12. SYS_XTALI Timing

Description

Sym

t_CYCLE

t_RISE

Min

Max

Units

SpecID

SYS_XTALI cycle time^{1, 2}

SYS_XTALI rise time³

SYS_XTALI fall time⁴

SYS_XTALI duty cycle⁵

64.1

1

28.57

ns

%

O.1.2

O.1.3

O.1.4

O.1.5

4

t_FALL

1

t_DUTY

40

60

1

2

3

The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed

their respective maximum or minimum operating frequencies. See the MPC5121e Microcontroller Reference Manual.

The MIN/Max cycle times are calculated using 1/f_{sys_xtal (MIN/MAX)}where the f_{sys_xtal (MIN/MAX)}(15.6/35 MHz) are taken from

Table 11.

Rise time is measured from 20% of vdd to 80% of V_DD

.

MPC5121E/MPC5123 Data Sheet, Rev. 5

26

Freescale Semiconductor

Electrical and Thermal Characteristics

4

5

Fall time is measured from 20% of vdd to 80% of V_DD

.

SYS_XTALI duty cycle is measured at V_M.

3.2.2

RTC Oscillator Electrical Characteristics

Table 13. RTC Oscillator Electrical Characteristics

Characteristic

RTC_XTALI frequency

Symbol

Min

Typical

Max

Unit

SpecID

f_{rtc_xtal}

—

32.768

—

kHz

O2.1

3.2.3

System PLL Electrical Characteristics

Table 14. System PLL Specifications

Characteristic

Symbol

Min

Typical

Max

Unit

SpecID

Sys PLL input clock frequency¹

f_{sys_xtal}

t_jitter

16

—

33.3

—

67

10

MHz

ps

O3.1

O3.2

O3.3

O3.4

O3.5

O3.6

O3.7

Sys PLL input clock jitter²

Sys PLL VCO frequency^

f_VCOsys

f_VCOjitterDj

f_VCOjitterRj

t_lock1

400

—

800

40

MHz

ps

Sys PLL VCO output jitter (Dj), peak to peak / cycle

Sys PLL VCO output jitter (Rj), RMS 1 sigma

Sys PLL relock time—after power up³

Sys PLL relock time—when power was on⁴

—

12

ps

—

200

170

s

t_lock2

—

s

1

The SYS_XTALI frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core)

frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.

2

This represents total input jitter—short term and long term combined. Two different types of jitter can exist on the input to

CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the

PLL to the internal clock circuitry.

3

4

PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached

during the power-on reset sequence.

PLL relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently

re-enabled during sleep modes.

3.2.4

e300 Core PLL Electrical Characteristics

The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled

core PLL.

Table 15. e300 PLL Specifications

Characteristic

Symbol

Min

Typical

Max

Unit

SpecID

e300 frequency¹

f_core

200

400

50

5

—

400

800

200

20

MHz

ns

O4.1

O4.3

O4.4

O4.5

O4.6

e300 PLL VCO frequency¹

e300 PLL input clock frequency

e300 PLL input clock cycle time

e300 PLL relock time²

f_VCOcore

f_{CSB_CLK}

t_{CSB_CLK}

t_lock

—

200

s

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

27

Electrical and Thermal Characteristics

1

The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core)

frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in

Table 16. There is a hard coded relationship between f_coreand f_VCOcore(f_core= f_VCOcore/2).

2

PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached

during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently

re-enabled during sleep modes.

MPC5121E/MPC5123 Data Sheet, Rev. 5

28

Freescale Semiconductor

Electrical and Thermal Characteristics

3.3

AC Electrical Characteristics

Overview

3.3.1

Hyperlinks to the indicated timing specification sections are provided in the following:

•

AC Operating Frequency Data

•

SDHC

DIU

Resets

External Interrupts

SDRAM (DDR)

PCI

SPDIF

CAN

2

I C

LPC

J1850

PSC

NFC

PATA

GPIOs and Timers

Fusebox

SATA PHY

FEC

IEEE 1149.1 (JTAG)

VIU

USB ULPI

On-Chip USB PHY

AC Test Timing Conditions:

Unless otherwise noted, all test conditions are as follows:

o

•

T = –40 to 85 C

A

V

= 1.33 to 1.47 V

= 3.0 to 3.6 V

DD_CORE

DD_IO

•

Input conditions:

All Inputs: tr, tf  1 ns

Output Loading:

All Outputs: 50 pF

3.3.2

AC Operating Frequency Data

Table 16 provides the operating frequency information for the MPC5121e/MPC5123.

Table 16. Clock Frequencies

Min

Max

Units

SpecID

e300 Processor Core

SDRAM Clock

CSB Bus Clock

IP Bus Clock

PCI Clock

200

28.6

50.0

8.3

400

200

83

MHz

A1.1

A1.2

A1.3

A1.4

A1.5

A1.6

4.43

2.08

66

LPC Clock

83

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

29

Electrical and Thermal Characteristics

Table 16. Clock Frequencies (continued)

Min

Max

Units

SpecID

NFC Clock

DIU Clock

2.08

0.78

6.25

83

MHz

A1.7

A1.8

100

66.6

100

SDHC Clock

MBX Clock

A1.9

A1.10

NOTES:

1. The SYS_XTALI frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK,

frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The values are valid for the user operation mode. There can be deviations for test modes.

3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency

limitation.

4.The DDR data rate is 2× the DDR memory bus frequency.

See the MPC5121e Microcontroller Reference Manual for more information on the clock subsystem.

3.3.3

Resets

The MPC5121e/MPC5123 has three reset pins:

•

PORESET—Power on Reset

HRESET—Hard Reset

SRESET—Software Reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires

the same input characteristics as other MPC5121e/MPC5123 inputs, as specified in Section 3.1, “DC Electrical

Characteristics.”

As long as V is not stable the HRESET output is not stable.

DD

Table 17. Reset Rise / Fall Timing

Description

Min

Max

Unit

SpecID

PORESET¹fall time

PORESET rise time

HRESET^2,3fall time

HRESET rise time

SRESET fall time

SRESET rise time

—

1

ms

A3.4

A3.5

A3.6

A3.7

A3.8

A3.9

1

Make sure that the PORESET does not carry any glitches. The

MPC5121e/MPC5123 has no filter to prevent them from getting into the chip.

2

3

HRESET and SRESET must have a monotonous rise time.

The assertion of HRESET becomes active at Power on Reset without any

SYS_XTALI clock.

The timing relationship is shown in Figure 4.

MPC5121E/MPC5123 Data Sheet, Rev. 5

30

Freescale Semiconductor

Electrical and Thermal Characteristics

SYS_XTALI

PORESET

t_HRVAL

HRESET

SRESET

t_SRVAL

t_{S_POR_CONF}

t_EXEC

RST_CONF[31:0]

ADDR[31:0]

t_{H_POR_CONF}

Figure 4. Power-Up Behavior

SYS_XTALI

t_PORHold

PORESET

HRESET

t_HRVAL

t_SRVAL

SRESET

t_{S_POR_CONF}

t_EXEC

RST_CONF[31:0]

ADDR[31:0]

t_{H_POR_CONF}

Figure 5. Power-On Reset Behavior

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

31

Electrical and Thermal Characteristics

SYS_XTALI

PORESET

t_HRHOLD

t_HRVAL

HRESET

SRESET

t_SRVAL

t_{HR_SR_Delay}

t_EXEC

RST_CONF[31:0]

ADDR[31:0]

no new fetch of the RST_CONF

Figure 6. HRESET Behavior

SYS_XTALI

PORESET

t_SRHOLD

HRESET

SRESET

t_SRMIN

t_EXEC

RST_CONF[31:0]

ADDR[31:0]

no new fetch of the RST_CONF

Figure 7. SRESET Behavior

Table 18. Reset Timing

Description

Value

SYS_XTALI

Symbol

SpecID

t_PORHOLD

t_HRVAL

t_SRVAL

Time PORESET must be held low before a qualified reset occurs

Time HRESET is asserted after a qualified reset occurs

Time SRESET is asserted after assertion of HRESET

4 cycles

26810 cycles

32 cycles

A3.10

A3.11

A3.12

A3.13

t_EXEC

Time between SRESET assertion and first core instruction fetch

4 cycles

MPC5121E/MPC5123 Data Sheet, Rev. 5

32

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 18. Reset Timing (continued)

Description

Value

SpecID

Symbol

SYS_XTALI

t_{S_POR_CONF}

t_{H_POR_CONF}

Reset configuration setup time before assertion of PORESET

Reset configuration hold time after assertion of PORESET

1 cycle

A3.14

A3.15

A3.16

A3.17

A3.18

A3.19

t_{HR_SR_DELAY}Time from falling edge of HRESET to falling edge of SRESET

4 cycles

1 cycles

t_HRHOLD

t_SRHOLD

t_SRMIN

Time HRESET must be held low before a qualified reset occurs

Time SRESET must be held low before a qualified reset occurs

Time SRESET is asserted after it has been qualified

3.3.4

External Interrupts

The MPC5121e/MPC5123 provides three different kinds of external interrupts:

•

IRQ interrupts

GPIO interrupts with simple interrupt capability (not available in power-down mode)

WakeUp interrupts

1

Table 19. IPIC Input AC Timing Specifications

Description

Symbol

Min

Unit

SpecID

IPIC inputs—minimum pulse witdh

t_PICWID

2T

ns

A4.1

1

T is the IP bus clock cycle. T = 12 ns is the minimum value (for the maximum IP bus freqency

of 83 MHz).

IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode.

3.3.5

SDRAM (DDR)

The MPC5121e/MPC5123 memory controller supports three types of DDR devices:

•

DDR-1 (SSTL_2 class II interface)

DDR-2 (SSTL_18 interface)

LPDDR/Mobile-DDR (1.8V I/O supply voltage)

JEDEC standards define the minimum set of requirements for complient memory devices:

— JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, May 2006

— JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005

— JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006

The MPC5121e/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR:

•

Full drive strength

Half drive strengh (intended for ligther loads or point-to-point environments)

The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory

device.

This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical

Characteristics.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

33

Electrical and Thermal Characteristics

3.3.5.1

DDR and DDR2 SDRAM AC Timing Specifications

Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications

At recommended operating conditions with V_{DD_MEM_IO}of 5%

Parameter

Symbol

Min

Max

Unit

Notes

SpecID

Clock cycle time, CL=x

CK HIGH pulse width

CK LOW pulse width

t_CK

t_CH

5000

0.47

—

ps

A5.1

A5.3

A5.4

A5.5

1 2

0.53

0.25

t_CK

,

1 2

t_CL

0.47

,

2 3

Skew between MCK and DQS

transitions

t_DQSS

0.25

,

2 3

Address and control output setup

time relative to MCK rising edge

t_OS(base)

t_OH(base)

t_DS1(base)

t_DH1(base)

t_DQSQ

(t_CK/2 – 750)

(t_CK/4 – 500)

–(t_CK/4 – 600)

TBD

—

ps

,

A5.6

A5.7

2 3

Address and control output hold

time relative to MCK rising edge

—

,

2 3

DQ and DM output setup time

relative to DQS

—

,

A5.8

2 3

DQ and DM output hold time relative

to DQS

,

A5.9

2

DQS-DQ skew for DQS and

associated DQ inputs

(t_CK/4 – 600)

TBD

A5.10

A5.11

DQS window start position related to

CAS read command

t_DQSEN

¹,²,³,⁴,⁵

1

2

3

4

5

Measured with clock pin loaded with differential 100 termination resistor.

All transitions measured at mid-supply (VDD_MEM_IO/2).

Measured with all outputs except the clock loaded with 50  termination resistor to V_{DD_MEM_IO}/2.

In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.

Window position is given for t_DQSEN= 2.0 t_CK.For other values of t_DQSEN,window position is shifted accordingly.

Figure 8 shows the DDR SDRAM write timing.

t_CL

t_CH

MCK

DQS

t_CK

t_DQSS

DQ, DM(out)

t_DS

t_DH

Figure 8. DDR Write Timing

Figure 9 and Figure 10 shows the DDR SDRAM read timing.

MPC5121E/MPC5123 Data Sheet, Rev. 5

34

Freescale Semiconductor

Electrical and Thermal Characteristics

DQS(in)

Any DQ(in)

t_DQSQ

Figure 9. DDR Read Timing, DQ vs DQS

Command

Address

Read

t_OS

t_OH

DQS (in)

t_{DQSEN (min)}

t_DQSEN

Figure 10. DDR Read Timing, DQSEN

Figure 11 provides the AC test load for the DDR bus.

Output

V_{DD_MEM_IO}/2

Z₀= 50 

R_L= 50 

Figure 11. DDR AC Test Load

3.3.6

PCI

The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations.

See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components

with the intent that components connect directly together whether on the planar or an expansion board, without any external

buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors.

The PCI_CLK is used as output clock, the MPC5121e/MPC5123 is a PCI host device only.

Figure 12 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 21 summarizes

the clock specifications.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

35

Electrical and Thermal Characteristics

t_cyc

t_high

t_low

0.6Vcc

0.5Vcc

0.4Vcc

0.3Vcc

0.4Vcc, p-to-p

(minimum)

PCI CLK

0.2Vcc

Figure 12. PCI CLK Waveform

2

Table 21. PCI CLK Specifications

66 MHz¹

33 MHz

Sym

Description

Units SpecID

Min²

Max

Min

Max

t_cyc

t_high

t_low

—

PCI CLK Cycle Time^1,3

PCI CLK High Time

PCI CLK Low Time

PCI CLK Slew Rate²

15

6

30

—

4

30

11

1

—

4

ns

A6.1

A6.2

A6.3

A6.4

6

ns

1.5

V/ns

1

2

3

In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK

requirements vary depending upon whether the clock frequency is above 33 MHz.

Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met

across the minimum peak-to-peak portion of the clock waveform as shown in Figure 12.

The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system

jitter.

1

Table 22. PCI Timing Parameters

66 MHz

33 MHz

Sym

Description

Units

SpecID

Min²

Max

Min

Max

t_val

CLK to Signal Valid Delay –

bused signals^1,2,3

2

6

2

11

ns

A6.5

A6.6

t_val(ptp) CLK to Signal Valid Delay – point

to point^1,2,3

6

12

t_on

t_off

t_su

Float to Active Delay¹

Active to Float Delay¹

—

14

—

28

—

ns

A6.7

A6.8

A6.9

Input Setup Time to CLK – bused

signals^3,4

3

5

0

7

10,12

0

t_su(ptp) Input Setup Time to CLK – point

to point^3,4

—

ns

A6.10

A6.11

t_h

Input Hold Time from CLK⁴

1

2

3

See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven

signal transitions drive to their Voh or Vol level within one Tcyc.

Minimum times are measured at the package pin with the load circuit, and maximum times are measured

with the load circuit as shown in the PCI Local Bus Specification.

REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#

and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.

MPC5121E/MPC5123 Data Sheet, Rev. 5

36

Freescale Semiconductor

Electrical and Thermal Characteristics

See the timing measurement conditions in the PCI Local Bus Specification.

For Measurement and Test Conditions, see the PCI Local Bus Specification.

4

3.3.7

LPC

The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects

(CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK.

The maximum bus frequency is 83 MHz.

Definition of Acronyms and Terms:

WS = Wait State

DC = Dead Cycle

HC = Hold Cycle

DS = Data Size in Bytes

BBT = Burst Bytes per Transfer

AL = Address latch enable Length

ALT = Chip select/Address Latch Timing

t

= LPC clock period

LPCck

Table 23. LPC Timing

Sym

Description

Min

Max

Units SpecID

t_ODCS[x], ADDR, R/W, TSIZ, DATA (wr),

TS, OE valid after LPC CLK

0

5

ns

A7.1

(Output Delay related to LPC CLK)

t₁

t₂

Non-MUXed non-Burst CS[x] pulse

width

(2 + WS) × t_LPCck

t_LPCck– t_OD

(2 + WS) × t_LPCck

t_LPCck+ t_OD

ns

A7.2

A7.3

ADDR, R/W, TSIZ, DATA (wr) valid

before CS[x] assertion

t₃

t₄

OE assertion after CS[x] assertion

t_LPCck– t_OD

t_LPCck+ t_OD

ns

A7.4

A7.5

ADDR, R/W, TSIZ, Data (wr) hold after

CS[x] negation

(HC + 1) × t_LPCck+ t_OD

t₅

t₆

t₇

t₈

TS pulse width

t_LPCck

—

ns

A7.6

A7.7

A7.8

A7.9

DATA (rd) setup before LPC CLK

DATA (rd) input hold

4

0

(DC + 1) × t_LPCck

Non-MUXed read Burst CS[x] pulse

width

(2 + WS + BBT/DS) × t_LPCck(2 + WS + BBT/DS) × t_LPCck

t₉

Burst ACK pulse width

(BBT/DS) × t_LPCck

0

(BBT/DS) × t_LPCck

—

ns

A7.10

A7.11

A7.12

t₁₀Burst DATA (rd) input hold

t₁₁Read Burst ACK assertion after CS[x]

assertion

(2 + WS) × t_LPCck

t₁₂Non-muxed write Burst CS[x] pulse

width

(2.5 + WS + BBT/DS) × t_LPCck(2.5 + WS + BBT/DS) × t_LPCck

ns

A7.13

A7.14

t₁₃Write Burst ADDR, R/W, TSIZ, DATA

(wr) hold after CS[x] negation

0.5 × t_LPCck– t_OD

(HC + 0.5) × t_LPCck+ t_OD

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

37

Electrical and Thermal Characteristics

Table 23. LPC Timing (continued)

Min

Sym

Description

Max

Units SpecID

t₁₄Write Burst ACK assertion after CS[x]

assertion

(2.5 + WS) × t_LPCck– t_OD

(2.5 + WS) × t_LPCck+ t_OD

ns

A7.15

t₁₅Write Burst DATA valid

t_LPCck– t_OD

—

ns

A7.16

A7.17

t₁₆Non-MUXed Mode: asynchronous write

Burst ADDR valid before write DATA

valid

0.5 × t_LPCck– t_OD

0.5 × t_LPCck+ t_OD

t₁₇MUXed Mode: ADDR cycle

t₁₈MUXed Mode: ALE cycle

AL × 2 × t_LPCck– t_OD

AL × t_LPCck

AL × 2 × t_LPCck

AL × t_LPCck

t_LPCck

ns

A7.18

A7.19

A7.20

t₁₉Non-MUXed Mode Page Burst: ADDR

cycle

t_LPCck– t_OD

t₂₀Non-MUXed Mode Page Burst: Burst

DATA (rd) input setup before next ADDR

cycle

t_OD+ t₆

ns

A7.21

A7.22

—

t₂₁Non-MUXed Mode Page Burst: Burst

DATA (rd) input hold after next ADDR

cycle

0

t₂₂MUXed Mode: non-Burst CS[x] pulse

width

(ALT × (AL × 2) + 2 + WS)

× t_LPCck

(ALT × (AL × 2) + 2 + WS)

× t_LPCck

ns

A7.23

A7.24

A7.25

t₂₃MUXed Mode: read Burst CS[x] pulse

width

[ALT (AL × 2) + 2 + WS

+ BBT/DS] × t_LPCck

[ALT × (AL × 2)+2+WS

+BBT/DS] × t_LPCck

t₂₄MUXed Mode: write Burst CS[x] pulse

width

[ALT × (AL × 2) + 2.5 + WS

+ BBT/DS] × t_LPCck

[ALT × (AL × 2)+2.5+WS

+BBT/DS] × t_LPCck

MPC5121E/MPC5123 Data Sheet, Rev. 5

38

Freescale Semiconductor

Electrical and Thermal Characteristics

3.3.7.1

Non-MUXed Mode

3.3.7.1.1

Non-MUXed Non-Burst Mode

t_LPCck

LPC CLK

t₁

CS[x]

ADDR

t₂

t₃

t₄

OE

R/W

DATA (wr)

t₆

t₇

DATA (rd)

ACK

t₅

TS

TSIZ[1:0]

Figure 13. Timing Diagram – Non-MUXed Non-Burst Mode

NOTE

ACK is asynchonous input signal and has no timing requirements. ACK needs to be

deasserted after CS[x] is deasserted.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

39

Electrical and Thermal Characteristics

3.3.7.1.2

Non-MUXed Synchronous Read Burst Mode

LPC_CLK

t₈

CS[x]

t₂

t₄

Valid Address

ADDR

TS

t₅

t₃

OE

R/W

t₁₀

t₆

t₇

DATA (rd)

ACK

t₁₁

t₉

Figure 14. Timing Diagram – Non-MUXed Synchronous Read Burst Mode

3.3.7.1.3

Non-MUXed Synchronous Write Burst Mode

LPC_CLK

CS[x]

t₁₂

t₂

t₁₃

Valid Address

ADDR

t₅

TS

R/W

t₁₅

DATA (wr)

ACK

t₉

t₁₄

Figure 15. Timing Diagram – Non-MUXed Synchronous Write Burst

MPC5121E/MPC5123 Data Sheet, Rev. 5

40

Freescale Semiconductor

Electrical and Thermal Characteristics

3.3.7.1.4

Non-MUXed Asynchronous Read Burst Mode (Page Mode)

LPC_CLK

CS[x]

t₈

t₂

t₄

Valid Address (Page address)

Valid Address

ADDR[31:n+1]

ADDR[n:0]

t₁₉

Valid Address

t₅

TS

t₃

OE

t₂₀

t₆

t₂₁

t₁₀

R/W

t₇

DATA (rd)

t₁₁

t₉

ACK

Figure 16. Timing Diagram – Non-MUXed Asynchronous Read Burst

3.3.7.1.5

Non-MUXed Aynchronous Write Burst Mode

LPC_CLK

CS[x]

t₁₂

t₂

t₁₃

Valid Address (Page address)

Valid Address

ADDR[31:n+1]

ADDR[n:0]

Valid Address

t₁₆

t₅

TS

R/W

DATA (wr)

ACK

t₁₅

t₉

t₁₄

Figure 17. Timing Diagram – Non-MUXed Aynchronous Write Burst

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

41

Electrical and Thermal Characteristics

3.3.7.2

MUXed Mode

3.3.7.2.1

MUXed Non-Burst Mode

LPC_CLK

t₁₇

AD[31:0] (wr)

Address

Valid Write Data

t₆t₇

AD[31:0] (rd)

Address

t₄

R/W

ALE

t₁₈

t₅

TS

t₂₂

CS[x]

t₃

OE

ACK

TSIZ[1:0]

Figure 18. Timing Diagram – MUXed Non-Burst Mode

NOTE

ACK is asynchonous input signal and has no timing requirements. ACK needs to be

deasserted after CS[x] is deasserted.

MPC5121E/MPC5123 Data Sheet, Rev. 5

42

Freescale Semiconductor

Electrical and Thermal Characteristics

3.3.7.2.2

MUXed Synchronous Read Burst Mode

LPC_CLK

t₇

t₆

t₁₀

t₁₇

AD[31:0] (rd)

Address

t₁₈

ALE

TS

t₅

t₂₃

CSx

OE

t₃

R/W

ACK

t₉

t₁₁

Figure 19. Timing Diagram – MUXed Synchronous Read Burst

3.3.7.2.3

MUXed Synchronous Write Burst Mode

LPC_CLK

AD[31:0] (wr)

ALE

t₁₇

Address

t₁₈

t₁₅

t₁₅t₁₃

t₅

TS

t₂₄

CSx

R/W

t₁₄

t₉

ACK

Figure 20. Timing Diagram – MUXed Synchronous Write Burst

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

43

Electrical and Thermal Characteristics

3.3.8

NFC

The NAND flash controller (NFC) implements the interface to standard NAND Flash memory devices. This section describes

the timing parameters of the NFC.

NFC_CLE

t_CLH

t_CLS

t_CS

t_CH

NFC_CE[1:0]

t_WP

NFC_WE

NFC_ALE

t_ALS

t_ALH

t_DS

t_DH

NFIO[7:0]

command

Figure 21. Command Latch Cycle Timing

NFC_CLE

t_CLS

t_CH

t_CS

NFC_CE[1:0]

t_WC

t_WH

t_WP

NFC_WE

NFC_ALE

t_ALH

t_ALS

t_DS

t_DH

NFIO[7:0]

Address

Figure 22. Address Latch Cycle Timing

MPC5121E/MPC5123 Data Sheet, Rev. 5

44

Freescale Semiconductor

Electrical and Thermal Characteristics

NFC_CLE

t_CLS

t_CS

NFC_CE[1:0]

t_WC

t_WH

t_WP

NFC_WE

NFC_ALE

t_DS

Data to NF

t_DH

NFIO[15:0]

Figure 23. Write Data Latch Timing

NFC_CLE

NFC_CE[1:0]

t_RC

t_REH

t_RP

NFC_RE

t_REA

t_AR

t_RHZ

NFC_ALE

NFIO[15:0]

R/B

Data from NF

t_RR

Figure 24. Read Data Latch Timing

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

45

Electrical and Thermal Characteristics

NFC_RE

tss

NFIO[15:0]

NFC SYMMETRIC MODE(SYM=1)

Figure 25. Read Data Latch Timing in Symmetric Mode

1

Table 24. NFC Timing Characteristics in asymmetric mode(SYM=0)

Timing

parameter

Description

NFC_CLE setup Time

Min. value

Max. value

Unit SpecID

t_CLS

t_CLH

t_CS

T + 1

T – 1

2T – 1

3T

—

ns

A8.1

A8.2

NFC_CLE Hold Time

NFC_CE[1:0] Setup Time

NFC_CE[1:0] Hold Time

NFC_WP Pulse Width

NFC_ALE Setup Time

NFC_ALE Hold Time

Data Setup Time

A8.3

t_CH

A8.4

t_WP

t_ALS

t_ALH

t_DS

T – 1

T – 2

T – 1

2T

A8.5

A8.6

A8.7

A8.8

t_DH

Data Hold Time

A8.9

t_WC

t_WH

t_RR

Write Cycle Time

A8.10

A8.11

A8.12

A8.13

A8.14

A8.15

NFC_WE Hold Time

Ready to NFC_RE Low

NFC_RE Pulse Width

READ Cycle Time

T – 1

5T + 2

1.5T – 1

2T

t_RP

t_RC

t_REH

NFC_RE High Hold Time

0.5T

1

T is the flash clock cycle.

T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)

T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)

MPC5121E/MPC5123 Data Sheet, Rev. 5

46

Freescale Semiconductor

Electrical and Thermal Characteristics

1

Table 25. NFC Timing Characteristics in Symmetric mode(SYM=1)

Timing

Parameter

Description

NFC_CLE Setup time

Min. value

Max. value

Unit

SpecID

t_CLS

t_CLH

t_CS

T

—

ns

A8.21

A8.22

A8.23

A8.24

A8.25

A8.26

A8.27

A8.28

A8.29

A8.30

A8.31

A8.32

A8.33

A8.34

A8.35

A8.36

NFC_CLE Hold time

NFC_CE[1:0] Setup time

NFC_CE[1:0] Hold time

NFC_WE Pulse width

NFC_ALE Setup time

NFC_ALE Hold time

Data Setup time

T-2

t_CH

1.5T-1

0.5T+1

T

t_WP

t_ALS

t_ALH

t_DS

T

0.5T-3

0.5T

T

t_DH

Data Hold time

t_WC

t_WH

t_RR

Write Cycle time

NFC_WE Hold time

Ready to NFC_RE low

NFC_RE pulse width

Read Cycle time

0.5T-1

5T+2

0.5T

T

t_RP

t_RC

t_REH

t_SS

NFC_RE High hold time

NFC Read Data setup time

0.5T

9.6

1

T is the flash clock cycle.

T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)

T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)

3.3.9

PATA

The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate

with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is

completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units

(nanoseconds).

ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data

setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the

ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and

ATA drive for different ATA protocols and their respective timing. See the MPC5121e Microcontroller Reference Manual.

The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE

strobe in PIO and Multiword DMA modes.

•

Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that

required by the ATA-4 specification.

•

Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that

required by the ATA-4 specification.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

47

Electrical and Thermal Characteristics

All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.

This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate

with the drive.

Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate

data transfer rates. Adequate data transfer rates are a function of the following:

•

The MPC5121e/MPC5123 operating frequency (IP bus clock frequency)

Internal MPC5121e/MPC5123 bus latencies

Other system load dependent variables

The ATA clock is the same frequency as the IP bus clock in MPC5121e/MPC5123. See the MPC5121e Microcontroller

Reference Manual.

NOTE

All output timing numbers are specified for nominal 50 pF loads.

3.3.9.1

PATA Timing Parameters

In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface

in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in Table 3-26 specify the ATA timing.

Table 3-26. PATA Timing Parameters

Name

Meaning

Controlled by

Value SpecID

T

PATA Bus clock period

MPC5121E/MPC5123 15 ns

A9.1

A9.2

A9.3

A9.4

t_{i_ds}

t_{i_dh}

t_co

Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only)

Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only)

MPC5121E/MPC5123

2 ns

5 ns

2 ns

Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2,

ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA,

ATA_BUFFER_EN

t_su

t_sui

t_hi

Set-up time ATA_DATA to bus clock L-to-H

Set-up time ATA_IORDY to bus clock H-to-L

Hold time ATA_IORDY to bus clock H to L

MPC5121E/MPC5123

2 ns

A9.5

A9.6

A9.7

A9.8

t_skew1Max difference in propagation delay bus clock L-to-H to any of following MPC5121E/MPC5123 1.7 ns

signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0,

ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE),

ATA_BUFFER_EN

t_skew2Max difference in buffer propagation delay for any of following signals:

ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,

ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN

Transceiver

A9.9

t_skew3Max difference in buffer propagation delay for any of following signals:

ATA_IORDY, ATA_DATA (read)

Transceiver

A9.10

t_buf

Max buffer propagation delay

Transceiver

Cable

A9.11

A9.12

A9.13

t_cable1Cable propagation delay for ata_data

t_cable2Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW,

ATA_IORDY, ATA_DMACK

Cable

MPC5121E/MPC5123 Data Sheet, Rev. 5

48

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 3-26. PATA Timing Parameters (continued)

Name

Meaning

Controlled by

Value SpecID

t_skew4Max difference in cable propagation delay between: ATA_IORDY and

ATA_DATA (read)

Cable

A9.14

t_skew5Max difference in cable propagation delay between: ATA_DIOR,

ATA_DIOW, ATA_DMACK and ATA_CS0, ATA_CS1, ATA_DA2,

ATA_DA1, ATA_DA0, ATA_DATA (write)

Cable

A9.15

A9.16

Max difference in cable propagation delay without accounting for ground

bounce

tskew6

3.3.9.2

PIO Mode Timing

A timing diagram for the PIO read mode is given in Figure 26.

t₁

t_2r

t₉

ADDR

t₅

DIOR

t₆

Read Data (15:0)

t_A

IORDY

t_rd1

Figure 26. PIO Read Mode Timing

To fulfill read mode timing, the different timing parameters given in Table 3-27 must be observed.

Table 3-27. Timing Parameters PIO Read

PIO Read

ATA

Parameter

Mode Timing

Parameter

Value

How to meet

SpecID

t₁

t₂r

t₉

t₁(min) = (time_1 × T) – (t_skew1+ t_skew2+ t_skew5

)

calculate and programming

time_1. ¹

A9.20

A9.21

A9.22

t₂

t₂(min) = (time_2r × T) – (t_skew1+ t_skew2+ t_skew5

)

calculate and programming

time_2r. ¹

t₉

t₉(min) = (time_9 × T) – (t_skew1+ t_skew2+ t_skew6

)

calculate and programming

time_9. ¹

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

49

Electrical and Thermal Characteristics

Table 3-27. Timing Parameters PIO Read (continued)

PIO Read

Mode Timing

Parameter

ATA

Parameter

Value

How to meet

SpecID

t₅

t₆

t_A

t₅

t₆

t_A

t₅(min) = t_co+ t_su+ t_buf+ t_buf+ t_cable1+ t_cable2

If not met, increase time_2r

—

A9.23

A9.24

A9.25

0

t_A(min)= (1.5 + time_ax) × T – 

calculate and programming

time_ax. ¹

(t_co+ t_sui+ t_cable2+ t_cable2+ 2 × t_buf

)

t_rd

t_rd1

t_rd1(max)= (–t_rd) + (t + t

t_rd1(min)= (time_pio_rdx – 0.5 )

)

skew4

calculate and programming

time_pio_rdx. ¹

A9.26

A9.27

skew3

×

T – (t + t )



su

hi

+ t

(time_pio_rdx – 0.5) × T > t + t + t

su

hi

skew3

skew4

t₀

—

t_0(min)= (time_1 + time_2 + time_9) × T

time_1, time_2r, time_9

1

See the MPC5121e Microcontroller Reference Manual.

In PIO write mode, timing waveforms are somewhat different as shown in Figure 27.

t₁t_2r

t₉

ADDR

DIOR

DIOW

buffer_en

Write Data (15:0)

t_on

t_A

t_B

t₄t_off

t₁

IORDY

Figure 27. PIO Write Mode Timing

To fulfill this timing, several parameters need to be observed as shown in Table 3-28.

MPC5121E/MPC5123 Data Sheet, Rev. 5

50

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 3-28. Timing Parameters PIO Write

Value

PIO Write

ModeTiming

Parameter

ATA

Parameter

How to meet

time_1. ¹

SpecID

t1

t2

t1

t1(min) = time_1 × T – (tskew1 + tskew2 + tskew5)

t2(min) = time_2w × T – (tskew1 + tskew2 + tskew5)

A9.30

A9.31

t2r

calculate and programming

time_2w. ¹

t9

t3

t9

t9(min) = time_9 × T – (tskew1 + tskew2 + tskew6)

time_9. ¹

A9.32

A9.33

—

t3(min) = (time_2w – time_on) × T

If not met, increase time_2w

– (tskew1 + tskew2 + tskew5)

t4

t4(min) = time_4 × T – tskew1

calculate and programming

time_4. ¹

A9.34

A9.35

tA

tA = (1.5 + time_ax) × T 

– (tco + tsui + tcable2 + tcable2 + 2 × tbuf)

calculate and programming

time_ax. ¹

t0

—

t0(min) = (time_1 + time_2 + time_9) × T

time_1, time_2r, time_9

—

A9.36

A9.37

—

Avoid bus contention when switching buffer on 

by making ton long enough

—

Avoid bus contention when switching buffer off 

by making toff long enough

A9.38

—

1

See the MPC5121e Microcontroller Reference Manual.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

51

Electrical and Thermal Characteristics

3.3.9.3

Timing in Multiword DMA Mode

Timing in multiword DMA mode is given in Figure 28 and Figure 29.

t_k1

DMARQ

ADDR

DMACK

DIOR

t_m

t_d

t_k

t_kjn

Read Data (15:0)

t_gr

t_fr

Figure 28. MDMA Read Timing

t_k1

DMARQ

ADDR

DMACK

buffer_en

DIOW

t_m

t_on

t_d1

t_k

t_d

t_kjn

t_off

Write Data (15:0)

Figure 29. MDMA Write Timing

To meet this timing, a number of timing parameters must be controlled as shown in Table 3-29.

MPC5121E/MPC5123 Data Sheet, Rev. 5

52

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 3-29. Timing Parameters MDMA Read and Write

MDMA

Read/Write

Timing

ATA

Parameter

Value

How to meet

SpecID

Parameter

t_m, t_i

t_m

t_d, t_d1

t_k

t_m(min)= t_i(min)= (time_m × T) – (t_skew1+ t_skew2+ t_skew5

)

calculate and

programming

time_m. ¹

A9.40

t_d

t

= t

= (time_d × T) – (t_skew1

+

t_skew2

+ )

tskew6

calculate and

programming

time_d. ¹

A9.41

A9.42

d1(min)

d(min)

t_k

t_k(min)= (time_k × T) – ( _skew1

t

+

t_skew2

+

)

calculate and

programming

time_k. ¹

tskew6

t₀

—

t_gr

t_0(min)= (time_d + time_k) × T

time_d, time_k

time_d. ¹

A9.43

A9.44

t_g(read)

t_gr(min-read)= t_co+ t_su+ t_buf+ t_buf+ t_cable1+ t_cable2

t_{gr(min-drive)}= td – te(drive)

t_f(read)

t_g(write)

t_f(write)

t_L

t_fr

_{tfr(min-drive)}= 0

—

A9.45

A9.46

A9.47

A9.48

—

t_g(min-write)= time_d × T – ( _skew1

t

+

t_skew2

+

t_skew5

)

time_d

t_f(min-write) = time_k × T – ( _skew1

t

+

)

time_k

tskew6

t_L(max)= [(time_d + time_k – 2) × T]

time_d, time_k

– [t_su+ t_co+ (2 × t_buf) + (2 × t_cable2)]

t_n, t_j

—

t_kjn

t_n= t_j= t_kjn= [max(time_k,. time_jn) × T]

calculate and

programming

time_jn. ¹

A9.49

A9.50

– ( _skew1

t

+

t_skew2

+

)

tskew6

t_on

t_off

t_on= (time_on × T) – t_skew1

t_off= (time_off × T) – t_skew1

—

1

See the MPC5121e Microcontroller Reference Manual.

3.3.9.4

UDMA In Timing Diagrams

UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in are

given:

•

Figure 30 gives timing for UDMA in transfer start

Figure 31 gives timing for host terminating UDMA in transfer

Figure 32 gives timing for device terminating UDMA in transfer.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

53

Electrical and Thermal Characteristics

t_ack

ADDR

DMARQ

DMACK

DIOR

t_env

DIOW

t_c1

IORDY

Data Read

t_ds

t_dh

Figure 30. UDMA In Transfer Start Timing Diagram

MPC5121E/MPC5123 Data Sheet, Rev. 5

54

Freescale Semiconductor

Electrical and Thermal Characteristics

ADDR

t_ack

DMARQ

DMACK

DIOR

t_rp

DIOW

t_mli

t_ont_dzfs

t_c1

t_x1

t_c1

IORDY

t_zah

Data Read

t_cvh

t_off

t_ds

t_dh

Data Write

buffer_en

Figure 31. UDMA In Host Terminates Transfer

ADDR

DMARQ

DMACK

t_ack

DIOR

DIOW

t_mli

t_c1

t_ss1t_li5

IORDY

t_mli

t_ont_dzfst_cvht_off

Data Read

t_ds

t_dh

t_zah

Data Write

buffer_en

Figure 32. UDMA In Device Terminates Transfer

Timing parameters are explained in Table 30.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

55

Electrical and Thermal Characteristics

Table 30. Timing Parameters UDMA in Burst

UDMA In

Timing

Parameter

ATA

Parameter

Value

How to Meet

SpecID

t_ack

t_ack(min)= (time_ack × T) – (t_skew1+ t_skew2

)

calculate and

A9.51

A9.52

programming time_ack. ¹

t_env

t_env(min)= (time_env × T) – (t_skew1+ t_skew2)

t_env(max) = (time_env × T) + (t_skew1+ t_skew2

calculate and

)

programming time_env. ¹

t_ds

t_dh

t_ds1

t_dh1

t_c1

t_ds– (_tskew3) – ti_ds > 0

t_skew3, ti_ds, ti_dh should A9.53

be low enough

t_dh– (_tskew3) – ti_dh > 0

A9.54

t_cyc

(t_cyc– t_skew) > T

Bus clock period T big

enough

A9.55

A9.56

A9.57

A9.58

A9.59

A9.60

A9.61

A9.62

t_rp

t_rp(min)= time_rp × T – (t_skew1+ t_skew2+ t_skew6

)

calculate and

1

programming time_rp

.

2

t_x1

(time_rp × T) – [tco + tsu + 3T + (2 × t_buf) + (2 × tcable2)]

trfs (drive)

>

calculate and

—

programming time_rp

.

t_mli

t_mli1

t_zah

t_dzfs

t_cvh

t_mli1(min) = (time_mlix + 0.4) × T

calculate and

programming time_mlix. ¹

t_zah

t_dzfs

t_cvh

t_zah(min)= (time_zah + 0.4) × T

calculate and

programming time_zah. ¹

t_dzfs= (time_dzfs × T) – (t_skew1+ t_skew2

)

calculate and

programming time_dzfs. ¹

t_cvh= (time_cvh × T) – (t_skew1+ t_skew2

)

calculate and

programming time_cvh. ¹

t_on₃

t_off

t_on= (time_on × T) – t_skew1

t_off= (time_off × T) – t_skew1

—

1

2

See the MPC5121e Microcontroller Reference Manual.

A special timing requirement in the ATA host requires the internal DIOW to go only high three clocks after the last active edge

on the DSTROBE signal. The equation given on this line tries to capture this constraint.

3

Make t_onand t_offlarge enough to avoid bus contention.

3.3.9.5

UDMA Out Timing Diagrams

UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA out are

given:

•

Figure 33 gives timing for UDMA out transfer start

Figure 34 gives timing for host terminating UDMA out transfer

Figure 35 gives timing for device terminating UDMA out transfer

MPC5121E/MPC5123 Data Sheet, Rev. 5

56

Freescale Semiconductor

Electrical and Thermal Characteristics

t_ack

ADDR

DMARQ

DMACK

DIOW

t_env

DIOR

t_cyc

buffer_en

t_on

t_dzfs

t_dvs

t_dvh

t_dvs

Data Write

IORDY

t_li1

t_rfs1

Figure 33. UDMA Out Transfer Start Timing Diagram

ADDR

t_ack

DMARQ

DMACK

DIOW

t_ss

DIOR

t_cyc

t_cyc1

t_li2

t_{dzfs_mli}

t_cvh

t_off

Data Write

IORDY

t_li3

buffer_en

Figure 34. UDMA Out Host Terminates Transfer

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

57

Electrical and Thermal Characteristics

r

ADDR

t_ack

DMARQ

t_li2

DMACK

DIOW

DIOR

t_rfs1

t_cyc

t_{dzfs_mli}

t_cvh

t_off

Data Write

IORDY

buffer_en

Figure 35. UDMA Out Device Terminates Transfer

Timing parameters are explained in Table 31.

Table 31. Timing Parameters UDMA Out Burst

Value

UDMA Out

Timing

Parameter

ATA

Parameter

How to meet

SpecID

t_ack

t_env

t_dvs

t_dvh

t_cyc

t_2cyc

t_ack

t_env

t_dvs

t_dvh

t_cyc

t_ack(min)= (time_ack × T) – (t_skew1+ t_skew2

)

calculate and program A9.63

time_ack. ¹

t_env(min)= (time_env × T) – (t_skew1+ t_skew2)

t_env(max)= (time_env × T) + (t_skew1+ t_skew2

calculate and program A9.64

1

)

time_env.

t_dvs= (time_dvs × T) – (t_skew1+ t_skew2

)

calculate and program A9.65

1

time_dvs

.

t_dvs= (time_dvh × T) – (t_skew1+ t_skew2

)

calculate and program A9.66

1

time_dvh

.

t_cyc= time_cyc × T – (t_skew1+ t_skew2

t_2cyc= time_cyc × 2 × T

)

calculate and program A9.67

1

time_cyc

.

calculate and program A9.68

—

1

time_cyc

.

t_rfs1

—

t_rfs1

t_dzfs

t_rfs1= 1.6 × T + t_sui+ t_co+ t_buf+ t_buf

—

A9.69

t_dzfs= time_dzfs × T – (t_skew1

)

calculate and program A9.70

time_dzfs

1

.

t_ss

t_{dzfs_mli}

t_li1

t_ss= time_ss × T – (t_skew1+ t_skew2

)

calculate and program

time_ss. ¹

A9.71

A9.72

A9.73

t_mli

t_li

t_{dzfs_mli}= max(time_dzfs, time_mli) × T –

(t_skew1+ t_skew2

—

)

t_li1> 0

—

MPC5121E/MPC5123 Data Sheet, Rev. 5

58

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 31. Timing Parameters UDMA Out Burst (continued)

UDMA Out

ATA

Parameter

Timing

Value

How to meet

SpecID

Parameter

t_li

t_li2

t_li3

t_li2> 0

t_li3> 0

—

A9.74

A9.75

t_cvh

t_cvh= (time_cvh × T) – (t_skew1+ t_skew2

)

calculate and program A9.76

1

time_cvh

.

t_on

t_off

t_on= time_on × T – t_skew1

t_off= time_off × T – t_skew1

—

A9.77

—

1

See the MPC5121e Microcontroller Reference Manual.

3.3.10 SATA PHY

1.5 Gbps SATA PHY Layer

See “Serial ATA: High Speed Serialized AT Attachment” Revision 1.0a, 7-January-2003.

3.3.11 FEC

AC Test Timing Conditions:

•

Output Loading

All Outputs: 25 pF

Table 32. MII Rx Signal Timing

Symbol

Description

Min

Max

Unit

SpecID

1

2

3

4

RXD[3:0], RX_DV, RX_ER to RX_CLK setup

RX_CLK to RXD[3:0], RX_DV, RX_ER hold

RX_CLK pulse width high

5

—

ns

A11.1

A11.2

A11.3

A11.4

5

35%

65%

RX_CLK Period¹

RX_CLK pulse width low

1

RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.

3

RX_CLK (Input)

4

RXD[3:0] (inputs)

RX_DV

RX_ER

1

2

Figure 36. Ethernet Timing Diagram – MII Rx Signal

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

59

Electrical and Thermal Characteristics

Table 33. MII Tx Signal Timing

Min

Symbol

Description

Max

Unit

SpecID

5

TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER

3

—

ns

A11.5

invalid

6

7

8

TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid

TX_CLK pulse width high

TX_CLK pulse width low

—

25

ns

A11.6

A11.7

A11.8

35%

65%

TX_CLK Period¹

1

The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide

a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See

the IEEE 802.3 Specification.

7

TX_CLK (Input)

5

8

TXD[3:0] (Outputs)

TX_EN

TX_ER

6

Figure 37. Ethernet Timing Diagram – MII Tx Signal

Table 34. MII Async Signal Timing

Symbol

Description

Min

Max

Unit

SpecID

9

CRS, COL minimum pulse width

1.5

—

TX_CLK Period

A11.9

CRS, COL

9

Figure 38. Ethernet Timing Diagram – MII Async

Table 35. MII Serial Management Channel Signal Timing

Symbol

Description

Min

Max

Unit

SpecID

10

11

12

13

14

15

MDC falling edge to MDIO output delay

MDIO (input) to MDC rising edge setup

MDIO (input) to MDC rising edge hold

MDC pulse width high¹

0

25

—

ns

A11.10

A11.11

A11.12

A11.13

A11.14

A11.15

10

0

160

400

MDC pulse width low¹

MDC period²

1

MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC

MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual.

MPC5121E/MPC5123 Data Sheet, Rev. 5

60

Freescale Semiconductor

Electrical and Thermal Characteristics

The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII

2

characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference

Manual.

13

14

MDC (Output)

15

10

MDIO (Output)

MDIO (Input)

11

12

Figure 39. Ethernet Timing Diagram – MII Serial Management

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

61

Electrical and Thermal Characteristics

3.3.12 USB ULPI

This section specifies the USB ULPI timing.

For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004.

Clock

T_SC

T_HC

Control In

(dir, nxt)

T_SD

T_HD

Data In

(8-bit)

T_DC

Control Out

(stp)

T_DD

Data Out

(8-bit)

Figure 40. ULPI Timing Diagram

Table 36. Timing Specifications – ULPI

Symbol

T_CK

Description

Min

Max

Units

SpecID

Clock Period

15

—

6.0

—

ns

A12.1

A12.2

A12.3

A12.4

T_SC, T_SDSetup time (control in, 8-bit data in)

T_HC, T_HDHold time (control in, 8-bit data in)

T_DC, T_DDOutput delay (control out, 8-bit data out)

0.0

—

9.0

NOTE

Output timing is specified at a nominal 50 pF load.

3.3.13 On-Chip USB PHY

The USB PHY is an USB2.0 compatible PHY integrated on-chip. See Chapter 7 in the USB Specification Rev. 2.0 at

www.usb.org.

3.3.14 SDHC

Figure 41 shows the timings of the SDHC.

MPC5121E/MPC5123 Data Sheet, Rev. 5

62

Freescale Semiconductor

Electrical and Thermal Characteristics

SD4

SD2

SD5

SD1

MMCx_CLK

SD3

MMCx_CMD

MMCx_DAT_0

MMCx_DAT_1

MMCx_DAT_2

MMCx_DAT_3

Output from SDHC to card

Input from card to SDHC

SD6

MMCx_CMD

MMCx_DAT_0

MMCx_DAT_1

MMCx_DAT_2

MMCx_DAT_3

SD7 SD8

Figure 41. SDHC Timing Diagram

Table 37 lists the timing parameters.

.

Table 37. MMC/SD Interface Timing Parameters

ID

Parameter

Symbols

Card Input Clock

Min

Max

Unit

SpecID

1

SD1 Clock Frequency (Low Speed)

f_PP

0

400

kHz

A14.1

A14.2

2

Clock Frequency (SD/SDIO Full

Speed/High Speed)

25/50

MHz

3

Clock Frequency (MMC Full Speed/High

Speed)

f_PP

0

20/52

400

MHz

A14.3

4

Clock Frequency (Identification Mode)

SD2 Clock Low Time (Full Speed/High Speed)

SD3 Clock High Time (Full Speed/High Speed)

SD4 Clock Rise Time (Full Speed/High Speed)

SD5 Clock Fall Time (Full Speed/High Speed)

f_OD

100

10/7

kHz

ns

A14.4

A14.5

A14.6

A14.7

A14.8

t_WL

t_WH

t_TLH

t_THL

ns

10/3

ns

SDHC Output / Card Inputs CMD, DAT (Reference to CLK)

SD6 SDHC Output Delay t_OD

TH⁵– 3

SDHC Input / Card Outputs CMD, DAT (Reference to CLK)

TH+3

ns

A14.9

SD7 SDHC Input Setup Time

SD8 SDHC Input Hold Time

t_ISU

t_IH

2.5

ns

A14.10

A14.11

1

2

3

4

5

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz.

In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz.

In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.

Suggested ClockPeriod = T, CLK_DIVIDER (in SDHC Clock Rate Register) = D, then TH = [(D + 1)/2]/(D + 1) × T

where the value is rounded.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

63

Electrical and Thermal Characteristics

3.3.15 DIU

The DIU is a display controller designed to manage the TFT LCD display.

3.3.15.1 Interface to TFT LCD Panels, Functional Description

Figure 42 shows the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with

positive polarity. The sequence of events for active matrix interface timing is:

•

DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,

DIU_CLK runs continuously. This signal frequency could be from 5 to 100 MHz depending on the panel type.

•

DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse.

DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse.

DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.

When disabled, the data is invalid and the trace is off.

DIU_VSYNC

DIU_HSYNC

LINE 1

LINE 3

LINE 4

LINE n-1 LINE n

LINE 2

DIU_HSYNC

DIU_DE

1

2

3

m

m-1

DIU_CLK

DIU_LD[23:0]

Figure 42. Interface Timing Diagram for TFT LCD Panels

3.3.15.2 Interface to TFT LCD Panels, Electrical Characteristics

Figure 43 shows the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters

shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal

(meaning the data and sync. signals change at the rising edge of it) and active-high polarity of the DIU_HSYNC, DIU_VSYNC

and DIU_DE signal. You can select the polarity of the DIU_HSYNC and DIU_VSYNC signal via the SYN_POL register,

whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. And, pixel clock

inversion and a flexible programmable pixel clock delay is also supported, programed via the DIU Clock Config Register

(DCCR) in the system clock module.

MPC5121E/MPC5123 Data Sheet, Rev. 5

64

Freescale Semiconductor

Electrical and Thermal Characteristics

t_HSP

Start of line

t_PWH

t_FPH

t_SW

t_BPH

t_PCP

DIU_CLK

Invalid Data

2

3

DELTA_X

Invalid Data

1

DIU_LD[23:0]

DIU_HSYNC

DIU_DE

Figure 43. TFT LCD Interface Timing Diagram – Horizontal Sync Pulse

Figure 44 shows the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown

in the diagram are programmable.

t_VSP

t_SH

t_FPV

t_BPV

t_PWV

t_HSP

Start of Frame

DIU_HSYNC

DIU_LD[23:0]

(Line Data)

Invalid Data

2

3

DELTA_Y

Invalid Data

11

DIU_VSYNC

DIU_DE

Figure 44. TFT LCD Interface Timing Diagram – Vertical Sync Pulse

Table 38 shows timing parameters of signals.

Table 38. LCD Interface Timing Parameters – Pixel Level

Name

Description

Value

Unit

SpecID

t_PCP

t_PWH

t_BPH

Display Pixel Clock Period

HSYNC Pulse Width

15¹

ns

A15.1

A15.2

A15.3

PW_H × t_PCP

BP_H × t_PCP

HSYNC Back Porch Width

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

65

Electrical and Thermal Characteristics

Table 38. LCD Interface Timing Parameters – Pixel Level (continued)

Name

Description

Value

Unit

SpecID

t_FPH

t_SW

HSYNC Front Porch Width

Screen Width

FP_H × t_PCP

ns

A15.4

A15.5

A15.6

A15.7

A15.8

A15.9

A15.10

A15.11

DELTA_X × t_PCP

t_HSP

t_PWV

t_BPV

t_FPV

t_SH

HSYNC (Line) Period

VSYNC Pulse Width

VSYNC Back Porch Width

VSYNC Front Porch Width

Screen Height

(PW_H + BP_H + DELTA_X + FP_H) × t_PCP

PW_V × t_HSP

BP_V × t_HSP

FP_V × t_HSP

DELTA_Y × t_HSP

t_VSP

VSYNC (Frame) Period

(PW_V + BP_V + DELTA_Y + FP_H) × t_HSP

1

Display interface pixel clock period immediate value (in nanosecond).

The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H

parameters are programmed via the HSYN_PARA register; And the PW_V, BP_V and FP_V parameters are programmed via

the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions on these parameters.

Figure 45 shows the synchronous display interface timing for access level, and Table 39 lists the timing parameters.

t_CHD

t_CSU

DIU_HSYNC

DIU_VSYNC

DIU_DE

DIU_CLK

t_CKH

t_CKL

t_DHD

t_DSU

DIU_LD[23:0]

Figure 45. LCD Interface Timing Diagram – Access Level

Table 39. LCD Interface Timing Parameters – Access Level

Parameter

Description

Min

Typ

Max

Unit

SpecID

t_CKH

t_CKL

t_DSU

t_DHD

t_CSU

t_CHD

LCD Interface Pixel Clock High Time

LCD Interface Pixel Clock Low Time

LCD Interface Data Setup Time

t_PCP× 0.4

5.0

t_PCP× 0.5

t_PCP× 0.6

ns

A15.12

A15.13

A15.14

A15.15

A15.16

A15.17

t_PCP× 0.5

t_PCP× 0.6

—

LCD Interface Data Hold Time

6.0

LCD Interface Control Signal Setup Time

LCD Interface Control Signal Hold Time

5.0

6.0

MPC5121E/MPC5123 Data Sheet, Rev. 5

66

Freescale Semiconductor

Electrical and Thermal Characteristics

3.3.16 SPDIF

The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the

clock.

3.3.17 CAN

The CAN functions are available as TX and CAN3/4_RX pins at normal IO pads and as CAN1/2 RX pins at the VBAT_RTC

domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.

3.3.18 I²C

2

This section specifies the timing parameters of the Inter-Integrated Circuit (I C) interface. Refer to the I C Bus Specification.

2

Table 40. I C Input Timing Specifications – SCL and SDA

Symbol

Description

Min

Max

Units

SpecID

1

2

4

6

7

8

9

Start condition hold time

Clock low time

2

8

—

IP-Bus Cycle¹

ns

A18.1

A18.2

A18.3

A18.4

A18.5

A18.6

A18.7

Data hold time

0.0

4

Clock high time

Data setup time

IP-Bus Cycle¹

0.0

2

ns

Start condition setup time (for repeated start condition only)

Stop condition setup time

IP-Bus Cycle¹

2

1

Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.

2

Table 41. I C Output Timing Specifications – SCL and SDA

Symbol

Description

Min

Max

Units

SpecID

1¹

2¹

3³

4¹

5¹

6¹

7¹

8¹

9¹

Start condition hold time

Clock low time

6

—

IP-Bus Cycle²

ns

A18.8

A18.9

10

—

7

SCL/SDA rise time

Data hold time

7.9

—

A18.10

A18.11

A18.12

A18.13

A18.14

A18.15

A18.16

IP-Bus Cycle²

SCL/SDA fall time

Clock high time

—

10

2

7.9

—

ns

IP-Bus Cycle²

Data setup time

—

Start condition setup time (for repeated start condition only)

Stop condition setup time

20

10

—

1

Programming IFDR with the maximum frequency results in the minimum output timings listed. The I²C interface is designed to

scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and

division values programmed in IFDR.

2

3

Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA

takes to reach a high level depends on external signal capacitance and pull-up resistor values.

Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

67

Electrical and Thermal Characteristics

NOTE

Output timing is specified at a nominal 50 pF load.

6

2

5

SCL

SDA

3

9

1

4

7

8

2

Figure 46. Timing Diagram – I C Input/Output

3.3.19 J1850

See the MPC5121e/MPC5123 Reference Manual.

3.3.20 PSC

The Programmable Serial Controllers (PSC) support different modes of operation (UART, Codec, AC97, SPI). UART is an

asynchronous interface, there is no AC characteristic.

2

3.3.20.1 Codec Mode (8,16,24 and 32-bit)/I S Mode

2

Table 42. Timing Specifications – 8,16, 24, and 32-bit CODEC/I S Master Mode

Symbol

Description

Min

Typ

Max

Units SpecID

1

2

3

4

5

6

7

8

Bit Clock cycle time, programmed in CCS register

Clock duty cycle

40.0

45

—

50

—

55

ns

A20.1

A20.2

A20.3

A20.4

A20.5

A20.6

A20.7

A20.8

1

%

Bit Clock fall time

7.9

8.4

9.3

—

ns

Bit Clock rise time

—

FrameSync valid after clock edge

FrameSync invalid after clock edge

Output Data valid after clock edge

Input Data setup time

—

6.0

1

Bit Clock cycle time

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

68

Freescale Semiconductor

Electrical and Thermal Characteristics

1

BitClk Output

(CLKPOL=0)

3

2

4

3

BitClk Output

(CLKPOL=1)

4

6

5

FrameSync Output

(SyncPol = 1)

FrameSync Output

(SyncPol = 0)

7

TxD

Output

8

RxD

Input

2

Figure 47. Timing Diagram – 8, 16, 24, and 32-bit CODEC/I S Master Mode

2

Table 43. Timing Specifications – 8, 16, 24, and 32-bit CODEC/I S Slave Mode

Symbol

Description

Min

Typ

Max

Units

SpecID

1

2

3

4

5

6

Bit Clock cycle time

Clock duty cycle

40.0

—

50

—

ns

A20.9

A20.10

A20.11

A20.12

A20.13

A20.14

1

%

FrameSync setup time

1.0

—

ns

Output Data valid after clock edge

Input Data setup time

14.0

—

1.0

Input Data hold time

—

1

Bit Clock cycle time

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

69

Electrical and Thermal Characteristics

1

BitClk Input

(CLKPOL=0)

2

BitClk Input

(CLKPOL=1)

FrameSync Input

(SyncPol = 1)

3

FrameSync Input

(SyncPol = 0)

4

TxD

Output

5

RxD

Input

6

2

Figure 48. Timing Diagram – 8,16, 24, and 32-bit CODEC/I S Slave Mode

3.3.20.2 AC97 Mode

Table 44. Timing Specifications – AC97 Mode

Symbol

Description

Min

Typ

Max

Units

SpecID

1

2

3

4

5

6

7

Bit Clock cycle time

Clock pulse high time

Clock pulse low time

—

81.4

40.7

—

ns

A20.15

A20.16

A20.17

A20.18

A20.19

A20.20

A20.21

—

FrameSync valid after rising clock edge

Output Data valid after rising clock edge

Input Data setup time

—

13.0

14.0

—

1.0

—

Input Data hold time

—

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

70

Freescale Semiconductor

Electrical and Thermal Characteristics

1

BitClk

(CLKPOL=0)

Input

3

2

4

FrameSync

(SyncPol = 1)

Output

5

Sdata_out

Output

6

7

Sdata_in

Input

Figure 49. Timing Diagram – AC97 Mode

3.3.20.3 SPI Mode

Table 45. Timing Specifications – SPI Master Mode, Format 0 (CPHA = 0)

Symbol

Description

Min

Max

Units SpecID

1

2

SCK cycle time, programable in the PSC CCS register

SCK pulse width, 50% SCK duty cycle

Slave select clock delay, programable in the PSC CCS register

Output Data valid after Slave Select (SS)

Output Data valid after SCK

30.0

15.0

30.0

—

ns

A20.26

A20.27

A20.28

A20.29

A20.30

A20.31

A20.32

A20.33

A20.34

A20.35

A20.36

3

—

4

8.9

—

5

—

6

Input Data setup time

6.0

1.0

—

7

Input Data hold time

—

8

Slave disable lag time

TSCK

—

9

Sequential Transfer delay, programmable in the PSC CTUR / CTLR register

Clock falling time

15.0

—

10

11

7.9

Clock rising time

—

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

71

Electrical and Thermal Characteristics

1

11

10

11

SCK

(CLKPOL=0)

Output

2

SCK

(CLKPOL=1)

Output

9

8

3

SS

Output

5

4

MOSI

Output

6

MISO

Input

7

Figure 50. Timing Diagram – SPI Master Mode, Format 0 (CPHA = 0)

Table 46. Timing Specifications – SPI Slave Mode, Format 0 (CPHA = 0)

Symbol

Description

Min

Max

Units

SpecID

1

2

3

4

5

6

7

8

9

SCK cycle time, programable in the PSC CCS register

SCK pulse width, 50% SCK duty cycle

Slave select clock delay

30.0

15.0

1.0

—

ns

—

A20.37

A20.38

A20.39

A20.40

A20.41

A20.42

A20.43

A20.44

A20.45

—

Input Data setup time

—

Input Data hold time

—

Output data valid after SS

14.0

—

Output data valid after SCK

—

Slave disable lag time

0.0

30.0

Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time

—

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

72

Freescale Semiconductor

Electrical and Thermal Characteristics

1

SCK

(CLKPOL=0)

Input

2

SCK

(CLKPOL=1)

Input

9

8

3

SS

Input

5

4

MOSI

Input

7

6

MISO

Output

Figure 51. Timing Diagram – SPI Slave Mode, Format 0 (CPHA = 0)

Table 47. Timing Specifications – SPI Master Mode, Format 1 (CPHA = 1)

Symbol

Description

Min

Max

Units

SpecID

1

2

SCK cycle time, programable in the PSC CCS register

SCK pulse width, 50% SCK duty cycle

Slave select clock delay, programable in the PSC CCS register

Output data valid

30.0

15.0

30.0

—

ns

A20.46

A20.47

A20.48

A20.49

A20.50

A20.51

A20.52

A20.53

A20.54

A20.55

3

—

4

8.9

—

5

Input Data setup time

6.0

1.0

—

6

Input Data hold time

—

7

Slave disable lag time

TSCK

—

8

Sequential Transfer delay, programable in the PSC CTUR / CTLR register

Clock falling time

15.0

—

9

7.9

10

Clock rising time

—

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

73

Electrical and Thermal Characteristics

1

10

9

SCK

(CLKPOL=0)

Output

2

10

SCK

(CLKPOL=1)

Output

3

8

7

SS

Output

4

MOSI

Output

5

MISO

Input

6

Figure 52. Timing Diagram – SPI Master Mode, Format 1 (CPHA = 1)

Table 48. Timing Specifications – SPI Slave Mode, Format 1 (CPHA = 1)

Symbol

Description

Min

Max

Units

SpecID

1

2

3

4

5

6

7

8

SCK cycle time, programable in the PSC CCS register

SCK pulse width, 50% SCK duty cycle

Slave select clock delay

30.0

15.0

0.0

—

ns

A20.56

A20.57

A20.58

A20.59

A20.60

A20.61

A20.62

A20.63

—

Output data valid

—

14.0

—

Input Data setup time

2.0

Input Data hold time

1.0

—

Slave disable lag time

0.0

—

Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time

30.0

—

NOTE

Output timing is specified at a nominal 50 pF load.

MPC5121E/MPC5123 Data Sheet, Rev. 5

74

Freescale Semiconductor

Electrical and Thermal Characteristics

1

SCK

(CLKPOL=0)

Input

2

SCK

(CLKPOL=1)

Input

8

7

3

SS

Input

5

6

MOSI

Input

4

MISO

Output

Figure 53. Timing Diagram – SPI Slave Mode, Format 1 (CPHA = 1)

3.3.21 GPIOs and Timers

The MPC5121e/MPC5123 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The

external events (GPIO or timer inputs) are asynchronous to the system clock. The inputs must be valid for at least tIOWID to

ensure proper capture by the internal IP clock.

Table 49. GPIO/Timers Input AC Timing Specifications

Symbol

Description

Min

Unit

SpecID

t_IOWID

GPIO/Timers inputs—minimum pulse width

2T¹

ns

A21.1

1

T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus frequency of 83 MHz).

3.3.22 Fusebox

Table 50 gives the Fusebox specification.

Table 50. Fusebox Characteristics

Description

Symbol

Min

Max

Units

SpecID

t_FUSEWRProgram time¹for Fuse

125

—

us

A22.1

A22.2

I_FUSEWRProgram current to program one fuse bit

10

mA

1

The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

75

Electrical and Thermal Characteristics

3.3.23 IEEE 1149.1 (JTAG)

Table 51. JTAG Timing Specification

Symbol

Characteristic

TCK frequency of operation

Min

Max

Unit

SpecID

—

1

0

40

1.08

0

25

—

3

MHz

ns

A23.1

A23.2

A23.3

A23.4

A23.5

A23.6

A23.7

A23.8

A23.9

A23.10

A23.11

A23.12

A23.13

A23.14

TCK cycle time

2

TCK clock pulse width measured at 1.5V

3

TCK rise and fall times

4

TRST setup time to tck falling edge¹

TRST assert time

10

5

—

30

—

15

5

6

Input data setup time²

5

7

Input data hold time^

15

0

8

TCK to output data valid³

TCK to output high impedance³

TMS, TDI data setup time.

TMS, TDI data hold time.

TCK to TDO data valid.

9

0

10

11

12

13

5

1

0

TCK to TDO high impedance.

0

1

2

3

TRST is an asynchronous signal. The setup time is for test purposes only.

Non-test, other than TDI and TMS, signal input timing with respect to TCK.

Non-test, other than TDO, signal output timing with respect to TCK.

1

2

VM

TCK

3

VM = Midpoint Voltage

Figure 54. Timing Diagram – JTAG Clock Input

MPC5121E/MPC5123 Data Sheet, Rev. 5

76

Freescale Semiconductor

Electrical and Thermal Characteristics

TCK

4

TRST

5

Figure 55. Timing Diagram – JTAG TRST

TCK

6

7

Input Data Valid

Data Inputs

8

Output Data Valid

Data Outputs

9

Data Outputs

Figure 56. Timing Diagram – JTAG Boundary Scan

TCK

10

11

Input Data Valid

TDI, TMS

12

13

Output Data Valid

TDO

Figure 57. Timing Diagram – Test Access Port

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

77

Electrical and Thermal Characteristics

3.3.24 VIU

The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream.

Figure 58 shows the VIU interface timing and Table 52 lists the timing parameters.

VIU_PIX_CLK

f_{PIX_CLK}

t_DHD

t_DSU

VIU_DATA[9:0]

Figure 58. VIU Interface Timing Diagram

Table 52. VIU Interface Timing Parameters

Parameter

Description

Min

Typ

Max

Unit

SpecID

f_{PIX_CK}

t_DSU

VIU Pixel Clock Frequency

VIU Data Setup Time

VIU Data Hold Time

—

83

—

MHz

ns

A24.1

A24.2

A24.3

2.5

t_DHD

ns

MPC5121E/MPC5123 Data Sheet, Rev. 5

78

Freescale Semiconductor

System Design Information

4

System Design Information

4.1

Power Up/Down Sequencing

Power sequencing between the 1.4 V power supply V

current during power up phase.

and the remaining supplies is required to prevent excessive

DD_CORE

The required power sequence is as follows:

•

Use 12 V/millisecond or slower time for all supplies.

Power up V , PLL_AV , V (if not applied permanently), V , USB PHY, and SATA PHY

DD_MEM_IO

DD_IO

DD

BAT_RTC

supplies first in any order and then power up V

. If required, AV

should be powered up afterwards.

DD_CORE

DD_FUSEWR

•

All the supplies must reach the specified operating conditions before the PORESET can be released.

For power down, drop AV to 0 V first, drop V to 0 V, and then drop all other supplies.

DD_FUSEWR

DD_CORE

V

should not exceed V

, V

, or PLL_AV s by more than 0.4 V at any time,

BAT_RTC DD

DD_CORE

DD_IO

DD_MEM_IO

including power-up.

4.2

System and CPU Core AVDD Power Supply Filtering

Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 59 is a

recommendation for the required filter circuit.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize noise coupled from

DD

nearby circuits.

All traces should be as low impedance as possible, especially ground pins to the ground plane.

The filter for System/Core PLLV to V should be connected to the power and ground planes, respectively, not fingers of the

DD

SS

planes.

In addition to keeping the filter components for System/Core PLLV as close as practical to the body of the MPC5121e as

DD

previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise

onto the portion of that supply between the filter and the MPC5121e.

R1 = 10 

AVDD device pin

Power supply

source

C1 = 1 F

C2 = 0.1 F

Figure 59. Power Supply Filtering

The capacitors for C2 in Figure 59 should be rated X5R or better due to temperature performance. It is recommended to add a

bypass capacitance of at least 1 µF for the V

pin.

BAT_RTC

4.3

Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to

. Unused active high inputs should be connected to V . All NC (no-connect) signals must remain unconnected.

V

DD_IO

SS

Power and ground connections must be made to all external V and V pins of the MPC5121e/MPC5123.

DD

SS

The unused AV

power should be connected to V directly or via a resistor.

SS

DD_FUSEWR

For DDR or LPDDR modes the unused pins MVTT[3:0] for DDR2 Termination voltage can be unconnected.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

79

System Design Information

The SATA PHY needs to be powered even if it is not used in an application. In this case, you should not enable the SATA

oscillator and the SATA PHY by software.

SATA_XTALI

SATA_XTALO

MPC5121e/

MPC5123

V_SS

NC

SATA_ANAVIZ

SATA_RESREF

NC

SATA_TXP

SATA_TXN

NC

SATA_RXP

SATA_RXN

NC

SATA_VDDA_3P3

SATA_VDDA_1P2

SATA_VDDA_VREG

V_{DD_IO}

V_{DD_CORE}

1.7–2.6 V

V_{DD_CORE}

SATA_PLL_VDDA1P2

SATA_PLL_VSSA

SATA_RX_VSSA

SATA_TX_VSSA

V_SS

Figure 60. Recommended Connection for Pins of Unused SATA PHY

USB_XTALI

USB_XTALO

V_SS

NC

MPC5121e/MPC5123

USB_TPA

NC

USB_DP

USB_DN

Weak pull-up or pull-down

USB_VBUS

USB_UID

V_{DD_IO}

V_SS

USB_PLL_GND

USB_PLL_PWR3

USB_RREF

V_SS

USB_VSSA_BIAS

USB_VDDA_BIAS

V_SS

USB_VSSA

USB_VDDA

V_{DD_IO}

Figure 61. Recommended connection for pins of unused USB PHY

4.4

Pull-Up/Pull-Down Resistor Requirements

The MPC5121e/MPC5123 requires external pull-up or pull-down resistors on certain pins.

4.4.1

Pull-Down Resistor Requirements for TEST pin

The MPC5121e/MPC5123 requires a pull-down resistor on the test pin TEST.

MPC5121E/MPC5123 Data Sheet, Rev. 5

80

Freescale Semiconductor

System Design Information

4.4.2

Pull-Up Requirements for the PCI Control Lines

PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain

stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,

PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.

Refer to the PCI Local Bus specification.

4.5

JTAG

The MPC5121e/MPC5123 provides you with an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides

a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port.

The COP Interface provides access to the MPC5121e/MPC5123’s embedded e300 processor and to other on-chip resources.

This interface provides a means for executing test routines and for performing software development and debug functions.

4.5.1

TRST

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1

specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset

performance, the TRST signal must be asserted during power-on reset.

4.5.1.1

TRST and PORESET

The JTAG interface can control the direction of the MPC5121e/MPC5123 I/O pads via the boundary scan chain. The JTAG

module must be reset before the MPC5121e/MPC5123 comes out of power-on reset; do this by asserting TRST before

PORESET is released.

For more details refer to the Reset and JTAG Timing Specification.

PORESET

Required assertion of TRST

TRST

Optional assertion of TRST

Figure 62. PORESET vs. TRST

4.5.2

e300 COP/BDM Interface

There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.

4.5.2.1

Boards Interfacing the JTAG Port via a COP Connector

The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core

through the Freescale standard COP/BDM interface. Table 53 gives the COP/BDM interface signals. The pin order shown

reflects only the COP/BDM connector order.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

81

System Design Information

Table 53. COP/BDM Interface Signals

Internal

External

Pull Up/Down

BDM Pin # MPC5121e/MPC5123 I/O Pin BDM Connector

I/O¹

Pull Up/Down

16

15

14

13

12

11

10

9

—

CKSTP_OUT

—

GND

ckstp_out

KEY

—

I

10 k Pull-up

—

O

—

O

—

O

—

I

HRESET

—

hreset

GND

sreset

N/C

Pull-up

—

10 k Pull-up

—

10 k Pull-up

—

SRESET

—

Pull-up

—

TMS

tms

Pull-up

—

10 k Pull-up

—

8

CKSTP_IN

TCK

ckstp_in

tck

7

Pull-up

—

6

—

VDD²

halted³

trst

5

See Note³

—

4

TRST

Pull-up

—

10 k Pull-up

—

O

I

3

TDI

tdi

2

See Note⁴

qack⁴

1

TDO

tdo

—

1

With respect to the emulator tool’s perspective:

Input is really an output from the embedded e300 core.

Output is really an input to the core.

2

3

4

From the board under test, power sense for chip power.

HALTED is not available from e300 core.

Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5121e/MPC5123

internally ties CORE_QACK to GND in its normal/functional mode (always asserted).

For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG

module, only wiring TRST and PORESET is not recommended.

To reset the MPC5121e/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET

pin of the MPC5121e/MPC5123. The circuitry shown in Figure 63 allows the COP to assert HRESET or TRST separately,

while any other board sources can drive PORESET.

MPC5121E/MPC5123 Data Sheet, Rev. 5

82

Freescale Semiconductor

System Design Information

PORESET

HRESET

COP Header

10 k



HRESET

SRESET

V_{DD_IO}

SRESET

V_{DD_IO}

13

11

16

10 k



10 k

COP Connector

Physical Pinout

TRST

TMS

TCK

4

TRST

1

3

2

4

14

10 k



V_{DD_IO}

TMS

9

5

6

12

10 k

7

8

V_{DD_IO}

TCK

7

V_{DD_IO}

9

10

12

K

2

6

TDO

TDI

TDO

1

3

11

13

15

10 k



V_{DD_IO}

TDI

10 k



16

CKSTP_OUT

CKSTP_IN

V_{DD_IO}

15

8

CKSTP_OUT

10 k



V_{DD_IO}

CKSTP_IN (LPC_CLK)

halted

5⁽³⁾

2⁽⁴⁾

10

NC

qack

NC

Figure 63. COP Connector Diagram

4.5.2.2

Boards Without COP Connector

If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal

(PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 64 shows the connection

of the JTAG interface without COP connector.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

83

System Design Information

PORESET

HRESET

10 k



HRESET

SRESET

V_{DD_IO}

SRESET

10 k



TRST

10 k



V_{DD_IO}

TMS

10 k

V_{DD_IO}

TCK

10 k

V_{DD_IO}

TDI

CKSTP_OUT

TDO

Figure 64. TRST Wiring for Boards without COP Connector

MPC5121E/MPC5123 Data Sheet, Rev. 5

84

Freescale Semiconductor

Package Information

5

Package Information

This section details package parameters and dimensions. The MPC5121e/MPC5123 is available in a Thermally Enhanced

Plastic Ball Grid Array (TEPBGA), see Section 5.1, “Package Parameters,” and Section 5.2, “Mechanical Dimensions,” for

information on the TEPBGA.

5.1

Package Parameters

Table 54. TEPBGA Parameters

Package outline

Interconnects

27 mm  27 mm

516

1.00 mm

Pitch

Module height (typical)

Solder Balls

2.25 mm

96.5 Sn/3.5Ag (VY package)

0.6 mm

Ball diameter (typical)

5.2

Mechanical Dimensions

Figure 65 shows the mechanical dimensions and bottom surface nomenclature of the MPC5121e/MPC5123 516 PBGA

package.

MPC5121E/MPC5123 Data Sheet, Rev. 5

Freescale Semiconductor

85

Package Information

Figure 65. Mechanical Dimension and Bottom Surface Nomenclature of the MPC5121e/MPC5123 TEPBGA

1

All dimensions are in millimeters.

2

Dimensions and tolerances per ASME Y14.5M-1994.

3

Maximum solder ball diameter measured parallel to datum A.

4

Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

MPC5121E/MPC5123 Data Sheet, Rev. 5

86

Freescale Semiconductor

Product Documentation

6

Product Documentation

This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these

types are available at: http://www.freescale.com.

Table 55 provides a revision history for this document.

Table 55. Document Revision History

Revision

Substantive Change(s)

Rev. 0, DraftA

Rev. 0, DraftB

Rev. 0, DraftC

Rev. 1

First Draft (5/2008)

Second Draft (5/2008)

Third Draft (7/2008)

Advance Information (10/2008)

Rev. 2

Technical Data (2/2009)

Rev. 3

Technical Data (2/2009). Corrected Table 5, Footnote 3.

Rev. 3.1

Technical Data (12/2009). Interim release for removing AVDD_FUSERD

throughout document, changing pin D9 to VDD_IO, and adding D9 to list of

pins for VDD_IO.

Rev. 4

Rev 5

Technical Data (1/2010). Minor editorial and graphical updates. 

No technical updates.

— Updated table “DDR and DDR2 SDRAM Timing Specification”, removed

the row of ‘MCK AC differential crosspoint voltage' .

— Updated table “Thermal Resistance Data”.

— Added table “NFC Timing Characteristics in Symmetric Mode ”and

added figure “Read data latch timing in Symmetric Mode”.

—Published as Rev. 5

MPC5121E/MPC5123 Data Sheet, Rev. 5

87

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

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www.freescale.com/support

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any

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limitation consequential or incidental damages. “Typical” parameters that may be

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Document Number: MPC5121E

Rev. 5

02/2012


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