935232410557 [NXP]
IC 0-BIT, 28.6 MHz, OTHER DSP, PQFP80, 12 X 12 X 1.40 MM, PLASTIC, LQFP-80, Digital Signal Processor;
| 型号： | 935232410557 |
| 厂家： | 
NXP |
| 描述： | IC 0-BIT, 28.6 MHz, OTHER DSP, PQFP80, 12 X 12 X 1.40 MM, PLASTIC, LQFP-80, Digital Signal Processor 时钟 外围集成电路 |
| 文件： | 总39页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA8110G
Digital Signal Processor (DSP) for
cameras
1997 Jun 13
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
FEATURES
• High precision digital processing with 9 or 10 bit input
• Different types of CCDs (PAL, NTSC and CIF)
(progressive, interlaced and non-interlaced)
• Black offset preprocessing (including optical black offset
control)
GENERAL DESCRIPTION
• RGB-separation (with contour and white clip signals
generation)
The SAA8110G is designed for desktop video applications
(teleconferencing, video grabbing), surveillance and
video-phone systems.
• RGB-processing (colour space matrix, black control,
knee and gamma)
• RGB-to-YUV conversion (including down-sampling
filters)
The SAA8110G may be applied together with an analog
front-end (TDA8786 including CDS/AGC/ADC), a timing
generator and a microcontroller as shown in
• White balance control
Figs 18 and 19. Other configurations are also possible.
• Y-processing (contour processing, false colour detector,
filters and noise reduction)
The CCD-sensor can be of PAL, NTSC or CIF type (with
complementary mosaic colour filter). The maximum
number of active pixels is limited to 800 samples/line.
The 10-bits digital input may have a pixel frequency of up
to 14.318 MHz.
• UV-processing (false colour correction and noise
reduction)
• Digital output formatter (including CIF-formatter, DTV2,
D1)
The SAA8110G output data is available in a digital and an
analog output format. Two digital output formats are
selectable: DTV2 (CCIR-601 at the input pixel frequency)
and D1 (CCIR-656 at twice the input pixel frequency). It is
also possible to generate the CIF and QCIF formats as
subsets from the processed CCD-image. The analog
output is available in one of four formats: RGB, YUV, YC
or CVBS. The SAA8110G includes a digital
• Analog output preprocessing (including
PAL/NTSC-encoder and DACs)
• Measurement engine (prepared for auto-exposure and
auto-white balance features)
• Miscellaneous functions (e.g. switched mode power
supply pulse generator, control DAC)
• VH-reference and window timing
• Serial interface (selectable I2C-bus or 80C51 UART
PAL/NTSC-encoder and 3 DACs for this purpose.
interface)
Two types of serial interface are selectable: a fast 400 kHz
I2C-bus interface or a 80C51 UART interface (with bit rates
from 1 Mbit/s up to 3.75 Mbit/s depending on the system
clock used). The power dissipation of the SAA8110G can
be optimized for each application using the built-in power
management function.
• Mode control (including power management).
APPLICATIONS
• Desktop video applications
• Surveillance systems
• Video-phone systems.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA8110G
LQFP80
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
SOT315-1
1997 Jun 13
2
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
5.25
UNIT
VDDD
VDDA
VIL
digital supply voltage
3
3
0
5
5
−
−
−
−
V
analog supply voltage
5.25
0.3VDDD
VDDD
0.5
V
LOW level digital input voltage
HIGH level digital input voltage
V
VIH
0.6VDDD
V
VOL
LOW level digital output voltage IOL = −20 µA
HIGH level digital output voltage IOH = 20 µA
−
V
VOH
V
DDD − 0.1
−
V
IDDD(tot)
total digital supply current
total analog supply current
operating ambient temperature
fclk = 14.3 MHz; VDDD = 5 V
−
180
80
30
22
−
200
100
40
mA
mA
mA
mA
°C
mA
fclk = 14.3 MHz; VDDD = 3.3 V −
IDDA(tot)
fclk = 14.3 MHz; VDDA = 5 V
−
f
clk = 14.3 MHz; VDDA = 3.3 V −
35
Tamb
IDMD
0
75
supply current in digital output
mode
fclk = 14.3 MHz; VDDD = 5 V;
note 1
−
185
−
fclk = 14.3 MHz; VDDD = 3.3 V −
85
−
mA
Note
1. When digital mode is selected, VDDA supply pins can be connected to ground.
1997 Jun 13
3
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
BLOCK DIAGRAM
GM1K58
f
1997 Jun 13
4
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
PINNING
SYMBOL
VDDD(C1)
PIN
I/O
DESCRIPTION
1
I
I
digital supply 1 for digital core and CLK1 related peripherals
system- or pixel clock
CLK1
2
VSYNCIN
HSYNCIN
FIIN
3
I
vertical synchronization input
4
I
horizontal synchronization input
5
I
field identification signal input
VSSD(C1)
CCD9
CCD8
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
VSSD(C2)
SCLK
6
I
digital ground 1 for digital core and CLK1 related peripherals
(preprocessed) AD-converted CDD-signal bit 9 (MSB)
(preprocessed) AD-converted CDD-signal bit 8
(preprocessed) AD-converted CDD-signal bit 7
(preprocessed) AD-converted CDD-signal bit 6
(preprocessed) AD-converted CDD-signal bit 5
(preprocessed) AD-converted CDD-signal bit 4
(preprocessed) AD-converted CDD-signal bit 3
(preprocessed) AD-converted CDD-signal bit 2
(preprocessed) AD-converted CDD-signal bit 1
(preprocessed) AD-converted CDD-signal bit 0 (LSB)
digital ground 2 for digital core and CLK1 related peripherals
serial clock to TDA8786
7
I
8
I
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I
I
I
I
I
I
I
I
O
I
VSSA(CD)
CDACOUT
CDACRBIAS
VDDA(CD)
SDATA
STROBE
SMP
analog ground for control DAC
O
I
output control DAC
pin to connect external bias resistor for control DAC
analog supply for control DAC
I
O
O
O
O
O
I
serial data to TDA8786
strobe to TDA8786
switch mode pulse for DC-DC
P0
quasi-static control output pin 0
P1
quasi-static control output pin 1
SIS
SNERT/I2C-bus select input signal
digital supply 2 for digital core and CLK1 related peripherals
reset input
VDDD(C2)
RESET
T2
I
I
I
test mode control signal bit 2
T1
I
test mode control signal bit 1
T0
I
test mode control signal bit 0
VSSA(OB)
OUT3
VDDA(O3)
OUT2
VDDA(O2)
OUT1
VDDA(O1)
I
analog ground for the three output buffers
output buffer 3 (R, V or CVBS)
O
I
analog supply for output buffer OUT3
output buffer 2 (B, U or C)
O
I
analog supply for output buffer OUT2
output buffer 1 (G or Y)
O
I
analog supply for output buffer OUT1
1997 Jun 13
5
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
SYMBOL
VDDA(DC)
PIN
I/O
DESCRIPTION
analog supply for analog core of triple DAC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I
VSSA(BG)
DECOUPL
RBIAS
VDDA(BG)
VDDD(P1)
CLK2
FIOUT
VSYNCOUT
HREF
CREF/PXQ
LLC
I
analog ground for to band gap
O
O
I
pin to be used for external decoupling of band gap
external bias resistor connection for band gap
analog supply for band gap
I
digital supply 1 for CLK2 related peripherals
output clock (CLK2 frequency is 2 × CLK1 frequency)
field identification output pulse
I
O
O
O
O
O
I
vertical synchronization output
horizontal reference output for YUV-port
clock/pixel qualifier output for YUV-port
line-locked system clock output
VSSD(P1)
UV7
digital ground 1 for CLK2 related peripherals
multiplex chrominance UV bit 7 (MSB)
multiplex chrominance UV bit 6
O
O
O
O
O
O
O
O
I
UV6
UV5
multiplex chrominance UV bit 5
UV4
multiplex chrominance UV bit 4
UV3
multiplex chrominance UV bit 3
UV2
multiplex chrominance UV bit 2
UV1
multiplex chrominance UV bit 1
UV0
multiplex chrominance UV bit 0 (LSB)
digital supply for CLK2 related peripherals
luminance Y or multiplexed YUV bit 7 (MSB)
luminance Y or multiplexed YUV bit 6
luminance Y or multiplexed YUV bit 5
luminance Y or multiplexed YUV bit 4
luminance Y or multiplexed YUV bit 3
luminance Y or multiplexed YUV bit 2
luminance Y or multiplexed YUV bit 1
luminance Y or multiplexed YUV bit 0 (LSB)
digital ground 2 for to CLK2 related peripherals
VDDD(P2)
Y7
O
O
O
O
O
O
O
O
I
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VSSD(P2)
VDDD(C3)
A1/SNRES
A0/SNDA
SDA
I
digital supply 3 for digital core and CLK1 related peripherals
I2C-bus address select pin A1 or SNERT reset input
I2C-bus address select pin A0 or SNERT data input/output
I2C-bus data input/output
I
I
I
VSSD(C3)
SCL/SNCL
VSSD(C4)
XIN
I
digital ground 3 for digital core and CLK1 related peripherals
I2C-bus clock/SNERT clock input
I
I
digital ground 4 for digital core and CLK1 related peripherals
input crystal oscillator for subcarrier lock applications
output crystal oscillator for subcarrier lock applications
I
XOUT
O
1997 Jun 13
6
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
V
1
2
3
4
5
6
7
8
9
60 UV1
59 UV2
58 UV3
57 UV4
56 UV5
55 UV6
54 UV7
DDD(C1)
CLK1
VSYNC
HSYNC
FI
IN
IN
IN
V
SSD(C1)
CCD9
CCD8
CCD7
53
V
SSD(P1)
52 LLC
CCD6 10
CCD5 11
CCD4 12
CCD3 13
CCD2 14
CCD1 15
CCD0 16
17
51 CREF/PXQ
50 HREF
SAA8110G
49 VSYNC
OUT
48 FI
OUT
47 CLK2
46
45
V
V
DDD(P1)
DDA(BG)
V
V
44 RBIAS
SSD(C2)
SCLK 18
19
43 DECOUPL
42
41
V
V
SSA(CD)
SSA(BG)
DDA(DC)
CDAC
OUT
20
MGK151
Fig.2 Pin configuration.
7
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
FUNCTIONAL DESCRIPTION
Black offset preprocessing
RGB processing
The RGB processing includes several features:
• Colour space matrix depending on CCD type to be
suitable with different sensor colour filters
The input data is clamped within the optical black pixel
area of the CCD. The size of the digital clamp window is
16 pixels by 128 lines (i.e. TDA8786). It is possible to
differentiate black levels for odd/even lines, pixels and
fields. This comes in addition to the analog preprocessing
clamp which is active on the clamp pulse generated by the
external timing circuit. The analog clamp is included in the
TDA8786.
• Gain correction for R and B signals for white balance
control
• Black offset
• Adjustable knee
• Adjustable gamma function.
The knee function is applied to all three RGB signals.
Its shape is continuously adjustable by changing the slope
and the knee offset point.
RGB separation
PAL/NTSC sensors generate interlaced data adding offset
in the complementary colour pixels. The RGB separation
block with its two line memories generates the three
components Y, 2R − G, and 2B − G for each input data
corresponding to a pixel value of the CCD. Then the
triplet R, G, B is derived. This block also delivers some
contour and white clip information.
To compensate for the non-linear response of display
devices, a gamma correction is applied to R, G and B
signals. It may be adjustable from linear to a 0.35 power
coefficient.
LINE
R
MEMORY
G
RGB
LINE
MEMORY
COLOUR
SEPARATION
B
10
white clip
CCD inputs
vertical contour
MGK153
Fig.3 RGB separation diagram.
R
R
G
B
gain
black
R
R
×
+
black
3 ×
3 ×
KNEE
GAMMA
COLOUR
MATRIX
G
B
G
B
+
black
B
gain
×
+
MGK154
Fig.4 RGB processing.
8
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
• Contour correction allowing an increase of the
RGB-to-YUV block
luminance transitions for a sharper picture
After RGB processing, the channels are separated in a
luminance and two colour difference path:
Y = 0.299 R + 0.597 G + 0.114 B, U = 0.49 (B − Y) and
V = 0.88 (R − Y) . It also contains two down-sampling
filters for U and V signals.
• Black stretch function for contrast enhancement in dark
scenes
• False colour detector used by the UV-processing block
to enable the colour killer
• Filters and noise reduction by coring (only in the high
frequency part of the signal).
Y-processing
The luminance component includes several features:
R
9
Y
(0 to 511)
CONVERSION
G
DOWN-
SAMPLING
& MUX
8
MATRIX
UV
(−128 to 127)
B
MGK155
Fig.5 RGB-to-YUV conversion.
vertical contour
10
false colour
(−512 to 511)
(from RGB-separation)
CONTOUR PROCESSING
AND
FALSE COLOUR DETECTION
8
9
Y
NOISE
REDUCTION
Y
BLACK STRETCH
+
(0, 0.5 to 255.5)
MGK156
Fig.6 Y processing.
9
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
8
8
NOISE
REDUCTION
FALSE COLOUR
CORRECTION
UV GAIN
CONTROL
UV
UV
(−127 to 128)
(−127 to 128)
false colour
white clip
MGK157
(from Y-processing) (from RGB-separation)
Fig.7 UV-processing.
Moreover, using a high resolution PAL and NTSC CCDs,
it is possible to generate the following formats by means of
cutting or down-sampling.
UV-processing
The chrominance component includes several features:
• Noise reduction for high frequencies
• CIF 352 × 288 at 25 frame/second and CIF 352 × 240 at
• False colour correction: a colour killer cuts the false
30 frame/second
colour components in the UV signals
• QCIF 176 × 144 at 25 frame/second and QCIF
176 × 120 at 30 frame/second.
• UV-gain control used to set the correct UV levels for
PAL/NTSC encoding.
Table 1 CIF/QCIF output format for different sensor
As the colour filter saturation levels may be different in the
CCD, the white clip is used in the UV-processing to
suppress colour errors in case of high exposure.
types
INPUT FORMAT
OUTPUT FORMAT
PAL/NTSC-sensor
CIF
CIF
‘full screen’
‘zoom-by-2’
Digital output formatter
This block contains several features:
QCIF ‘full screen’
QCIF ‘zoom-by-2’
QCIF ‘zoom-by-4’
QCIF ‘full screen’
QCIF ‘zoom-by-2’
• Generation of a synchronous clock LLC (twice the clock
frequency)
• Generation of three synchronization signals (HREF,
CREF and VS)
CIF
• Synchronization of the output data to the output clock
LLC
• Generation of a CIF/QCIF output format for several type
of sensors (see Table 1)
• Selection of the required digital output format (8-bit
multiplexed YUV standard D1/CCIR 656, including the
generator of SAV/EAV codes or 16-bit multiplexed YUV
4 : 2 : 2 standard DTV2/CCIR601).
Note that the D1 frequency data rate is twice the DTV2
frequency data rate.
1997 Jun 13
10
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
521 522 523 524 525 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 18 19 20 21 22 23
HSYNC
IN
VSYNC
IN
FI
IN
VSYNC
OUT
FI
OUT
CSYNC
BLANK
BURST
MGK159
Fig.8 Vertical timing NTSC odd field.
258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 280 281 282 283 284 285
HSYNC
IN
VSYNC
IN
FI
IN
VSYNC
OUT
FI
OUT
CSYNC
BLANK
BURST
MGK160
Fig.9 Vertical timing NTSC even field.
11
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
621 622 623 624 625 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 20 2 1 22 23 24 25
HSYNC
IN
VSYNC
IN
FI
IN
VSYNC
OUT
FI
OUT
CSYNC
BLANK
−
+
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
even frame
odd frame
odd frame
(1)
BURST
+
even frame
MGK161
(1) +: burst phase = +135°.
−: burst phase = −135°.
Fig.10 Vertical timing PAL odd field.
308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 332 333 334 335 336 337
HSYNC
IN
VSYNC
IN
FI
IN
VSYNC
OUT
FI
OUT
CSYNC
BLANK
−
+
+
−
+
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
−
+
+
−
odd frame
(1)
BURST
+
even frame
MGK162
(1) +: burst phase = +135°.
−: burst phase = −135°.
Fig.11 Vertical timing PAL even field.
12
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
0
NPIX
HSYNC
BLANK
BURST
HREF
IN
MGK163
Fig.12 Horizontal timing for non-CIF processing.
Y(UV)7
to
YUV
Y(UV)0
SAA8110G
(OUTPUTS
CLOCKED
AT
HOST
LLC
PXQ
CLK2)
HREF
VSYNC
OUT
U
Y
V
Y
U
Y
V
Y
6
Y(UV)
LLC
FF
00
00
SAV
0
0
0
2
4
4
4
PXQ
HREF
MGK164
sample moment
Fig.13 8-bits multiplexed format (D1, CCIR656); example: CIF down-sampling.
13
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Y(UV)7
YUV
to
Y(UV)0
SAA8110G
(OUTPUTS
CLOCKED
AT
LLC
HOST
PXQ
CLK2)
HREF
VSYNC
OUT
U
Y
V
Y
U
Y
V
U Y
N−1 N−1
YUV
LLC
FF
00
00
SAV
FF
00
00
EAV
0
0
0
1
2
2
2
PXQ
HREF
sample moment
MGK165
Fig.14 8-bits multiplexed format (D1, CCIR656); SAV/EAV included.
Y7 to Y0
Y(UV)
UV7 to UV0
UV
SAA8110G
(OUTPUTS
CLOCKED
AT
CLK2)
HOST
LLC
CREF
HREF
VSYNC
OUT
FI
OUT
Y
U
Y
V
Y
2
Y
V
Y
U
Y
V
Y
6
Y(UV)
0
1
3
4
5
U
2
U
6
UV
0
0
2
4
4
LLC
CREF
HREF
MGK166
sample moment
Fig.15 16-bits multiplexed format (DTV2, CCIR601).
14
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Analog output preprocessing
Serial interface
This block contains several features:
• Delay compensation for the luminance signal
• Up-sampling of the UV signal
• PAL/NTSC encoding
The serial interface can either be an I2C-bus or a 80C51
UART (SNERT) (selectable with the SIS pin). Via the serial
interface the external microcontroller can control the
internal settings of the SAA8110G and read/write from/to
the internal RAM work-space linked to the measurement
engine (see list of parameter settings in
• YUV to RGB conversion
Chapter “Programming”). Some of the registers are
double-buffered to prevent that the change of control data
becomes visible on the output display.
• Selection of the required analog output format (RGB,
YUV, YC or CVBS).
The analog outputs are given by three voltage DACs in
RGB or YUV or CVBS or YC format. Channels Y and G
include the sync information. Over-sampling at twice fclk is
made so that external filtering becomes easier. It is also
possible to have an adjustment of the subcarrier via the
serial interface. When CVBS output is used, chrominance
range is halved compared to luminance.
Miscellaneous functions
A three wire bus is used to send 10-bit settings from a
microcontroller to the TDA8786 via the SAA8110G
registers.The SAA8110G supplies picture parameters and
needs some configuration parameters. Those values are
contained in registers and are updated during every
vertical synchronization pulse.
Measurement engine
The measurement engine performs measurements on
some selectable internal signals on frame/field basis and
prepares data for auto exposure, auto focus and auto
white balance processing. It uses an internal RAM
work-space for its control and data handling operations.
The contents of the work-space can be accessed via the
serial interface.
Mode control
This block controls the operation mode of the SAA8110G.
As described in Table 2, four modes may be selected:
depending on power reduction and I2C-bus timing.
Power dissipation management
The power dissipation of the SAA8110G will depend on the
required activity for a certain application. It is possible to
switch off via the serial interface unconcerned parts for a
given application. When an analog output is not used, the
power voltage pin of the DAC can be connected to ground
to limit the power consumption.
Vertical/horizontal reference and window timing and
control
The SAA8110G uses two vertical and horizontal
synchronization input signals (VSYNCIN and HSYNCIN) to
derive internal vertical and horizontal reference signals.
Besides a Field Identification input (FIIN) signal is required.
The timing of the vertical and horizontal input signals
should be such that:
Clock configurations
Following conditions must be fulfilled:
1. The pixel frequency (CLK1) must be line-locked to the
line frequency of HSYNCIN: the number of clock
periods between two HSYNCIN pulses must be a fixed
integer number. The HSYNCIN should be at least one
clock period active HIGH.
• CLK1 should be generated as divide-by-two from CLK2
• The RESET pin should not go LOW before CLK1 and
CLK2 are both HIGH or LOW.
Table 2 SAA8110G mode control
2. The VSYNCIN signal indicates the start of a field
(or frame in case of progressive scanning); this
signal is also required for non-interlaced applications.
The VSYNCIN should be at least one clock period
HIGH.
POWER
to(h)
T2 T1 T0
MODE
REDUCTION I2C-BUS
0
0
0
0
0
0
1
1
0
1
0
1
application on
short
long
short
long
mode
on
3. The FIIN pulse indicates the phase of the field in case
of interlaced applications (FIIN = 0 means odd field).
off
off
1997 Jun 13
15
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Table 3 Sensor and output formats covered by the SAA8110G
PIXEL
FREQUENCY
(MHz)
CCD-formats
RESOLUTION
OUTPUT FORMATS
DIGITAL
ANALOG
FRAME SCANNING AND ACTIVE
TOTAL
H/V
STANDARD
CIF
FREQUENCY (Hz)
H/V
DTV2/D1 CIF
non-interlaced
non-interlaced
non-interlaced
interlaced
60
50
352/243
352/288
429/262
432/312
910/262
910/525
908/312
908/625
606/262
606/525
618/312
618/625
6.75
6.75
no
no
yes
yes
yes
yes
CIF
NTSC
high resolution
60.054 768/243
29.997 768/494
14.3181
yes
yes
yes
yes
yes
yes
no
yes
yes
yes
yes
PAL
high resolution
non-interlaced
interlaced
50
25
60
30
50
25
752/288
752/582
512/243
512/492
512/288
512/582
14.1875
9.53495
NTSC
medium resolution
non-interlaced
interlaced
PAL
non-interlaced
interlaced
9.65625
no
medium resolution
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
VDDD
PARAMETER
MIN.
MAX.
UNIT
digital supply voltage
analog supply voltage
−0.3
−0.3
−0.1
+7.0
+7.0
+0.1
V
V
V
VDDA
∆VDDD-DDA supply voltage difference between the digital and the analog
supply voltages
VI
input voltage
−0.3
−0.3
−
VDD + 0.3
VDD + 0.3
1
V
VO
Ptot
Tstg
Tj
output voltage
V
total allowed power dissipation at Tamb = 75 °C
storage temperature
W
°C
°C
−55
−
+150
junction temperature
125
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
50
UNIT
K/W
thermal resistance from junction to ambient
1997 Jun 13
16
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDACs specification
OUTPUTS PINS OUT1 TO OUT3 (IN CASE OF SCALE FACTOR = 1)
Vo
output voltage (see note 1)
code 0
0
0.2
0.3
V
V
code 511
1.3
1.5
1.6
Voffset
amplitude offset voltage between
DACs
−60
+60
mV
INPUTS
Rbias
bias resistor
note 2
note 3
note 2
note 3
14
44
−
15
47
21
70.6
−
16
50
−
kΩ
kΩ
Ω
Rext
external anti-reflection resistor
decoupling capacitor
−
−
Ω
Cdecoup
10
100
nF
TRANSFER FUNCTION
RES
resolution
−
−
−
−
9
−
bit
NLdiff
NLint
differential non-linearity
integral non-linearity
−
1.5
1.5
45
LSB
LSB
dB
−
THD60
total harmonic distortion at 60%
of full-scale
fclk = 30 MHz, fi = 1 MHz,
VDDA = 5 V
55
S/N
signal-to-noise ratio
fclk = 30 MHz, fo = 1 MHz,
−
45
38
dB
VDDA = 5 V
APPLICATION1: PAL/NTSC HIGH RESOLUTION
VDD1
VDD2
CR
supply voltage
supply voltage
conversion rate
clock frequency
analog bandwidth
4.5
3.0
−
5.0
5.5
3.6
−
V
3.3
V
28.6
28.6
7.6
MHz
MHz
MHz
fclk
−
−
Ba
−
−
APPLICATION 2: PAL/NTSC MEDIUM RESOLUTION
VDD1
VDD2
fclk
supply voltage
supply voltage
clock frequency
analog bandwidth
4.5
3.0
−
5.0
3.3
19
5.5
3.6
−
V
V
MHz
MHz
Ba
−
6.5
−
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP (see Fig.16)
tPD
propagation delay time
settling time
to 50% value
−
−
−
9
13
11
30
ns
ns
ns
tst(10-90)
tst(LSB)
10% to 90% full-scale
9
setting time (to ±1 LSB)
25
1997 Jun 13
17
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CDAC specification (VDD = 5 V)
Lint
integral linearity
−
−
−
−
−
1
LSB
1
Ldiff
differential linearity
output voltage at pin CDAC
⁄
LSB
mV
V
2
Vo(CDAC)
code 0
10
300
−
code 61, VDDA = 5 V
code 61, VDDA = 3.3 V
−4.6
3
4.95
3.25
13
−
V
Ro(CDAC)
fclk
output resistance at pin CDAC
clock frequency
−
−
Ω
−
28.6
10
−
MHz
kΩ
pF
ns
RL
load resistance
−
−
CL
load capacitance
−
−
10
104
tPD
propagation delay time
to 50% value (see Fig.17),
−
−
VDDA = 5 V
tst(10-90)
settling time
setting time
10% to 90% full-scale (see
Fig.16)
−
−
9
−
−
ns
ns
tst(LSB)
to ±1 LSB (see Fig.16)
25
INPUTS RELATED TO CLK1: CCD0 TO CCD9, VSYNCIN, HSYNCIN, FIIN
tsu(i)(D)1
data input set-up time CCD
inputs, HSYNCIN, VSYNCIN, FIIN
0
0
3
1
5
2
ns
ns
tsu(i)(D)2
data input set-up time SNRES and
SNDA
th(i)(CCD)
th(i)(D)
data hold time CCD inputs
data input hold time
−1
−
+1
3
ns
ns
VSYNCIN, HSYNCIN, FIIN
0
1
OUTPUTS RELATED TO CLK2: Y7 TO Y0, UV7 TO UV0, CREF, HREF, VSYNCOUT, FIOUT AND LLC
th(o)(D)
td(o)(D)
data output hold time
data output delay time
−
−
8
22
31
ns
ns
25
OUTPUTS RELATED TO CLK1: SDATA, STROBE, SMP, P0, P1 AND SCLK
th(o)(D)
td(o)(D)
δclk
data output hold time
data output delay time
clock duty cycle
−
13
15
−
21
24
60
ns
ns
%
−
40
Notes
1. When CVBS output is used the chrominance range is halved compared to luminance.
2. Monitor load of 75 Ω with Rext = 21 Ω and Rbias = 15 kΩ at 3.3 V application.
3. Monitor load of 75 Ω with Rext = 70.6 Ω and Rbias = 47 kΩ at 5.0 V application.
1997 Jun 13
18
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
CLK2
code FS
code 0
input code
(example of a full-scale
input data transmission)
1 LSB
(code FS)
10%
50%
90%
(code 0)
1 LSB
t
st(10−90)
MGK167
t
t
st(LSB)
PD
Fig.16 Switching characteristics.
CLK1
t
t
h(i)(D)
su
DATA IN
t
PD
DATA OUT
MGK168
Fig.17 Data input/output timing.
19
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
PROGRAMMING
Overview available write
ADDRESS
SYMBOL
CONTROL0
FUNCTION
miscellaneous; see Table 4
miscellaneous; see Table 5(1)
FORMAT RANGE/VALUE
0
byte
byte
byte
byte
byte
byte
byte
byte
byte
n.a.
n.a.
1
CONTROL1
CONTROL2
OB_STARTL_F0
OB_STARTL_F1
OB_STARTP
OB_PE_F0
2
miscellaneous; see Table 6
n.a.
4
first line optical black window in field 0
first line optical black window in field 1/frame
first pixel optical black window
0 to 255
0 to 255
0 to 255
0
5
7
8
fixed optical black level for even pixel in field 0
fixed optical black level for odd pixel in field 0
9
OB_PO_F0
0
10
OB_PE_F1
fixed optical black level for even pixel in
field 1/frame
0
11
OB_PO_F1
fixed optical black level for odd pixel in
field 1/frame
byte
0
12
13
14
OB_OFFSET_LE
OB_OFFSET_LO
MOSAIC_SEP_S1
optical black offset for even line
optical black offset for odd line
byte
byte
byte
0
0
multiplication-factor for Yn at even line and even
pixel
0 to 255
15
16
17
MOSAIC_SEP_S2
MOSAIC_SEP_S3
MOSAIC_SEP_S4
multiplication-factor for Yn at even line and odd
pixel
byte
byte
byte
0 to 255
0 to 255
0 to 255
multiplication-factor for Yn at odd line and even
pixel
multiplication-factor for Yn at odd line and odd
pixel
18
19
20
21
22
23
24
25
26
27
28
29
34
35
36
37
38
WHITE_CLIP_THR
COL_MAT_P11
COL_MAT_P12
COL_MAT_P13
COL_MAT_P21
COL_MAT_P22
COL_MAT_P23
COL_MAT_P31
COL_MAT_P32
COL_MAT_P33
COL_MAT_RGAIN
COL_MAT_BGAIN
BLACK_LEVEL_R
BLACK_LEVEL_G
BLACK_LEVEL_B
threshold for white clip
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
6 bits
768 to 1023
−128 to 127
−128 to 127
−128 to 127
−128 to 127
−128 to 127
−128 to 127
−128 to 127
−128 to 127
−128 to 127
0 to 255
colour matrix coefficient p11
colour matrix coefficient p12
colour matrix coefficient p13
colour matrix coefficient p21
colour matrix coefficient p22
colour matrix coefficient p23
colour matrix coefficient p31
colour matrix coefficient p32
colour matrix coefficient p33
colour matrix R-gain factor(1)
colour matrix B-gain factor(1)
fixed R-black level offset(1)
fixed G-black level offset(1)
fixed B-black level offset(1)
0 to 255
−128 to 127
−128 to 127
−128 to 127
0 to 255
RGB_KNEE_OFFSET offset for RGB-knee(1)
GAMMA_BALANCE
gamma multiplication factor (LS)(1)
0 to 63
1997 Jun 13
20
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
ADDRESS
SYMBOL
NPIX_LSB
FUNCTION
number of pixels on a line
FORMAT RANGE/VALUE
39
40
41
42
43
44
45
46
47
48
byte
2 bits
byte
byte
byte
byte
byte
byte
byte
byte
0 to 255
0 to 3
NPIX_MSB
number of pixels on a line
FPIX_ACT
number of first active pixel on a line
number of last active pixel on a line
number of first active line in field 0
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
see Table 7
0 to 255
LPIX_ACT_LSB
FLINE_ACT_F0
LLINE_ACT_F0_LSB number of last active line in field 0
FLINE_ACT_F1_LSB number of first active line in field 1/frame
LLINE_ACT_F1_LSB number of last active line in field 1/frame
ACT_LINES_MSB
CTR_UPD_LINE
MSBs of active line numbers
number of line for double buffered update control
registers
49
KCOMB
vertical contour comb filter coefficient (MS)
3 bits
4 bits
byte
0 to 7
0 to 15
0 to 255
0 to 15
0 to 15
0 to 63
0 to 63
0 to 255
0 to 127
0
VCGAIN
CLDLEV
HCHGAIN
HCLGAIN
CNCLEV
CONGAIN
FCDLEV
YNCLEV
YGAIN
vertical contour gain (LS)
50
51
contour level dependancy level(1)
horizontal contour band pass filter high gain (MS)
horizontal contour band pass filter low gain (LS)
contour noise coring level(1)
4 bits
4 bits
6 bits
byte
52
53
54
55
56
57
contour gain factor
false colour detect level
byte
Y (luminance) noise coring level
Y (luminance) gain factor(1)
byte
byte
YCMPDEL
Y (luminance) compensation delay
4 bits
−3 to 4
see Table 8
58
59
60
61
62
63
64
65
66
UVNCLEV
UV (chrominance) noise coring level
U(B − Y) gain factor(1)
V(R − Y) gain factor(1)
DTO frequency (MSB)(1)
DTO frequency(1)
DTO frequency (LSB)(1)
PHASE_SHIFT colour subcarrier
BURST_LEVEL colour burst
AWB_A (ME)
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
6 bits
byte
6 bits
byte
byte
0 to 255
0
UGAIN
VGAIN
0
DTO_FREQ_LSB
DTO_FREQ_ISB
DTO_FREQ_MSB
PHASESHIFT
BURST_LEVEL
A
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
−98
pole_thresh #A (DPD)
0 to 255
−104
−68
67
68
69
70
B
C
D
E
AWB_B (ME); pole_thresh #B (DPD)
AWB_C (ME); pole_thresh #A (DPD)
AWB_D (ME); pole_thresh #B (DPD)
AWB_E (ME)
126
63
pole_thresh #A (DPD)
63
71
72
F
AWB_F (ME)
0
pole_thresh #B (DPD)
0
HIGHLIGHTTHR
highlight-threshold (ME); pole_thresh #A(DPD)
60
1997 Jun 13
21
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
ADDRESS
SYMBOL
FUNCTION
FORMAT RANGE/VALUE
73
ME_RESSCALE
ME_sync + ME_Resultscale (ME)
4 bits
0, 1
see Table 9
pole_thresh #B (DPD)
byte
6 bits
byte
2 bits
byte
byte
byte
byte
byte
5 bits
byte
byte
byte
byte
byte
byte
4 bits
byte
byte
0 to 255
see Table 10
256 + (0 to 255)
see Table 20
see Table 11
see Table 12
0 to 255
74
78
79
82
83
84
85
86
87
88
89
90
91
92
93
94
126
127
MWHVGRID
WHITECLIP
measurement horizontal and vertical grid
white clip limiter level for analog outputs
auto black attack slope control
digital output processing control
digital output processing control(1)
CIF-window start pixel (LSBs)
AUTO_BLACK
DOP_CNTRL0
DOP_CNTRL1
CIF_WSTRT
CIF_WSTRT
PRE_SI_LSB
PRE_SI_MSB
SMP_CNTRL
PRE_CNTRL
DIG_SETUP
BLANKLEV
CIF-window start line (LSBs)
0 to 255
control data for analog preprocessing
control data/address for analog preprocessing
control for switched mode power supply
preprocessing/timing control
0 to 255
see Table 13
0
see Table 14
0.255
set-up in digital output
blanking level in analog output
set-up level in analog output
analog output format control(1)
0 to 255
BL-SETUP
0 to 255
AOF_CNTRL
PRE_PROC_DEL
RAMWRPTR
RAMWRDATA
see Table 15
0 to 15
control compensation delay W.I.L preprocessing
write pointer for RAM work-space
write data for RAM work-space
0 to 223
0 to 255
Note
1. Double buffered write register.
1997 Jun 13
22
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Register details
Table 4 CONTROL0
NAME.BITNR
CONTROL0.0
NAME
FUNCTION
Auto Optical Black ON/OFF
AUTO_OPT_BLACK
SENS_VGA
CONTROL0.1
CONTROL0.2
CONTROL0.3
CONTROL0.4
CONTROL0.5
RGB-bayer/complementary mosaic colour filter
complementary mosaic colour filter
MOSAIC_FIL_TYPE
PIX_PHASE
toggle phase for pixel in colour separation
toggle phase for line in colour separation
toggle phase for field in colour separation
LINE_PHASE
FIELD_PHASE
Table 5 CONTROL1
NAME.BITNR
NAME
FUNCTION
CONTROL1.2
CONTROL1.3
CONTROL1.4
CONTROL1.5
CONTROL1.6
CONTROL1.7
RGB_KNEE_K
RGB_KNEE_K
MED_RES
compression factor for RGB-knee (see Table 16)(1)
compression factor for RGB-knee (see Table 16)(1)
medium resolution for PAL/NTSC encoder
choose between PAL/NTSC
black stretch scaling factor (see Table 17)(1)
black stretch scaling factor (see Table 17)(1)
PAL_NTSC
BSSCALE
BSSCALE
Note
1. Double buffered write register.
Table 6 CONTROL2
NAME.BITNR
NAME
FCC_FILTER+
NI
FUNCTION
CONTROL2.0
CONTROL2.1
CONTROL2.2
CONTROL2.3
CONTROL2.4
CONTROL2.5
CONTROL2.6
CONTROL2.7
false colour low-pass filter ON/OFF
non-interlaced/interlaced
DTOMWL_LSB
DTOMWL_MSB
WH_CL_MAP
WH_CL_MAP
FC_MAP
DTO measurement window length(1)
DTO measurement window length(1)
white clip mapping on UV-grid (see Table 18)
white clip mapping on UV-grid (see Table 18)
false colour mapping on UV-grid (see Table 19)
false colour mapping on UV-grid (see Table 19)
FC_MAP
Note
1. Double buffered write register.
Table 7 ACT_LINES_MSB
NAME.BITNR
FUNCTION
ACT_LINES_MSB.0 and ACT_LINES_MSB.1
ACT_LINES_MSB.2 and ACT_LINES_MSB.3
ACT_LINES_MSB.4 and ACT_LINES_MSB.5
ACT_LINES_MSB.6 and ACT_LINES_MSB.7
bits 8 and 9 for last active pixel number on a line
bits 8 and 9 for last active line number in field 0
bits 8 and 9 for first active line number in field 1/frame
bits 8 and 9 for last active line number in field 1/frame
1997 Jun 13
23
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Table 8 YCMPDEL
FUNCTION
(1 + 4 × B3 + B2 + 2 × B1 + 1 × B0) × td
CONTENT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1td
2td
3td
4td
5td
6td
7td
8td
5td
6td
7td
8td
9td
10td
11td
12td
Table 9 MECNTRL
NAME.BITNR
FUNCTION
DEFAULT
MECNRTL.0, MECNRTL.1,
MECNRTL.2
ME_Resultscaler selection (0, 2, 4, 8, 16, 32)
1
MECNRTL.3
ME_Sync (synchronize field/frame toggle of measurement engine)
0
Table 10 MWHVGRID
NAME.BITNR
FUNCTION
DEFAULT
MWHVGRID.0, MWHVGRID.1,
horizontal ME-window pixel size selection
4
MWHVGRID.2 and MWHVGRID.3
MWHVGRID.4 and MWHVGRID.5 vertical ME-window pixel size selection
4
Table 11 DOP_CNTRL0
NAME.BITNR
FUNCTION
horizontal CIF-processing control bits HCIF.0 and HCIF.1 (see Table 21)
DOP_CNTRL0.0 and
DOP_CNTRL0.1
DOP_CNTRL0.2 and
DOP_CNTRL0.3
vertical CIF-processing control bits VCIF.0 and VCIF.1 (see Table 22)
temporal CIF-processing control bits TCIF.0 and TCIF.1 (see Table 23)
DOP_CNTRL0.4 and
DOP_CNTRL0.5
DOP_CNTRL0.6
DOP_CNTRL0.7
CIF-processing enabled/disabled (by-pass)
CIF-format/QCIF format
1997 Jun 13
24
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Table 12 DOP_CNTRL1
NAME.BITNR
FUNCTION
DEFAULT
DOP_CNTRL1.0 and DOP_CNTRL1.1
DOP_CNTRL1.2 and DOP_CNTRL1,3
DOP_CNTRL1.4
horizontal pixel start MSBs for CIF-window
vertical line start MSBs for CIF-window
PXQ-output/CREF-output
−
−
−
−
−
1
DOP_CNTRL1.5
CIF-sensor applied/non CIF-sensor applied
d1/d2 output format
DOP_CNTRL1.6
DOP_CNTRL1.7
DOP-processing active/disabled
Table 13 PRE_SI_MSB
NAME.BITNR
FUNCTION
PRE_SI_MSB.0 and PRE_SI_MSB.1
PRE_SI_MSB.2 to PRE_SI_MSB.4
control data bits d8 and d9
control address bits a0 to a2
Table 14 PRE_CNTRL
NAME.BITNR
FUNCTION
PRE_CNTRL.0 to PRE_CNTRL.5
PRE_CNTRL.6 and PRE_CNTRL.7
control DAC-data bits 0 to 5
static control outputs P0 and P1
Table 15 AOF_CNTRL
NAME.BITNR
FUNCTION
DEFAULT
AOF_CNTRL.0 and AOF_CNTRL.1
AOF_CNTRL.2 and AOF_CNTRL.3
AOF_CNTRL.4 and AOF_CNTRL.5
AOF_CNTRL.6
analog output format selection (see Table 24)
scale factor #1 for GY-multiplex (see Table 25)
1
−
scale factor #2 for BU-, C- and RV-multiplex (see Table 26)
analog output processing active/disabled
−
1
−
AOF_CNTRL.7
triple DAC output range control large/small
Table 16 Knee compression factors
Table 17 Black stretch scaling factors
W 1.n
W 1.n
COMPRESSION FACTOR
SCALING FACTOR
n = 3
n = 2
n = 7
n = 6
1
⁄
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
8
1
⁄
1
⁄
4
4
3
⁄
1
⁄
8
2
1
⁄
3
⁄
2
4
1997 Jun 13
25
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
Table 18 White-clip detection spreading
Table 23 TCIF-control
W 2.n
W 82.n
SPREADING FILTER
PROCESSING
n = 5
n = 4
n = 5
n = 4
0
0
1
0
1
X
[0 0 1 0 0]
[0 1 1 1 0]
[1 1 1 1 1]
0
0
1
1
0
1
0
1
one-to-one copy
down-sample by 2
down-sample by 4
down-sample by 8
Table 19 False colour detection spreading
Table 24 Analog output format selection
W 2.n
SPREADING FILTER
W 93.n
n = 7
n = 6
FORMAT
n = 1
n = 0
0
0
1
0
1
X
[0 0 1 0 0]
[0 1 1 1 0]
[1 1 1 1 1]
0
0
1
1
0
1
0
1
RGB
YUV
YC
Table 20 Auto black attack slope control
CVBS
W 79.n
SLOPE FACTOR
Table 25 Scale #1 selection
n = 7
n = 6
W 93.n
1
⁄
0
0
1
1
0
1
0
1
4
SCALE FACTOR
1
⁄
n = 3
n = 2
8
1
⁄
0
1
1
X
0
1
1
2
16
1
⁄
32
3
⁄
2
Table 21 HCIF-control
Table 26 Scale #2 selection
W 82.n
SLOPE FACTOR
W 93.n
n = 1
n = 0
SCALE FACTOR
n = 5
n = 4
0
0
1
0
1
X
down-sample by 4
down-sample by 2
one-to-one copy
0
1
1
X
0
1
1
2
3
⁄
2
Table 22 VCIF-control
W 82.n
PROCESSING
n = 3
n = 2
0
0
1
1
0
1
0
1
down-sample by 4
down-sample by 2
one-to-one copy
up-sample by 2
1997 Jun 13
26
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
APPLICATION INFORMATION
TDA8786 and SAA8110G can be used with Sharp CCDs. TDA8786A and SAA8110G can be used with Sony CCDs.
Table 27 gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110G. This
overview is not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more
recent ones.
Table 27 Possible components for the application of Figs 18 and 19.
NTSC
PAL
CCD TYPE
COMPONENT TYPE
MEDIUM
HIGH
MEDIUM
HIGH
RESOLUTION
RESOLUTION
RESOLUTION
RESOLUTION
SONY CCDs
CCD
LZ2313H5
LZ2353A
LZ2323H5
LZ2363
V-driver
LR36683N
timing generator
CCD
LZ95G55
LZ95G71
LZ95G55
LZ95G71
SHARP CCDs
ICX056AK
ICX068AK
ICX057AK
ICX069AK
V-driver
CXD1250MN; CXD1267N
timing generator
CXD1257AR
CXD1265R
CXD1257AR
CXD1265R
Notes to the application diagram
• In the configuration of Figs 18 and 19, the microcontroller reads and writes data from/to the DSP using the SNERT-bus
(UART-mode 0). Optional external control is available through the I2C-bus.
• Free I/O pins of the microcontroller can be used to control PGG, or for other purposes.
• 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD.
• A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office.
1997 Jun 13
27
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
P0
P1
P0 (optional, PPG setting)
P1 (optional, PPG settings)
CDAC
CDAC (optional, can be used for frequency tuning)
OUT
OUT
CLK1
CLK1 (to ADC and DSP)
CLK2 (to DSP, CLK2 = 2 × CLK1)
CDSPULSE1
CLK2
CDSPULSE1
CDSPULSE2
CLAMPCDS
CLAMPOPB
CLAMPADC
PreBlank
CDSPULSE2
VERTICAL DRIVER
CLAMPCDS (CLAMP CDS, OPB, ADC can be the same)
CLAMPOPB
(PPG)
digital ground
CLAMPADC
analog ground
PreBlank (optional)
Horizontal Drive
Vertical Drive
Field Id
HD (to DSP and µC)
VD (to DSP and µC)
CLK1
FI (to DSP and µC)
CLAMPCDS
CDSPULSE1
CDSPULSE2
Electrical Reset
Shutter Pulse
V4
V3 V2 V1
VERTICAL
H1
H1
H2
100 nF
V
V
DDA1
DDA1
100 nF
DRIVER BUFFER
OEN (optional)
(from microcontroller)
1 µF
Reset
V4 V3 V2 V1
H2
Shutter
V
DDD
CCDout
CCD
OFD level
(optional)
100 nF
CLAMPOPB
PreBlank
48 47 46 45 44 43 42 41 40 39 38 37
CLPOPB
1
OGND1
D9
36
35
34
33
32
31
30
29
28
27
26
25
PBK
−xxV
+xxV
100 nF
2
A
D8
OFDOUT
3
SWITCH MODE
POWER SUPPLIES
(optional)
SMP_CLK
(from DSP)
B
C
D
E
F
G
H
I
D7
AMPOUT
ANALOG TO DIGITAL INTERFACE
AMPOUT
100 nF
4
V
D6
AGND1
DDA1
5
V
D5
CCA1
6
V
DDD
D4
AGCOUT
PBIN
5 V
5 V
5 V
V
V
V
DDA1
DDA2
DDA3
7
TDA8786G
or
TDA8786AG
D3
8
220 nF
220 nF
D2
PBOUT
ADCIN
9
D1
10
11
12
D0
CLPADC
J
V
DGND1
ref
13 14 15 16 17 18 19 20 21 22 23 24
K
10 kΩ
VD (from PPG)
BC848C
CLAMPADC
(from PPG)
100 nF
10 µF
1 nF
V
V
V
DDD
P1.0
DDD
DD
10 kΩ
2
3
4
5
6
7
8
9
V
DDD
44
43
42
41
40
39
38
37
36
35
33
32
31
30
29
28
27
26
25
24
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P1.1
P1.2
V
DDA1
V
SDA
5
SS
MICRO-
CONTROLLER
100
nF
4
EPROM
P1.3
SCL
A2
OEN (optional)
(to ADC)
6
7
8
3
PCF8598
PCF8594
PCF8582
P1.4
PTC
NC
2
V
DDD
4.7
4.7
kΩ
L
V
P1.5
DD
WP
kΩ
1
M
P1.6/SCL
P1.7/SDA
1
nF
1
nF
2.2
nF
200
nF
V
V
V
100 nF
DDD
DDD DDD
4.7 µF
RST
V
10
11
13
14
15
16
17
18
19
20
21
22
DDD
P3.0/RxD
83C54/
83C654
(OM-XXX)
V
DDD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
A0/SN
DA
SCL/SN
RESET_DSP
(to DSP)
CL
P3.5/T1
HD (opt.)
P3.6/WR
FI
IN
P3.7/RD
XTAL2
XTAL1
A1/SN
RES
18 pF
V
12 MHz
SS
MGK393
18 pF
Fig.18 SAA8110G system configuration for camera application (continued in Fig.19).
28
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
26
24
22
20
18
16
14
12
10
8
25
23
21
19
17
15
13
11
9
A1/SN
RES
A0/SN
DA
SDA
SCL/SN
CL
V
DDD
100
nF
7
V
6
5
DDD
100 nF
optional
4
3
2
1
V
V
DDD
DDD
V
DDD
100 nF
V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DDD(C1)
CLK1
UV1
UV2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CLK1
2
VSYNC
HSYNC
IN
IN
UV3
UV4
UV5
UV6
3
VD
HD
4
FI
IN
FI
5
V
SSD(C1)
CCD9
CCD8
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
DIGITAL SIGNAL PROCESSOR
6
UV7
V
7
A
SSD(P1)
8
B
C
D
E
F
G
H
I
LLC
9
CREF/PXQ
HREF
10
11
12
13
14
15
16
17
18
19
20
SAA8110G
VSYNC
OUT
FI
OUT
CLK2
CLK2 (from PPG)
V
V
DDD(P1)
V
DDD
V
DDA(BG)
J
DDA3
100 nF
V
V
47 kΩ
RBIAS
SSD(C2)
SCLK
100 nF
DECOUPL
K
V
SSA(CD)
SSA(BG)
100 nF
V
CDAC
OUT
DDA(DC)
V
DDA3
100 nF
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CDAC
OUT
3
4
1 6
5
10 nF
SVHS
7
2
L(1)
L(1)
Y
68 Ω
L(1)
150 kΩ
V
V
DDA3
DDA3
6
100
nF
100 nF
Green
C
1
11
7
100 nF
100 nF
V
2
3
4
5
12
13
14
15
DDA2
8
V
L(1)
L(1)
DDD
L
68 Ω
L(1)
9
M
RESET_DSP
(from µC)
10
SMP_CLK (to power supply)
U, Blue
V, Red
P0
P1
V
DDD
L(1)
L(1)
68 Ω
L(1)
digital ground
analog ground
CVBS-RCA
CVBS
MGK394
(1) Values depend on DSP output configuration.
Fig.19 SAA8110G system configuration for camera application (continued from Fig.18).
29
1997 Jun 13
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
PACKAGE OUTLINE
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
Q
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v M
A
e
w M
b
p
D
B
H
v M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
4o
0o
0.16 1.5
0.04 1.3
0.25 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.7 0.70
0.3 0.58
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1.0
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-03-24
95-12-19
SOT315-1
1997 Jun 13
30
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Jun 13
31
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 13
32
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
NOTES
1997 Jun 13
33
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
NOTES
1997 Jun 13
34
Philips Semiconductors
Preliminary specification
Digital Signal Processor (DSP) for
cameras
SAA8110G
NOTES
1997 Jun 13
35
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Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp36
Date of release: 1997 Jun 13
Document order number: 9397 750 01576
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The SAA8110G is designed for desktop video applications (teleconferencing, video grabbing), surveillance and video-phone systems.
Cross reference
The SAA8110G may be applied together with an analog front-end (TDA8786 including CDS/AGC/ADC), a timing generator and a
microcontroller . Other configurations are also possible. The CCD-sensor can be of PAL, NTSC or CIF type (with complementary mosaic
colour filter). The maximum number of active pixels is limited to 800 samples/line. The 10-bits digital input may have a pixel frequency of up
to 14.318 MHz.
Models
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
The SAA8110G output data is available in a digital and an analog output format. Two digital output formats are selectable: DTV2 (CCIR-
601 at the input pixel frequency) and D1 (CCIR-656 at twice the input pixel frequency). It is also possible to generate the CIF and QCIF
formats as subsets from the processed CCD-image. The analog output is available in one of four formats: RGB, YUV, YC or CVBS. The
SAA8110G includes a digital PAL/NTSC-encoder and 3 DACs for this purpose.
Two types of serial interface are selectable: a fast 400 kHz I2C-bus interface or a 80C51 UART interface (with bit rates from 1 Mbit/s up to
3.75 Mbit/s depending on the system clock used). The power dissipation of the SAA8110G can be optimized for each application using the
built-in power management function.
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Features
SAA8110G
SAA8110G
l High precision digital processing with 9 or 10 bit input
l Different types of CCDs (PAL, NTSC and CIF) (progressive, interlaced and non-interlaced)
l Black offset preprocessing (including optical black offset control)
l RGB-separation (with contour and white clip signals generation)
l RGB-processing (colour space matrix, black control, knee and gamma)
l RGB-to-YUV conversion (including down-sampling filters)
l White balance control
l Y-processing (contour processing, false colour detector, filters and noise reduction)
l UV-processing (false colour correction and noise reduction)
l Digital output formatter (including CIF-formatter, DTV2, D1)
l Analog output preprocessing (including PAL/NTSC-encoder and DACs)
l Measurement engine (prepared for auto-exposure and auto-white balance features)
l Miscellaneous functions (e.g. switched mode power supply pulse generator, control DAC)
l VH-reference and window timing Serial interface (selectable I2C-bus or 80C51 UART interface)
l Mode control (including power management).
Applications
l Desktop video applications
l Surveillance systems
l Video-phone systems.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr.
Title
Datasheet
Download
SAA8110G Digital Signal Processor (DSP) for
cameras
13-Jun-97
Preliminary
Specification
36
232
Blockdiagram
Blockdiagram of SAA8110G
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
Standard Marking * Reel Dry
Pack, SMD, 13"
SAA8110G/C1
9352 324 10518
SOT315 Full production
SOT315 Full production
SOT315 Full production
-
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
SAA8110GBE
9352 324 10557
9352 566 70518
Standard Marking * Reel Dry
Pack, SMD, 13"
SAA8110G/C1/R1
-
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
9352 566 70557
SOT315 Full production
-
Please read information about some discontinued variants of this product.
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number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and
products from the same functional category.
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Royal Philips Electronics
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