935233310118 [NXP]
IC 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, SO-8, Programmable ROM;
| 型号： | 935233310118 |
| 厂家： | 
NXP |
| 描述： | IC 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, SO-8, Programmable ROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总23页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF85116-3
2048 × 8-bit CMOS EEPROM with
I2C-bus interface
1997 Apr 02
Product specification
Supersedes data of 1997 Feb 24
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
CONTENTS
9
LIMITING VALUES
10
11
12
13
14
CHARACTERISTICS
1
FEATURES
I2C-BUS CHARACTERISTICS
WRITE CYCLE LIMITS
PACKAGE OUTLINES
SOLDERING
2
DESCRIPTION
2.1
3
Remark
QUICK REFERENCE DATA
ORDERING INFORMATION
DEVICE SELECTION
BLOCK DIAGRAM
PINNING
4
14.1
14.2
Introduction
DIP
5
6
14.2.1
14.2.2
14.3
14.3.1
14.3.2
14.3.3
Soldering by dipping or by wave
Repairing soldered joints
SO
Reflow soldering
Wave soldering
Repairing soldered joints
7
8
I2C-BUS PROTOCOL
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.5
Bus conditions
Data transfer
Device addressing
Write operations
Byte/word write
Page Write
Remark
Read operations
Remark
15
16
17
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
8.5.1
1997 Apr 02
2
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
1
FEATURES
2
DESCRIPTION
• Low power CMOS:
The PCF85116-3 is an 16 kbits (2048 × 8-bit) floating gate
Electrically Erasable Programmable Read Only Memory
(EEPROM). By using redundant EEPROM cells it is fault
tolerant to single bit errors. In most cases multi bit errors
are also covered. This feature dramatically increases
reliability compared to conventional EEPROM memories.
Power consumption is low due to the full CMOS
– maximum operating current 1.0 mA
– maximum standby current 10 µA (at 5.5 V),
typical 4 µA
• Non-volatile storage of 16 kbits organized as eight
blocks of 256 × 8-bit each
technology used. The programming voltage is generated
on-chip, using a voltage multiplier.
• Single supply with full operation down to 2.7 V
• On-chip voltage multiplier
As data bytes are received and transmitted via the serial
I2C-bus, a package using eight pins is sufficient. Only one
PCF85116-3 device is required to support all eight blocks
of 256 × 8-bit each.
• Serial input/output I2C-bus (100 kbits/s standard-mode
and 400 kbits/s fast-mode)
• Write operations: multi byte write mode up to 32 bytes
• Write-protection input
Timing of the E/W cycle is carried out internally, thus no
external components are required. A write-protection input
at pin 7 (WP) allows disabling of write-commands from the
master by a hardware signal. When pin 7 is HIGH the data
bytes received will not be acknowledged by the
• Read operations:
– sequential read
– random read
• Internal timer for writing (no external components)
• Power-on-reset
PCF85116-3 and the EEPROM contents are not changed.
2.1
Remark
• High reliability by using redundant EEPROM cells
• Endurance: 1000000 Erase/Write (E/W) cycles at
Tamb = 22 °C
The PCF85116-3 is pin and address compatible to the
PCx85xxC-2 family. The PCF85116-3 covers the whole
address space of 16 kbits; address inputs are no longer
needed. Therefore, pins 1 to 3 are not connected.
The write-protection input is at pin 7.
• 20 years non-volatile data retention time (minimum)
• Pin and address compatible to the PCx85xxC-2 family
(see also Section 2.1)
• 2 kV ESD protection (Human Body model).
3
QUICK REFERENCE DATA
SYMBOL
VDD
PARAMETER
CONDITIONS
MIN.
2.7
MAX.
5.5
UNIT
supply voltage
V
IDDR
IDDW
Istb
supply current read
supply current E/W
standby supply current
fSCL = 400 kHz; VDD = 5.5 V
fSCL = 400 kHz; VDD = 5.5 V
VDD = 2.7 V
−
−
−
−
1.0
1.0
6
mA
mA
µA
VDD = 5.5 V
10
µA
1997 Apr 02
3
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
PCF85116-3P
PCF85116-3T
DIP8
SO8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
SOT96-1
plastic small outline package; 8 leads; body width 3.9 mm
5
DEVICE SELECTION
Table 1 Device selection code
SELECTION
DEVICE CODE
CHIP ENABLE
b2
MEM SEL MEM SEL MEM SEL
R/W
Bit
b7(1)
1
b6
0
b5
1
b4
0
b3
b1
b0
Device
R/W
Note
1. The Most Significant Bit (MSB) ‘b7’ is sent first.
1997 Apr 02
4
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
6
BLOCK DIAGRAM
BM9H2
1997 Apr 02
5
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
7
PINNING
SYMBOL PIN
DESCRIPTION
not connected
handbook, halfpage
n.c.
n.c.
n.c.
VSS
SDA
SCL
WP
VDD
1
2
3
4
5
6
7
8
V
n.c.
n.c.
n.c.
1
2
3
4
8
7
6
5
DD
not connected
WP
PCF85116-3
not connected
SCL
SDA
negative supply voltage
serial data input/output (I2C-bus)
serial clock input (I2C-bus)
write-protection input
positive supply voltage
V
SS
MBH923
Fig.2 Pin configuration.
I2C-BUS PROTOCOL
Data transfer is unlimited in the read mode.
The information is transmitted in bytes and each receiver
acknowledges with a ninth bit.
8
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The serial bus consists of two
bidirectional lines: one for data signals (SDA), and one for
clock signals (SCL).
Within the I2C-bus specifications a low-speed mode (2 kHz
clock rate), a high speed mode (100 kHz clock rate) and a
fast speed mode (400 kHz clock rate) are defined.
The PCF85116-3 operates in all three modes.
Both the SDA and SCL lines must be connected to a
positive supply voltage via a pull-up resistor.
By definition a device that sends a signal is called a
‘transmitter’, and the device which receives the signal is
called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the
master are called ‘slaves’.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not
busy
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
control signals.
Each byte is followed by one acknowledge bit.
This acknowledge bit is a HIGH level, put on the bus by the
transmitter. The master generates an extra acknowledge
related clock pulse. The slave receiver which is addressed
is obliged to generate an acknowledge after the reception
of each byte.
8.1
Bus conditions
The following bus conditions have been defined:
The master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the
slave transmitter.
• Bus not busy: both data and clock lines remain HIGH.
• Start data transfer: a change in the state of the data line,
from HIGH-to-LOW, while the clock is HIGH, defines the
START condition
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse.
• Stop data transfer: a change in the state of the data line,
from LOW-to-HIGH, while the clock is HIGH, defines the
STOP condition
• Data valid: the state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
Set-up and hold times must be taken into account.
A master receiver must signal an end of data to the slave
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master generation of the STOP condition.
8.2
Data transfer
Each data transfer is initiated with a START condition and
terminated with a STOP condition; the number of the data
bytes, transferred between the START and STOP
conditions is limited to 32 bytes in the E/W mode.
1997 Apr 02
6
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
8.3
Device addressing
8.4.2
PAGE WRITE
read: auto increment
handbook, halfpage
handbook, halfpage
1
0
1
0
B
B
B
R/W
B
B
B
WORD ADDRESS
MBH924
write: unchanged
write: auto increment
MBH925
Fig.3 Slave address.
Fig.4 Auto increment of memory address.
Following a START condition the bus master must output
the address of the slave it is accessing. The 4 MSBs of the
slave address are the device type identifier (see Fig.3).
For the PCF85116-3 this is fixed to ‘1010’.
The PCF85116-3 is capable of an 32-byte page write
operation. It is initiated in the same manner as the byte
write operation. The master can transmit up to 32 data
bytes within one transmission. After receipt of each byte
the PCF85116-3 will respond with an acknowledge.
The master terminates the transfer by generating a STOP
condition. The maximum total E/W time in this mode is
10 ms.
The next three significant bits of the slave address field are
the block selection bits. It is used by the host to select one
out of eight blocks (1 block = 256 bytes of memory). These
are, in effect, the three most significant bits of the word
address.
After the receipt of each data byte the six high order bits of
the memory address providing access to one of the
64 pages of the memory remain unchanged. The five low
order bits of the memory address will be incremented only
(see Fig.3). By these five bits a single byte within the page
in access is selected. By an increment the memory
address may change from 31 to 0, from 63 to 32, etc. If the
master transmits more than 32 bytes prior to generating
the STOP condition, data within the addressed page may
be overwritten and unpredictable results may occur. As in
the byte write operation, all inputs are disabled until
completion of the internal write cycles.
The last bit of the slave address defines the operation to
be performed. When R/W is set to logic 1 a read operation
is selected.
8.4
Write operations
8.4.1
BYTE/WORD WRITE
For a write operation the PCF85116-3 requires a second
address field. This address field is a word address
providing access to any one of the eight blocks of memory.
Upon receipt of the word address the PCF85116-3
responds with an acknowledge and awaits the next eight
bits of data, again responding with an acknowledge. Word
address is automatically incremented. The master
terminates the transfer by generating a STOP condition.
8.4.3
REMARK
Write accesses to the EEPROM are enabled if the pin WP
is LOW. When WP is HIGH the EEPROM is
write-protected and no acknowledge will be given by the
PCF85116-3 when data is sent. However, an
acknowledge will be given after the slave address and the
word address.
After this stop condition the E/W cycle starts and the bus
is free for another transmission. Its duration is maximum
10 ms.
During the E/W cycle the slave receiver does not send an
acknowledge bit if addressed via the I2C-bus.
1997 Apr 02
7
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
B
B
B
0
A
A
DATA
A
DATA
A
P
S
WORD ADDRESS
R/W
SLAVE ADDRESS
auto increment
word address
auto increment
word address
MBH926
Fig.5 Auto increment memory address; two byte write.
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
DATA N
DATA N + 1
S
B
B
B
0
A
WORD ADDRESS
A
A
A
R/W
SLAVE ADDRESS
auto increment
word address
auto increment
word address
acknowledge
from slave
P
DATA N + 31
last byte
A
auto increment
word address
MBH927
Fig.6 Page write operation; 32 bytes.
8
1997 Apr 02
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
8.5
Read operations
8.5.1
REMARK
Read operations are initiated in the same manner as write
operations with the exception that the LSB of the slave
address (R/W) is set to logic 1. There are three basic read
operations; current address read, random read and
sequential read.
During read operations all bits of the memory address are
incremented after each transmission of a data byte.
Contrary to write operations an overflow of the memory
address occurs from 2047 to 0 (see Fig.3).
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from master
DATA
S
B
B
B
0
A
WORD ADDRESS
A
S
B
B
B
1
A
A
n bytes
SLAVE ADDRESS
R/W
SLAVE ADDRESS
R/W
auto increment
word address
at this moment master
transmitter becomes
master receiver and
EEPROM slave receiver
becomes slave transmitter
no acknowledge
from master
P
DATA
1
last byte
auto increment
word address
MBH928
Fig.7 Master reads PCx85116-3 slave after setting word address (write word address; read data).
acknowledge
from slave
acknowledge
from master
no acknowledge
from master
B
B
B
1
A
A
DATA
1
P
S
DATA
n bytes
last bytes
SLAVE ADDRESS
R/W
auto increment
word address
auto increment
word address
MBH929
Fig.8 Master reads PCx85116-3 immediately after first byte (read mode).
9
1997 Apr 02
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+6.5
UNIT
VDD
VI
V
V
input voltage on any pin
input current on any pin
output current
Zi > 500 Ω
V
−
−
SS − 0.8 +6.5
II
1
mA
mA
°C
IO
10
Tstg
Tamb
Vesd
storage temperature
−65
−40
2
+150
+85
−
operating ambient temperature
electrostatic discharge voltage
°C
note 1
kV
Note
1. ESD Human Body model Q22 at Tamb = 22 °C; discharge procedure according to MIL-STD-883C Method 3015.
10 CHARACTERISTICS
VDD = 2.7 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS
MIN.
MAX.
UNIT
Supplies
VDD
IDDR
supply voltage
2.7
5.5
V
supply current read
supply current E/W
standby supply current
fSCL = 400 kHz;
VDD = 5.5 V
−
1.0
mA
IDDW
fSCL = 400 kHz;
VDD = 5.5 V
−
1.0
mA
IDD(stb)
VDD = 2.7 V
VDD = 5.5 V
−
−
6
µA
µA
10
SDA input/output (pin 5)
VIL
LOW level input voltage
−0.8
+0.3VDD
6.5
V
VIH
HIGH level input voltage
LOW level output voltage
0.7VDD
V
VOL1
VOL2
ILO
IOL = 3 mA; VDD(min)
IOL = 6 mA; VDD(min)
VOH = VDD
−
−
−
0.4
V
0.6
V
output leakage current
1
µA
to(f)
output fall time from VIHmin to VILmax
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
pulse width of spikes suppressed by filter
input capacitance
note 1
20 + 0.1Cb 250
20 + 0.1Cb 250
ns
ns
ns
pF
tSP
CI
0
100
10
VI = VSS
−
1997 Apr 02
10
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
SCL input (pin 6)
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
−0.8
+0.3VDD
6.5
V
V
0.7VDD
input leakage current
VI = VDD or VSS
−
0
0
−
±1
µA
kHz
ns
fSCL
tSP
CI
clock input frequency
400
100
7
pulse width of spikes suppressed by filter
input capacitance
VI = VSS
pF
WP input (pin 7)
VIL
VIH
LOW level input voltage
HIGH level input voltage
−0.8
+0.1VDD
V
V
0.9VDD
VDD + 0.8
Data retention time
tS
data retention time
Tamb = 55 °C
20
−
years
Note
1. The bus capacitance ranges from 10 to 400 pF (Cb = total capacitance of one bus line in pF).
11 I2C-BUS CHARACTERISTICS
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and
VIH with an input voltage swing from VSS to VDD
.
STANDARD MODE
FAST MODE
MIN. MAX.
SYMBOL
PARAMETER
clock frequency
CONDITIONS
UNIT
MIN.
MAX.
fSCL
tBUF
0
100
0
400
kHz
time the bus must be free before
new transmission can start
4.7
−
1.3
−
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
−
0.6
−
µs
tLOW
LOW level clock period
HIGH level clock period
set-up time for START condition
data hold time
4.7
4.0
−
−
−
1.3
0.6
0.6
−
−
−
µs
µs
µs
tHIGH
tSU; STA
tHD; DAT
repeated start 4.7
for CBUS compatible masters
for I2C-bus devices
5
−
−
−
−
−
µs
ns
ns
ns
ns
µs
note 1
0
0
−
tSU; DAT
data set-up time
250
−
100
−
(2)
(2)
tr
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
1000 20 + 0.1Cb
300
300
−
tf
−
300
20 + 0.1Cb
0.6
tSU; STO
4.0
−
Notes
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
2. Cb = total capacitance of one bus line in pF.
1997 Apr 02
11
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
BM7A05
a n d b o o k , f u l l p a g e w
1997 Apr 02
12
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
12 WRITE CYCLE LIMITS
The Power-on-reset circuit resets the I2C-bus logic with a set-up time of ≤10 µs.Enabling the chip is achieved by
connecting the WP input to VSS
.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
E/W cycle timing
tE/W
E/W cycle time
−
−
10
ms
Endurance
NE/W
E/W cycle per byte
Tamb = −40 to +85 °C
Tamb = 22 °C
100000
−
−
−
−
cycles
cycles
1000000
1997 Apr 02
13
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
13 PACKAGE OUTLINES
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.0098 0.057
0.0039 0.049
0.019 0.0098 0.20
0.014 0.0075 0.19
0.16
0.15
0.24
0.23
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT96-1
076E03S
MS-012AA
1997 Apr 02
14
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
D
M
E
A
2
A
A
1
L
c
w M
Z
b
1
e
(e )
1
M
H
b
b
2
8
5
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
1.15
0.068 0.021 0.042 0.014
0.045 0.015 0.035 0.009
0.39
0.36
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.045
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT97-1
050G01
MO-001AN
1997 Apr 02
15
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
14 SOLDERING
14.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
14.3.2 WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
14.2 DIP
14.2.1 SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
14.2.2 REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
14.3.3 REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
14.3 SO
14.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1997 Apr 02
16
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
15 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 02
17
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
NOTES
1997 Apr 02
18
Philips Semiconductors
Product specification
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
PCF85116-3
NOTES
1997 Apr 02
19
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/02/pp20
Date of release: 1997 Apr 02
Document order number: 9397 750 01994
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The PCF85116-3 is an 16 kbits (2048 x 8-bit) floating gate Electrically Erasable Programmable Read Only Memory (EEPROM). By using
redundant EEPROM cells it is fault tolerant to single bit errors. In most cases multi bit errors are also covered. This feature dramatically
increases reliability compared to conventional EEPROM memories. Power consumption is low due to the full CMOS technology used. The
programming voltage is generated on-chip, using a voltage multiplier.
PC/PC-peripherals
Cross reference
Models
As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Only one PCF85116-3 device is
required to support all eight blocks of 256 x 8-bit each.
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
Timing of the E/W cycle is carried out internally, thus no external components are required. A write-protection input at pin 7 (WP) allows
disabling of write-commands from the master by a hardware signal. When pin 7 is HIGH the data bytes received will not be acknowledged
by the PCF85116-3 and the EEPROM contents are not changed.
Remark
Relevant Links
The PCF85116-3 is pin and address compatible to the PCx85xxC-2 family. The PCF85116-3 covers the whole address space of 16 kbits;
address inputs are no longer needed. Therefore, pins 1 to 3 are not connected. The write-protection input is at pin 7.
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Features
PCF85116-3
PCF85116-3
l Low power CMOS:
- maximum operating current 1.0 mA
- maximum standby current 10 µA (at 5.5 V), typical 4 µA
l Non-volatile storage of 16 kbits organized as eight blocks of 256 x 8-bit each
l Single supply with full operation down to 2.7 V
l On-chip voltage multiplier
l Serial input/output I2C-bus (100 kbits/s standard-mode and 400 kbits/s fast-mode)
l Write operations: multi byte write mode up to 32 bytes
l Write-protection input
l Read operations:
- sequential read
- random read
l Internal timer for writing (no external components)
l Power-on-reset
l High reliability by using redundant EEPROM cells
l Endurance: 1000000 Erase/Write (E/W) cycles at Tamb =22°C
l 20 years non-volatile data retention time (minimum)
l Pin and address compatible to the PCx85xxC-2 family (see also Section 2.1)
l 2 kV ESD protection (Human Body model).
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
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Title
Datasheet
Download
PCF85116-3 2048 x 8-bit CMOS EEPROM with I2C- 02-Apr-97
bus interface
Product
Specification
20
147
Blockdiagram
Blockdiagram of PCF85116-3P
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
PCF85116-
3P/01
9352 333 00112 Standard Marking * Tube
9352 333 10112 Standard Marking * Tube
SOT97 Full production
SOT96 Full production
SOT96 Full production
-
PCF85116-
3T/01
PCF85116-3D
Standard Marking * Reel Pack,
PCF85116-3D-T
9352 333 10118
SMD, 13"
Please read information about some discontinued variants of this product.
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PCF85116-3 links to the similar products page containing an overview of products that are similar in function or related to the part
number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and
products from the same functional category.
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Royal Philips Electronics
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