74HC166 [NXP]
8-bit parallel-in/serial-out shift register; 8位并行输入/串行输出移位寄存器
| 型号： | 74HC166 |
| 厂家： | 
NXP |
| 描述： | 8-bit parallel-in/serial-out shift register |
| 文件： | 总10页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT166
8-bit parallel-in/serial-out shift
register
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q0
from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0 → Q1 → Q2, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q7 output to the Ds input of the succeeding
stage.
FEATURES
• Synchronous parallel-to-serial applications
• Synchronous serial data input for easy expansion
• Clock enable for “do nothing” mode
• Asynchronous master reset
• For asynchronous parallel data load see “165”
• Output capability: standard
• ICC category: MSI
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CP to Q7
CL = 15 pF; VCC = 5 V
15
14
20
19
ns
ns
MR to Q7
fmax
CI
maximum clock frequency
input capacitance
63
3.5
41
50
3.5
41
MHz
pF
CPD
power dissipation capacitance per package notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
PIN DESCRIPTION
PIN NO.
SYMBOL
Ds
NAME AND FUNCTION
1
serial data input
2, 3, 4, 5, 10, 11, 12, 14
D0 to D7
CE
parallel data inputs
6
clock enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
7
CP
8
GND
MR
9
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
13
15
16
Q7
PE
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
CP
Qn REGISTER
Q0 Q1-Q6
OUTPUT
Q7
OPERATING MODES
PE
CE
DS
D0-D7
I - I
I
I
I
I
↑
↑
X
X
L
H
L - L
H - H
L
H
parallel load
serial shift
h - h
h
h
I
I
↑
↑
I
h
X - X
X - X
L
H
q0 - q5
q0 - q5
q6
q6
hold “do nothing”
X
h
X
X
X - X
q0
q1 - q6
q7
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990
4
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.5 Logic diagram.
Fig.6 Typical clear, shift, load, inhibit, and shift sequences.
5
December 1990
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q7
50
18
14
150
30
26
190
38
33
225
45
38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
4.5
6.0
Fig.7
Fig.8
Fig.7
Fig.7
Fig.8
Fig.8
Fig.9
Fig.8
Fig.8
Fig.9
Fig.7
tPHL
propagation delay
MR to Q7
47
17
14
160
32
27
200
40
34
240
48
41
2.0
4.5
6.0
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
tW
tW
trem
tsu
tsu
th
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0
4.5
6.0
master reset pulse width 100 25
LOW
125
25
21
150
30
26
2.0
4.5
6.0
20
17
9
7
removal time
MR to CP
0
0
0
−19
−7
−6
0
0
0
0
0
0
2.0
4.5
6.0
set-up time
Dn, CE to CP
80
16
14
14
5
4
100
20
17
120
24
20
2.0
4.5
6.0
set-up time
PE to CP
100 33
125
25
21
150
30
26
2.0
4.5
6.0
20
17
12
10
hold time
2
2
2
−8
−3
−2
2
2
2
2
2
2
2.0
4.5
6.0
Dn, CE to CP
th
hold time
PE to CP
0
0
0
−28
−10
−8
0
0
0
0
0
0
2.0
4.5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
19
57
68
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
D0 to D7
Ds
CP
CE
MR
0.35
0.35
0.80
0.80
0.40
0.60
PE
December 1990
7
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q7
23
22
7
40
40
15
50
50
19
60
60
22
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.7
Fig.8
Fig.7
Fig.7
Fig.8
Fig.8
Fig.9
Fig.8
tPHL
propagation delay
MR to Q7
t
THL/ tTLH output transition time
tW
tW
trem
tsu
tsu
clock pulse width
HIGH or LOW
20
9
25
31
0
30
38
0
master reset pulse width 25
LOW
11
−7
8
removal time
MR to CP
0
set-up time
Dn, CE to CP
16
30
20
38
24
45
set-up time
PE to CP
15
hold time
Dn, CE to CP
th
0
−3
0
0
ns
ns
4.5
4.5
Fig.9
Fig.9
Fig.7
hold time
PE to CP
th
0
−13
45
0
0
maximum clock pulse
width
fmax
25
20
17
MHz 4.5
December 1990
8
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
AC WAVEFORMS
The changing to output assumes internal Q6 opposite state from Q7.
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
(1) HC : VM = 50%; VI = GND to VCC
HCT: VM = 1.3V; VI = GND to 3V.
.
Fig.7 Waveforms showing the clock (CP) to output (Q7) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
(1) HC : VM = 50%; VI = GND to VCC
HCT: VM = 1.3V; VI = GND to 3V.
.
Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay
and the master reset to clock (CP) removal time.
December 1990
9
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
HCT: VM = 1.3V; VI = GND to 3V.
.
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds), the data inputs (Dn), the
clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
10
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NXP
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