74HC166D-Q100 [NEXPERIA]
8-bit parallel-in/serial out shift register;
| 型号： | 74HC166D-Q100 |
| 厂家： | 
Nexperia |
| 描述： | 8-bit parallel-in/serial out shift register |
| 文件： | 总19页 (文件大小：1161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC166-Q100; 74HCT166-Q100
8-bit parallel-in/serial out shift register
Rev. 1 — 25 September 2013
Product data sheet
1. General description
The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift
register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7)
and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to
D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input
(CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH
transition of CP. When the clock enable input (CE) is LOW data is shifted on the
LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include
clamp diodes which enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standard no. 7A
Input levels:
For 74HC166-Q100: CMOS level
For 74HCT166-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC166D-Q100
74HCT166D-Q100
74HC166PW-Q100
40 C to +125 C
SO16
plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
40 C to +125 C
TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
4. Functional diagram
15
1
SRG8
6
PE DS
D0
7
15
9
≥1
C1/2
2
3
M2
R
D1
D2
D3
D4
D5
D6
D7
4
5
1
2
2,1D
2,1D
2,1D
10
11
12
14
3
4
Q7
13
5
10
11
12
14
9
MR
CP CE
13
7
6
aaa-008816
aaa-008817
Fig 1. Logic symbol
Fig 2. IEC logic symbol
2
3
4
5
10 11 12 14
D0 D1 D2 D3 D4 D5 D6 D7
PE
15
DS
1
MR
9
CP
8-BIT PARALLEL/SERIAL-IN/
SERIAL-OUT SHIFT REGISTER
7
CE
6
Q7
13
aaa-008818
Fig 3. Functional diagram
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
2 of 19
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
D0
D1
D2
D3
D4
D5
D6
D7
PE
DS
S
S
S
S
S
S
S
S
CP
CE
FF
FF
FF
FF
FF
FF
FF
FF
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
1
2
3
4
5
6
7
8
RD
RD
RD
RD
RD
RD
RD
RD
MR
Q7
aaa-008819
Fig 4. Logic diagram
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢃꢃꢄ4ꢂꢅꢅ
ꢀꢁ+&7ꢂꢃꢃꢄ4ꢂꢅꢅ
ꢁ
ꢃ
ꢄ
ꢇ
ꢆ
ꢅ
ꢂ
ꢈ
ꢁꢅ
ꢁꢆ
ꢁꢇ
ꢁꢄ
ꢁꢃ
ꢁꢁ
ꢁꢀ
ꢉ
'6
'ꢀ
9
&&
3(
'ꢂ
4ꢂ
'ꢅ
'ꢆ
'ꢇ
05
'ꢁ
'ꢃ
'ꢄ
&(
&3
*1'
DDDꢀꢁꢁꢂꢃꢂꢄ
Fig 5. Pin configuration (SO16 and TSSOP16)
5.2 Pin description
Table 2.
Symbol
DS
Pin description
Pin
Description
1
serial data input
D0 to D7
CE
2, 3, 4, 5, 10, 11, 12, 14
parallel data inputs
6
clock enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
CP
7
GND
MR
8
9
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
Q7
13
15
16
PE
VCC
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
4 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
6. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
Qn registers
Output
PE
I
CE
CP
DS
X
X
l
D0 to D7
Q0
L
Q1 to Q6 Q7
parallel load
I
I
L to L
L
I
I
h
X
X
X
H
H to H
H
serial shift
h
I
L
q0 to q5
q0 to q5
q1 to q6
q6
q6
q7
h
I
h
H
hold “do nothing”
X
H
X
X
q0
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
CP
mode
control
inputs
CE
MR
DS
shift/
load
D0
D1
D2
D3
D4
D5
D6
H
L
H
L
parallel
inputs
H
L
H
H
D7
Q7
output
L
L
L
H
H
H
H
H
serial shift
serial shift
inhibit
clear
load
aaa-008820
Fig 6. Typical clear, shift, load, inhibit, and shift sequences
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
5 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
+150
Tamb = 40 C to +125 C
SO16 package
[2]
[3]
-
-
500
500
mW
mW
TSSOP16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] tot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
P
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
6 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC166-Q100
74HCT166-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
-
40
-
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
74HC166-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VI = VIH or VIL
1.5
1.2
-
1.5
-
-
-
1.5
-
-
-
V
V
V
V
V
V
3.15 2.4
-
3.15
3.15
4.2
3.2
0.8
2.1
2.8
-
4.2
4.2
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
-
-
-
0.5
1.35
1.8
1.35
1.8
VOH
HIGH-level
output voltage
IO = 20 A; VCC = 2.0 V 1.9
IO = 20 A; VCC = 4.5 V 4.4
IO = 20 A; VCC = 6.0 V 5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
4.4
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
0.1
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
7 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT166-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 4.5 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.16 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 4.5 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 4.5 V
-
-
8.0
-
80
-
160
A
additional
supply current VI = VCC 2.1 V;
other inputs at VCC or GND;
per input pin;
VCC = 4.5 V to 5.5 V
Dn and DS inputs
CP and CE inputs
MR input
-
-
-
-
-
35
80
40
60
3.5
126
288
144
216
-
-
-
-
-
-
157.5
360
180
270
-
-
-
-
-
-
171.5
392
196
294
-
A
A
A
A
pF
PE input
CI
input
capacitance
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
8 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC166-Q100
[1]
tpd
propagation
delay
CP to Q7; see Figure 7
VCC = 2.0 V
-
-
50
18
150
30
-
-
-
190
-
-
225
ns
ns
ns
ns
VCC = 4.5 V
38
45
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
-
15
-
-
-
-
-
-
-
-
14
26
-
33
-
38
MR to Q7; see Figure 8
VCC = 2.0 V
-
-
47
17
160
32
-
-
-
200
40
-
-
240
48
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
14
-
-
14
27
-
34
-
41
[2]
tt
transition
time
output; see Figure 7
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
MR input LOW; see Figure 8
VCC = 2.0 V
100 25
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
9
7
VCC = 6.0 V
21
26
trec
recovery time MR to CP; see Figure 8
VCC = 2.0 V
0
0
0
19
7
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
tsu
set-up time
Dn, CE to CP; see Figure 9
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
PE to CP; see Figure 9
VCC = 2.0 V
100 33
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
12
10
VCC = 6.0 V
21
26
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
9 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
th
hold time
Dn, CE to CP; see Figure 9
VCC = 2.0 V
2
2
2
8
3
2
-
-
-
2
2
2
-
-
-
2
2
2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
PE to CP; see Figure 9
VCC = 2.0 V
0
0
0
28
10
8
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
6
19
57
63
68
41
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
30
-
20
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
35
-
28
-
24
-
[3]
[1]
CPD
power
dissipation
capacitance
per package;
VI = GND to VCC
74HCT166-Q100
tpd
propagation
delay
CP to Q7; see Figure 7
VCC = 4.5 V
-
23
20
40
-
-
-
50
50
19
-
-
-
60
60
22
ns
ns
VCC = 5.0 V; CL = 15 pF
MR to Q7; see Figure 8
VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
-
-
22
19
40
ns
ns
VCC = 5.0 V; CL = 15 pF
output; see Figure 7
VCC = 4.5 V
-
-
[2]
tt
transition
time
7
15
ns
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 4.5 V
20
25
0
9
-
-
-
-
-
-
-
25
31
0
-
-
-
-
-
-
-
30
38
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
MR input LOW; see Figure 8
VCC = 4.5 V
11
7
8
trec
recovery time MR to CP; see Figure 8
VCC = 4.5 V
tsu
set-up time
Dn, CE to CP; see Figure 9
VCC = 4.5 V
16
30
0
20
38
0
24
45
0
PE to CP; see Figure 9
VCC = 4.5 V
15
3
13
th
hold time
Dn, CE to CP; see Figure 9
VCC = 4.5 V
PE to CP; see Figure 9
VCC = 4.5 V
0
0
0
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
10 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
fmax
maximum
frequency
CP input; see Figure 7
VCC = 4.5 V
25
-
45
50
41
-
-
-
20
-
-
-
17
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
-
-
-
-
[3]
CPD
power
per package;
-
dissipation
capacitance
VI = GND to VCC
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
90 %
90 %
Q7 output
V
M
10 %
10 %
TLH
V
OL
t
t
THL
aaa-008821
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum
frequency
74HC_HCT166_Q100
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
11 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
V
I
MR input
V
M
GND
t
W
t
rec
V
I
V
CP input
M
GND
t
PHL
V
OH
Q7 output
V
M
V
OL
aaa-008822
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 8. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
see note (1)
V
I
CE input
GND
V
M
t
su
t
t
t
su
su
t
t
t
t
t
h
h
h
V
I
PE input
GND
V
M
t
su
su
h
h
V
I
stable
Dn input
GND
V
M
t
su
t
h
V
I
stable
DS input
GND
V
M
t
su
t
t
W
h
V
I
CP input
GND
V
M
aaa-008823
condition: MR = HIGH
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up and hold times
74HC_HCT166_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
12 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
Table 8.
Type
Measurement points
Input
VI
Output
VM
VM
74HC166-Q100
74HCT166-Q100
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 10. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC166-Q100
74HCT166-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
74HC_HCT166_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
13 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 11. Package outline SOT109-1 (SO16)
74HC_HCT166_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
14 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 12. Package outline SOT403-1 (TSSOP16)
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
15 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT166_Q100 v.1 20130925
Product data sheet
-
-
74HC_HCT166_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
16 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
15.2 Definitions
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
15.3 Disclaimers
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT166_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
17 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74HC_HCT166_Q100
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 25 September 2013
18 of 19
74HC166-Q100; 74HCT166-Q100
Nexperia
8-bit parallel-in/serial out shift register
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 25 September 2013
相关型号：
74HC166NB
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16
NXP
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