74HC166DB,112 [NXP]
74HC(T)166 - 8-bit parallel-in/serial-out shift register SSOP1 16-Pin;型号: | 74HC166DB,112 |
厂家: | NXP |
描述: | 74HC(T)166 - 8-bit parallel-in/serial-out shift register SSOP1 16-Pin 光电二极管 逻辑集成电路 触发器 |
文件: | 总21页 (文件大小:639K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Rev. 3 — 11 September 2013
Product data sheet
1. General description
The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The
device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial
output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded
into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When
PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of
CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH
transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which
enable the use of current limiting resistors to interface inputs to voltages in excess of VCC
.
2. Features and benefits
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standard no. 7A
Input levels:
For 74HC166: CMOS level
For 74HCT166: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC166N
40 C to +125 C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
74HCT166N
74HC166D
40 C to +125 C
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT166D
74HC166DB
74HCT166DB
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads; body width SOT338-1
5.3 mm
74HC166PW 40 C to +125 C
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
4. Functional diagram
15
1
SRG8
6
PE DS
D0
7
15
9
≥1
C1/2
2
3
M2
R
D1
D2
D3
D4
D5
D6
D7
4
5
1
2
2,1D
2,1D
2,1D
10
11
12
14
3
4
Q7
13
5
10
11
12
14
9
MR
CP CE
13
7
6
aaa-008816
aaa-008817
Fig 1. Logic symbol
Fig 2. IEC logic symbol
2
3
4
5
10 11 12 14
D0 D1 D2 D3 D4 D5 D6 D7
PE
15
DS
1
MR
9
CP
8-BIT PARALLEL/SERIAL-IN/
SERIAL-OUT SHIFT REGISTER
7
CE
6
Q7
13
aaa-008818
Fig 3. Functional diagram
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
2 of 21
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D0
D1
D2
D3
D4
D5
D6
D7
PE
DS
S
S
S
S
S
S
S
S
CP
CE
FF
FF
FF
FF
FF
FF
FF
FF
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
1
2
3
4
5
6
7
8
RD
RD
RD
RD
RD
RD
RD
RD
MR
Q7
aaa-008819
Fig 4. Logic diagram
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
5. Pinning information
5.1 Pinning
74HC166
74HCT166
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DS
D0
V
CC
PE
D7
Q7
D6
D5
D4
MR
D1
D2
D3
CE
CP
GND
aaa-008815
Fig 5. Pin configuration (DIP16, SO16 and (T)SSOP16)
5.2 Pin description
Table 2.
Symbol
DS
Pin description
Pin
Description
1
serial data input
parallel data inputs
D0 to D7
CE
2, 3, 4, 5, 10, 11, 12, 14
6
clock enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
CP
7
GND
MR
8
9
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
Q7
13
15
16
PE
VCC
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
4 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
6. Functional description
Table 3.
Function table[1]
Operating modes
Inputs
Qn registers
Output
PE
I
CE
CP
DS
X
X
l
D0 to D7
Q0
L
Q1 to Q6 Q7
parallel load
I
I
L to L
L
I
I
h
X
X
X
H
H to H
H
serial shift
h
I
L
q0 to q5
q0 to q5
q1 to q6
q6
q6
q7
h
I
h
H
hold “do nothing”
X
H
X
X
q0
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
CP
mode
control
inputs
CE
MR
DS
shift/
load
D0
D1
D2
D3
D4
D5
D6
H
L
H
L
parallel
inputs
H
L
H
H
D7
Q7
output
L
L
L
H
H
H
H
H
serial shift
serial shift
inhibit
clear
load
aaa-008820
Fig 6. Typical clear, shift, load, inhibit, and shift sequences
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
5 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
+150
Tamb = 40 C to +125 C
DIP16 package
[2]
[3]
[4]
-
-
-
750
500
500
mW
mW
mW
SO16 package
(T)SSOP16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] tot derates linearly with 12 mW/K above 70 C.
P
[3] Ptot derates linearly with 8 mW/K above 70 C.
[4] Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
6 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC166
74HCT166
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
0
-
0
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
-
40
-
+125 C
-
-
-
-
1.67
-
-
-
-
-
1.67
-
-
ns/V
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC166
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
7 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT166
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 4.5 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.16 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 4.5 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 4.5 V
-
-
8.0
-
80
-
160
A
additional
supply current VI = VCC 2.1 V;
other inputs at VCC or GND;
per input pin;
VCC = 4.5 V to 5.5 V
Dn and DS inputs
CP and CE inputs
MR input
-
-
-
-
-
35
80
40
60
3.5
126
288
144
216
-
-
-
-
-
-
157.5
360
180
270
-
-
-
-
-
-
171.5 A
392
196
294
-
A
A
A
pF
PE input
CI
input
capacitance
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
8 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC166
[1]
tpd
propagation
delay
CP to Q7; see Figure 7
VCC = 2.0 V
-
-
-
-
50 150
-
-
-
-
190
38
-
-
-
-
-
225
45
-
ns
ns
ns
ns
VCC = 4.5 V
18
15
14
30
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
26
33
38
MR to Q7; see Figure 8
VCC = 2.0 V
-
-
-
-
47 160
-
-
-
-
200
40
-
-
-
-
-
240
48
-
ns
ns
ns
ns
VCC = 4.5 V
17
14
14
32
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
27
34
41
[2]
tt
transition
time
output; see Figure 7
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
MR input LOW; see Figure 8
VCC = 2.0 V
100 25
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
9
7
VCC = 6.0 V
21
26
trec
recovery time MR to CP; see Figure 8
VCC = 2.0 V
0
0
0
19
7
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
tsu
set-up time
Dn, CE to CP; see Figure 9
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
PE to CP; see Figure 9
VCC = 2.0 V
100 33
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
12
10
VCC = 6.0 V
21
26
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
9 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
th
hold time
Dn, CE to CP; see Figure 9
VCC = 2.0 V
2
2
2
8
3
2
-
-
-
2
2
2
-
-
-
2
2
2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
PE to CP; see Figure 9
VCC = 2.0 V
0
0
0
28
10
8
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
6
30
-
19
57
63
68
41
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
35
-
28
-
24
-
[3]
[1]
CPD
power
per package;
VI = GND to VCC
dissipation
capacitance
74HCT166
tpd
propagation
CP to Q7; see Figure 7
VCC = 4.5 V
delay
-
-
23
20
40
-
-
-
50
-
-
-
60
-
ns
ns
VCC = 5.0 V; CL = 15 pF
MR to Q7; see Figure 8
VCC = 4.5 V
-
-
22
19
40
-
-
-
50
-
-
-
60
-
ns
ns
VCC = 5.0 V; CL = 15 pF
output; see Figure 7
VCC = 4.5 V
[2]
tt
transition
time
-
7
15
-
19
-
22
ns
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 4.5 V
20
25
0
9
11
7
8
-
-
-
-
-
-
-
25
31
0
-
-
-
-
-
-
-
30
38
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
MR input LOW; see Figure 8
VCC = 4.5 V
trec
recovery time MR to CP; see Figure 8
VCC = 4.5 V
tsu
set-up time
Dn, CE to CP; see Figure 9
VCC = 4.5 V
16
30
0
20
38
0
24
45
0
PE to CP; see Figure 9
VCC = 4.5 V
15
3
13
th
hold time
Dn, CE to CP; see Figure 9
VCC = 4.5 V
PE to CP; see Figure 9
VCC = 4.5 V
0
0
0
74HC_HCT166
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
10 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
fmax
maximum
frequency
CP input; see Figure 7
VCC = 4.5 V
25
-
45
50
41
-
-
-
20
-
-
-
-
17
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
-
-
dissipation
capacitance
VI = GND to VCC
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
90 %
90 %
Q7 output
V
M
10 %
10 %
TLH
V
OL
t
t
THL
aaa-008821
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum
frequency
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
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74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
V
I
MR input
V
M
GND
t
W
t
rec
V
I
V
M
CP input
GND
t
PHL
V
OH
Q7 output
V
M
V
OL
aaa-008822
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 8. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
see note (1)
V
I
CE input
GND
V
M
t
su
t
t
t
su
su
t
t
t
t
t
h
h
h
V
I
PE input
GND
V
M
t
su
su
h
h
V
I
stable
Dn input
GND
V
M
t
su
t
h
V
I
stable
DS input
GND
V
M
t
su
t
t
W
h
V
I
CP input
GND
V
M
aaa-008823
condition: MR = HIGH
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up and hold times
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
12 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 8.
Type
Measurement points
Input
Output
VM
VI
VM
74HC166
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT166
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 10. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC166
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT166
open
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
13 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 11. Package outline SOT38-4 (DIP16)
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
14 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 12. Package outline SOT109-1 (SO16)
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
15 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 13. Package outline SOT338-1 (SSOP16)
74HC_HCT166
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
16 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
17 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74HC_HCT166_3
Modifications:
Release date
20130911
Data sheet status
Change notice
Supersedes
Product data sheet
-
74HC_HCT166_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Family data added, see Section 9 “Static characteristics”
74HC_HCT166_CNV_2
December 1990 Product specification
-
-
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
18 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT166
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Product data sheet
Rev. 3 — 11 September 2013
19 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT166
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 11 September 2013
20 of 21
74HC166; 74HCT166
NXP Semiconductors
8-bit parallel-in/serial out shift register
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2013
Document identifier: 74HC_HCT166
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