2N7002F [NXP]
TrenchMOS Logic Level FET; 的TrenchMOS逻辑电平FET
| 型号： | 2N7002F |
| 厂家： | 
NXP |
| 描述： | TrenchMOS Logic Level FET |
| 文件： | 总11页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2N7002F
TrenchMOS™ Logic Level FET
Rev. 01 — 11 February 2002
Product data
M3D088
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
2N7002F in SOT23.
2. Features
■ TrenchMOS™ technology
■ Very fast switching
■ Logic level compatible
■ Subminiature surface mount package.
3. Applications
■ Relay driver
■ High speed line driver
■ Logic level translator.
4. Pinning information
Table 1:
Pinning - SOT23, simplified outline and symbol
Pin
1
Description
gate (g)
Simplified outline
Symbol
3
d
2
source (s)
drain (d)
3
g
03ab44
03ab30
s
1
2
SOT23
1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
60
Unit
V
VDS
ID
drain-source voltage (DC)
Tj = 25 to 150 °C
Tsp = 25 °C; VGS = 10 V
Tsp = 25 °C
-
drain current (DC)
-
475
0.83
150
2
mA
W
Ptot
Tj
total power dissipation
junction temperature
-
-
°C
Ω
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 500 mA; Tj = 25
VGS = 4.5 V; ID = 75 mA; Tj = 25
1.7
2.25
4
Ω
6. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
60
Unit
V
VDS
VDGR
VGS
VGSM
ID
drain-source voltage (DC)
Tj = 25 to 150 °C
-
drain-gate voltage (DC)
gate-source voltage (DC)
peak gate-source voltage
drain current (DC)
Tj = 25 to 150 °C; RGS = 20 kΩ
-
60
V
-
±30
±40
475
300
1.9
V
tp ≤ 50 µs; pulsed; duty cycle = 25%
Tsp = 25 °C; VGS = 10 V; Figure 2 and 3
Tsp = 100 °C; VGS = 10 V; Figure 2
Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tsp = 25 °C; Figure 1
-
V
-
mA
mA
A
-
IDM
Ptot
Tstg
Tj
peak drain current
-
total power dissipation
storage temperature
-
0.83
+150
+150
W
−65
−65
°C
°C
operating junction temperature
Source-drain diode
IS
source (diode forward) current (DC) Tsp = 25 °C
-
-
475
1.9
mA
A
ISM
peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
2 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
03aa17
03aa25
120
120
der
I
P
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
(oC)
T
(oC)
T
sp
sp
V
GS ≥ 4.5 V
Ptot
Pder
=
× 100%
-----------------------
ID
P
°
tot(25 C)
Ider
=
× 100%
-------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
10
I
D
(A)
t
= 10 ms
p
R
= V
/ I
DS D
DSon
1
100 ms
1 ms
-1
10
10 ms
DC
100 ms
-2
10
2
10
1
10
V
(V)
DS
Tsp = 25 °C; IDM is single pulse; VGS = 10 V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
3 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-sp) thermal resistance from junction to solder point mounted on a metal clad board; Figure 4
-
-
-
-
150 K/W
350 K/W
Rth(j-a)
thermal resistance from junction to ambient
mounted on a printed circuit board;
minimum footprint
7.1 Transient thermal impedance
3
10
Z
th(j-sp)
K/W
2
10
δ = 0.5
0.2
0.1
10
1
0.05
0.02
t
p
P
δ =
T
single pulse
t
t
p
T
t
-1
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
10
(s)
p
Mounted on metal clad substrate.
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
4 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
8. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 10 µA; VGS = 0 V
Tj = 25 °C
60
55
75
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
1
2
-
-
V
V
V
Tj = 150 °C
0.6
-
-
Tj = −55 °C
-
3.5
IDSS
VDS = 48 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.01 1.0
µA
µA
Tj = 150 °C
-
10
IGSS
gate-source leakage current
VGS = ±15 V; VDS = 0 V
VGS = 10 V; ID = 500 mA; Figure 7 and 8
Tj = 25 °C
10
100 nA
RDSon
drain-source on-state resistance
-
-
1.7
-
2
Ω
Ω
Tj = 150 °C
3.7
VGS = 4.5 V; ID = 75 mA; Figure 7 and 8
Tj = 25 °C
-
2.25
4
Ω
Dynamic characteristics
gfs
forward transconductance
VDS = 10 V; ID = 200 mA
100 300
-
mS
pF
pF
pF
ns
Ciss
Coss
Crss
ton
input capacitance
output capacitance
reverse transfer capacitance
turn-on time
VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 11
-
-
-
-
-
25
18
7.5
3
40
30
10
10
15
VDD = 50 V; RD = 250 Ω; VGS = 10 V;
RG = 50 Ω; RGS = 50 Ω
toff
turn-off time
12
ns
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 300 mA; VGS = 0 V; Figure 12
-
-
-
0.85 1.5
V
reverse recovery time
recovered charge
IS = 300 mA; dIS/dt = −100 A/µs; VGS = 0 V;
VDS = 25 V
30
30
-
-
ns
nC
Qr
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
5 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
1
I
0.8
10 V 7 V 6 V
T = 25oC
D
j
I
V
> I X R
DSon
D
(A)
DS
D
(A)
5 V
0.8
0.6
0.4
0.2
0
0.6
T = 25oC
4.5 V
150oC
j
4 V
0.4
0.2
0
3.5 V
3 V
V
= 2.5 V
GS
0
0.8
1.6
2.4
0
2
4
6
V
(V)
GS
V
(V)
DS
Tj = 25 °C.
Tj = 25 °C and 150 °C; VDS > ID × RDSon.
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
4
2.4
a
4 V
T = 25oC
j
V
= 3.5 V
GS
R
DSon
(Ω)
4.5 V
5 V
3
2
1
0
1.8
6 V
7 V
1.2
0.6
0
10 V
0
0.2
0.4
0.6
0.8
1
-60
0
60
120
180
T (oC)
I
(A)
D
j
Tj = 25 °C.
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
6 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
-1
2.4
10
I
V
D
GS(th)
(A)
-2
(V)
typ
10
10
10
10
10
1.8
-3
-4
-5
-6
min
typ
1.2
0.6
0
min
-60
0
60
120
180
0
0.6
1.2
1.8
2.4
T (oC)
V
(V)
j
GS
ID = 1 mA; VDS = VGS
.
Tj = 25 °C; VDS = 5 V.
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
2
10
0.8
I
V
= 0 V
S
GS
(A)
0.6
C
(pF)
C
iss
10
0.4
0.2
0
C
oss
150 o
C
C
T = 25 o
C
rss
j
1
-1
10
2
1
10
10
0
0.4
0.8
1.2
V
(V)
V
(V)
SD
DS
VGS = 0 V; f = 1 MHz.
Tj = 25 °C and 150 °C; VGS = 0 V.
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
7 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
9. Package outline
Plastic surface mounted package; 3 leads
SOT23
D
B
E
A
X
H
v
M
A
E
3
Q
A
A
1
c
1
2
e
b
w M
B
1
L
p
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
b
p
c
D
E
e
e
H
L
Q
v
w
A
p
1
E
max.
1.1
0.9
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
mm
0.1
1.9
0.95
0.2
0.1
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
97-02-28
99-09-13
SOT23
TO-236AB
Fig 13. SOT23.
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
8 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
10. Revision history
Table 6:
Revision history
Rev Date
CPCN
-
Description
1
20020211
Product spec; initial version
9397 750 09096
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 11 February 2002
9 of 11
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
11. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
12. Definitions
13. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
10 of 11
9397 750 09096
Product data
Rev. 01 — 11 February 2002
2N7002F
TrenchMOS™ Logic Level FET
Philips Semiconductors
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 10
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
3
4
5
6
7
7.1
8
9
10
11
12
13
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 11 February 2002
Document order number: 9397 750 09096
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