LMX2485SQ [NSC]
50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL; 50兆赫 - 3.0 GHz的高性能Δ-Σ低功耗双半导体PLLatinum ？频率合成器具有800 MHz的整数PLL
| 型号： | LMX2485SQ |
| 厂家： | 
National Semiconductor |
| 描述： | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
| 文件： | 总37页 (文件大小：881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2006
LMX2485/LMX2485E
50 MHz - 3.0 GHz High Performance Delta-Sigma Low
™
Power Dual PLLatinum Frequency Synthesizers with
800 MHz Integer PLL
n Direct digital modulation applications
General Description
n Satellite and cable TV tuners
The LMX2485 is a low power, high performance delta-sigma
n WLAN Standards
fractional-N PLL with an auxiliary integer-N PLL. The device
is fabricated using National Semiconductor’s advanced pro-
cess.
Features
With delta-sigma architecture, fractional spurs at lower offset
frequencies are pushed to higher frequencies outside the
loop bandwidth. The ability to push close in spur and phase
noise energy to higher frequencies is a direct function of the
modulator order. Unlike analog compensation, the digital
feedback technique used in the LMX2485 is highly resistant
to changes in temperature and variations in wafer process-
ing. The LMX2485 delta-sigma modulator is programmable
up to fourth order, which allows the designer to select the
optimum modulator order to fit the phase noise, spur, and
lock time requirements of the system.
Quadruple Modulus Prescalers for Lower Divide Ratios
n RF PLL: 8/9/12/13 or 16/17/20/21
n IF PLL: 8/9 or 16/17
Advanced Delta Sigma Fractional Compensation
n 12 bit or 22 bit selectable fractional modulus
n Up to 4th order programmable delta-sigma modulator
Features for Improved Lock Times and Programming
n Fastlock / Cycle slip reduction
n Integrated time-out counter
n Single word write to change frequencies with Fastlock
Serial data for programming the LMX2485 is transferred via
a three line high speed (20 MHz) MICROWIRE interface.
The LMX2485 offers fine frequency resolution, low spurs,
fast programming speed, and a single word write to change
the frequency. This makes it ideal for direct digital modula-
tion applications, where the N counter is directly modulated
with information. The LMX2485 is available in a 24 lead
4.0 X 4.0 X 0.8 mm LLP package.
Wide Operating Range
n LMX2485 RF PLL: 500 MHz to 3.0 GHz
n LMX2485E RF PLL: 50 MHz to 3.0 GHz
Useful Features
n Digital lock detect output
n Hardware and software power-down control
n On-chip crystal reference frequency doubler.
n RF phase comparison frequency up to 50 MHz
n 2.5 to 3.6 volt operation with ICC = 5.0 mA at 3.0 V
Applications
n Cellular phones and base stations
CDMA, WCDMA, GSM/GPRS, TDMA, EDGE, PDC
Functional Block Diagram
20087701
™
PLLatinum is a trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS200877
www.national.com
Connection Diagram
Top View
24-Pin LLP (SQ)
20087722
Pin Descriptions
Pin #
Pin
Name
GND
I/O
Pin Description
0
1
2
3
4
5
-
O
-
Ground Substrate. This is on the bottom of the package and must be grounded.
RF PLL charge pump output.
CPoutRF
GND
RF PLL analog ground.
VddRF1
FinRF
FinRF*
-
RF PLL analog power supply.
I
RF PLL high frequency input pin.
I
RF PLL complementary high frequency input pin. Shunt to ground with a 100 pF
capacitor.
6
LE
I
MICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift
registers is loaded into the internal latches when LE goes HIGH
MICROWIRE Data. High impedance binary serial data input.
MICROWIRE Clock. High impedance CMOS Clock input. Data for the various counters is
clocked into the 24 bit shift register on the rising edge
Power supply for RF PLL digital circuitry.
7
8
DATA
CLK
I
I
9
VddRF2
CE
-
I
10
11
12
13
14
15
16
17
18
19
Chip Enable control pin. Must be pulled high for normal operation.
Power supply for RF PLL circuitry.
VddRF5
Ftest/LD
FinIF
I
O
I
Test frequency output / Lock Detect.
IF PLL high frequency input pin.
VddIF1
GND
-
IF PLL analog power supply.
-
IF PLL digital ground.
CPoutIF
VddIF2
OSCout
ENOSC
O
-
IF PLL charge pump output
IF PLL power supply.
O
I
Buffered output of the OSCin signal.
Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the
state of other pins or register bits.
20
21
22
23
24
OSCin
NC
I
I
Input for TCXO signal.
This pin must be left open.
VddRF3
FLoutRF
VddRF4
-
Power supply for RF PLL digital circuitry.
O
-
RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
RF PLL analog power supply.
www.national.com
2
Absolute Maximum Ratings (Notes 1, 2)
Value
Typ
Parameter
Symbol
Units
Min
-0.3
-0.3
-65
Max
4.25
Power Supply Voltage
VCC
Vi
V
V
Voltage on any pin with GND = 0V
Storage Temperature Range
VCC+0.3
+150
Ts
˚C
˚C
Lead Temperature (Solder 4 sec.)
TL
+260
Recommended Operating Conditions
Value
Typ
3.0
Parameter
Symbol
Units
Min
2.5
-40
Max
3.6
Power Supply Voltage (Note 1)
Operating Temperature
VCC
TA
V
25
+85
˚C
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions" indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3,
VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. V will be used to refer to the voltage at these pins and I will be used to refer to the sum of all currents
CC
CC
through all these power pins.
<
Note 2: This Device is a high performance RF integrated circuit with an ESD rating 2 kV and is ESD sensitive. Handling and assembly of this device should only
be done at ESD-free workstations.
Electrical Characteristics (VCC = 3.0V; -40˚C ≤ TA ≤ +85˚C unless otherwise specified)
Value
Symbol
Parameter
Conditions
Units
Min
Typ
3.3
1.7
Max
Icc PARAMETERS
IF PLL OFF
RF PLL ON
Power Supply Current,
RF Synthesizer
I
CCRF
mA
mA
Charge Pump TRI-STATE
IF PLL ON
Power Supply Current,
IF Synthesizer
ICCIF
RF PLL OFF
Charge Pump TRI-STATE
IF PLL ON
Power Supply Current,
Entire Synthesizer
ICCTOTAL
ICCPD
RF PLL ON
5.0
1
mA
µA
Charge Pump TRI-STATE
CE = ENOSC = 0V
CLK, DATA, LE = 0V
Power Down Current
10
RF SYNTHESIZER PARAMETERS
RF_P = 8
500
500
50
2000
3000
2000
3000
0
LMX2485
LMX2485E
Operating
Frequency
(Note 3)
RF_P = 16
fFinRF
MHz
RF_P = 8
RF_P = 16
50
500 - 3000 MHz
50 - 500 MHz (LMX2485E only)
-15
pFinRF
Input Sensitivity
dBm
MHz
µA
-5
Phase Detector
Frequency
(Note 4)
fCOMP
50
RF_CPG = 0
VCPoutRF = VCC/2
RF_CPG = 1
VCPoutRF = VCC/2
...
95
RF Charge Pump
Source Current
(Note 5)
190
...
µA
µA
µA
ICPoutRFSRCE
RF_CPG = 15
VCPoutRF = VCC/2
1520
3
www.national.com
Electrical Characteristics (VCC = 3.0V; -40˚C ≤ TA ≤ +85˚C unless otherwise specified) (Continued)
Value
Symbol
Parameter
Conditions
Units
Min
Typ
Max
RF SYNTHESIZER PARAMETERS
RF_CPG = 0
-95
µA
VCPoutRF = VCC/2
RF_CPG = 1
VCPoutRF = VCC/2
...
RF Charge Pump Sink
-190
...
µA
µA
µA
I
CPoutRFSINK
Current
(Note 5)
RF_CPG = 15
VCPoutRF = VCC/2
-1520
RF Charge Pump
TRI-STATE Current
Magnitude
ICPoutRFTRI
0.5 ≤ VCPoutRF ≤ VCC -0.5
2
10
nA
Magnitude of RF CP
>
RF_CPG
2
3
3
10
13
%
%
VCPoutRF = VCC/2
TA = 25˚C
| ICPoutRF%MIS | Sink vs. CP Source
Mismatch
RF_CPG ≤ 2
Magnitude of RF CP
| ICPoutRF%V |
0.5 ≤ VCPoutRF ≤ VCC -0.5
Current vs. CP Voltage TA = 25˚C
2
4
8
%
%
Magnitude of RF CP
| ICPoutRF%T |
VCPoutRF = VCC/2
Current vs. Temperature
IF SYNTHESIZER PARAMETERS
fFinIF
Operating Frequency
IF Input Sensitivity
Phase Detector
Frequency
75
800
5
MHz
dBm
pFinIF
-10
fCOMP
10
MHz
mA
IF Charge Pump Source
Current
ICPoutIFSRCE
ICPoutIFSINK
VCPoutIF = VCC/2
VCPoutIF = VCC/2
3.5
IF Charge Pump Sink
Current
-3.5
mA
IF Charge Pump
TRI-STATE Current
Magnitude
ICPoutIFTRI
0.5 ≤ VCPoutIF ≤ VCC RF -0.5
2
10
nA
Magnitude of IF CP Sink VCPoutIF = VCC/2
vs. CP Source Mismatch TA = 25˚C
| ICPoutIF%MIS |
| ICPoutIF%V |
1
4
4
8
%
%
%
Magnitude of IF CP
0.5 ≤ VCPoutIF ≤ VCC -0.5
10
Current vs. CP Voltage TA = 25˚C
Magnitude of IF CP
| ICPoutIF%TEMP
VCPoutIF = VCC/2
Current vs. Temperature
OSCILLATOR PARAMETERS
Oscillator Operating
OSC2X = 0
OSC2X = 1
5
5
110
20
MHz
MHz
fOSCin
Frequency
Oscillator Input
Sensitivity
vOSCin
0.5
VCC
100
VP-P
µA
IOSCin
Oscillator Input Current
-100
SPURS
Spurs in band
(Note 6)
-55
dBc
www.national.com
4
Electrical Characteristics (VCC = 3.0V; -40˚C ≤ TA ≤ +85˚C unless otherwise specified) (Continued)
Value
Symbol
Parameter
Conditions
Units
Min
Typ
Max
PHASE NOISE
RF_CPG = 0
RF_CPG = 1
-202
-202
-206
-208
-210
RF Synthesizer
L
F1HzRF
Normalized Phase Noise RF_CPG = 3
dBc/Hz
dBc/Hz
Contribution (Note 7)
RF_CPG = 7
RF_CPG = 15
IF Synthesizer
LF1HzIF
Normalized Phase Noise
Contribution
-209
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH
VIL
IIH
High-Level Input Voltage
1.6
VCC
0.4
1.0
1.0
V
V
Low-Level Input Voltage
High-Level Input Current VIH = VCC
Low-Level Input Current VIL = 0 V
High-Level Output
-1.0
-1.0
µA
µA
IIL
VOH
VOL
IOH = -500 µA
VCC-0.4
V
V
Voltage
Low-Level Output
Voltage
IOL = 500 µA
0.4
MICROWIRE INTERFACE TIMING
Data to Clock Set Up
tCS
See MICROWIRE Input Timing
25
ns
Time
tCH
Data to Clock Hold Time See MICROWIRE Input Timing
Clock Pulse Width High See MICROWIRE Input Timing
Clock Pulse Width Low See MICROWIRE Input Timing
8
ns
ns
ns
tCWH
tCWL
25
25
Clock to Load Enable
See MICROWIRE Input Timing
Set Up Time
tES
25
25
ns
ns
Load Enable Pulse
See MICROWIRE Input Timing
Width
tEW
Note 3: A slew rate of at least 100 V/uS is recommended for frequencies below 500 MHz for optimal performance.
Note 4: For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Note 5: Refer to table in Section 2.4.2 RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
Note 6: In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset
frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the
impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency =
20 MHz, RF_CPG = 7, DITH = 0, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
Note 7: Normalized Phase Noise Contribution is defined as: L (f) = L(f) – 20log(N) – 10log(f
) where L(f) is defined as the single side band phase noise
COMP
N
measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for
RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0.
MICROWIRE INPUT TIMING DIAGRAM
20087775
5
www.national.com
Typical Performance Characteristics : Sensitivity (Note 8)
RF PLL Fin Sensitivity
TA = 25˚C, RF_P = 16
20087745
RF PLL Fin Sensitivity
VCC = 3.0 V, RF_P = 16
20087746
www.national.com
6
Typical Performance Characteristics : Sensitivity (Note 8) (Continued)
IF PLL Fin Sensitivity
TA = 25˚C, IF_P = 16
20087747
IF PLL Fin Sensitivity
VCC = 3.0 V, IF_P = 16
20087748
7
www.national.com
Typical Performance Characteristics : Sensitivity (Note 8) (Continued)
OSCin Sensitivity
TA = 25˚C, OSC_2X = 0
20087749
OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 0
20087756
www.national.com
8
Typical Performance Characteristics : Sensitivity (Note 8) (Continued)
OSCin Sensitivity
TA = 25˚C, OSC_2X = 1
20087773
OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 1
20087774
9
www.national.com
Typical Performance Characteristic : FinRF Input Impedance (Note 8)
20087768
FinRF Input Impedance
Frequency (MHz)
50
Real (Ohms)
670
531
452
408
373
337
302
270
241
215
192
172
154
139
127
114
104
96
Imaginary (Ohms)
-276
-247
-209
-212
-222
-231
-237
-239
-236
-231
-221
-218
-209
-200
-192
-184
-175
-168
-160
-153
-147
-134
-123
-113
-103
-94
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
88
80
74
64
56
50
45
39
37
-86
33
-78
30
-72
28
-69
26
-66
www.national.com
10
Typical Performance Characteristic : FinIF Input Impedance (Note 8)
20087754
FinIF Input Impedance
Frequency (MHz)
Real (Ohms)
583
Imaginary (Ohms)
50
75
-286
-256
-241
-209
-209
-219
-224
-228
-228
-223
-218
-208
530
100
200
300
400
500
600
700
800
900
1000
499
426
384
347
310
276
244
216
192
173
11
www.national.com
Typical Performance Characteristic : OSCin Input Impedance (Note 8)
20087755
Frequency (MHz)
Powered Up
Imaginary
-3779
-2236
-1196
-863
Powered Down
Imaginary
-8137
-4487
-2215
-1495
-1144
-912
Real
1730
846
466
351
316
278
261
252
239
234
230
225
219
214
208
207
Magnitude
4157
2391
1284
932
Real
392
155
107
166
182
155
153
154
147
145
140
138
133
133
132
133
Magnitude
5
8146
4490
2217
-1504
1158
925
10
20
30
40
-672
742
50
-566
631
60
-481
547
-758
774
70
-425
494
-652
669
80
-388
456
-576
595
90
-358
428
-518
538
100
110
120
130
140
150
-337
407
-471
492
-321
392
-436
458
-309
379
-402
123
-295
364
-374
397
-285
353
-349
373
-279
348
-329
355
www.national.com
12
Typical Performance Characteristics : Currents (Note 8)
Power Supply Current
CE = High
20087759
Power Supply Current
CE = LOW
20087761
13
www.national.com
Typical Performance Characteristics : Currents (Note 8) (Continued)
RF PLL Charge Pump Current
VCC = 3.0 Volts
20087767
IF PLL Charge Pump Current
VCC = 3.0 Volts
20087765
www.national.com
14
Typical Performance Characteristics : Currents (Note 8) (Continued)
Charge Pump Leakage
RF PLL
VCC = 3.0 Volts
20087764
Charge Pump Leakage
IF PLL
VCC = 3.0 Volts
20087763
Note 8: Typical performance characteristics do not imply any sort of guarantee. Guaranteed specifications are in the electrical characteristics section.
15
www.national.com
Bench Test Setups
20087769
Charge Pump Current Measurement Procedure
The above block diagram shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current
level, mismatch, and leakage measurement. In order to measure the charge pump currents, a signal is applied to the high
frequency input pins. The reason for this is to guarantee that the phase detector gets enough transitions in order to be able to
change states. If no signal is applied, it is possible that the charge pump current reading will be low due to the fact that the duty
cycle is not 100%. The OSCin Pin is tied to the supply. The charge pump currents can be measured by simply programming the
phase detector to the necessary polarity. For instance, in order to measure the RF charge pump, a 10 MHz signal is applied to
the FinRF pin. The source current can be measured by setting the RF PLL phase detector to a positive polarity, and the sink
current can be measured by setting the phase detector to a negative polarity. The IF PLL currents can be measured in a similar
way. Note that the magnitude of the RF PLL charge pump current is controlled by the RF_CPG bit. Once the charge pump
currents are known, the mismatch can be calculated as well. In order to measure leakage, the charge pump is set to a TRI-STATE
mode by enabling the RF_CPT and IF_CPT bits. The table below shows a summary of the various charge pump tests.
Current Test
RF Source
RF Sink
RF_CPG
RF_CPP
RF_CPT
IF_CPP
IF_CPT
0 to 15
0
1
0
0
X
X
X
0
X
X
X
0
0
1
0 to 15
RF TRI-STATE
IF Source
X
X
X
X
X
X
X
X
1
X
X
X
IF Sink
1
IF TRI-STATE
X
www.national.com
16
Bench Test Setups (Continued)
Charge Pump Current Specification Definitions
20087750
I1 = Charge Pump Sink Current at VCPout = Vcc - ∆V
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ∆V
I4 = Charge Pump Source Current at VCPout = Vcc - ∆V
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ∆V
∆V = Voltage offset from the positive and negative supply rails. Defined to be 0.5 volts for this part.
vCPout refers to either VCPoutRF or VCPoutIF
ICPout refers to either ICPoutRF or ICPoutIF
Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
20087751
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
20087752
Charge Pump Output Current Magnitude Variation vs. Temperature
20087753
17
www.national.com
Bench Test Setups (Continued)
20087770
Frequency Input Pin
DC Blocking Capacitor
1000 pF
Corresponding Counter
RF_R / 2
Default Counter Value
MUX Value
OSCin
FinRF
FinIF
50
14
15
13
12
100 pF// 1000 pF
100 pF
RF_N / 2
502 + 2097150 / 4194301
IF_N / 2
534
50
OSCin
1000 pF
IF_R / 2
Sensitivity Measurement Procedure
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz or more of its
expected value. It is typically measured over frequency, voltage, and temperature. In order to test sensitivity, the MUX[3:0] word
is programmed to the appropriate value. The counter value is then programmed to a fixed value and a frequency counter is set
to monitor the frequency of this pin. The expected frequency at the Ftest/LD pin should be the signal generator frequency divided
by twice the corresponding counter value. The factor of two comes in because the LMX2485 has a flip-flop which divides this
frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter
input impedance should be set to high impedance. In order to perform the measurement, the temperature, frequency, and voltage
is set to a fixed value and the power level of the signal is varied. Note that the power level at the part is assumed to be 4 dB less
than the signal generator power level. This accounts for 1 dB for cable losses and 3 dB for the pad. The power level range where
the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for the sensitivity limits. The temperature,
frequency, and voltage can be varied in order to produce a family of sensitivity curves. Since this is an open-loop test, the charge
pump is set to TRI-STATE and the unused side of the PLL (RF or IF) is powered down when not being tested. For this part, there
are actually four frequency input pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin
are shown in above table.
Note that for the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a fraction of 2097150 / 4194301
is used. The reason for this long fraction is to test the RF N counter and supporting fractional circuitry as completely as possible.
www.national.com
18
Bench Test Setups (Continued)
20087771
Input Impedance Measurement Procedure
The above block diagram shows the test setup used for measuring the input impedance for the LMX2485. The DC blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a zero Ohm resistor. This
procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the network analyzer, ensure that
the part is powered up, and then measure the input impedance. The network analyzer can be calibrated by using either calibration
standards or by soldering resistors directly to the evaluation board. An open can be implemented by putting no resistor, a short
can be implemented by soldering a zero ohm resistor as close as possible to the pin being measured, and a short can be
implemented by soldering two 100 ohm resistors in parallel as close as possible to the pin being measured. Calibration is done
with the PLL removed from the PCB. This requires the use of a clamp down fixture that may not always be generally available.
If no clamp down fixture is available, then this procedure can be done by calibrating up to the point where the DC blocking
capacitor usually is, and then implementing port extensions with the network analyzer. Zero ohm resistor is added back for the
actual measurement. Once the setup is calibrated, it is necessary to ensure that the PLL is powered up. This can be done by
toggling the power down bits (RF_PD and IF_PD) and observing that the current consumption indeed increases when the bit is
disabled. Sometimes it may be necessary to apply a signal to the OSCin pin in order to program the part. If this is necessary,
disconnect the signal once it is established that the part is powered up. It is useful to know the input impedance of the PLL for
the purposes of debugging RF problems and designing matching networks. Another use of knowing this parameter is make the
trace width on the PCB such that the input impedance of this trace matches the real part of the input impedance of the PLL
frequency of operation. In general, it is good practice to keep trace lengths short and make designs that are relatively resistant
to variations in the input impedance of the PLL.
19
www.national.com
be rather involved, but there are many simulation tools and
references available, such as the one given at the end of the
functional description block.
Functional Description (Note 9)
1.0 GENERAL
The LMX2485 consists of integrated N counters, R counters,
and charge pumps. The TCXO, VCO and loop filter are
supplied external to the chip. The various blocks are de-
scribed below.
1.5 N COUNTERS AND HIGH FREQUENCY INPUT PINS
The N counter divides the VCO frequency down to the
comparison frequency. Because prescalers are used, there
are limitations on how small the N value can be. The N
counters are discussed in greater depth in the programming
section. Since the input pins to these counters ( FinRF and
FinIF ) are high frequency, layout considerations are impor-
tant.
1.1 TCXO, OSCILLATOR BUFFER, AND R COUNTER
The oscillator buffer must be driven single-ended by a signal
source, such as a TCXO. The OSCout pin is included to
provide a buffered output of this input signal and is active
when the OSC_OUT bit is set to one. The ENOSC pin can
be also pulled high to ensure that the OSCout pin is active,
regardless of the status of the registers in the LMX2485.
High Frequency Input Pins, FinRF and FinIF
It is generally recommended that the VCO output go through
a resistive pad and then through a DC blocking capacitor
before it gets to these high frequency input pins. If the trace
The R counter divides this TXCO frequency down to the
comparison frequency.
<
length is sufficiently short ( 1/10th of a wavelength ), then
the pad may not be necessary, but a series resistor of about
39 ohms is still recommended to isolate the PLL from the
VCO. The DC blocking capacitor should be chosen at least
to be 27 pF, depending on frequency. It may turn out that the
frequency is above the self-resonant frequency of the ca-
pacitor, but since the input impedance of the PLL tends to be
capacitive, it actually is a benefit to exceed the tune fre-
quency. The pad and the DC blocking capacitor should be
placed as close to the PLL as possible
1.2 PHASE DETECTOR
The maximum phase detector operating frequency for the IF
PLL is straightforward, but it is a little more involved for the
RF PLL since it is fractional. The maximum phase detector
frequency for the LMX2485 RF PLL is 50 MHz. However, this
is not possible in all circumstances due to illegal divide ratios
of the N counter. The crystal reference frequency also limits
the phase detector frequency, although the doubler helps
with this limitation. There are trade-offs in choosing the
phase detector frequency. If this frequency is run higher,
then phase noise will be lower, but lock time may be in-
creased due to cycle slipping and the capacitors in the loop
filter may become rather large.
Complementary High Frequency Pin, FinRF*
These inputs may be used to drive the PLL differentially, but
it is very common to drive the PLL in a single ended fashion.
A shunt capacitor should be placed at the FinRF* pin. The
value of this capacitor should be chosen such that the im-
pedance, including the ESR of the capacitor, is as close to
an AC short as possible at the operating frequency of the
PLL. 100 pF is a typical value, depending on frequency.
1.3 CHARGE PUMP
For the majority of the time, the charge pump output is high
impedance, and the only current through this pin is the
Tri-State leakage. However, it does put out fast correction
pulses that have a width that is proportional to the phase
error presented at the phase detector.
1.6 POWER PINS, POWER DOWN, AND POWER UP
MODES
It is recommended that all of the power pins be filtered with
a series 18 ohm resistor and then placing two capacitors
shunt to ground, thus creating a low pass filter. Although it
makes sense to use large capacitor values in theory, the
ESR ( Equivalent Series Resistance ) is greater for larger
capacitors. For optimal filtering minimize the sum of the ESR
and theoretical impedance of the capacitor. It is therefore
recommended to provide two capacitors of very different
sizes for the best filtering. 1 µF and 100 pF are typical
values. The small capacitor should be placed as close as
possible to the pin.
The charge pump converts the phase error presented at the
phase detector into a correction current. The magnitude of
this current is theoretically constant, but the duty cycle is
proportional to the phase error. For the IF PLL, this current is
not programmable, but for the RF PLL it is programmable in
16 steps. Also, the RF PLL allows for a higher charge pump
current to be used when the PLL is locking in order to reduce
the lock time.
1.4 LOOP FILTER
The power down state of the LMX2485 is controlled by many
factors. The one factor that overrides all other factors is the
CE pin. If this pin is low, the part will be powered down.
Asserting a high logic level on this pin is necessary to power
up the chip, however, there are other bits in the programming
registers that can override this and put the PLL back in a
power down state. Provided that the voltage on the CE pin is
high, programming the RF_PD and IF_PD bits to zero guar-
antees that the part will be powered up. Programming either
one of these bits to one will power down the appropriate
section of the synthesizer, provided that the ATPU bit does
not override this.
The loop filter design can be rather involved. In addition to
the regular constraints and design parameters, delta-sigma
PLLs have the additional constraint that the order of the loop
filter should be one greater than the order of the delta sigma
modulator. This rule of thumb comes from the requirement
that the loop filter must roll off the delta sigma noise at 20
dB/decade faster than it rises. However, since the noise can
not have infinite power, it must eventually roll off. If the loop
bandwidth is narrow, this requirement may not be necessary.
For the purposes of discussion in this datasheet, the pole of
the loop filter at 0 Hz is not counted. So a second order filter
has 3 components, a 3rd order loop filter has 5 components,
and the 4th order loop filter has 7 components. Although a
5th order loop filter is theoretically necessary for use with a
4th order modulator, typically a 4th order filter is used in this
case. The loop filter design, especially for higher orders can
www.national.com
20
Functional Description (Note 9)
(Continued)
ATPU
Bit Enabled +
Write to RF
CE Pin RF_PD
N Counter
PLL State
Powered Down
(Asynchronous)
Powered Up
Low
X
X
High
High
High
X
0
1
Yes
No
No
Powered Up
Powered Down
( Asynchronous )
1.7 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of e. To indicate a locked state
(Lock = HIGH) the phase error must be less than the e RC
delay for 5 consecutive reference cycles. Once in lock (Lock
= HIGH), the RC delay is changed to approximately δ. To
indicate an out of lock state (Lock = LOW), the phase error
must become greater δ. The values of e and δ are dependent
on which PLL is used and are shown in the table below:
PLL
RF
IF
e
δ
10 ns
15 ns
20 ns
30 ns
When the PLL is in the power down mode and the Ftest/LD
pin is programmed for the lock detect function, it is forced
LOW. The accuracy of this circuit degrades at higher com-
parison frequencies. To compensate for this, the DIV4 word
should be set to one if the comparison frequency exceeds 20
MHz. The function of this word is to divide the comparison
frequency presented to the lock detect circuit by 4. Note that
if the MUX[3:0] word is set such as to view lock detect for
both PLLs, an unlocked (LOW) condition is shown whenever
either one of the PLLs is determined to be out of lock.
20087704
21
www.national.com
nally intended only for second order filters, so when imple-
menting it with higher order filters, the third and fourth poles
can not be too close in, or it will not be possible to keep the
loop filter well optimized when the higher charge pump cur-
rent and Fastlock resistor are engaged.
Functional Description (Note 9)
(Continued)
1.8 CYCLE SLIP REDUCTION AND FASTLOCK
The LMX2485 offers both cycle slip reduction (CSR) and
Fastlock with timeout counter support. This means that it
requires no additional programming overhead to use them. It
is generally recommended that the charge pump current in
the steady state be 8X or less in order to use cycle slip
reduction, and 4X or less in steady state in order to use
Fastlock. The next step is to decide between using Fastlock
or CSR. This determination can be made based on the ratio
of the comparison frequency ( fCOMP ) to loop bandwidth
( BW ).
1.8.1 Using Cycle Slip Reduction (CSR) to Avoid Cycle
Slipping
Once it is decided that CSR is to be used, the cycle slip
reduction factor needs to be chosen. The available factors
are 1/2, 1/4, and 1/16. In order to preserve the same loop
characteristics, it is recommended that the following con-
straint be satisfied: (Fastlock Charge Pump Current) /
(Steady State Charge Pump Current) = CSR
In order to satisfy this constraint, the maximum charge pump
current in steady state is 8X for a CSR of 1/2, 4X for a CSR
of 1/4, and 1X for a CSR of 1/16. Because the PLL phase
noise is better for higher charge pump currents, it makes
sense to choose CSR only as large as necessary to prevent
cycle slipping. Choosing it larger than this will not improve
lock time, and will result in worse phase noise.
Comparison
Frequency
Cycle Slip
Reduction
( CSR )
Fastlock
( fCOMP
)
Noticeable better
than CSR
fCOMP ≤ 1.25 MHz
Likely to provide
a benefit,
<
1.25 MHz
Marginally better
Consider an example where the desired loop bandwidth in
steady state is 100 kHz and the comparison frequency is 20
MHz. This yields a ratio of 200. Cycle slipping may be
present, but would not be too severe if it was there. If a CSR
factor of 1/2 is used, this would reduce the ratio to 100 during
frequency acquisition, which is probably sufficient. A charge
pump current of 8X could be used in steady state, and a
factor of 16X could be used during frequency acquisition.
This yields a ratio of 1/2, which is equal to the CSR factor
and this satisfies the above constraint. In this circumstance,
it could also be decided to just use 16X charge pump current
all the time, since it would probably have better phase noise,
and the degradation in lock time would not be too severe.
provided that
fCOMP ≤ 2 MHz than CSR
>
fCOMP 100 X
>
fCOMP 2 MHz Same or worse
BW
than CSR
Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison fre-
quency during frequency acquisition while keeping the same
loop bandwidth, thereby reducing the ratio of the comparison
frequency to the loop bandwidth. In cases where the ratio of
the comparison frequency exceeds about 100 times the loop
bandwidth, cycle slipping can occur and significantly de-
grade lock times. The greater this ratio, the greater the
benefit of CSR. This is typically the case of high comparison
frequencies. In circumstances where there is not a problem
with cycle slipping, CSR provides no benefit. There is a glitch
when CSR is disengaged, but since CSR should be disen-
gaged long before the PLL is actually in lock, this glitch is not
an issue. A good rule of thumb for CSR disengagement is to
do this at the peak time of the transient response. Because
this time is typically much sooner than Fastlock should be
disengaged, it does not make sense to use CSR and Fast-
lock in combination.
1.8.2 Using Fastlock to Improve Lock Times
20087740
Fastlock
Once it is decided that Fastlock is to be used, the loop
bandwidth multiplier, K, is needed in order to determine the
theoretical impact of Fastlock on the loop bandwidth and the
resistor value, R2p, that is switched in parallel during Fast-
lock. This ratio is calculated as follows: K = ( Fastlock
Charge Pump Current ) / ( Steady State Charge Pump
Current )
Fastlock works by increasing the loop bandwidth only during
frequency acquisition. In circumstances where the compari-
son frequency is less than or equal to 2 MHz, Fastlock may
provide a benefit beyond what CSR can offer. Since Fastlock
also reduces the ratio of the comparison frequency to the
loop bandwidth, it may provide a significant benefit in cases
where the comparison frequency is above 2 MHz. However,
CSR can usually provide an equal or larger benefit in these
cases, and can be implemented without using an additional
resistor. The reason for this restriction on frequency is that
Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the
order of the fast lock time, this glitch grows and limits the
benefits of Fastlock. This effect becomes worse at higher
comparison frequencies. There is always the option of re-
ducing the comparison frequency at the expense of phase
noise in order to satisfy this constraint on comparison fre-
quency. Despite this glitch, there is still a net improvement in
lock time using Fastlock in these circumstances. When using
Fastlock, it is also recommended that the steady state
charge pump state be 4X or less. Also, Fastlock was origi-
K
1
Loop Bandwidth
1.00 X
R2p Value
Open
Lock Time
100 %
71 %
58%
2
1.41 X
R2/0.41
R2/0.73
R2
3
1.73 X
4
2.00 X
50%
8
2.83 X
R2/1.83
R2/2
35%
9
3.00 X
33%
16
4.00 X
R2/3
25%
The above table shows how to calculate the Fastlock resistor
and theoretical lock time improvement, once the ratio , K, is
www.national.com
22
usually one-half or one-fourth. There are trade-offs between
fractional spurs, sub-fractional spurs, and phase noise. The
rules of thumb presented in this section are just that. There
will be exceptions. The bits that impact the fractional spurs
are FM and DITH, and these bits should be set in this order.
Functional Description (Note 9)
(Continued)
known. This all assumes a second order filter (not counting
the pole at 0 Hz). However, it is generally recommended that
the loop filter order be one greater than the order of the delta
sigma modulator, which means that a second order filter is
never recommended. In this case, the value for R2p is
typically about 80% of what it would be for a second order
filter. Because the Fastlock disengagement glitch gets larger
and it is harder to keep the loop filter optimized as the K
value becomes larger, designing for the largest possible
value for K usually, but not always yields the best improve-
ment in lock time. To get a more accurate estimate requires
more simulation tools, or trial and error.
The first step to do is choose FM, for the delta sigma
modulator order. It is recommended to start with FM = 3 for
a third order modulator and use strong dithering. In general,
there is a trade-off between primary and sub-fractional
spurs. Choosing the highest order modulator (FM = 0 for 4th
order) typically provides the best primary fractional spurs,
but the worst sub-fractional spurs. Choosing the lowest
modulator order (FM = 2 for 2nd order), typically gives the
worst primary fractional spurs, but the best sub-fractional
spurs. Choosing FM = 3, for a 3rd order modulator is a
compromise.
1.8.3 Capacitor Dielectric Considerations for Lock
Time
The second step is to choose DITH, for dithering. Dithering
has a very small impact on primary fractional spurs, but a
much larger impact on sub-fractional spurs. The only prob-
lem is that it can add a few dB of phase noise, or even more
if the loop bandwidth is very wide. Disabling dithering (DITH
= 0), provides the best phase noise, but the sub-fractional
spurs are worst (except when the fractional numerator is 0,
and in this case, they are the best). Choosing strong dither-
ing (DITH = 2) significantly reduces sub-fractional spurs, if
not eliminating them completely, but adds the most phase
noise. Weak dithering (DITH = 1) is a compromise.
The LMX2485 has a high fractional modulus and high
charge pump gain for the lowest possible phase noise. One
consideration is that the reduced N value and higher charge
pump may cause the capacitors in the loop filter to become
larger in value. For larger capacitor values, it is common to
have a trade-off between capacitor dielectric quality and
physical size. Using film capacitors or NPO/COG capacitors
yields the best possible lock times, where as using X7R or
Z5R capacitors can increase lock time by 0 – 500%. How-
ever, it is a general tendency that designs that use a higher
compare frequency tend to be less sensitive to the effects of
capacitor dielectrics. Although the use of lesser quality di-
electric capacitors may be unavoidable in many circum-
stances, allowing a larger footprint for the loop filter capaci-
tors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values.
Capacitor dielectrics have very little impact on phase noise
and spurs.
The third step is to tinker with the fractional word. Although
1/10 and 400/4000 are mathematically the same, expressing
fractions with much larger fractional numerators often im-
prove the fractional spurs. Increasing the fractional denomi-
nator only improves spurs to a point. A good practical limit
could be to keep the fractional denominator as large as
possible, but not to exceed 4095, so it is not necessary to
use the extended fractional numerator or denominator.
This steps can be done in different orders and it might take
a few iterations to find the optimum performance. Special
considerations should be taken for lower frequencies that
are below about 100 MHz. In addition squaring up the wave,
it is often helpful to use lowest terms fractions instead of
highest terms fractions. Also, dithering may turn out to not be
so useful. All the things are to introduce a methodical way of
thinking about optimizing spurs, not an exact method. There
will be exceptions to all these rules.
1.9 FRACTIONAL SPUR AND PHASE NOISE
CONTROLS
Control of the fractional spurs is more of an art than an exact
science. The first differentiation that needs to be made is
between primary fractional and sub-fractional spurs. The
primary fractional spurs are those that occur at increments of
the channel spacing only. The sub-fractional spurs are those
that occur at a smaller resolution than the channel spacing,
Note 9: For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction, Fastlock, and many other topics, visit wireless.national.com. Here
there is the EasyPLL simulation tool and an online reference called "PLL Performance, Simulation, and Design", by Dean Banerjee.
23
www.national.com
Programming Description
2.0 GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter,
the N counter, and the internal mode control latches. The data format of a typical 24-bit data register is shown below. The control
bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift register is loaded into one of the
appropriate latches (selected by address bits). Data is shifted in MSB first. Note that it is best to program the N counter last, since
doing so initializes the digital lock detector and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT
program values into these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program
the R7 register.
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4
3
2
1
0
2.0.1 Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are mapped to the
target control register.
C3
x
C2
x
C1
x
C0
0
DATA Location
R0
R1
R2
R3
R4
R5
R6
R7
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
2.0.2 Control Register Content Map
Because the LMX2485 registers are complicated, they are organized into two groups, basic and advanced. The first four registers
are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that
optimize spur, phase noise, and lock time performance. The next page shows these registers.
www.national.com
24
25
www.national.com
Programming Description (Continued)
2.1 R0 REGISTER
Note that this register has only one control bit, so the N counter value to be changed with a single write statement to the PLL.
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA[22:0]
9
8
7
6
5
4
3
2
1
0
C0
0
R0
RF_N[10:0]
RF_FN[11:0]
2.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL
Refer to section 2.6.1 for a more detailed description of this control word.
2.1.2 RF_N[10:0] -- RF N Counter Value
The RF N counter contains an 8/9/12/13 and a 16/17/20/21 prescaler. The N counter value can be calculated as follows:
N = RF_P·RF_C + 4·RF_B + RF_A
RF_C ≥Max{RF_A, RF_B} , for N-2FM-1 ... N+2FM is a necessary condition. This rule is slightly modified in the case where the
RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for the purposes of modulation.
Consult the tables below for valid operating ranges for each prescaler.
Operation with the 8/9/12/13 Prescaler (RF_P=0)
RF_N
RF_N [10:0]
RF_C [6:0]
RF_B [1:0]
N values less than 25 are prohibited.
RF_A [1:0]
<
25
25-26
27-30
31
Possible only with a second order delta-sigma engine.
Possible only with a second or third order delta-sigma engine.
0
.
0
.
0
.
0
.
0
.
1
.
1
.
0
0
0
1
.
1
.
1
.
...
1023
1
1
1
1
1
1
1
1
1
1
>
1023
N values above 1023 are prohibited.
Operation with the 16/17/20/21 Prescaler (RF_P=1)
RF_N [10:0]
RF_N
RF_C [6:0]
RF_B [1:0]
RF_A [1:0]
<
49
N values less than 49 are prohibited.
49-50
51-54
Possible only with a second order delta-sigma engine.
Possible with a second or third order delta-sigma engine.
55
0
.
0
.
0
.
0
.
0
.
1
.
1
.
0
.
1
.
1
.
1
.
...
2039
1
1
1
1
1
1
1
0
1
1
1
2040-2043
2044-2045
Possible with a second or third order delta-sigma engine.
Possible only with a second order delta-sigma engine.
N values greater than 2045 are prohibited.
>
2045
www.national.com
26
Programming Description (Continued)
2.2 R1 REGISTER
REGISTER
R1
23
22
21 20 19 18 17 16 15 14 13 12 11 10
DATA[19:0]
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
RF_PD RF_P
RF_R[5:0]
RF_FD[11:0]
0
0
1
1
2.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator
The function of these bits are described in section 2.6.2.
2.2.2 RF_R [5:0] -- RF R Divider Value
The RF R Counter value is determined by this control word. Note that this counter does allow values down to one.
R Value
RF_R[5:0]
1
0
.
0
.
0
.
0
.
0
.
1
.
...
63
1
1
1
1
1
1
2.2.3 RF_P -- RF Prescaler bit
The prescaler used is determined by this bit.
RF_P
Prescaler
Maximum Frequency
2000 MHz
0
1
8/9/12/13
16/17/20/21
3000 MHz
2.2.4 RF_PD -- RF Power Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and the RF Charge
pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions, and will override the RF_PD bit.
The order of precedence is as follows. First, if the CE pin is LOW, then the PLL will be powered down. Provided this is not the
case, the PLL will be powered up if the ATPU bit says to do so, regardless of the state of the RF_PD bit. After the CE pin and the
ATPU bit are considered, then the RF_PD bit then takes control of the power down function for the RF PLL.
27
www.national.com
Programming Description (Continued)
2.3 R2 REGISTER
REGISTER
R2
23
22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
IF_N[18:0]
C3 C2 C1 C0
IF_PD
0
1
0
1
2.3.1 IF_N[18:0] -- IF N Divider Value
IF_N Counter Programming with the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
N Value
IF_B
IF_A
≤23
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
Legal divide ratios in this range are:
24-55
24-27, 32-36, 40-45, 48-54
56
57
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
0
0
.
0
0
0
.
0
1
.
0
.
...
262143
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Operation with the 16/17 Prescaler (IF_P=1)
N Value
IF_B
IF_A
≤47
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
48-239
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
240
241
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
1
1
.
0
0
.
0
0
.
0
0
.
0
1
.
...
524287
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.3.4 IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL
charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written to, the IF_PD will be reset to 0 and the
IF PLL will be powered up. If the CE pin is held low, the IF PLL will be powered down, overriding the IF_PD bit.
www.national.com
28
Programming Description (Continued)
2.4 R3 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA[19:0]
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R3
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
0
1
1
1
2.4.1 IF_R[11:0] -- IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for IF_R is 3.
R Value
IF_R[11:0]
3
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
1
.
4095
1
1
1
1
1
1
1
1
1
1
1
1
2.4.2 RF_CPG -- RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady state operation.
RF_CPG
Charge Pump State
Typical RF Charge Pump Current at 3 Volts (µA)
0
1
1X
2X
95
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
11X
12X
13X
14X
15X
16X
950
10
11
12
13
14
15
1045
1140
1235
1330
1425
1520
2.4.3 ACCESS -- Register Access word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional. The
ACCESS[3:0] bits determine which additional registers need to be programmed. Any one of these registers can be individually
programmed. According to the table below, when the state of a register is in default mode, all the bits in that register are forced
to a default state and it is not necessary to program this register. When the register is programmable, it needs to be programmed
through the MICROWIRE. Using this register access technique, the programming required is reduced up to 37%.
ACCESS Bit
ACCESS[0]
ACCESS[1]
ACCESS[2]
ACCESS[3]
Register Location
R3[20]
Register Controlled
Must be set to 1
R3[21]
R5
R6
R7
R3[22]
R3[23]
The default conditions the registers is shown below:
Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data[19:0]
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R4
R5
R6
R7
R4 Must be programmed manually.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
29
www.national.com
Programming Description (Continued)
This corresponds to the following bit settings.
Register Bit Location
R4[23]
Bit Name
ATPU
Bit Description
Autopowerup
Bit Value
Bit State
Disabled
0
2
3
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
R4[17:16]
DITH
Dithering
Strong
R4[15:14]
FM
Modulation Order
Oscillator Doubler
OSCout Pin Enable
IF Charge Pump Polarity
RF Charge Pump Polarity
IF PLL Prescaler
Ftest/LD Output
3rd Order
Disabled
R4[12]
OSC_2X
OSC_OUT
IF_CPP
RF_CPP
IF_P
R4
R4[11]
R4[10]
R4[9]
Disabled
Positive
Positive
R4[8]
16/17
R4[7:4]
R5[23:14]
R5[13:4]
R6[23:22]
R6[21:18]
R6[17:4]
R7[13]
R7[7]
MUX
Disabled
RF_FD[21:12] Extended Fractional Denominator
Disabled
R5
R6
RF_FN[21:12]
CSR
Extended Fractional Numerator
Cycle Slip Reduction
Fastlock Charge Pump Current
RF Timeout Counter
Disabled
Disabled
RF_CPF
RF_TOC
DIV4
Disabled
Disabled
Lock Detect Adjustment
IF PLL Counter Reset
RF PLL Counter Reset
IF PLL Tri-State
Disabled (Fcomp ≤ 20 MHz)
Disabled
IF_RST
RF_RST
IF_CPT
RF_CPT
R7
R7[6]
Disabled
R7[5]
Disabled
R7[4]
RF PLL Tri-State
Disabled
www.national.com
30
Programming Description (Continued)
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REGISTER
R4
23
22 21 20 19 18 17 16 15 14 13
DATA[19:0]
OSC_ OSC_ IF_ RF_
12
11
10
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
DITH
[1:0]
FM
MUX
[3:0]
ATPU
0
1
0
0
0
0
IF_P
1
0
0
1
[1:0]
2X
OUT CPP CPP
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
High Impedance
Push-Pull
Output Description
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled
General purpose output, Logical “High” State
General purpose output, Logical “Low” State
RF & IF Digital Lock Detect
RF Digital Lock Detect
Push-Pull
Push-Pull
Push-Pull
Push-Pull
IF Digital Lock Detect
Open Drain
Open Drain
Open Drain
Push-Pull
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
Push-Pull
Push-Pull
IF Analog Lock Detect
Push-Pull
IF R Divider divided by 2
IF N Divider divided by 2
RF R Divider divided by 2
RF N Divider divided by 2
Push-Pull
Push-Pull
Push-Pull
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
IF_P
IF Prescaler
8/9
Maximum Frequency
800 MHz
0
1
16/17
800 MHz
2.5.3 RF_CPP -- RF PLL Charge Pump Polarity
RF_CPP
RF Charge Pump Polarity
0
1
Negative
Positive (Default)
2.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase
detector polarity.
IF_CPP
IF Charge Pump Polarity
Negative
0
1
Positive
2.5.5 OSC_OUT Oscillator Output Buffer Enable
OSC_OUT
OSCout Pin
0
1
Disabled (High Impedance)
Buffered output of OSCin pin
31
www.national.com
Programming Description (Continued)
2.5.6 OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is
equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency presented to the RF R counter
is doubled. Phase noise added by the doubler is negligible.
OSC2X
Frequency Presented to RF R Counter
Frequency Presented to IF R Counter
0
1
fOSCin
fOSCin
2 x fOSCin
2.5.7 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the
carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least
one greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off.
FM
0
Function
Fractional PLL mode with a 4th order delta-sigma modulator
Disable the delta-sigma modulator. Recommended for test use only.
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
1
2
3
2.5.8 DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also
give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also
increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the
loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional
spurs much, but has a much larger impact on the sub-fractional spurs. If it is decided that dithering will be used, best results will
be obtained when the fractional denominator is at least 1000.
DITH
Dithering Mode Used
Disabled
0
1
2
3
Weak Dithering
Strong Dithering
Reserved
2.5.9 ATPU -- PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0 register is written to,
the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when the CE pin is low. In this
case, the ATPU function is disabled.
www.national.com
32
Programming Description (Continued)
2.6 R5 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA[19:0]
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R5
RF_FD[21:12]
RF_FN[21:12]
1
0
1
1
2.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] }
In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] bits become do
not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from
12 to 22-bits.
Fractional
RF_FN[21:12]
RF_FN[11:0]
Numerator
( These bits only apply in 22- bit mode)
0
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
In 12- bit mode, these are do not care.
<
In 22- bit mode, for N 4096,
...
these bits should be all set to 0.
4095
4096
...
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.6.2 Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], ACCESS[1]}
In the case that the ACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the RF_FD[21:12] bits become
do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode and the fractional denominator is expanded
from 12 to 22-bits.
Fractional
RF_FD[21:12]
RF_FD[11:0]
Denominator
( These bits only apply in 22- bit mode)
In 12- bit mode, these are do not care.
0
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
<
In 22- bit mode, for N 4096,
these bits should be all set to 0.
...
4095
4096
...
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
33
www.national.com
Programming Description (Continued)
2.7 R6 REGISTER
REGISTER 23
R6 CSR[1:0]
2.7.1 RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin
22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3 C2 C1 C0
RF_CPF[3:0]
RF_TOC[13:0]
1
1
0
1
The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the FLoutRF output pin.
When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and the FLoutRF pin operates as a general
purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value between 4 and 16383, the RF Fastlock mode is enabled and
the FLoutRF pin is utilized as the RF Fastlock output pin. The value programmed into the RF_TOC[13:0] word represents two
times the number of phase detector comparison cycles the RF synthesizer will spend in the Fastlock state.
RF_TOC
Fastlock Mode
Disabled
Fastlock Period [CP events]
FLoutRF Pin Functionality
High Impedance
Logic “0” State.
Forces all Fastlock conditions
Logic “0” State
Logic “1” State
Fastlock
0
1
N/A
N/A
Manual
2
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
N/A
N/A
3
4
4X2 = 8
5X2 = 10
…
5
Fastlock
…
Fastlock
16383
16383X2 = 32766
Fastlock
2.7.2 RF_CPF -- RF PLL Fastlock Charge Pump Current
Specify the charge pump current for the Fastlock operation mode for the RF PLL. Note that the Fastlock charge pump current,
steady state current, and CSR control are all interrelated.
RF_CPF
RF Charge Pump State
Typical RF Charge Pump Current at 3 Volts (µA)
0
1
1X
2X
95
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
11X
12X
13X
14X
15X
16X
950
10
11
12
13
14
15
1045
1140
1235
1330
1425
1520
www.national.com
34
Programming Description (Continued)
2.7.3 CSR[1:0] -- RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase
detector cycle slips. Note that the Fastlock charge pump current, steady state current, and CSR control are all interrelated. Refer
to section 1.8 for information on how to use this.
CSR
CSR State
Disabled
Enabled
Enabled
Enabled
Sample Rate Reduction Factor
0
1
2
3
1
1/2
1/4
1/16
35
www.national.com
Programming Description (Continued)
2.8 R7 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Data[19:0]
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R7
0
0
0
0
0
0
0
0
0
0
DIV4
0
1
0
0 1 IF_RST RF_RST IF_CPT RF_CPT
1
1
1
1
2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked condition for larger
comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison frequency (it does not apply to the IF
comparison frequency) presented to the digital lock detect circuitry by 4. This enables this circuitry to work at higher comparison
frequencies. It is recommended that this bit be enabled whenever the comparison frequency exceeds 20 MHz and RF digital lock
detect is being used.
2.8.2 IF_RST -- IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a Tri-State condition. This feature
should be disabled for normal operation. Note that a counter reset is applied whenever the chip is powered up via software or CE
pin.
IF_RST
0 (Default)
1
IF PLL N and R Counters
Normal Operation
IF PLL Charge Pump
Normal Operation
Tri-State
Counter Reset
2.8.3 RF_RST -- RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a Tri-State condition. This feature
should be disabled for normal operation. This feature should be disabled for normal operation. Note that a counter reset is applied
whenever the chip is powered up via software or CE pin.
RF_RST
0 (Default)
1
RF PLL N and R Counters
Normal Operation
RF PLL Charge Pump
Normal Operation
Tri-State
Counter Reset
2.8.4 RF_TRI -- RF Charge Pump Tri-State
When this bit is enabled, the RF PLL charge pump is put in a Tri-State condition, but the counters are not reset. This feature is
typically disabled for normal operation.
RF_TRI
0 (Default)
1
RF PLL N and R Counters
Normal Operation
RF PLL Charge Pump
Normal Operation
Tri-State
Normal Operation
2.8.5 IF_TRI -- IF Charge Pump Tri-State
When this bit is enabled, the IF PLL charge pump is put in a Tri-State condition, but the counters are not reset. This feature is
typically disabled for normal operation.
IF_TRI
0 (Default)
1
IF PLL N and R Counters
Normal Operation
IF PLL Charge Pump
Normal Operation
Tri-State
Normal Operation
www.national.com
36
Physical Dimensions inches (millimeters) unless otherwise noted
Plastic Quad LLP (SQ), Bottom View
Order Number LMX2485SQ or LMX2485ESQ for 1000 Unit Reel
Order Number LMX2485SQX or LMX2485ESQX for 4500 Unit Reel
NS Package Number SQA24A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
相关型号：
LMX2485SQ/NOPB
IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, PQCC24, 4 X 4 MM, 0.8 MM, PLASTIC, LLP-24, PLL or Frequency Synthesis Circuit
NSC
LMX2485SQX
50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
NSC
LMX2485_0610
50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
NSC
LMX2485_08
50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL
NSC
LMX2486
1.0 GHz - 4.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum TM Frequency Synthesizers with 3.0 GHz Integer PLL
NSC
LMX2486SQ
IC PLL FREQUENCY SYNTHESIZER, 4500 MHz, PQCC24, 4 X 4 MM, 0.8 MM HEIGHT, PLASTIC, LLP-24, PLL or Frequency Synthesis Circuit
NSC
LMX2487
1.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™ Frequency Synthesizers with 3.0 GHz Integer PLL
NSC
©2020 ICPDF网 联系我们和版权申明