LMX2487 [TI]
Low-Power Dual PLLatinum Frequency Synthesizers;
| 型号： | LMX2487 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power Dual PLLatinum Frequency Synthesizers |
| 文件： | 总47页 (文件大小：1189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMX2487
www.ti.com
SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
LMX2487 1.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™
Frequency Synthesizers with 3.0 GHz Integer PLL
Check for Samples: LMX2487
1
FEATURES
APPLICATIONS
23
•
Quadruple Modulus Prescalers for Lower
Divide Ratios
•
•
•
•
Cellular Phones and Base Stations
Direct Digital Modulation Applications
Satellite and Cable TV Tuners
WLAN Standards
–
–
RF PLL: 16/17/20/21 or 32/33/36/37
IF PLL: 8/9 or 16/17
•
•
Advanced Delta Sigma Fractional
Compensation
DESCRIPTION
The LMX2487 is a low power, high performance
delta-sigma fractional-N PLL with an auxiliary integer-
N PLL. It is fabricated using TI’s advanced process.
–
12 Bit or 22 Bit Selectable Fractional
Modulus
–
Up to 4th Order Programmable Delta-Sigma
Modulator
With delta-sigma architecture, fractional spurs at
lower offset frequencies are pushed to higher
frequencies outside the loop bandwidth. The ability to
push close in spur and phase noise energy to higher
frequencies is a direct function of the modulator
order. Unlike analog compensation, the digital
feedback technique used in the LMX2487 is highly
resistant to changes in temperature and variations in
wafer processing. The LMX2487 delta-sigma
modulator is programmable up to fourth order, which
allows the designer to select the optimum modulator
order to fit the phase noise, spur, and lock time
requirements of the system.
Features for Improved Lock Times and
Programming
–
–
–
Fastlock / Cycle Slip Reduction
Integrated Time-Out Counter
Single Word Write to Change Frequencies
with Fastlock
•
•
Wide Operating Range
LMX2487 RF PLL: 1.0 GHz to 6.0 GHz
Useful Features
–
–
–
Digital Lock Detect Output
Serial data for programming the LMX2487 is
transferred via a three line high speed (20 MHz)
MICROWIRE interface. The LMX2487 offers fine
frequency resolution, low spurs, fast programming
speed, and a single word write to change the
frequency. This makes it ideal for direct digital
modulation applications, where the N counter is
directly modulated with information. The LMX2487 is
available in a 24 lead 4.0 X 4.0 X 0.8 mm WQFN
package.
Hardware and Software Power-down
Control
–
–
–
On-chip Crystal Reference Frequency
Doubler.
RF Phase Comparison Frequency up to 50
MHz
2.5 to 3.6 Volt Operation with ICC = 8.5 mA
at 3.0 V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PLLatinum is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMX2487
SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
www.ti.com
Functional Block Diagram
VddIF1
VddIF2
IF N Divider
B Counter
8/9
or
FinIF
ENOSC
OSCin
Phase
Comp
Charge
Pump
16/17
Prescaler
CPoutIF
A Counter
IF
LD
IF R
Divider
OSCout
VddRF1
Ftest/LD
MUX
Ftest/LD
RF R
Divider
1X / 2X
VddRF2
VddRF3
VddRF4
VddRF5
FinRF
RF LD
RF N Divider
C Counter
16/17/20/21
or
32/33/36/37
Prescaler
Charge
Pump
CPoutRF
FLoutRF
B Counter
FinRF*
A Counter
CE
RF Fastlock
CLK
MICROWIRE
Interface
DATA
GND
GND
GND
SD
Compensation
LE
Connection Diagram
24 23 22 21 20 19
CPoutRF
GND
18 OSCout
17 VddIF2
1
2
3
4
5
6
VddRF1
CPoutIF
GND
16
15
Pin 0
(Ground Substrate)
FinRF
FinRF*
LE
14 VddIF1
FinIF
13
7
8
9
10 11 12
Figure 1. Top View
24-Pin WQFN (RTW)
2
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin #
Pin Name
GND
I/O
Pin Description
0
1
2
3
4
5
6
-
O
-
Ground Substrate. This is on the bottom of the package and must be grounded.
RF PLL charge pump output.
CPoutRF
GND
RF PLL analog ground.
VddRF1
FinRF
FinRF*
LE
-
RF PLL analog power supply.
I
RF PLL high frequency input pin.
I
RF PLL complementary high frequency input pin. Shunt to ground with a 100 pF capacitor.
I
MICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift registers is loaded
into the internal latches when LE goes HIGH
7
8
DATA
CLK
I
I
MICROWIRE Data. High impedance binary serial data input.
MICROWIRE Clock. High impedance CMOS Clock input. Data for the various counters is clocked
into the 24 bit shift register on the rising edge
9
VddRF2
CE
-
I
Power supply for RF PLL digital circuitry.
Chip Enable control pin. Must be pulled high for normal operation.
Power supply for RF PLL digital circuitry.
Test frequency output / Lock Detect.
IF PLL high frequency input pin.
IF PLL analog power supply.
10
11
12
13
14
15
16
17
18
19
VddRF5
Ftest/LD
FinIF
I
O
I
VddIF1
GND
-
-
IF PLL digital ground.
CPoutIF
VddIF2
OSCout
ENOSC
O
-
IF PLL charge pump output
IF PLL power supply.
O
I
Buffered output of the OSCin signal.
Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the state of other
pins or register bits.
20
21
22
23
24
OSCin
NC
I
I
Reference Input.
This pin must be left open.
VddRF3
FLoutRF
VddRF4
-
Power supply for RF PLL digital circuitry.
RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
RF PLL analog power supply.
O
-
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Value
Parameter
Symbol
Units
Min
-0.3
-0.3
-65
Typ
Max
4.25
Power Supply Voltage
VCC
Vi
V
V
Voltage on any pin with GND = 0V
Storage Temperature Range
VCC+0.3
+150
Ts
°C
°C
Lead Temperature (Solder 4 sec.)
TL
+260
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions"
indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. The
voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC will
be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.
(2) This Device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this
device should only be done at ESD-free workstations.
Recommended Operating Conditions
Value
Parameter
Symbol
Units
Min
2.5
-40
Typ
3.0
25
Max
3.6
(1)
Power Supply Voltage
VCC
TA
V
Operating Temperature
+85
°C
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions"
indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. The
voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC will
be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.
Electrical Characteristics
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
Value
Symbol
Parameter
Conditions
Units
Min
Typ
Max
Icc PARAMETERS
IF PLL OFF
Power Supply Current, RF Synthesizer RF PLL ON
Charge Pump TRI-STATE
ICCRF
ICCIF
5.7
2.5
mA
mA
IF PLL ON
Power Supply Current, IF Synthesizer
RF PLL OFF
Charge Pump TRI-STATE
IF PLL ON
RF PLL ON
Charge Pump TRI-STATE
Power Supply Current, Entire
Synthesizer
ICCTOTAL
ICCPD
8.5
< 1
mA
µA
CE = ENOSC = 0V
CLK, DATA, LE = 0V
Power Down Current
4
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
Electrical Characteristics (continued)
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
Value
Symbol
Parameter
Conditions
Units
Min
Typ
Max
RF SYNTHESIZER PARAMETERS
RF_P = 16
RF_P = 32
1000
1000
-10
4000
6000
0
Operating
Frequency
fFinRF
LMX2487
MHz
pFinRF
fCOMP
Input Sensitivity
dBm
MHz
Phase Detector Frequency(1)
50
RF_CPG = 0
VCPoutRF = VCC/2
95
µA
RF_CPG = 1
VCPoutRF = VCC/2
190
...
µA
µA
µA
ICPoutRFSRCE
RF Charge Pump Source Current(2)
...
RF_CPG = 15
VCPoutRF = VCC/2
1520
RF_CPG = 0
VCPoutRF = VCC/2
-95
µA
RF_CPG = 1
VCPoutRF = VCC/2
-190
...
µA
µA
µA
ICPoutRFSINK
RF Charge Pump Sink Current(2)
...
RF_CPG = 15
VCPoutRF = VCC/2
-1520
RF Charge Pump TRI-STATE Current
Magnitude
ICPoutRFTRI
0.5 ≤ VCPoutRF ≤ VCC -0.5
2
10
nA
RF_CPG > 2
3
3
10
13
%
%
Magnitude of RF CP Sink vs. CP
Source Mismatch
VCPoutRF = VCC/2
TA = 25°C
| ICPoutRF%MIS |
RF_CPG ≤ 2
Magnitude of RF CP Current vs. CP
Voltage
0.5 ≤ VCPoutRF ≤ VCC -0.5
TA = 25°C
| ICPoutRF%V |
| ICPoutRF%T |
2
4
8
%
%
Magnitude of RF CP Current vs.
Temperature
VCPoutRF = VCC/2
IF SYNTHESIZER PARAMETERS
IF_P = 8
250
250
-10
2000
3000
+5
fFinIF
Operating Frequency
MHz
IF_P = 16
pFinIF
IF Input Sensitivity
dBm
MHz
mA
fCOMP
Phase Detector Frequency
IF Charge Pump Source Current
IF Charge Pump Sink Current
10
ICPoutIFSRCE
ICPoutIFSINK
VCPoutIF = VCC/2
VCPoutIF = VCC/2
3.5
-3.5
mA
IF Charge Pump TRI-STATE Current
Magnitude
ICPoutIFTRI
0.5 ≤ VCPoutIF ≤ VCC RF -0.5
2
1
4
4
10
8
nA
%
%
%
Magnitude of IF CP Sink vs. CP
Source Mismatch
VCPoutIF = VCC/2
TA = 25°C
| ICPoutIF%MIS |
| ICPoutIF%V |
| ICPoutIF%TEMP
Magnitude of IF CP Current vs. CP
Voltage
0.5 ≤ VCPoutIF ≤ VCC -0.5
TA = 25°C
10
Magnitude of IF CP Current vs.
Temperature
VCPoutIF = VCC/2
OSCILLATOR PARAMETERS
OSC2X = 0
OSC2X = 1
5
5
110
20
MHz
MHz
VP-P
µA
fOSCin
Oscillator Operating Frequency
vOSCin
Oscillator Input Sensitivity
Oscillator Input Current
0.5
-100
VCC
100
IOSCin
SPURS
Spurs in band(3)
-55
dBc
(1) For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
(2) Refer to the table in RF_CPG – RF PLL Charge Pump Gain for a complete listing of charge pump currents.
(3) In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is
one. The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop
bandwidth must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency =
10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, VCO Frequency =
3 GHz, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
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Electrical Characteristics (continued)
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
PHASE NOISE
RF_CPG = 0
RF_CPG = 1
RF_CPG = 3
RF_CPG = 7
RF_CPG = 15
-202
-204
-206
-210
-210
RF Synthesizer Normalized Phase
Noise Contribution(4)
LF1HzRF
dBc/Hz
dBc/Hz
IF Synthesizer Normalized Phase
Noise Contribution
LF1HzIF
-209
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
Low-Level Output Voltage
1.6
VCC
0.4
1.0
1.0
V
V
VIH = VCC
-1.0
-1.0
µA
µA
V
IIL
VIL = 0 V
VOH
VOL
IOH = -500 µA
IOL = 500 µA
VCC-0.4
0.4
V
MICROWIRE INTERFACE TIMING
tCS
Data to Clock Set Up Time
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
25
8
ns
ns
ns
ns
ns
ns
tCH
Data to Clock Hold Time
Clock Pulse Width High
tCWH
tCWL
tES
25
25
25
25
Clock Pulse Width Low
Clock to Load Enable Set Up Time
Load Enable Pulse Width
tEW
(4) Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band
phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than
the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement
conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency =
20 MHz, FM = 0, DITH = 0, VCO Frequency = 3 GHz.
MICROWIRE INPUT TIMING DIAGRAM
MSB
LSB
C0
DATA
CLK
LE
D19
D18
D17
D16
D15
D0
C3
C2
C1
t
t
CWH
CS
t
ES
t
CH
t
CWL
t
EW
Figure 2. MICROWIRE Input Timing Diagram
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
Typical Performance Characteristics: Sensitivity
NOTE
Typical performance characteristics do not imply any sort of ensured specification.
Ensured specifications are in Electrical Characteristics.
RF PLL Fin Sensitivity
TA = 25°C, RF_P = 32
20
10
V
CC
= 2.5V
V
CC
= 3.0V and 3.6V
0
-10
-20
-30
-40
V
= 3.6V
CC
V
= 2.5V
CC
V
= 3.0V
CC
1000
2000
4000
(MHz)
6000
0
3000
5000
7000
f
FinRF
Figure 3.
RF PLL Fin Sensitivity
VCC = 3.0 V, RF_P = 32
20
T
A
= 85oC
10
0
T
A
= 25oC
T
= -40oC
A
-10
-20
-30
-40
T
= 85oC
A
T
= -40oC
A
T
A
= 25oC
2000
1000
4000
fFinRF (MHz)
6000
0
3000
5000
7000
Figure 4.
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Typical Performance Characteristics: Sensitivity (continued)
IF PLL Fin Sensitivity
TA = 25°C, IF_P = 16
20
10
0
V
CC
= 3.0 and 3.6V
V
CC
= 2.5V
-10
-20
-30
-40
V
CC
= 3.0V
V
CC
= 3.6V
V
CC
= 2.5V
2000
(MHz)
3000
0
1000
4000
f
FinIF
Figure 5.
IF PLL Fin Sensitivity
VCC = 3.0 V, IF_P = 16
20
10
0
T
A
= -40oC
T
= 25oC, and 85oC
A
-10
-20
-30
-40
-50
T
= 25oC
A
T
A
= -40oC
T
A
= 85oC
2000
(MHz)
0
1000
3000
4000
f
FinIF
Figure 6.
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
Typical Performance Characteristics: Sensitivity (continued)
OSCin Sensitivity
TA = 25°C, OSC_2X = 0
20
10
V
CC
= 2.5V, 3.0V, and 3.6V
0
-10
-20
-30
-40
-50
V
= 3.6V
CC
V
= 3.0V
CC
V
= 2.5V
CC
0
30
60
120
150
90
10
f
(MHz)
OSCin
Figure 7.
OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 0
20
10
0
T
A
= -40oC, 25oC, and 85oC
-10
-20
-30
-40
-50
T
= 25oC
A
T
A
= 85oC
T
= -40oC
A
0
10
30
90
120
150
60
f
(MHz)
OSCin
Figure 8.
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Typical Performance Characteristics: Sensitivity (continued)
OSCin Sensitivity
TA = 25°C, OSC_2X =1
20
10
V
= 2.5V, 3.0V, and 3.6V
CC
0
V
CC
= 3.6V
-10
-20
-30
-40
-50
V
CC
= 3.0V
V
CC
=2.5V
10
0
5
15
20
25
f
(MHz)
OSCin
Figure 9.
OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 1
20
10
T
A
= -40oC, 25oC, and 85oC
0
-10
-20
-30
-40
-50
T
= 85oC
A
T
A
= -40oC
T
= 25oC
A
10
0
5
15
20
25
f
(MHz)
OSCin
Figure 10.
10
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
Typical Performance Characteristics: FinRF Input Impedance
NOTE
Typical performance characteristics do not imply any sort of ensured specification.
Ensured specifications are in Electrical Characteristics.
Marker 1:
3 GHz
Marker 2:
4 GHz
Marker 3:
5 GHz
Marker 4:
6 GHz
1
Start 2.5 GHz
Stop 7.0 GHz
2
3
4
Figure 11.
FinRF Input Impedance
Frequency (MHz)
3000
Real (Ohms)
Imaginary (Ohms)
39
37
33
30
28
26
24
23
22
20
19
18
17
17
16
16
16
16
-94
-86
-78
-72
-69
-66
-63
-60
-57
-54
-50
-49
-47
-45
-44
-42
-40
-39
3200
3400
3600
3800
4000
4250
4500
4750
5000
5250
5500
5750
6000
6250
6500
6750
7000
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Typical Performance Characteristics: FinIF Input Impedance
NOTE
Typical performance characteristics do not imply any sort of ensured specification.
Ensured specifications are in Electrical Characteristics.
Marker 1:
100 MHz
Marker 2:
250 MHz
Marker 3:
2300 MHz
2
1
Marker 4:
3000 MHz
3
Start 100 MHz
Stop 3000 MHz
4
Figure 12.
FinIF Input Impedance
Frequency (MHz)
100
Real (Ohms)
508
456
420
403
370
344
207
274
242
242
214
171
137
112
91
Imaginary (Ohms)
-233
-215
-206
-205
-207
-215
-223
-225
-225
-225
-222
-208
-191
-176
-158
-139
-122
-105
-96
150
200
250
300
400
500
600
700
800
900
1000
1200
1400
1600
1800
2000
2200
2300
2400
2600
2800
3000
76
62
51
46
42
-88
37
-74
29
-63
25
-54
12
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
Typical Performance Characteristics: OSCin Input Impedance
NOTE
Typical performance characteristics do not imply any sort of ensured specification.
Ensured specifications are in Electrical Characteristics.
6000
5000
4000
3000
Powered
Down
2000
1000
Powered
Up
0
100
0
25
50
75
125
150
FREQUENCY (MHz)
Figure 13.
Frequency (MHz)
Powered Up
Imaginary
-3779
-2236
-1196
-863
Powered Down
Imaginary
-8137
-4487
-2215
-1495
-1144
-912
Real
1730
846
466
351
316
278
261
252
239
234
230
225
219
214
208
207
Magnitude
4157
2391
1284
932
Real
392
155
107
166
182
155
153
154
147
145
140
138
133
133
132
133
Magnitude
8146
4490
2217
-1504
1158
925
5
10
20
30
40
-672
742
50
-566
631
60
-481
547
-758
774
70
-425
494
-652
669
80
-388
456
-576
595
90
-358
428
-518
538
100
110
120
130
140
150
-337
407
-471
492
-321
392
-436
458
-309
379
-402
123
-295
364
-374
397
-285
353
-349
373
-279
348
-329
355
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Typical Performance Characteristics: Currents
NOTE
Typical performance characteristics do not imply any sort of ensured specification.
Ensured specifications are in Electrical Characteristics.
Power Supply Current
CE = High
10
T
A
= 85oC
9.0
8.0
7.0
6.0
5.0
4.0
T
A
= 25oC
T
= -40oC
A
3.0
2.0
1.0
0
2.5
3.3
3.6
2.75
3.0
V
CC
(V)
Figure 14.
RF PLL Charge Pump Current
VCC = 3.0 Volts
2000
1500
1000
500
RF_CPG = 15
RF_CPG = 8
0
-500
RF_CPG = 0
RF_CPG = 1
-1000
-1500
-2000
0
0.5
1.0
1.5
2.0
3.0
2.5
V
(V)
CPoutRF
Figure 15.
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Typical Performance Characteristics: Currents (continued)
IF PLL Charge Pump Current
VCC = 3.0 Volts
5.0
4.0
3.0
2.0
1.0
0
-1.0
-2.0
-3.0
-4.0
-5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
CPoutIF
Figure 16.
Charge Pump Leakage
RF PLL
VCC = 3.0 Volts
10
8
6
4
TA = 85o C
2
0
TA = -40o C
-2
-4
TA = 25o C
-6
-8
-10
0
0.5
1.0
1.5
2.0
3.0
2.5
V
(V)
CPoutRF
Figure 17.
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Typical Performance Characteristics: Currents (continued)
Charge Pump Leakage
IF PLL
VCC = 3.0 Volts
10
8
6
TA = 85o C
4
2
0
-2
-4
TA = -40o C
TA = 25o C
-6
-8
-10
2.5
0
0.5
1.0
1.5
2.0
3.0
VCPoutIF (V)
Figure 18.
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BENCH TEST SETUPS
DC
Blocking
Capacitor
10 MHz
SMA Cable
SMA Cable
Frequency
Input Pin
Signal Generator
Device
Under
Test
Semiconductor
Parameter
Analyzer
CPout
Pin
OSCin
Pin
Evaluation Board
Power Supply
Figure 19. Block Diagram
Charge Pump Current Measurement Procedure
Figure 19 shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current
level, mismatch, and leakage measurements. In order to measure the charge pump currents, a signal is applied
to the high frequency input pins. The reason for this is to ensure that the phase detector gets enough transitions
in order to be able to change states. If no signal is applied, it is possible that the charge pump current reading
will be low due to the fact that the duty cycle is not 100%. The OSCin Pin is tied to the supply. The charge pump
currents can be measured by simply programming the phase detector to the necessary polarity. For instance, in
order to measure the RF charge pump, a 10 MHz signal is applied to the FinRF pin. The source current can be
measured by setting the RF PLL phase detector to a positive polarity, and the sink current can be measured by
setting the phase detector to a negative polarity. The IF PLL currents can be measured in a similar way. Note the
magnitude of the RF PLL charge pump current is controlled by the RF_CPG bit. Once the charge pump currents
are known, the mismatch can be calculated. In order to measure leakage, the charge pump is set to a TRI-
STATE mode by enabling the RF_CPT and IF_CPT bits. The table below shows a summary of the various
charge pump tests.
Current Test
RF Source
RF Sink
RF_CPG
RF_CPP
RF_CPT
IF_CPP
IF_CPT
0 to 15
0
1
0
0
X
X
X
0
X
X
X
0
0
1
0 to 15
RF TRI-STATE
IF Source
X
X
X
X
X
X
X
X
1
X
X
X
IF Sink
1
IF TRI-STATE
X
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Charge Pump Current Specification Definitions
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 volts for this part.
vCPout refers to either VCPoutRF or VCPoutIF
ICPout refers to either ICPoutRF or ICPoutIF
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Charge Pump Output Current Variation vs. Charge Pump Output Voltage
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
Charge Pump Output Current Variation vs. Temperature
SMA Cable
Matching
Network
Frequency
Input Pin
Signal Generator
DC
Blocking
Capacitor
Device
Under
Test
SMA Cable
Ftest/LD
Pin
Frequency Counter
Evaluation Board
Power Supply
Frequency Input Pin
DC Blocking Capacitor
Corresponding Counter
RF_R / 2
Default Counter Value
MUX Value
OSCin
FinRF
FinIF
1000 pF
100 pF// 1000 pF
100 pF
50
14
15
13
12
RF_N / 2
502 + 2097150 / 4194301
IF_N / 2
534
50
OSCin
1000 pF
IF_R / 2
Sensitivity Measurement Procedure
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz
or more of its expected value. It is typically measured over frequency, voltage, and temperature. In order to test
sensitivity, the MUX[3:0] word is programmed to the appropriate value. The counter value is then programmed to
a fixed value and a frequency counter is set to monitor the frequency of this pin. The expected frequency at the
Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The
factor of two comes in because the LMX2487 has a flip-flop which divides this frequency by two to make the duty
cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance
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should be set to high impedance. In order to perform the measurement, the temperature, frequency, and voltage
is set to a fixed value and the power level of the signal is varied. Note the power level at the part is assumed to
be 4 dB less than the signal generator power level. This accounts 1 dB for cable losses and 3 dB for the pad.
The power level range where the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for
the sensitivity limits. The temperature, frequency, and voltage can be varied in order to produce a family of
sensitivity curves. Since this is an open-loop test, the charge pump is set to TRI-STATE and the unused side of
the PLL (RF or IF) is powered down when not being tested. For this part, there are actually four frequency input
pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown in
the table in the Charge Pump Output Current Variation vs. Temperature section.
Note for the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a fraction of 2097150 /
4194301 is used. The reason for this long fraction is to test the RF N counter and supporting fractional circuitry
as completely as possible.
Frequency
Input Pin
Network Analyzer
Device
Under
Test
Evaluation Board
Power Supply
Figure 20. Block Diagram
Input Impedance Measurement Procedure
Figure 20 shows the test setup used for measuring the input impedance for the LMX2487. The DC blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a zero Ohm
resistor. This procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the
network analyzer, ensure the part is powered up, and then measure the input impedance. The network analyzer
can be calibrated by using either calibration standards or by soldering resistors directly to the evaluation board.
An open can be implemented with no resistor. A short can be implemented by soldering a zero ohm resistor as
close as possible to the pin being measured, and can also be implemented by soldering two 100 ohm resistors in
parallel as close as possible to the pin being measured. Calibration is done with the PLL removed from the PCB.
This requires the use of a clamp down fixture that may not always be generally available. If no clamp down
fixture is available, then this procedure can be done by calibrating up to the point where the DC blocking
capacitor usually is, and then implementing port extensions with the network analyzer. A zero ohm resistor is
added back in for the actual measurement. Once the setup is calibrated, it is necessary to ensure the PLL is
powered up. This can be done by toggling the power down bits (RF_PD and IF_PD) and observing the current
consumption increases when the bit is disabled. Sometimes it may be necessary to apply a signal to the OSCin
pin in order to program the part. If this is necessary, disconnect the signal once it is established the part is
powered up. It is useful to know the input impedance of the PLL for the purposes of debugging RF problems and
designing matching networks. Another use for knowing this parameter is make the trace width on the PCB such
that the input impedance of this trace matches the real part of the input impedance of the PLL frequency of
operation. In general, it is good practice to keep trace lengths short and make designs that are relatively resistant
to variations in the input impedance of the PLL.
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Functional Description
GENERAL
The LMX2487 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter
are supplied external to the chip. The various blocks are described below.
TCXO, OSCILLATOR BUFFER, AND R COUNTER
The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is
included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The
ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the
registers in the LMX2487.
The R counter divides this TCXO frequency down to the comparison frequency.
PHASE DETECTOR
The maximum phase detector operating frequency for the IF PLL is straightforward, but is a little more involved
for the RF PLL since it is fractional. The maximum phase detector frequency for the LMX2487 RF PLL is
50 MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The
crystal reference frequency also limits the phase detector frequency, although the doubler helps with this
limitation. There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then
phase noise will be lower; but lock time may be increased due to cycle slipping and the capacitors in the loop
filter may become rather large.
CHARGE PUMP
For the majority of the time, the charge pump output is high impedance, and the only current through this pin is
the Tri-State leakage. However, it does put out fast correction pulses that have a width that is proportional to the
phase error presented at the phase detector.
The charge pump converts the phase error presented at the phase detector into a correction current. The
magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF
PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL
allows for a higher charge pump current to be used when the PLL is locking in order to reduce the lock time.
LOOP FILTER
The loop filter design can be rather involved. In addition to the regular constraints and design parameters, delta-
sigma PLLs have the additional constraint that the order of the loop filter should be one greater than the order of
the delta sigma modulator. This rule of thumb comes from the requirement that the loop filter must roll off the
delta sigma noise at 20 dB/decade faster than it rises. However, since the noise can not have infinite power, it
must eventually roll off. If the loop bandwidth is narrow, this requirement may not be necessary. For the purposes
of discussion in this datasheet, the pole of the loop filter at 0 Hz is not counted. So a second order filter has
3 components, a 3rd order loop filter has 5 components, and the 4th order loop filter has 7 components. Although
a 5th order loop filter is theoretically necessary for use with a 4th order modulator, typically a 4th order filter is
used in this case. The loop filter design, especially for higher orders can be rather involved, but there are many
simulation tools and references available, such as the one given at the end of the functional description block.
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N COUNTERS AND HIGH FREQUENCY INPUT PINS
The N counter divides the VCO frequency down to the comparison frequency. Because prescalers are used,
there are limitations on how small the N value can be. The N counters are discussed in greater depth in
Programming Description. Since the input pins to these counters ( FinRF and FinIF ) are high frequency, layout
considerations are important.
High Frequency Input Pins, FinRF and FinIF
It is generally recommended that the VCO output go through a resistive pad and then through a DC blocking
capacitor before it gets to these high frequency input pins. If the trace length is sufficiently short ( < 1/10th of a
wavelength ), then the pad may not be necessary, but a series resistor of about 39 ohms is still recommended to
isolate the PLL from the VCO. The DC blocking capacitor should be chosen at least to be 27 pF. It may turn out
that the frequency is above the self-resonant frequency of the capacitor, but since the input impedance of the
PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad and the DC blocking
capacitor should be placed as close to the PLL as possible
Complementary High Frequency Pin, FinRF*
These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended
fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such
that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating
frequency of the PLL. 100 pF is a typical value.
POWER PINS, POWER DOWN, AND POWER UP MODES
It is recommended that all of the power pins be filtered with a series 18 ohm resistor and then placing two
capacitors shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values
in theory, the ESR ( Equivalent Series Resistance ) is greater for larger capacitors. For optimal filtering minimize
the sum of the ESR and theoretical impedance of the capacitor. It is therefore recommended to provide two
capacitors of very different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor
should be placed as close as possible to the pin.
The power down state of the LMX2487 is controlled by many factors. The one factor that overrides all other
factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is
necessary to power up the chip, however, there are other bits in the programming registers that can override this
and put the PLL back in a power down state. Provided that the voltage on the CE pin is high, programming the
RF_PD and IF_PD bits to zero ensures that the part will be powered up. Programming either one of these bits to
one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this.
ATPU
Bit Enabled +
Write to RF
N Counter
CE Pin
RF_PD
PLL State
Low
X
X
Powered Down
(Asynchronous)
High
High
High
X
0
1
Yes
No
Powered Up
Powered Up
No
Powered Down
( Asynchronous )
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DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase
detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less
than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to
approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The
values of ε and δ are dependent on which PLL is used and are shown in the table below:
PLL
RF
IF
ε
δ
10 ns
15 ns
20 ns
30 ns
When the PLL is in the power down mode and the Ftest/LD pin is programmed for the lock detect function, it is
forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the
DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to
divide the comparison frequency presented to the lock detect circuit by 4. Note that if the MUX[3:0] word is set
such as to view lock detect for both PLLs, an unlocked (LOW) condition is shown whenever either one of the
PLLs is determined to be out of lock.
START
LD = LOW
(Not Locked)
NO
Phase Error < e
YES
NO
Phase Error < e
YES
NO
Phase Error < e
YES
NO
Phase Error < e
YES
NO
Phase Error < e
YES
LD = HIGH
(Locked)
NO
YES
Phase Error > d
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CYCLE SLIP REDUCTION AND FASTLOCK
The LMX2487 offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that
it requires no additional programming overhead to use them. It is generally recommended that the charge pump
current in the steady state be 8X or less in order to use cycle slip reduction, and 4X or less in steady state in
order to use Fastlock. The next step is to decide between using Fastlock or CSR. This determination can be
made based on the ratio of the comparison frequency ( fCOMP ) to loop bandwidth ( BW ).
Comparison Frequency
( fCOMP
Cycle Slip Reduction
( CSR )
Fastlock
)
fCOMP ≤ 1.25 MHz
1.25 MHz < fCOMP ≤ 2 MHz
fCOMP > 2 MHz
Noticeable better than CSR
Marginally better than CSR
Same or worse than CSR
Likely to provide a benefit, provided that
fCOMP > 100 X BW
Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the
same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases
where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can
occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically
the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR
provides no benefit. There is a glitch when CSR is disengaged, but since CSR should be disengaged long before
the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to do this at
the peak time of the transient response. Because this time is typically much sooner than Fastlock should be
disengaged, it does not make sense to use CSR and Fastlock in combination.
Fastlock
Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the
comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can
offer. Since Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide a
significant benefit in cases where the comparison frequency is above 2 MHz. However, CSR can usually provide
an equal or larger benefit in these cases, and can be implemented without using an additional resistor. The
reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits
the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option
of reducing the comparison frequency at the expense of phase noise in order to satisfy this constraint on
comparison frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these
circumstances. When using Fastlock, it is also recommended that the steady state charge pump state be 4X or
less. Also, Fastlock was originally intended only for second order filters, so when implementing it with higher
order filters, the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well
optimized when the higher charge pump current and Fastlock resistor are engaged.
Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available
factors are 1/2, 1/4, and 1/16. In order to preserve the same loop characteristics, it is recommended that the
following constraint be satisfied:
(Fastlock Charge Pump Current) / (Steady State Charge Pump Current) = CSR
In order to satisfy this constraint, the maximum charge pump current in steady state is 8X for a CSR of 1/2, 4X
for a CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump
currents, it makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger
than this will not improve lock time, and will result in worse phase noise.
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Consider an example where the desired loop bandwidth in steady state is 100 kHz and the comparison
frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it
was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is
probably sufficient. A charge pump current of 8X could be used in steady state, and a factor of 16X could be
used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies
the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the
time, since it would probably have better phase noise, and the degradation in lock time would not be too severe.
Using Fastlock to Improve Lock Times
Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed in order to determine
the theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel
during Fastlock. This ratio is calculated as follows:
K = ( Fastlock Charge Pump Current ) / ( Steady State Charge Pump Current )
K
1
Loop Bandwidth
1.00 X
R2p Value
Open
Lock Time
100 %
71 %
58%
2
1.41 X
R2/0.41
R2/0.73
R2
3
1.73 X
4
2.00 X
50%
8
2.83 X
R2/1.83
R2/2
35%
9
3.00 X
33%
16
4.00 X
R2/3
25%
The above table shows how to calculate the fastlock resistor and theoretical lock time improvement, once the
ratio, K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, it is generally
recommended that the loop filter order be one greater than the order of the delta sigma modulator, which means
that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it
would be for a second order filter. Because the fastlock disengagement glitch gets larger and it is harder to keep
the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but
not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation
tools, or trial and error.
Capacitor Dielectric Considerations for Lock Time
The LMX2487 has a high fractional modulus and high charge pump gain for the lowest possible phase noise.
One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop
filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor
dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock
times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general
tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor
dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances,
allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase
noise and spurs.
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FRACTIONAL SPUR AND PHASE NOISE CONTROLS
Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be
made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at
increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than
the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional
spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The
bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order.
The first step to do is choose FM, for the delta sigma modulator order. It is recommended to start with FM = 3 for
a third order modulator and use strong dithering. In general, there is a trade-off between primary and sub-
fractional spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary
fractional spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order),
typically gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd
order modulator can be a compromise.
The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs,
but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or
even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but
the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best).
Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them
completely, but adds the most phase noise. Weak dithering (DITH = 1) can be a compromise.
The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same,
expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the
fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional
denominator as large as possible, not exceeding 4095. It is not necessary to use the extended fractional
numerator or denominator.
NOTE
For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction,
Fastlock, and many other topics, visit http://www.ti.com. The EasyPLL simulation tool and
an online reference called "PLL Performance, Simulation, and Design", by Dean Banerjee,
are available.
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Programming Description
GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program
the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data
register is shown below. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data
stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is shifted
in MSB first. Note that it is best to program the N counter last, since doing so initializes the digital lock detector
and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT program values into
these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program the
R7 register.
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4
3
2
1
0
Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are
mapped to the target control register.
C3
x
C2
x
C1
x
C0
0
DATA Location
R0
R1
R2
R3
R4
R5
R6
R7
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
Control Register Content Map
Because the LMX2487 registers are complicated, they are organized into two groups, basic and advanced. The
first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The
last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page
shows these registers.
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Quick Start Register Map
Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2487, the quick start register map is shown in order for the user to get the part up and
running quickly using only those bits critical for basic functionality. The following default conditions for this programming state are a third order delta-sigma modulator in 12-bit mode with no
dithering and no Fastlock.
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C0
0
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
C3
C2
C1
R0
R1
RF_N[10:0]
RF_FN[11:0]
RF_
PD
RF_P
RF_R[5:0]
RF_FD[11:0]
IF_R[11:0]
0
0
1
1
R2
R3
R4
IF_PD
IF_N[18:0]
0
0
1
1
1
0
0
1
0
1
1
1
0001
RF_CPG[3:0]
0
0
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
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Complete Register Map
The complete register map shows all the functionality of all registers, including the last five.
REGIS
TER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
C3
C2
C1
C0
0
R0
R1
R2
R3
R4
RF_N[10:0]
RF_FN[11:0]
RF_PD
IF_PD
RF_P
RF_R[5:0]
RF_FD[11:0]
IF_R[11:0]
0
0
0
1
0
1
1
0
1
0
1
0
1
IF_N[18:0]
1
ACCESS[3:0]
RF_CPG[3:0]
0
1
ATPU
0
1
0
0
DITH
[1:0]
FM
[1:0]
0
OSC
_2X
OSC
_OUT
IF_
RF_
CPP
IF_P
MUX
[3:0]
1
CPP
R5
R6
R7
RF_FD[21:12]
RF_CPF[3:0]
RF_FN[21:12]
1
1
1
0
1
1
1
0
1
1
1
1
CSR[1:0]
RF_TOC[13:0]
0
0
0
0
0
0
0
0
0
0
DIV4
0
1
0
0
1
IF_
RST
RF_
RST
IF_
CPT
RF_
CPT
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R0 REGISTER
Note that this register has only one control bit, so the N counter value to be changed with a single write
statement to the PLL.
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C0
0
REGISTER
R0
DATA[22:0]
RF_N[10:0]
RF_FN[11:0]
RF_FN[11:0] – Fractional Numerator for RF PLL
Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] } for a more detailed
description of this control word.
RF_N[10:0] – RF N Counter Value
The RF N counter contains an 16/17/20/21 and a 32/33/36/37 prescaler. The N counter value can be calculated
as follows:
N = RF_P·RF_C + 4·RF_B + RF_A
RF_C ≥Max{RF_A, RF_B} , for N-2FM-1 ... N+2FM is a necessary condition. This rule is slightly modified in the
case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for
the purposes of modulation. Consult Table 1 and Table 2 for valid operating ranges for each prescaler.
Table 1. Operation with the 16/17/20/21 Prescaler (RF_P=0)
RF_N [10:0]
RF_N
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
<49
N Values Below 49 are Illegal.
Legal Divide Ratios are:
2nd Order Modulator: 49-61
3rd Order Modulator: 51-59
4th Order Modulator: 55
49-63
Legal Divide Ratios are:
2nd and 3rd Order Modulator: All
4th Order Modulator: 64-75
64-79
80
...
0
.
0
.
0
1
.
0
.
1
.
0
0
0
0
.
0
.
0
0
.
.
.
1023
>1023
1
1
1
1
1
1
1
1
1
1
N values above 1023 are prohibited.
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Table 2. Operation with the 32/33/36/37 Prescaler (RF_P=1)
RF_N [10:0]
RF_N
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
<97
N Values Below 97 are Illegal.
Legal Divide Ratios are:
2nd Order Modulator: 97-109, 129-145, 161-181, 193-217, 225-226
3rd Order Modulator: 99-107, 131-143, 163-179, 195-215
4th Order Modulator: 103, 135-139, 167-175, 199-211
97-226
Legal Divide Ratios are:
2nd and 3rd Order Modulator: All
4th Order Modulator: None
227–230
231
...
0
.
0
.
0
.
1
.
1
.
1
.
0
.
0
.
1
.
1
1
.
.
2039
1
1
1
1
1
1
1
0
1
1
1
2040-2043
2044-2045
>2045
Possible with a second or third order delta-sigma engine.
Possible only with a second order delta-sigma engine.
N values greater than 2045 are prohibited.
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R1 REGISTER
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3
C2
C1
C0
RF_ RF_
PD
R1
RF_R[5:0]
RF_FD[11:0]
0
0
1
1
P
RF_FD[11:0] – RF PLL Fractional Denominator
The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0],
ACCESS[1]}.
RF_R [5:0] – RF R Divider Value
The RF R Counter value is determined by this control word. Note that this counter does allow values down to
one.
R Value
RF_R[5:0]
1
0
.
0
.
0
.
0
.
0
.
1
.
...
63
1
1
1
1
1
1
RF_P – RF Prescaler bit
The prescaler used is determined by this bit.
RF_P
Prescaler
Maximum Frequency
4000 MHz
0
1
16/17/20/21
32/33/36/37
6000 MHz
RF_PD – RF Power Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and
the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions,
and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL
will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so,
regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit
then takes control of the power down function for the RF PLL.
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R2 REGISTER
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3
C2
C1
C0
R2
IF_
PD
IF_N[18:0]
0
1
0
1
IF_N[18:0] – IF N Divider Value
Table 3. IF_N Counter Programming with the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
N Value
IF_B
IF_A
≤23
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
24-55
56
57
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
0
0
.
0
0
.
0
0
1
.
0
.
...
262143
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Table 4. Operation with the 16/17 Prescaler (IF_P=1)
N Value
IF_B
IF_A
≤47
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
48-239
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
240
241
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
1
1
.
0
0
.
0
0
.
0
0
.
0
1
.
...
524287
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IF_PD – IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the
output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written
to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be
powered down, overriding the IF_PD bit.
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R3 REGISTER
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
C3
0
2
C2
1
1
C1
1
0
C0
1
DATA[19:0]
R3
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
IF_R[11:0] – IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for
IF_R is 3.
R Value
IF_R[11:0]
3
...
0
.
0
.
0
.
0
.
0
.
0
0
.
0
.
0
.
0
.
1
.
1
.
.
4095
1
1
1
1
1
1
1
1
1
1
1
1
RF_CPG – RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady state operation.
Typical RF Charge Pump Current
at 3 Volts (µA)
RF_CPG
Charge Pump State
0
1
1X
2X
95
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
11X
12X
13X
14X
15X
16X
950
10
11
12
13
14
15
1045
1140
1235
1330
1425
1520
ACCESS – Register Access word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional.
The ACCESS[3:0] bits determine which additional registers need to be programmed. Any one of these registers
can be individually programmed. According to the table below, when the state of a register is in default mode, all
the bits in that register are forced to a default state and it is not necessary to program this register. When the
register is programmable, it needs to be programmed through the MICROWIRE. Using this register access
technique, the programming required is reduced up to 37%.
ACCESS Bit
ACCESS[0]
ACCESS[1]
ACCESS[2]
ACCESS[3]
Register Location
R3[20]
Register Controlled
Must be set to 1
R3[21]
R5
R6
R7
R3[22]
R3[23]
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The default conditions the registers is shown below:
Register
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data[19:0]
R4 Must be programmed manually.
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R4
R5
R6
R7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
This corresponds to the following bit settings.
Register
Bit Location
R4[23]
Bit Name
ATPU
Bit Description
Autopowerup
Dithering
Bit Value
Bit State
Disabled
Strong
0
2
3
0
0
R4[17:16]
R4[15:16]
R4[23]
DITH
FM
Modulator Order
3rd Order
Disabled
Disabled
OSC_2X
OSC_OUT
Oscillator Doubler
OSCout Pin Enable
R4[23]
R4
IF Charge Pump
Polarity
R4[23]
R4[23]
IF_CPP
1
1
Positive
Positive
RF Charge Pump
Polarity
RF_CPP
R4[23]
R4[7:4]
IF_P
MUX
IF PLL Prescaler
Ftest/LD Output
1
0
16/17
Disabled
Extended Fractional
Denominator
R5[23:14]
RF_FD[21:12]
0
Disabled
R5
R6
Extended Fractional
Numerator
R5[13:4]
R6[23:22]
R6[21:18]
R6[17:4]
R7[13]
RF_FN[21:12]
CSR
0
0
0
0
0
0
0
Disabled
Disabled
Disabled
Cycle Slip Reduction
Fastlock Charge
Pump Current
RF_CPF
RF_TOC
DIV4
RF Timeout Counter
Disabled
Disabled
(Fcomp ≤ 20 MHz)
Lock Detect
Adjustment
R7[7]
IF_RST
RF_RST
IF PLL Counter Reset
Disabled
R7
RF PLL Counter
Reset
R7[6]
Disabled
R7[5]
R7[4]
IF_CPT
IF PLL Tri-State
RF PLL Tri-State
0
0
Disabled
Disabled
RF_CPT
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R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REG
ISTE
R
23
22
0
21
20
19
18
17
16
15
14
DATA[19:0]
FM
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3
C2
C1
C0
DITH
[1:0]
OSC
_2X
OSC
IF_
RF_
MUX
[3:0]
R4
ATPU
1
0
0
0
0
IF_P
1
0
0
1
[1:0]
_OUT CPP CPP
MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
High Impedance
Push-Pull
Output Description
0
0
0
0
0
0
0
1
Disabled
General purpose output, Logical “High”
State
0
0
1
0
Push-Pull
General purpose output, Logical “Low”
State
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Push-Pull
Push-Pull
Push-Pull
Open Drain
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
RF & IF Digital Lock Detect
RF Digital Lock Detect
IF Digital Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
RF & IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
IF R Divider divided by 2
IF N Divider divided by 2
RF R Divider divided by 2
RF N Divider divided by 2
IF_P – IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
IF_P
IF Prescaler
8/9
Maximum Frequency
800 MHz
0
1
16/17
800 MHz
RF_CPP – RF PLL Charge Pump Polarity
RF_CPP
RF Charge Pump Polarity
0
1
Negative
Positive (Default)
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IF_CPP – IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a
negative phase detector polarity.
IF_CPP
IF Charge Pump Polarity
Negative
0
1
Positive
OSC_OUT Oscillator Output Buffer Enable
OSC_OUT
OSCout Pin
0
1
Disabled (High Impedance)
Buffered output of OSCin pin
OSC2X – Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF
R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency
presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.
OSC2X
Frequency Presented to RF R Counter
Frequency Presented to IF R Counter
0
1
fOSCin
fOSCin
2 x fOSCin
FM[1:0] – Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels
closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the
loop filter should be at least one greater than the order of the delta-sigma modulator in order to allow for
sufficient roll-off.
FM
0
Function
Fractional PLL mode with a 4th order delta-sigma modulator
Disable the delta-sigma modulator. Recommended for test use only.
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
1
2
3
DITH[1:0] – Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional
spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific.
Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero,
dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often
occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends
not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is
decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.
DITH
Dithering Mode Used
Disabled
0
1
2
3
Weak Dithering
Strong Dithering
Reserved
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ATPU – PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0
register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case
is when the CE pin is low. In this case, the ATPU function is disabled.
R5 REGISTER
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
C3
1
2
C2
0
1
C1
1
0
C0
1
DATA[19:0]
R5
RF_FD[21:12]
RF_FN[21:12]
Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] }
In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12]
bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the
fractional numerator is expanded from 12 to 22-bits.
Fractional
RF_FN[21:12]
RF_FN[11:0]
Numerator
( These bits only apply in 22- bit mode)
0
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
In 12- bit mode, these are do not care.
In 22- bit mode, for N <4096,
...
these bits should be all set to 0.
4095
4096
...
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], ACCESS[1]}
In the case that the ACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the
RF_FD[21:12] bits become do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode
and the fractional denominator is expanded from 12 to 22-bits.
Fractional
RF_FD[21:12]
RF_FD[11:0]
Denominator
( These bits only apply in 22- bit mode)
0
1
In 12- bit mode, these are do not care.
In 22- bit mode, for N <4096,
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
these bits should be all set to 0.
...
4095
4096
...
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
38
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R6 REGISTER
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
C3
1
2
C2
1
1
C1
0
0
C0
1
DATA[19:0]
R6
CSR[1:0]
RF_CPF[3:0]
RF_TOC[13:0]
RF_TOC – RF Time Out Counter and Control for FLoutRF Pin
The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the
FLoutRF output pin. When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and
the FLoutRF pin operates as a general purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value
between 4 and 16383, the RF Fastlock mode is enabled and the FLoutRF pin is utilized as the RF Fastlock
output pin. The value programmed into the RF_TOC[13:0] word represents two times the number of phase
detector comparison cycles the RF synthesizer will spend in the Fastlock state.
RF_TOC
Fastlock Mode
Disabled
Fastlock Period [CP events]
FLoutRF Pin Functionality
0
1
N/A
N/A
High Impedance
Manual
Logic “0” State.
Forces all Fastlock conditions
2
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
N/A
N/A
Logic “0” State
Logic “1” State
Fastlock
3
4
4X2 = 8
5X2 = 10
…
5
Fastlock
…
Fastlock
16383
16383X2 = 32766
Fastlock
RF_CPF – RF PLL Fastlock Charge Pump Current
Specify the charge pump current for the Fastlock operation mode for the RF PLL. Note that the Fastlock charge
pump current, steady state current, and CSR control are all interrelated.
Typical RF Charge Pump Current
RF_CPF
RF Charge Pump State
at 3 Volts (µA)
0
1
1X
2X
95
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
11X
12X
13X
14X
15X
16X
950
10
11
12
13
14
15
1045
1140
1235
1330
1425
1520
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CSR[1:0] – RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence
of phase detector cycle slips. Note that the Fastlock charge pump current, steady state current, and CSR control
are all interrelated. Refer to CYCLE SLIP REDUCTION AND FASTLOCK for information on how to use this.
CSR
CSR State
Disabled
Enabled
Enabled
Enabled
Sample Rate Reduction Factor
0
1
2
3
1
1/2
1/4
1/16
R7 REGISTER
REG
ISTE
R
23
22
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
13
12
0
11
10
0
9
0
8
0
7
6
5
4
3
2
1
0
Data[19:0]
C3
C2
C1
C0
IF_
RF_
IF_
RF_
R7
0
0
0
DIV4
1
1
1
1
1
RST RST CPT CPT
DIV4 – RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked
condition for larger comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison
frequency (it does not apply to the IF comparison frequency) presented to the digital lock detect circuitry by 4.
This enables this circuitry to work at higher comparison frequencies. It is recommended that this bit be enabled
whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is being used.
IF_RST – IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a Tri-State
condition. This feature should be disabled for normal operation. Note that a counter reset is applied whenever the
chip is powered up via software or CE pin.
IF_RST
0 (Default)
1
IF PLL N and R Counters
Normal Operation
IF PLL Charge Pump
Normal Operation
Tri-State
Counter Reset
RF_RST – RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a Tri-State
condition. This feature should be disabled for normal operation. This feature should be disabled for normal
operation. Note that a counter reset is applied whenever the chip is powered up via software or CE pin.
RF_RST
0 (Default)
1
RF PLL N and R Counters
Normal Operation
RF PLL Charge Pump
Normal Operation
Tri-State
Counter Reset
RF_TRI – RF Charge Pump Tri-State
When this bit is enabled, the RF PLL charge pump is put in a Tri-State condition, but the counters are not reset.
This feature is typically disabled for normal operation.
RF_TRI
0 (Default)
1
RF PLL N and R Counters
Normal Operation
RF PLL Charge Pump
Normal Operation
Tri-State
Normal Operation
40
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
IF_TRI – IF Charge Pump Tri-State
When this bit is enabled, the IF PLL charge pump is put in a Tri-State condition, but the counters are not reset.
This feature is typically disabled for normal operation.
IF_TRI
0 (Default)
1
IF PLL N and R Counters
Normal Operation
IF PLL Charge Pump
Normal Operation
Tri-State
Normal Operation
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SNAS322B –FEBRUARY 2006–REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 41
42
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMX2487SQ/NOPB
LMX2487SQX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WQFN
WQFN
RTW
24
24
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-3-260C-168 HR
L2487SQ
L2487SQ
ACTIVE
RTW
4500
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX2487SQ/NOPB
LMX2487SQX/NOPB
WQFN
WQFN
RTW
RTW
24
24
1000
4500
178.0
330.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMX2487SQ/NOPB
LMX2487SQX/NOPB
WQFN
WQFN
RTW
RTW
24
24
1000
4500
213.0
367.0
191.0
367.0
55.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
www.ti.com
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