LM96000CIMT/NOPB [NSC]
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24, MO-153AD, TSSOP-24, Power Management Circuit;
| 型号： | LM96000CIMT/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24, MO-153AD, TSSOP-24, Power Management Circuit 光电二极管 |
| 文件： | 总32页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 23, 2008
LM96000
Hardware Monitor with Integrated Fan Control
Noise filtering of temperature reading for fan control
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General Description
1.0°C digital temperature sensor resolution
3 PWM fan speed control outputs
The LM96000, hardware monitor, has a two wire digital inter-
face compatible with SMBus 2.0. Using an 8-bit ΣΔ ADC, the
LM96000 measures:
Provides high and low PWM frequency ranges
4 fan tachometer inputs
– the temperature of two remote diode connected transis-
tors as well as its own die
Monitors 5 VID control lines
24-pin TSSOP package
– the VCCP, 2.5V, 3.3VSBY, 5.0V, and 12V supplies (in-
ternal scaling resistors).
XOR-tree test mode
To set fan speed, the LM96000 has three PWM outputs that
are each controlled by one of three temperature zones. High
and low PWM frequency ranges are supported. The LM96000
includes a digital filter that can be invoked to smooth temper-
ature readings for better control of fan speed. The LM96000
has four tachometer inputs to measure fan speed. Limit and
status registers for all measured values are included.
Key Specifications
Voltage Measurement Accuracy
±2% FS (max)
8-bits, 1°C
■
Resolution
■
Temperature Sensor Accuracy
±3°C (max)
■
Temperature Range
■
LM96000 Operational
Remote Temp Accuracy
Power Supply Voltage
Power Supply Current
0°C to +85°C
0°C to +125°C
+3.0V to +3.6V
0.53 mA
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—
Features
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2-wire, SMBus 2.0 compliant, serial digital interface
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8-bit ΣΔ ADC
Monitors VCCP, 2.5V, 3.3 VSBY, 5.0V, and 12V
motherboard/processor supplies
Applications
Monitors 2 remote thermal diodes
Desktop PC
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Programmable autonomous fan control based on
temperature readings
Microprocessor based equipment
(e.g. Base-stations, Routers, ATMs, Point of Sales)
Block Diagram
20084601
© 2008 National Semiconductor Corporation
200846
www.national.com
Connection Diagram
24 Pin TSSOP
20084602
NS Package MTC24E
Top View
LM96000CIMT (61 units per rail), or
LM96000CIMTX (2500 units per tape and reel)
Pin Descriptions
Symbol
Pin
Type
Name and Function/Connection
SMBDAT
1
Digital I/O
(Open-Drain)
System Management Bus Data. Open-drain output. 5V tolerant,
SMBus 2.0 compliant.
SMBus
SMBCLK
2
5
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
POWER
System Management Bus Clock. Tied to Open-drain output. 5V
tolerant, SMBus 2.0 compliant.
VID0
VID1
Voltage identification signal from the processor. This value is read in
the VID0–VID4 Status Register.
6
Voltage identification signal from the processor. This value is read in
the VID0–VID4 Status Register.
Processor
VID Lines
VID2
VID3
VID4
3.3V
7
Voltage identification signal from the processor. This value is read in
the VID0–VID4 Status Register.
8
Voltage identification signal from the processor. This value is read in
the VID0–VID4 Status Register.
19
4
Voltage identification signal from the processor. This value is read in
the VID0–VID4 Status Register.
+3.3V pin. Can be powered by +3.3V Standby power if monitoring in
low power states is required. This pin also serves as the analog input
to monitor the 3.3V supply. This pin should be bypassed with a 0.1µf
capacitor in parallel with 100pf. A bulk capacitance of approximately
10µf needs to be in the near vicinity of the LM96000.
Power
GND
5V
3
GROUND
Analog Input
Analog Input
Analog Input
Analog Input
Ground for all analog and digital circuitry.
Analog input for +5V monitoring.
20
21
22
23
12V
Analog input for +12V monitoring.
Voltage
Inputs
2.5V
Analog input for +2.5V monitoring.
VCCP_IN
Analog input for VCCP (processor voltage) monitoring.
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2
Symbol
Pin
Type
Name and Function/Connection
Remote1+
18
Remote Thermal Positive input (current source) from the first remote thermal diode.
Diode Positive
Input
Serves as the positive input into the A/D. Connected to THERMDA
pin of Pentium processor or the base of a diode connected
MMBT3904 NPN transistor.
Remote1−
Remote2+
Remote2−
17
16
15
Remote Thermal Negative input (current sink) from the first remote thermal diode.
Diode Negative Serves as the negative input into the A/D. Connected to THERMDC
Input
pin of Pentium processor or the emmiter of a diode connected
MMBT3904 NPN transistor.
Remote
Diodes
Remote Thermal Positive input (current source) from the first remote thermal diode.
Diode Positive
Output
Serves as the positive input into the A/D. Connected to THERMDA
pin of Pentium processor or the base of a diode connected
MMBT3904 NPN transistor.
Remote Thermal Negative input (current sink) from the first remote thermal diode.
Diode Negative Serves as the negative input into the A/D. Connected to THERMDC
Input
pin of Pentium processor or the emmiter of a diode connected
MMBT3904 NPN transistor.
TACH1
TACH2
TACH3
11
12
9
Digital Input
Digital Input
Digital Input
Digital Input
Input for monitoring tachometer output of fan 1.
Input for monitoring tachometer output of fan 2.
Input for monitoring tachometer output of fan 3.
Fan
Tachometer
Inputs
TACH4/Address
Select
14
Input for monitoring tachometer output of fan 4. If in Address Select
Mode, determines the SMBus address of the LM96000.
PWM1/xTest Out
24
10
13
Digital Open-Drain Fan speed control 1. When in XOR tree test mode, functions as XOR
Output Tree output.
PWM2
Digital Open-Drain Fan speed control 2.
Output
Fan Control
PWM3/Address
Enable
Digital Open-Drain Fan speed control 3. Pull to ground at power on to enable Address
Output
Select Mode (Address Select pin controls SMBus address of the
device).
3
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Storage Temperature
−65°C to +150°C
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Soldering process must comply with National's reflow
temperature profile specifications. Refer to
www.national.com/packaging/. (Note 6)
Supply Voltage, V+
Voltage on Any Digital Input or
Output Pin
−0.5V to 6.0V
−0.5V to 6.0V
Operating Ratings (Notes 1, 2)
LM96000 Operating Temperature
0°C ≤ TA ≤ +85°C
Range
Voltage on 12V Analog Input
Voltage on 5V Analog Input
Voltage on Remote1+, Remote2+,
Current on Remote1−, Remote2−
Voltage on Other Analog Inputs
Input Current on Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at TA = 25°C
ESD Susceptibility (Note 4)
Human Body Model
−0.5V to 16V
−0.5V to 6.66V
−0.5V to (V+ + 0.05V)
±1 mA
Remote Diode Temperature Range
0°C ≤ TD ≤ +125°C
Supply Voltage (3.3V nominal)
VIN Voltage Range
+12V VIN
+3.0V to +3.6V
−0.05V to 16V
−0.05V to 6.66V
3.0V to 4.4V
−0.5V to 6.0V
±5 mA
±20 mA
See (Note 5)
+5V VIN
+3.3V VIN
VCCP_IN and All Other Inputs
VID0–VID4
Typical Supply Current
−0.05V to (V+ + 0.05V)
−0.05V to 5.5V
0.53 mA
2500V
250V
Machine Model
DC Electrical Characteristics
The following specifications apply for V+ = 3.0V to 3.6V, and all analog input source impedance RS = 50Ω unless otherwise specified
in conditions. Boldface limits apply for TA = TJ over TMIN =0°C to TMAX=85°C; all other limits TA =TJ= 25°C. TA is the ambient
temperature of the LM96000; TJ is the junction temperature of the LM96000; TD is the thermal diode junction temperature.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Limits)
(Note 7)
(Note 8)
POWER SUPPLY CHARACTERISTICS
Supply Current (Note 9)
Converting, Interface and
Fans Inactive, Peak Current
1.8
3.5
mA (max)
mA
Converting, Interface and
Fans Inactive, Average
Current
0.53
Power-On Reset Threshold Voltage
1.6
2.8
V (min)
V (max)
TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS
Resolution
1
8
°C
Bits
Temperature Accuracy (See (Note 10) for Thermal TD=25°C
Diode Processor Type)
±2.5
±3
°C (max)
°C (max)
°C (max)
°C (max)
TD=0°C to 100°C
±1
±1
TD=100°C to 125°C
±4
Temperature Accuracy using Internal Diode (Note
11)
±3
IDS
External Diode Current Source
High Level
Low Level
188
11.75
16
280
µA (max)
µA
External Diode Current Ratio
ANALOG TO DIGITAL CONVERTER CHARACTERISTICS
TUE
DNL
Total Unadjusted Error(Note 12)
Differential Non-linearity
±2
%FS (max)
LSB
1
Power Supply Sensitivity
±1
%/V
Total Monitoring Cycle Time (Note 13)
All Voltage and Temperature
readings
182
200
ms (max)
Input Resistance, all analog inputs
210
140
400
kΩ (min)
kΩ (max)
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4
Symbol
Parameter
Conditions
Typical
Limits
Units
(Limits)
(Note 7)
(Note 8)
DIGITAL OUTPUT: PWM1, PWM2, PWM3, XTESTOUT
IOL
Logic Low Sink Current
Logic Low Level
VOL=0.4V
8
mA (min)
V (max)
VOL
IOUT = +8 mA
0.4
SMBUS OPEN-DRAIN OUTPUT: SMBDAT
VOL
IOH
Logic Low Output Voltage
High Level Output Current
IOUT = +4 mA
VOUT = V+
0.4V
10
V (max)
0.1
µA (max)
SMBUS INPUTS: SMBCLK. SMBDAT
VIH
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Hysteresis Voltage
2.1
0.8
V (min)
V (max)
mV
VIL
VHYST
300
DIGITAL INPUTS: ALL
VIH
VIL
VTH
IIH
Logic Input High Voltage
2.1
0.8
V (min)
V (max)
V
Logic Input Low Voltage
Logic Input Threshold Voltage
Logic High Input Current
Logic Low Input Current
Digital Input Capacitance
1.5
0.005
−0.005
20
VIN = V+
10
µA (max)
µA (max)
pF
IIL
VIN = GND
−10
CIN
AC Electrical Characteristics
The following specifications apply for V+ = 3.0V to 3.6V unless otherwise specified in conditions. Boldface limits apply for TA
TJ over TMIN =0°C to TMAX=85°C; all other limits TA =TJ= 25°C.
=
Symbol
Parameter
Conditions
Typical
Limits
Units
(Limits)
(Note 7)
(Note 8)
TACHOMETER ACCURACY
Fan Count Accuracy
±10
% (max)
(max)
Fan Full-Scale Count
65536
Fan Counter Clock Frequency
Fan Count Conversion Time
90
kHz
0.7
1.4
sec (max)
FAN PWM OUTPUT
Frequency Setting Accuracy
Frequency Range
±10
% (max)
10
30
Hz
kHz
Duty-Cycle Range
Low frequency range
0 to 100
% (max)
%
Duty-Cycle Resolution (8-bits)
Spin-Up Time Interval Range
0.390625
100
4000
ms
ms
Spin-Up Time Interval Accuracy
±10
±10
% (max)
SPIKE SMOOTHING FILTER
Time Interval Deviation
Time Interval Range
% (max)
35
0.8
sec
sec
SMBUS TIMING CHARACTERISTICS
fSMB
SMBus Operating Frequency
10
100
kHz (min)
kHz (max)
fBUF
SMBus Free Time Between Stop And
Start Condition
4.7
4.0
µs (min)
tHD_STA
Hold Time After (Repeated) Start
Condition (after this period, the first clock
is generated)
µs (min)
5
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Symbol
Parameter
Conditions
Typical
Limits
Units
(Limits)
(Note 7)
(Note 8)
tSU:STA
tSU:STO
tHD:DAT
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Output Hold Time
4.7
4.0
µs (min)
µs (min)
ns (min)
ns (max)
ns (min)
300
930
250
tSU:DAT
Data Input Setup Time
tTIMEOUT
Data And Clock Low Time To Reset Of
SMBus Interface Logic(Note 14)
25
35
ms (min)
ms (max)
tLOW
tHIGH
Clock Low Period
Clock High Period
4.7
µs (min)
4.0
50
µs (min)
µs (max)
tF
Clock/Data Fall Time
Clock/Data Rise Time
300
1000
500
ns (max)
ns (max)
ms (max)
tR
tPOR
Time from Power-On-Reset to LM96000 V+ > 2.8V
Reset and Operational
20084603
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise noted.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN >V+ ), the current at that pin should be limited to 5mA. The 20mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four. Parasitic
components and/or ESD protection circuitry are shown below for the LM96000's pins. The nominal breakdown voltage the zener is 6.5V. Care should be taken
not to forward bias the parasitic diode D1 present on pins D+ and D−. Doing so by more that 50 mV may corrupt temperature measurements. SNP stands for
snap-back device.
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6
Pin #
Pin Name
SMBDAT
SMBCLK
GND
Circuit
All Input Circuits
1
2
3
4
A
B
3.3V
5
6
7
8
9
VID0
VID1
A
VID2
VID3
TACH3
10
11
12
13
14
PWM2
TACH1
TACH2
PWM3/AddEnable
TACH4/AddSel
15
16
17
18
19
REMOTE2−
REMOTE2+
REMOTE1−
REMOTE1+
VID4
C
D
C
D
A
20
21
22
23
24
5V
12V
E
A
2.5V
VCCP_IN
PWM1/xTEXTOUT
Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Machine model, 200pF discharged directly into each pin.
Note 5: Thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1 oz. foil is 113 °C/W.
Note 6: Reflow temperature profiles are different for packages containing lead (Pb) than for those that do not.
Note 7: Typicals are at TA = 25°C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 9: The average current can be calculated from the peak current using the following equation:
Quiescent current will not increase substantially with an SMBus transaction.
Note 10: The accuracy of the LM96000CIMT is guaranteed when using the thermal diode of Intel Pentium 4 90nm processors or any thermal diode with a non-
ideality of 1.011 and series resistance of 3.33Ω. When using a 2N3904 type transistor as a thermal diode the error band will be typically shifted by -?°C.
Note 11: Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power
dissipation of the LM96000 and the thermal resistance. See (Note 5) for the thermal resistance to be used in the self-heating calculation.
Note 12: TUE , total unadjusted error, includes ADC gain, offset, linearity and reference errors. TUE is defined as the "actual Vin" to achieve a given code transition
minus the "theoretical Vin" for the same code. Therefore, a positive error indicates that the input voltage is greater than the theoretical input voltage for a given
code. If the theoretical input voltage was applied to an LM96000 that has positive error, the LM96000's reading would be less than the theoretical.
Note 13: This specification is provided only to indicate how often temperature and voltage data is updated. The LM96000 can be read at any time without regard
to conversion state (and will yield last conversion result).
Note 14: Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM96000's SMBus state machine, therefore setting
the SMBDAT pin to a high impedance state.
7
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During the first SMBus communication TACH4 and PWM3
can be used to change the SMBus address of the LM96000
to 0101101b or 0101100b. LM96000 address selection pro-
cedure:
Functional Description
1.0 SMBUS
The LM96000 is compatible with devices that are compliant
to the SMBus 2.0 specification. More information on this bus
can be found at: http://www.smbus.org/. Compatibility of SM-
Bus2.0 to other buses is discussed in the SMBus 2.0 speci-
fication.
A 10 kΩ pull-down resistor to ground on the PWM3/
Address Enable pin is required. Upon power up, the
LM96000 will be placed into Address Enable mode and
assign itself an SMBus address according to the state of
the Address Select input. The LM96000 will latch the
address during the first valid SMBus transaction in which
the first five bits of the targeted address match those of the
LM96000 address, 0 1011b. This feature eliminates the
possibility of a glitch on the SMBus interfering with address
selection. When the PWM3/Address Enable pin is not
used to change the SMBus address of the LM96000, it will
remain in a high state until the first communication with the
LM96000. After the first SMBus transaction is completed
PWM3 and TACH4 will return to normal operation.
1.1 Addressing
LM96000 is designed to be used primarily in desktop systems
that require only one monitoring device.
If only one LM96000 is used on the motherboard, the designer
should be sure that the PWM3/Address Enable pin is High
during the first SMBus communication addressing the
LM96000. PWM3/Address Enable is an open drain I/O pin
that at power-on defaults to the input state of Address En-
able. A maximum of 10k pull-up resistance on PWM3/Ad-
dress Enable is required to assure that the SMBus address
of the device will be locked at 010 1110b, which is the default
address of the LM96000.
Address Enable
Address Select
Board Implementation
SMBus Address
0
0
1
0
1
X
010 1100b, 2Ch
010 1101b, 2Dh
010 1110b, 2Eh
Pulled to ground through a 10 kΩ resistor
Pulled to 3.3V or to GND through a 10 kΩ resistor
Pulled to 3.3V through a 10 kΩ resistor
In this way, up to three LM96000 devices can exists on an
SMBus at any time. Multiple LM96000 devices can be used
to monitor additional processors and temperature zones.
When using the non-default addresses the TACH4 and
PWM3 will not function. As shown in the timing diagram the
Address Enable pin must remain low in order for the latched
address to remain in effect. If the address enable pin is pulled
high after the first SMBus communication, then the LM96000
SMBus address will revert to the default value (2Eh) after the
first five clocks of next SMBus communication.
20084604
Address Latch Enable low during and after first communication
20084610
Address Latch Enable high during first communication
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8
2.0 FAN REGISTER DEVICE SET-UP
– [6A-6Ch] Set the temperature absolute limits.
– [64-66h] Set the PWM minimum duty cycle.
– [6D-6Eh] Set the temperature Hysteresis values.
The BIOS will follow the following steps to configure the fan
registers on the LM96000. The registers corresponding to
each function are listed. All steps may not be necessary if
default values are acceptable. Regardless of all changes
made by the BIOS to the fan limit and parameter registers
during configuration, the LM96000 will continue to operate
based on default values until the START bit (bit 0), in the
Ready/Lock/Start/Override register (address 40h), is set.
Once the fan mode is updated, by setting the START bit to 1,
the LM96000 will operate using the values that were set by
the BIOS in the fan control limit and parameter registers
(adress 5Ch through 6Eh).
2. [40h] Set bit 0 (START) to update fan control and limit
register values and start fan control based on these new
values.
3. [40h] Set bit 1 (LOCK) to lock the fan limit and parameter
registers (optional).
3.0 AUTO FAN CONTROL OPERATING MODE
The LM96000 includes the circuitry for automatic fan control.
In Auto Fan Mode, the LM96000 will automatically adjust the
PWM duty cycle of the PWM outputs. PWM outputs are as-
signed to a thermal zone based on the fan configuration
registers. It is possible to have more than one PWM output
assigned to a thermal zone. For example, PWM outputs 2 and
3, connected to two chassis fans, may both be controlled by
thermal zone 2. At any time, the temperature of a zone ex-
ceeds its absolute limit, all PWM outputs will go to 100% duty
cycle to provide maximum cooling to the system.
1. Set limits and parameters (not necessarily in this order):
– [5F-61h] Set PWM frequencies and auto fan
control range.
– [62-63h] Set spike smoothing and min/off.
– [5C-5Eh] Set the fan spin-up delays.
– [5C-5Eh] Match each fan with a corresponding
thermal zone.
– [67-69h] Set the fan temperature limits.
9
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4.0 REGISTER SET
Register Read/ Register
Address Write Name
Bit 7 Bit 6 Bit 5 Bit 4
(MSB)
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default Lock?
Value
20h
21h
22h
23h
24h
25h
R
R
R
R
R
R
2.5V
7
7
7
7
7
7
6
6
6
6
6
6
5
5
5
5
5
5
4
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
VCCP_IN
3.3V
5V
12V
Processor (Zone1)
Temp
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
R
R
R
R
R
R
R
R
R
R
Internal (Zone2) Temp
Remote (Zone3) Temp
Tach1 LSB
7
7
6
6
5
5
4
4
3
3
2
2
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
0
7
6
5
4
3
2
LEVEL1
LEVEL0
Tach1 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
Tach2 LSB
LEVEL1
LEVEL0
Tach2 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
Tach3 LSB
LEVEL1
LEVEL0
Tach3 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
Tach4 LSB
LEVEL1
LEVEL0
Tach4 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
R/W Fan1 Current PWM
Duty
31h
32h
R/W Fan2 Current PWM
Duty
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
1
1
0
0
N/A
N/A
R/W Fan3 Current PWM
Duty
3Eh
3Fh
40h
R
R
Company ID
2
1
0
01h
68h
00h
Version/Stepping
VER3 VER2 VER1 VER0 STP3
STP2
STP1
LOCK
STP0
START
R/W Ready/Lock/Start/
Override
RES RES RES RES OVRID READY
41h
42h
R
R
R
Interrupt Status
Register 1
ERR ZN3
ZN2
ZN1
5V
3.3V
VCCP
RES
2.5V
12V
00h
00h
Interrupt Status
Register 2
ERR2 ERR1 FAN4 FAN3 FAN2
FAN1
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
VID0–4
RES RES RES VID4 VID3
VID2
VID1
VID0
N/A
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
81h
R/W 2.5V Low Limit
R/W 2.5V High Limit
R/W VCCP Low Limit
R/W VCCP High Limit
R/W 3.3V Low Limit
R/W 3.3V High Limit
R/W 5V Low Limit
R/W 5V High Limit
R/W 12V Low Limit
R/W 12V High Limit
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
R/W Processor (Zone1)
Low Temp
4Fh
50h
R/W Processor (Zone1)
High Temp
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
7Fh
81h
R/W Internal (Zone2) Low
Temp
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10
Register Read/ Register
Address Write Name
Bit 7 Bit 6 Bit 5 Bit 4
(MSB)
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default Lock?
Value
51h
52h
53h
R/W Internal (Zone2) High
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
7Fh
81h
7Fh
Temp
R/W Remote (Zone3) Low
Temp
R/W Remote (Zone3) High
Temp
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
R/W Tach1 Minimum LSB
R/W Tach1 Minimum MSB
R/W Tach2 Minimum LSB
R/W Tach2 Minimum MSB
R/W Tach3 Minimum LSB
R/W Tach3 Minimum MSB
R/W Tach4 Minimum LSB
R/W Tach4 Minimum MSB
R/W Fan1 Configuration
7
15
7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
0
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
9
8
1
0
15
7
14
6
13
5
12
4
11
3
10
2
9
8
1
0
15
7
14
6
13
5
12
4
11
3
10
2
9
8
1
9
0
8
15
14
13
12
11
RES
10
SPIN2
ZON2 ZON1 ZON0 INV
ZON2 ZON1 ZON0 INV
ZON2 ZON1 ZON0 INV
SPIN1
SPIN0
62h
✓
✓
✓
✓
5Dh
5Eh
5Fh
R/W Fan2 Configuration
R/W Fan3 Configuration
RES
RES
SPIN2
SPIN2
FRQ2
SPIN1
SPIN1
FRQ1
SPIN0
SPIN0
FRQ0
62h
62h
R/W Fan1 Range/
Frequency
RAN3 RAN2 RAN1 RAN0 HLFRQ
RAN3 RAN2 RAN1 RAN0 HLFRQ
RAN3 RAN2 RAN1 RAN0 HLFRQ
C4h
60h
61h
62h
63h
R/W Fan2 Range/
Frequency
FRQ2
FRQ2
ZN1-2
ZN3-2
FRQ1
FRQ1
ZN1-1
ZN3-1
FRQ0
FRQ0
ZN1-0
ZN3-0
C4h
✓
R/W Fan3 Range/
Frequency
C4h
✓
R/W Min/Off, Zone1 Spike OFF3 OFF2 OFF1 RES ZN1E
Smoothing
00H
✓
R/W Zone2, Zone3 Spike
Smoothing
ZN2E ZN2-2 ZN2-1 ZN2-0 ZN3E
00h
✓
64h
65h
66h
67h
68h
69h
6Ah
R/W Fan1 PWM Minimum
R/W Fan2 PWM Minimum
R/W Fan3 PWM Minimum
R/W Zone1 Fan Temp Limit
R/W Zone2 Fan Temp Limit
R/W Zone3 Fan Temp Limit
7
7
7
7
7
7
7
6
6
6
6
6
6
6
5
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
0
0
0
0
0
0
0
80h
✓
✓
✓
✓
✓
✓
✓
80h
80h
5Ah
5Ah
5Ah
R/W Zone1 Temp Absolute
Limit
64h
6Bh
6Ch
6Dh
R/W Zone2 Temp Absolute
Limit
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
64h
✓
R/W Zone3 Temp Absolute
Limit
64h
✓
R/W Zone1, Zone2
Hysteresis
H1-3 H1-2 H1-1 H1-0
H2-3
H2-2
H2-1
H2-0
44h
✓
6Eh
6Fh
R/W Zone3 Hysteresis
H3-3 H3-2 H3-1 H3-0
RES
RES
RES
RES
T2-0
RES
RES
T1-1
RES
XEN
T1-0
40h
✓
✓
R/W XOR Test Tree Enable RES RES RES RES
00h
74h
75h
R/W Tach Monitor Mode
R/W Fan Spin-up Mode
RES RES T3/4-1 T3/4-0 T2-1
RES RES RES RES
00h
RES PWM3 SU PWM2 SU PWM1 SU
7h
✓
Note: Reserved bits will always return 0 when read.
11
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4.1 Register 20-24h: Voltage Reading
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
20h
21h
22h
23h
24h
R
R
R
R
R
2.5V
VCCP
3.3V
5V
7
7
7
7
7
6
6
6
6
6
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
12V
The Register Names difine the typical input voltage at which the reading is ¾ full scale or C0h.
The Voltage Reading registers are updated automatically by the LM96000 at a minimum frequency of 4 Hz. These registers are
read only — a write to these registers has no effect.
4.2 Register 25-27h: Temperature Reading
Register
Address
Read/ Register
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default
Write
Name
(LSB) Value
25h
26h
27h
R
R
R
Processor (Zone1) Temp
Internal (Zone2) Temp
Remote (Zone3) Temp
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
N/A
N/A
N/A
The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Processor (Zone1) Temp
register reports the temperature measured by the thermal diode connected to the Remote1− and Remote1+ pins, Remote (Zone3)
Temp register reports the temperature measured by the thermal diode connected to the the Remote2− and Remote2+ pins, and
the Internal (Zone2) Temp register reports the temperature measured by the internal (junction) temperature sensor. Temperatures
are represented as 8 bit, 2’s complement, signed numbers, in Celsius, as shown below in Table 1. The Temperature Reading
register will return a value of 80h if the remote diode pins are not used by the board designer or are not functioning properly. This
reading will cause the zone limit bit(s) (bits 6 and 4) in the Interrupt Status Register (41h) and the remote diode fault status bit(s)
(bit 6 or 7) in the Interrupt Status Register 2 (42h) to be set. The Temperature Reading registers are updated automatically by the
LM96000 at a minimum frequency of 4 Hz. These registers are read only — a write to these registers has no effect.
TABLE 1. Temperature vs Register Reading
Temperature
Reading (Dec)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
80h
(SENSOR ERROR)
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12
4.3 Register 28-2Fh: Fan Tachometer Reading
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
28h
29h
R
R
Tach1 LSB
Tach1 MSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
2Ah
2Bh
R
R
Tach2 LSB
Tach2 MSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
2Ch
2Dh
R
R
Tach3 LSB
Tach3 MSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
2Eh
2Fh
R
R
Tach4 LSB
Tach4 MSB
7
15
6
14
5
13
4
12
3
11
2
10
LEVEL1
9
LEVEL0
8
N/A
N/A
The Fan Tachometer Reading registers contain the number of 11.111 µs periods (90 kHz) between full fan revolutions. The results
are based on the time interval of two tachometer pulses, since most fans produce two tachometer pulses per full revolution. These
registers will be updated at least once every second.
The value, for each fan, is represented by a 16-bit unsigned number.
The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled
or non-functional.
The least two significant bits (LEVEL1 and LEVEL2) of the least significant byte are used to indicate the accuracy level of the
tachometer reading. The accuracy ranges from most to least accurate. [LEVEL1:LEVEL2]=11indicates a most accurate value,
[LEVEL1:LEVEL2]=01 indicates the least accurate value and [LEVEL1:LEVEL2]=00 is reserved for future use.
FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. These registers are
read only — a write to these registers has no effect.
When the LSByte of the LM96000 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At
the end of the MSByte read the Fan Tachometer Reading registers are updated.
During spin-up, the PWM duty cycle reported is 0%.
13
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4.4 Register 30-32h: Current PWM Duty
Register
Address
Read/ Register
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default
Write
R/W
R/W
R/W
Name
(LSB) Value
30h
31h
32h
Fan1 Current PWM Duty
Fan2 Current PWM Duty
Fan3 Current PWM Duty
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
N/A
N/A
N/A
The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM duty cycle is 100%
and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register Start bit is set, this register and the
PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode section.
When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read only unless the fan is in
manual (test) mode, in which case a write to these registers will directly control the PWM duty cycle for each fan. The PWM duty
cycle is represented as shown in the following table.
Current Duty
0%
Value (Decimal)
Value (Hex)
00h
0
1
0.3922%
01h
.
.
.
.
.
.
.
.
.
25.098%
64
40h
.
.
.
.
.
.
.
.
.
50.196%
128
80h
.
.
.
.
.
.
.
.
.
100%
255
FFh
4.5 Register 3Eh: Company ID
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
3Eh
R
Company ID
7
6
5
4
3
2
1
0
01h
The company ID register contains the company identification number. For National Semiconductor this is 01h. This number is
assigned by Intel and is a method for uniquely identifying the part manufacturer. This register is read only — a write to this register
has no effect.
4.6 Register 3Fh: Version/Stepping
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
3Fh
R
Version/Stepping
VER3
VER2
VER1
VER0
STP3
STP2
STP1
STP0
68h
The four least significant bits of the Version/Stepping register [3.0] contain the current stepping of the LM96000 silicon. The four
most significant bits [7.4] reflect the LM96000 base device number when set to a value of 0110b. For the LM96000, this register
will read 01101000b (68h). Bit 3 of the stepping field is set to indicate that the LM96000 is a super-set of the LM85 family of products.
The register is used by application software to identify which device in the hardware monitor family of ASICs has been implemented
in the given system. Based on this information, software can determine which registers to read from and write to. Further, application
software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping.
This register is read only — a write to this register has no effect.
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14
4.7 Register 40h: Ready/Lock/Start/Override
Register Read/ Register
Address Write Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
40h
R/W
Ready/Lock/Start/Override
RES
RES RES RES OVRID READY LOCK START 00h
Bit
Name
R/W
Default
Description
0
START
R/W
0
When software writes a 1 to this bit, the LM96000 fan monitoring and PWM output
control functions will use the values set in the fan control limit and parameter registers
(address 5Ch through 6Eh). Before this bit is set, the LM96000 will not update the used
register values, the default values will remain in effect. Whenever this bit is set to 0, the
LM96000 fan monitoring and PWM output control functions use the default fan limits
and parameters, regardless of the current values in the limit and parameter registers
(5C through 6Eh). The LM96000 will preserve the values currently stored in the limit and
parameter registers when this bit is set or cleared. This bit is not effected by the state
of the Lock bit.
It is expected that all limit and parameter registers will be set by BIOS or application
software prior to setting this bit.
1
LOCK
R/W
0
0
Setting this bit to 1 locks specified limit and parameter registers. Once this bit is set, limit
and parameter registers become read only and will remain locked until the device is
powered off. This register bit becomes read only once it is set.
2
3
READY
OVRID
R
The LM96000 sets this bit automatically after the part is fully powered up, has completed
the power-up-reset process, and after all A/D converters are properly functioning.
R/W
If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of whether
or not the lock bit is set. The OVRID bit has precedence over the disabled mode.
Therefore, when OVRID is set the PWM will go to 100% even if the PWM is in the
disabled mode.
4–7
Reserved
R
0
Reserved
15
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4.8 Register 41h: Interrupt Status Register 1
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
41h
R
Interrupt Status 1
ERR
ZN3
ZN2
ZN1
5V
3.3V
VCCP
2.5V
00h
The Interrupt Status Register 1 bits will be automatically set, by the LM96000, whenever a fault condition is detected. A fault
condition is detected whenever a measured value is outside the window set by its limit registers. ZN3 and ZN1 bits will be set when
a diode fault condition, such as a disconect or short, is detected. More than one fault may be indicated in the interrupt register
when read. This register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to
0) automatically by the LM96000 after it is read by software, if the fault condition is no longer exists. Once set, the Interrupt Status
Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists
This register is read only — a write to this register has no effect.
Bit
Name
R/W
Default
Description
0
2.5V_Error
R
0
The LM96000 automatically sets this bit to 1 when the 2.5V input voltage is less
than or equal to the limit set in the 2.5V Low Limit register or greater than the limit
set in the 2.5V High Limit register.
1
2
3
4
VCCP_Error
3.3V_Error
5V_Error
R
R
R
R
0
0
0
0
The LM96000 automatically sets this bit to 1 when the VCCP input voltage is less
than or equal to the limit set in the VCCP Low Limit register or greater than the limit
set in the VCCP High Limit register.
The LM96000 automatically sets this bit to 1 when the 3.3V input voltage is less
than or equal to the limit set in the 3.3V Low Limit register or greater than the limit
set in the 3.3V High Limit register.
The LM96000 automatically sets this bit to 1 when the 5V input voltage is less than
or equal to the limit set in the 5V Low Limit register or greater than the limit set in
the 5V High Limit register.
Zone 1 Limit
Exceeded
The LM96000 automatically sets this bit to 1 when the temperature input measured
by the Remote1− and Remote1+ inputs is less than or equal to the limit set in the
Processor (Zone1) Low Temp register or more than the limit set in the Processor
(Zone1) High Temp register. This bit will be set when a diode fault is detected.
5
6
7
Zone 2 Limit
Exceeded
R
R
R
0
0
0
The LM96000 automatically sets this bit to 1 when the temperature input measured
by the internal temperature sensor is less than or equal to the limit set in the Internal
(Zone2) Low Temp register or greater than the limit set in the Internal (Zone2) High
Temp register.
Zone 3 Limit
Exceeded
The LM96000 automatically sets this bit to 1 when the temperature input measured
by the Remote2− and Remote2+ inputs is less than or equal to the limit set in the
Internal (Zone2) Low Temp register or greater than the limit set in the Remote
(Zone3) High Temp register. This bit will be set when a diode fault is detected.
Error in Status
Register 2
If there is a set bit in Status Register 2, this bit will be set to 1.
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16
4.9 Register 42h: Interrupt Status Register 2
Register Read/ Register
Address Write Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
(LSB) Value
ERR2 ERR1 FAN4 FAN3 FAN2 FAN1 RES 12V 00h
Default
42h
R
Interrupt Status Register 2
The Interrupt Status Register 2 bits will be automatically set, by the LM96000, whenever a fault condition is detected. Interrupt
Status Register 2 identifies faults caused by temperature sensor error, fan speed droping below minimum set by the tachometer
minimum register, the 12V input voltage going outside the window set by its limit registers. Interrupt Status Register 2 will hold a
set bit until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the LM96000 after
it is ready by software, if fault condition no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read
event occurs, even if the fault no longer exists
This register is read only — a write to this register has no effect.
Bit
Name
R/W
Default
Description
0
+12V_Error
R
0
The LM96000 automatically sets this bit to 1 when the 12V input voltage either falls
below the limit set in the 12V Low Limit register or exceeds the limit set in the 12V
High Limit register.
1
2
Reserved
R
R
0
0
Reserved
Fan1 Stalled
The LM96000 automatically sets this bit to 1 when the TACH1 input reading is above
the value set in the Tach1 Minimum MSB and LSB registers.
3
4
5
6
Fan2 Stalled
Fan3 Stalled
Fan4 Stalled
R
R
R
R
0
0
0
0
The LM96000 automatically sets this bit to 1 when the TACH2 input reading is above
the value set in the Tach2 Minimum MSB and LSB registers.
The LM96000 automatically sets this bit to 1 when the TACH3 input reading is above
the value set in the Tach3 Minimum MSB and LSB registers.
The LM96000 automatically sets this bit to 1 when the TACH4 input reading is above
the value set in the Tach4 Minimum MSB and LSB registers.
Remote Diode 1
Fault
The LM96000 automatically sets this bit to 1 when there is either a short or open
circuit fault on the Remote1+ or Remote1− thermal diode input pins. A diode fault
will also set bit 4, Diode 1 Zone Limit bit, of Interrupt Status Register 1.
7
Remote Diode 2
Fault
R
0
The LM96000 automatically sets this bit to 1 when there is either a short or open
circuit fault on the Remote2+ or Remote2− thermal diode input pins. A diode fault
will also set bit 6, Diode 2 Zone Limit bit, of Interrupt Status Register 1.
4.10 Register 43h: VID
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
43h
R
VID0–4
RES
RES
RES
VID4
VID3
VID2
VID1
VID0
The VID register contains the values of LM96000 VID0–VID4 input pins. This register indicates the status of the VID lines that
interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information in this register to determine the
voltage that the processor is designed to operate at. With this information, software can then dynamically determine the correct
values to place in the VCCP Low Limit and VCCP High Limit registers.
This register is read only — a write to this register has no effect.
17
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4.11 Registers 44-4Dh: Voltage Limit Registers
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2.5V Low Limit
2.5V High Limit
VCCP Low Limit
VCCP High Limit
3.3V Low Limit
3.3V High Limit
5V Low Limit
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
5V High Limit
12V Low Limit
12V High Limit
If a voltage input either exceeds the value set in the voltage high limit register or falls below the value set in the voltage low limit
register, the corresponding bit will be set automatically by the LM96000 in the interrupt status registers (41-42h). Voltages are
presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each input will be C0h, as shown
in Table 2.
Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
TABLE 2. Voltage Limits vs Register Setting
Input
Nominal
Voltage
Register Setting at
Nominal Voltage
Maximum
Voltage
Register Reading at
Maximum Voltage
Minimum
Voltage
Register Reading at
Minimum Voltage
2.5V
2.5V
C0h
C0h
C0h
C0h
C0h
3.32V
3.00V
4.38V
6.64V
16.00V
FFh
FFh
FFh
FFh
FFh
0V
00h
00h
AFh
00h
00h
VCCP 2.25V
0V
3.3V
5V
3.3V
5.0V
12.0V
3.0V
0V
12V
0V
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18
4.12 Registers 4E-53h: Temperature Limit Registers
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
4Eh
4Fh
50h
51h
52h
53h
R/W
R/W
R/W
R/W
R/W
R/W
Processor (Zone1)
Low Temp
7
7
7
7
7
7
6
6
6
6
6
6
5
5
5
5
5
5
4
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
81h
7Fh
81h
7Fh
81h
7Fh
Processor (Zone1)
High Temp
Processor (Zone2)
Low Temp
Processor (Zone2)
High Temp
Processor (Zone3)
Low Temp
Processor (Zone3)
High Temp
If an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit
register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automatically by the
LM96000 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote1− and Remote1+ inputs
exceeds the Processor (Zone1) High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature
limits in these registers are represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown below in Table 3.
Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
TABLE 3. Temperature Limits vs Register Settings
Temperature
Reading (Decimal)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
.
.
.
.
.
.
.
.
.
50°C
50
32h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
19
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4.13 Registers 54-5Bh: Fan Tachometer Low Limit
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(LSB)
Default
Value
54h
55h
R/W
R/W
Tach1 Minimum LSB
Tach1 Minimum MSB
7
15
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
56h
57h
R/W
R/W
Tach2 Minimum LSB
Tach2 Minimum MSB
7
15
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
58h
59h
R/W
R/W
Tach3 Minimum LSB
Tach3 Minimum MSB
7
15
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
5Ah
5Bh
R/W
R/W
Tach4 Minimum LSB
Tach4 Minimum MSB
7
15
6
14
5
13
4
12
3
11
2
10
1
9
0
8
FFh
FFh
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the
Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so care should be taken in software
to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be set in Interrupt
Status Register 2 if the current value in Current PWM Duty registers is 00h or if the fan 1 disabled via the Fan Configuration Register.
Interrupts will never be generated for a fan if its minimum is set to FF FFh.
Given the insignificance of Bit 0 and Bit 1, these bits could be programmed to remember which fan is which, as follows.
Fan
Bit 1
Bit 0
CPU
0
0
1
1
0
1
0
1
Memory
Chassis Front
Chassis Rear
Setting the Ready/Lock/Start/Override register Lock bit has no effect these registers.
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20
4.14 Registers 5C-5Eh: Fan Configuration
Register Read/ Register
Address Write Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
(LSB) Value
Default Lock?
5Ch
5Dh
5Eh
R/W
R/W
R/W
Fan1 Configuration
Fan2 Configuration
Fan3 Configuration
ZON2 ZON1 ZON0 INV
ZON2 ZON1 ZON0 INV
ZON2 ZON1 ZON0 INV
RES SPIN2 SPIN1 SPIN0 62h
RES SPIN2 SPIN1 SPIN0 62h
RES SPIN2 SPIN1 SPIN0 62h
✓
✓
✓
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is
cleared even though modifications to this register are possible.
Bits [7:5] Zone/Mode
Bits [7:5] of the Fan Configuration registers associate each fan with a temperature sensor. When in Auto Fan Mode the fan will be
assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If ‘Hottest’ option is selected
(101 or 110), the fan will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. To determine the ‘Hottest’ zone the
PWM level for each zone is calculated then the the highest PWM value is selected. When in manual control mode, the Current
PWM duty registers (30h-32h) become Read/Write. It is then possible to control the PWM outputs with software by writing to these
registers. When the fan is disabled (100) the corresponding PWM output should be driven low (or high, if inverted).
Zone 1: External Diode 1 (processor)
Zone 2: Internal Sensor
Zone 3: External Diode 2
TABLE 4. Fan Zone Setting
ZON[2:0]
000
Fan Configuration
Fan on zone 1 auto
001
Fan on zone 2 auto
010
Fan on zone 3 auto
011
Fan always on full
100
Fan disabled
101
Fan controlled by hottest of zones 2, 3
Fan controlled by hottest of zones 1, 2, 3
Fan manually controlled (Test Mode)
110
111
Bit [4] PWM Invert
Bit [4] inverts the PWM output. If set to 0, 100% duty cycle will yield an output that is always high. If set to 1, 100% duty cycle will
yield an output that is always low.
Bit [3] Reserved
Bits [2:0] Spin Up
Bits [2:0] specify the ‘spin up’ time for the fan. When a fan is being started from a stationary state, the PWM output is held at 100%
duty cycle for the time specified in the table below before scaling to a lower speed.
TABLE 5. Fan Spin-Up Register
SPIN[2:0]
000
Spin Up Time
0 sec
001
100 ms
010
250 ms
011
400 ms
100
700 ms
101
1000 ms
2000 ms
4000 ms
110
111
21
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4.15 Registers 5F-61h: Auto Fan Speed Range, PWM Frequency
Register Read/ Register
Address Write Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB) Value
Default Lock?
5Fh
60h
61h
R/W
R/W
R/W
Zone1 Range/Fan1
Frequency
RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2 FRQ1 FRQ0 C4h
RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2 FRQ1 FRQ0 C4h
RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2 FRQ1 FRQ0 C4h
✓
✓
✓
Zone2 Range/Fan2
Frequency
Zone3 Range/Fan3
Frequency
In Auto Fan Mode, when the temperature for a zone is above the Temperature Limit (Registers 67-69h) and below its Absolute
Temperature Limit (Registers 6A-6Ch), the speed of a fan assigned to that zone is determined as follows.
When the temperature reaches the Fan Temp Limit for a zone, the PWM output assigned to that zone will be Fan PWM Minimum.
Between Fan Temp Limit and (Fan Temp Limit + Range), the PWM duty cycle will increase linearly according to the temperature
as shown in the figure below. The PWM duty cycle will be 100% at (Fan Temp Limit + Range).
20084606
FIGURE 1. Fan Activity above Fan Temp Limit
Example for PWM1 assigned to Zone 1:
– Zone 1 Fan Temp Limit (Register 67h) is set to 50°C (32h).
– Range (Register 5Fh) is set to 8°C (6xh).
– Fan 1 PWM Minimum (Register 64h) is set to 50% (32h).
In this case, the PWM1 duty cycle will be 50% at 50°C.
Since (Zone 1 Fan Temp Limit) + (Zone 1 Range) = 50°C + 8°C = 58°C, the fan will run at 100% duty cycle when the temperature
of the Zone 1 sensor reaches 58°C.
Since the midpoint of the fan control range is 54°C, and the median duty cycle is 75% (Halfway between the PWM Minimum and
100%), PWM1 duty cycle would be 75% at 54°C.
Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%.
PWM frequency bits [3:0]
The PWM frequency bits [3:0] determine the PWM frequency for the fan.The LM96000 has high and low frequency ranges for the
PWM outputs, that are controlled by the HLFRQ bit.
PWM Frequency Selection (Default = 0011 = 30.04 Hz).
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22
TABLE 6. Register Setting vs PWM Frequency
HLFRQ
Freq [2:0]
000
PWM Frequency
10.01 Hz
15.02 Hz
23.14 Hz
30.04 Hz
38.16 Hz
47.06 Hz
61.38 Hz
94.12 Hz
22.5 kHz
24 kHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
001
010
011
100
101
110
111
000
001
010
25.7 kHz
25.7 kHz
27.7 kHz
27.7 kHz
30 kHz
011
100
101
110
111
30 kHz
Range Selection RAN [3:0]
RAN [3:0]
Range (°C)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2
2.5
3.33
4
5
6.67
8
10
13.33
16
20
26.67
32
40
53.33
80
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is
cleared even though modifications to this register are possible.
4.16 Registers 62, 63h: Min/Off, Spike Smoothing
Register Read/ Register
Address Write Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lock?
(MSB) (LSB) Value
62h
63h
R/W Min/Off, Zone1 Spike Smoothing OFF3 OFF2 OFF1 RES ZN1E ZN1-2 ZN1-1 ZN1-0 00h
R/W Zone2, Zone3 Spike Smoothing ZN2E ZN2-2 ZN2-1 ZN2-0 ZN3E ZN3-2 ZN3-1 ZN3-0 00h
✓
✓
The Off/Min Bits [7:5] specify whether the duty cycle will be 0% or Minimum Fan Duty when the measured temperature falls below
the Temperature LIMIT register setting (see table below). OFF1 applies to fan 1, OFF2 applies to fan 2, and OFF3 applies to fan
3.
23
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If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by
the LM96000. If these spikes are not ignored, the CPU fan (if connected to LM96000) may turn on prematurely and produce
unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled.
When spike smoothing is enabled, the temperature reading registers will still reflect the current value of the temperature — not the
‘smoothed out’ value.
ZN1E, ZN2E, and ZN3E enable temperature smoothing for zones 1, 2, and 3 respectively.
ZN1-2, ZN1-1, and ZN1-0 control smoothing time for Zone 1.
ZN2-2, ZN2-1, and ZN2-0 control smoothing time for Zone 2.
ZN3-2, ZN3-1, and ZN3-0 control smoothing time for Zone 3.
These registers become ready only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to
these registers shall have no effect.
20084607
FIGURE 2. What LM96000 Auto Fan Control Sees With and Without Spike Smoothing
TABLE 7. Spike Smoothing
ZN-X[2:0]
000
Spike Smoothed Over
35 seconds
001
17.6 seconds
11.8 seconds
7.0 seconds
010
011
100
4.4 seconds
101
3.0 seconds
110
1.6 seconds
111
.8 seconds
TABLE 8. PWM Output Below Limit Depending on Value of Off/Min
Off/Min
PWM Action
0
1
At 0% duty below LIMIT
At Min PWM Duty below LIMIT
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24
4.17 Registers 64-66h: Minimum PWM Duty Cycle
Register
Address
Read/ Register
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default Lock?
Write
Name
(LSB) Value
64h
65h
66h
R/W
Fan1 PWM Minimum
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
80h
80h
80h
✓
✓
✓
R/W
R/W
Fan2 PWM Minimum
Fan3 PWM Minimum
These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature
LIMIT register setting.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is
cleared even though modifications to this register are possible.
TABLE 9. PWM Duty vs Register Setting for PWM Low Frequency Range
Current Duty
0%
Value (Decimal)
Value (Hex)
00h
0
1
0.3922%
01h
.
.
.
.
.
.
.
.
.
25.098%
64
40h
.
.
.
.
.
.
.
.
.
50.196%
128
80h
.
.
.
.
.
.
.
.
.
100%
255
FF
PWM Duty Cycle vs Register Setting for PWM High Frequency Range
22.5KHz PWM Frequency
24KHz PWM Frequency
PWM Duty Cycle Value in Decimal
Level (%)
Value in Hex
PWM Duty Cycle Value in Decimal
Level (%)
Value in Hex
0.00
6.25
0
0
0
0
0
1 - 15
01 - 0F
10 - 1F
20 - 2F
30 - 3F
40 - 4F
50 - 5F
60 - 6F
70 - 7F
80 - 8F
90 - 9F
A0 - AF
B0 - BF
C0 - CF
D0 - DF
E0 - EF
F0 - FF
6.67
1 - 16
01 - 10
11 - 21
22 - 32
33 - 43
44 - 54
55 - 65
66 - 76
77 - 88
89 - 99
9A - AA
AB - BB
BC - CC
CD - DD
DE - EE
EF - FF
12.50
18.75
25.00
31.25
37.50
43.75
50.00
56.25
62.50
68.75
75.00
81.25
87.50
93.75
100.00
16 - 31
13.33
20.00
26.67
33.33
40.00
46.67
53.33
60.00
66.67
73.33
80.00
86.67
93.33
100.00
17 - 33
32 - 47
34 - 50
48 - 63
51 - 67
64 - 79
68 - 84
80 - 95
85 - 101
102 - 118
119 - 136
137 - 153
154 - 170
171 - 187
188 - 204
205 - 221
222 - 238
239 - 255
96 - 111
112 - 127
128 - 143
144 - 159
160 - 175
176 - 191
192 - 207
208 - 223
224 - 239
240 - 255
25
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25.7KHz PWM Frequency
27.7KHz PWM Frequency
PWM Duty Cycle Value in Decimal
Level (%)
Value in Hex
PWM Duty Cycle Value in Decimal
Level (%)
Value in Hex
0
0
0
0
0
0
7.14
1 - 17
01 - 11
12 - 24
25 - 36
37 - 48
49 - 5A
5B - 6D
6E - 7F
80 - 91
92 - A4
A5 - B6
B7 - C8
C9 - DA
DB - ED
EE - FF
7.69
1 - 19
01 - 13
14 - 26
27 - 3A
3B - 4E
4F - 61
62 - 75
76 - 89
8A - 9D
9E - B0
B1 - C4
C5 - D8
D9 - EB
EC - FF
14.29
21.43
28.57
35.71
42.86
50.00
57.14
64.29
71.43
78.57
85.71
92.86
100.00
18 - 36
15.38
23.08
30.77
38.46
46.15
53.85
61.54
69.23
76.92
84.62
92.31
100.00
20 - 38
37 - 54
39 - 58
55 - 72
59 - 78
73 - 90
79 - 97
91 - 109
110 - 127
128 - 145
146 - 164
165 - 182
183 - 200
201 - 218
219 - 237
238 - 255
98 - 117
118 - 137
138 - 157
158 - 176
177 - 196
197 - 216
217 - 235
236 - 255
30KHz PWM Frequency
PWM Duty Cycle Value in Decimal
Level (%)
Value in Hex
0
0
0
8.33
1 - 20
01 - 14
15 - 2A
2B - 3F
40 - 54
55 - 6A
6B - 7F
80 - 94
95 - AA
AB - BF
C0 - D4
D5 - EA
EB - FF
16.67
25.00
33.33
41.67
50.00
58.33
66.67
75.00
83.33
91.67
100.00
21 - 42
43 - 63
64 - 84
85 - 106
107 - 127
128 - 148
149 - 170
171 - 191
192 - 212
213 - 234
235 - 255
4.18 Registers 67-69h: Temperature Limit
Register
Address
Read/ Register
Write Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default Lock?
(LSB) Value
67h
68h
69h
R/W
R/W
R/W
Zone1 Fan Temp Limit
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
5Ah
5Ah
5Ah
✓
✓
✓
Zone2 Fan Temp Limit
Zone3 Fan Temp Limit
These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be turned on
if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the algorithm set forth in
the Auto Fan Range, PWM Frequency register description. Default = 90°C = 5Ah
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is
cleared even though modifications to this register are possible.
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26
TABLE 10. Temperature Limit vs Register Setting
Temperature Reading (Decimal)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
.
.
.
.
.
.
.
.
.
50°C
50
32h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
4.19 Registers 6A-6Ch: Absolute Temperature Limit
Register Read/
Address Write
Register
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lock?
(MSB)
(LSB) Value
6Ah
6Bh
6Ch
R/W
R/W
R/W
Zone1 Absolute Temp Limit
Zone2 Absolute Temp Limit
Zone3 Absolute Temp Limit
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
64h
64h
64h
✓
✓
✓
7
7
In the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, all of the PWM outputs
will incresase its duty cycle to 100%. This is a safety feature that attempts to cool the system if there is a potentially catastrophic
thermal event. If set to 80h (-128°C), the feature is disabled. Default=100°C=64h
These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to
these registers shall have no effect. After power up the default values are used whenever the Ready/Lock/Start/Override register
Start bit is cleared even though modifications to these registers are possible.
TABLE 11. Absolute Limit vs Register Setting
Temperature Reading (Decimal)
Reading (Hex)
−127°C
−127
81h
.
.
.
.
.
.
.
.
.
−50°C
−50
CEh
.
.
.
.
.
.
.
.
.
0°C
0
00h
.
.
.
.
.
.
.
.
.
50°C
50
32h
.
.
.
.
.
.
.
.
.
127°C
127
7Fh
27
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4.20 Registers 6D-6Eh: Zone Hysteresis Registers
Register Read/ Register
Address Write Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default Lock?
(LSB) Value
6Dh
6Eh
R/W
R/W
Zone1 and Zone2 Hysteresis
Zone3 Hysteresis
H1-3
H1-2 H1-1 H1-0 H2-3 H2-2 H2-1 H2-0
H3-2 H3-1 H3-0 RES RES RES RES
44h
✓
✓
H3-3
40h
If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur:
– The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit.
– The Hysteresis registers control this amount. See below table for details.
These registers become Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to
thses registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start
bit is cleared even though modifications to this register are possible.
TABLE 12. Hysteresis Settings
Setting
HYSTERESIS
0h
0°C
.
.
.
.
.
.
5h
5°C
.
.
.
.
.
.
Fh
15°C
4.21 Register 6Fh: Test Register
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
RES
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
6Fh
R/W
Test Register
RES
RES
RES
RES
RES
RES
XEN
00h
If the XEN bit is set high, the part will be placed into XOR tree test mode. Clearing the bit (writing a 0 to the XEN bit) brings the
part out of XOR tree test mode.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit
is cleared even though modifications to this register are possible.
4.22 Registers 70-7Fh: Vendor Specific Registers
These registers are for vendor specific features, including test registers. They will not default to a specific value on power up.
4.22.1 Register 74h: Tachometer Monitor Mode
Register Read/
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
(LSb)
Default Lock?
Value
Address
Write
74h
R/W
Tach Monitor Mode
RES
RES T3/4-1 T3/4-0 T2-1 T2-0 T1-1 T1-0
00h
Each fan TACH input has 4 possible modes of operation when using the low frequency range for the PWM outputs. Mode 0 is the
only mode that is available when using the high frequecy range for the PWM outputs. The modes for TACH3 and TACH4 share
control bits T3/4-[1:0]; TACH2 is controlled by T2-[1:0]; TACH1 is controlled by T1-[1:0]. The result reported in all modes is based
on 2 pulses per revolution. In order for modes 2 and 3 to function properly it is required that the:
PWM1 output must control the fan that has it's tachometer output connected to the TACH1 LM96000 input.
PWM2 output must control the fan that has it's tachometer output connected to the TACH2 LM96000 input.
PWM3 output must control the fans that have their tachometer outputs connected to the TACH3 or TACH4 LM96000 inputs.
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Setting (Tn[1:0]) Mode Function
00
01
10
11
0
1
2
3
Traditional tach input monitor, false readings when under minimum detctable RPM
Traditional tach input monitor, FFFFh reading when under minimum detectable RPM
Most accurate readings, FFFFh reading when under minimum detectable RPM
Least effect on programmed PWM of Fan, FFFFh reading when under minimum detectable RPM
•
Mode 0: This mode uses the conventional method for fan tachometer pulse detection and does not include any circuitry to
compensate for PWM Fan drive. This mode should be used when PWM drive is not used to power the fan. This
mode may report a false RPM reading when under minimum detectable RPM as shown in the following table.
Mode 1: This mode uses the conventional method for fan tach detection. The reading will be FFFFh if it is below minimum
detectable RPM.
•
•
•
Mode 2: This mode is optimized for accurate RPM readings and activates circuitry that extends the lower side of the RPM
reading as shown in the following table.
Mode 3: This mode minimizes the effect on the RPM setting and activates circuitry that extends the lower side of the RPM
reading as shown in the following table.
PWM Frequency
10.01
Mode 0 and 1 Minimum RPM
Mode 2 and 3 Minimum RPM
841
210
315
420
420
420
420
420
420
15.02
1262
1944
2523
3205
3953
5156
7906
23.14
30.04
38.16
47.06
61.38
94.12
This register is not effected when the Ready/Lock/Start/Override register Lock bit is set. After power up the default value is used
whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
4.22.2 Register 75h: Fan Spin-up Mode
Register Read/
Address Write
Register
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
(MSB)
Bit 2
Bit 1
Bit 0
(LSB)
Default Lock?
Value
75h
R/W Fan Spin-up Mode
RES RES RES RES RES PWM3 SU PWM2 SU PWM1 SU
7h
✓
The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time programmed
by the Fan Configuration register has elapsed. When set to a 1, the spin-up time will terminate early if the TACH reading exceeds
the Tach Minimum value or after the time programmed by the Fan Configuration register has elapsed, whichever occurs first.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this
register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is
cleared even though modifications to this register are possible.
4.23 Undefined Registers
Any reads to undefined registers will always return 00h. Writes to undefined registers will have no effect and will not return an error.
29
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5.0 XOR TEST MODE
Since the test mode an XOR tree, the order of the signals in
the tree is not important. SMBDAT and SMBCLK are not to
be included in the test tree.
The LM96000 incorporates a XOR tree test mode. When the
test mode is enabled by setting the “XEN” bit high in the Test
Register at address 6Fh via the SMBus, the part will enter
XOR test mode.
20084608
Applications Information
20084609
Typical Applications Schematic
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30
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Molded TSSOP Package,
Order Number LM96000CIMT or LM96000CIMTX
NS Package Number MTC24E
JEDEC Registration MO-153, Variation AD
31
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Notes
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