LM3310SQ_技术文档

August 2005

LM3310

Step-up PWM DC/DC Converter with Integrated Op-Amp

and Gate Pulse Modulation Switch

General Description

Features

n Boost converter with a 2A, 0.18Ω switch

n Boost output voltage adjustable up to 20V

n Operating voltage range of 2.5V to 7V

n 660kHz/1.28MHz pin selectable switching frequency

n Adjustable soft-start function

The LM3310 is a step-up DC/DC converter integrated with

an Operational Amplifier and a gate pulse modulation switch.

The boost (step-up) converter is used to generate an adjust-

able output voltage and features a low R_DSONinternal switch

for maximum efficiency. The operating frequency is select-

able between 660kHz and 1.28MHz allowing for the use of

small external components. An external soft-start pin en-

ables the user to tailor the soft-start time to a specific appli-

cation and limit the inrush current. The Op-Amp is capable of

sourcing/sinking 135mA of current (typical). The gate pulse

modulation switch can operate with a VGH voltage of 5V to

30V. The LM3310 is available in a low profile 24-lead LLP

package.

n Input undervoltage protection

n Over temperature protection

n Integrated Op-Amp

n Integrated gate pulse modulation (GPM) switch

n 24-Lead LLP package

Applications

n TFT Bias Supplies

n Portable Applications

Typical Application Circuit

20133331

DS201333

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Connection Diagram

20133304

LLP-24 (Top View)

_JA=37˚C/W

θ

Ordering Information

Order Number

Spec.

Package

Type

NSC Package Drawing

Supplied As

1000 units/reel

LM3310SQ

LLP-24

SQA24A

tape and reel

4500 units/reel

tape and reel

1000 units/reel

tape and reel

4500 units/reel

tape and reel

LM3310SQX

LM3310SQ

LLP-24

NOPB

LM3310SQX

Pin Descriptions

1

Name

NC

Function

Not internally connected. Leave pin open.

2

VGHM

VFLK

Output of GPM circuit. This output directly drives the supply for the gate driver circuits.

Determines when the TFT LCD is on or off. This is controlled by the timing controller in

the LCD module.

3

4

5

VDPM

V_DD

VDPM pin is the enable signal for the GPM block. Pulling this pin high enables the GPM

while pulling this pin low disables it. VDPM is used for timing sequence control.

Reference input for gate pulse modulation (GPM) circuit. The voltage at V_DDis used to set

the lower VGHM voltage.

6

7

AV_IN

OUT

Op-Amp analog power input.

Output of the Op-Amp.

8

NEG

POS

Negative input terminal of the Op-Amp.

9

Positive input terminal of the Op-Amp.

10

AGND

Analog ground for the step-up regulator, LDO, and Op-Amp. Connect directly to DAP and

PGND beneath the device.

11

12

NC

Not internally connected. Leave pin open.

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Pin Descriptions (Continued)

13

14

15

Name

NC

Function

Not internally connected. Leave pin open.

SS

Boost converter soft start pin.

V_C

Boost compensation network connection. Connected to the output of the voltage error

amplifier.

16

FREQ

Switching frequency select input. Connect this pin to V_INfor 1.28MHz operation and

AGND for 660kHz operation.

17

18

19

20

21

V_IN

SW

Boost converter and GPM power input.

Boost power switch input. Switch connected between SW pin and PGND pin.

Shutdown pin. Active low, pulling this pin low disable the LM3310.

Boost output voltage feedback input.

SHDN

FB

PGND

Power Ground. Source connection of the step-up regulator NMOS switch and ground for

the GPM circuit. Connect AGND and PGND directly to the DAP beneath the device.

Connect capacitor from this pin to AGND.

22

23

CE

RE

Connect a resistor between RE and PGND.

24

VGH

GPM power supply input. VGH range is 5V to 30V.

Die Attach Pad. Internally connected to GND. Connect AGND and PGND pins directly to

this pad beneath the device.

DAP

Block Diagrams

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Block Diagrams (Continued)

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Power Dissipation(Note 3)

Lead Temperature

Internally Limited

300˚C

Vapor Phase (60 sec.)

Infrared (15 sec.)

215˚C

220˚C

V_IN

7.5V

21V

ESD Susceptibility (Note 4)

Human Body Model

SW Voltage

2kV

FB Voltage

V_IN

V_CVoltage (Note 2)

SHDN Voltage

FREQ

1.265V 0.3V

7.5V

Operating Conditions

Operating Junction

Temperature Range (Note 5)

Storage Temperature

Supply Voltage

V_IN

−40˚C to +125˚C

−65˚C to +150˚C

2.5V to 7V

20V

AV_IN

12V

Amplifier Inputs/Output

VGH Voltage

VGHM Voltage

VFLK, VDPM, V_DDVoltage

CE Voltage (Note 2)

RE Voltage

Rail-to-Rail

31V

Maximum SW Voltage

VGH Voltage Range

Op-Amp Supply, AV_IN

VGH

5V to 30V

7.5V

4V to 12V

1.265 + 0.3V

VGH

Maximum Junction

Temperature

150˚C

Electrical Characteristics V_IN=2.5V and I_L= 0A

Specifications in standard type face are for T_J= 25˚C and those with boldface type apply over the full Operating Tempera-

ture Range ( T_J= −40˚C to +125˚C). Unless otherwise specified, V_IN=2.5V and I_L= 0A.

Symbol

Parameter

Conditions

FB = 2V (Not Switching)

V_SHDN= 0V

Min(Note 5) Typ(Note 6) Max(Note 5)

Units

I_Q

Quiescent Current

690

1100

0.5

µA

0.04

8.5

660kHz Switching

1.28MHz Switching

2.1

3.1

2.8

mA

4.0

V_FB

Feedback Voltage

1.231

-0.26

1.263

0.089

1.287

0.42

V

%V_FB/∆V_INFeedback Voltage Line

2.5V ≤ V_IN≤ 7V

%/V

Regulation

I_CL

Switch Current Limit (Note 7) (Note 8)

2.0

2.6

27

A

nA

I_B

FB Pin Bias Current (Note 9)

SS Pin Current

160

13.5

1.28

7

I_SS

V_SS

V_IN

g_m

8.5

1.20

2.5

26

11

µA

SS Pin Voltage

1.24

V

Input Voltage Range

V

Error Amp Transconductance ∆I = 5µA

74

69

133

µmho

V/V

A_V

Error Amp Voltage Gain

D_MAX

Maximum Duty Cycle

Switching Frequency

Shutdown Pin Current

f_S= 660kHz

80

91

%

f_S= 1.28MHz

89

f_S

FREQ = Ground

FREQ = V_IN

440

1.0

660

1.28

8

760

1.5

13.5

2

kHz

MHz

µA

I_SHDN

V_SHDN= 2.5V

V_SHDN= 0.3V

1

I_L

Switch Leakage Current

Switch R_DSON

V_SW= 20V

0.03

0.18

5

µA

Ω

R_DSON

Th_SHDN

I_SW= 500mA

0.35

SHDN Threshold

Output High, V_IN= 2.5V to

7V

V

1.4

2.5

Output Low, V_IN= 2.5V to 7V

On Threshold (Switch On)

Off Threshold (Switch Off)

0.4

2.1

UVP

Undervoltage Protection

Threshold

2.4

2.3

V

5

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Electrical Characteristics V_IN=2.5V and I_L= 0A (Continued)

Specifications in standard type face are for T_J= 25˚C and those with boldface type apply over the full Operating Tempera-

ture Range ( T_J= −40˚C to +125˚C). Unless otherwise specified, V_IN=2.5V and I_L= 0A.

Symbol

I_FREQ

Parameter

Conditions

Min(Note 5) Typ(Note 6) Max(Note 5)

2.7 13.5

Units

FREQ Pin Current

FREQ = V_IN= 2.5V

µA

Electrical Characteristics V_IN=2.5V and AV_IN= 8V

Specifications in standard type face are for T_J= 25˚C and those with boldface type apply over the full Operating Tempera-

ture Range ( T_J= −40˚C to +125˚C). Unless otherwise specified V_IN=2.5V and AV_IN= 8V.

Operational Amplifier

Symbol

V_OS

Parameter

Conditions

Buffer configuration, V_O

AV_IN/2, no load

Min(Note 5) Typ(Note 6) Max(Note 5)

Units

Input Offset Voltage

=

5.7

15

mV

I_B

Input Bias Current (POS Pin) Buffer configuration, V_O

AV_IN/2, no load (Note 9)

200

550

nA

V

V_OUTSwing

Buffer, R_L=2kΩ, V_Omin.

0.001

7.97

0.03

Buffer, R_L=2kΩ, V_Omax.

7.9

4

AV_IN

Is+

Supply Voltage

Supply Current

Output Current

12

7.8

V

Buffer, V_O= AV_IN/2, No Load

1.5

138

135

mA

I_OUT

Source

Sink

90

195

175

mA

105

Electrical Characteristics V_IN=2.5V

Specifications in standard type face are for T_J= 25˚C and those with boldface type apply over the full Operating Tempera-

ture Range ( T_J= −40˚C to +125˚C). Unless otherwise specified V_IN=2.5V.

Gate Pulse Modulation

Symbol

VFLK

Parameter

Conditions

Rising edge threshold

Falling edge threshold

Rising edge threshold

Falling edge threshold

VGHM = 30V

Min(Note 5) Typ(Note 6) Max(Note 5)

Units

VFLK Voltage Levels

1.4

V

0.4

1.4

0.4

VDPM

V_DD(TH)

I_VFLK

VDPM Voltage Levels

V_DDThreshold

V

2.8

0.4

3

3.3

0.7

11

V

VGHM = 5V

0.5

4.8

1.1

4.8

1.1

59

VFLK Current

VFLK = 1.5V

µA

VFLK = 0.3V

2.5

11

I_VDPM

I_VGH

VDPM Current

VDPM = 1.5V

VDPM = 0.3V

2.5

300

35.5

28.5

VGH Bias Current

VGH = 30V, VFLK High

VGH = 30V, VFLK Low

20mA Current, VGH = 30V

20mA Current, VGH = VGHM

= 30V

11

R_VGH-VGHMVGH to VGHM Resistance

R_VGHM-REVGHM to RE Resistance

14

Ω

27

55

R_VGHM(OFF)VGH Resistance

VDPM is Low, VGHM = 2V

CE = 0V

1.2

11

1.7

16

kΩ

µA

V

I_CE

CE Current

7

V_CE(TH)

CE Voltage Threshold

1.16

1.22

1.34

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to

be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: Under normal operation the V and CE pins may go to voltages above this value. The maximum rating is for the possibility of a voltage being applied to

C

the pin, however the V and CE pins should never have a voltage directly applied to them.

C

Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T (MAX), the junction-to-ambient thermal resistance, θ

,

JA

J

and the ambient temperature, T . See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation

A

at any ambient temperature is calculated using: P (MAX) = (T

− T )/θ . Exceeding the maximum allowable power dissipation will cause excessive die

D

J(MAX)

A JA

temperature, and the regulator will go into thermal shutdown.

Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin per JEDEC standard JESD22-A114.

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Electrical Characteristics V_IN=2.5V (Continued)

Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%

production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to

calculate Average Outgoing Quality Level (AOQL).

Note 6: Typical numbers are at 25˚C and represent the most likely norm.

Note 7: Duty cycle affects current limit due to ramp generator.

Note 8: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. V

Note 9: Bias current flows into pin.

IN

Typical Performance Characteristics

SHDN Pin Current vs. SHDN Pin Voltage

SS Pin Current vs. Input Voltage

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FREQ Pin Current vs. Input Voltage

FB Pin Current vs. Temperature

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Typical Performance Characteristics (Continued)

CE Pin Current vs. Input Voltage

VDPM Pin Current vs. VDPM Pin Voltage

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VFLK Pin Current vs. VFLK Pin Voltage

660kHz Switching Quiescent Current vs. Input Voltage

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1.28MHz Switching Quiescent Current vs. Input Voltage

660kHz Switching Quiescent Current vs. Temperature

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Typical Performance Characteristics (Continued)

1.28MHz Switching Quiescent Current vs. Temperature

660kHz Switching Frequency vs. Temperature

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20133389

1.28MHz Switching Frequency vs. Temperature

Switch Current Limit vs. Input Voltage

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Non-Switching Quiescent Current vs. Input Voltage

GPM Disabled

Non-Switching Quiescent Current vs. Input Voltage

GPM Enabled

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Typical Performance Characteristics (Continued)

Non-Switching Quiescent Current vs. Temperature

GPM Disabled

Non-Switching Quiescent Current vs. Temperature

GPM Enabled

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20133374

Power NMOS R_DSONvs. Input Voltage

660kHz Max. Duty Cycle vs. Input Voltage

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20133391

1.28MHz Max. Duty Cycle vs. Input Voltage

660kHz Max. Duty Cycle vs. Temperature

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Typical Performance Characteristics (Continued)

1.28MHz Max. Duty Cycle vs. Temperature

1.28MHz Application Efficiency

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1.28MHz Application Efficiency

VGH Pin Bias Current vs. VGH Pin Voltage

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VGH Pin Bias Current vs. VGH Pin Voltage

VGH-VGHM PMOS R_DSONvs. VGH Pin Voltage

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Typical Performance Characteristics (Continued)

VGHM-RE PMOS R_DSONvs. VGHM Pin Voltage

VGHM OFF Resistance vs. Temperature

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Op-Amp Source Current vs. AV_IN

Op-Amp Sink Current vs. AV_IN

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20133397

Op-Amp Quiescent Current vs. AV_IN

Op-Amp Offset Voltage vs. AV_IN(No Load)

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Typical Performance Characteristics (Continued)

Op-Amp Offset Voltage vs. Load Current

1.28MHz, 8.5V Application Boost Load Step

20133351

V

= 8.5V, V = 3.3V, C

= 20µF

OUT

IN

1) V

, 200mV/div, AC

OUT

3) I

, 200mA/div, DC

LOAD

T = 200µs/div

20133318

1.28MHz, 8.5V Application Boost Startup Waveform

20133353

20133352

V

= 8.5V, V = 3.3V, C

IN

= 20µF, R

= 20Ω, C = 100nF

LOAD SS

V

OUT

= 8.5V, V = 3.3V, C

IN

= 20µF, R

= 20Ω, C = 10nF

LOAD SS

OUT

1) V

2) V

, 2V/div, DC

1) V

2) V

, 2V/div, DC

SHDN

, 5V/div, DC

OUT

3) I , 500mA/div, DC

IN

3) I , 500mA/div, DC

IN

T = 1ms/div

T = 200µs/div

1.28MHz, 8.5V Application Boost Startup Waveform

20133354

V

= 8.5V, V = 3.3V, C

= 20µF, R

= 20Ω, C = open

LOAD SS

OUT

IN

OUT

1) V

2) V

, 2V/div, DC

SHDN

, 5V/div, DC

OUT

3) I , 1A/div, DC

IN

T = 40µs/div

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Operation

20133302

FIGURE 1. Simplified Boost Converter Diagram

(a) First Cycle of Operation (b) Second Cycle Of Operation

CONTINUOUS CONDUCTION MODE

The LM3310 contains a current-mode, PWM boost regulator.

A boost regulator steps the input voltage up to a higher

output voltage. In continuous conduction mode (when the

inductor current never reaches zero at steady state), the

boost regulator operates in two cycles.

SOFT-START CAPACITOR

In the first cycle of operation, shown in Figure 1 (a), the

transistor is closed and the diode is reverse biased. Energy

is collected in the inductor and the load current is supplied by

The LM3310 has a soft-start pin that can be used to limit the

inductor inrush current on start-up. The external SS pin is

used to tailor the soft-start for a specific application but is not

required for all applications and can be left open when not

needed. When used a current source charges the external

soft-start capacitor C_SSuntil it reaches its typical clamp

voltage, V_SS. The soft-start time can be estimated as:

C_OUT

.

The second cycle is shown in Figure 1 (b). During this cycle,

the transistor is open and the diode is forward biased. The

energy stored in the inductor is transferred to the load and

output capacitor.

T_SS= C_SS*V_SS/I_SS

The ratio of these two cycles determines the output voltage.

The output voltage is defined approximately as:

THERMAL SHUTDOWN

The LM3310 includes thermal shutdown. If the die tempera-

ture reaches 145˚C the device will shut down until it cools to

a safe temperature at which point the device will resume

operation. If the adverse condition that is heating the device

is not removed (ambient temperature too high, short circuit

conditions, etc...) the device will continue to cycle on and off

to keep the die temperature below 145˚C. The thermal shut-

down has approximately 20˚C of hysteresis. When in ther-

mal shutdown the boost regulator, Op-Amp, and GPM blocks

will all be disabled.

where D is the duty cycle of the switch, D and D' will be

required for design calculations.

SETTING THE OUTPUT VOLTAGE (BOOST

CONVERTER)

The output voltage is set using the feedback pin and a

resistor divider connected to the output as shown in the

typical operating circuit. The feedback pin voltage is 1.263V,

so the ratio of the feedback resistors sets the output voltage

according to the following equation:

INPUT UNDER-VOLTAGE PROTECTION

The LM3310 includes input under-voltage protection (UVP).

The purpose of the UVP is to protect the device both during

start-up and during normal operation from trying to operate

with insufficient input voltage. During start-up using a ramp-

ing input voltage the UVP circuitry ensures that the device

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14

driven by the op-amp. The current from the power pins goes

through the output pin and into the load and feedback loop.

The current exiting the load and feedback loops then must

have a return path back to the op-amp power supply pins.

Ideally this return path must follow the same path as the

output pin trace to the load. Any deviation that makes the

loop area larger between the output current path and the

return current path adds to the probability of noise pick up.

Operation (Continued)

does not begin switching until the input voltage reaches the

UVP On threshold. If the input voltage is present and the

shutdown pin is pulled high the UVP circuitry will prevent the

device from switching if the input voltage present is lower

than the UVP On threshold. During normal operation the

UVP circuitry will disable the device if the input voltage falls

below the UVP Off threshold for any reason. In this case the

device will not turn back on until the UVP On threshold

voltage is exceeded.

GATE PULSE MODULATION

The Gate Pulse Modulation (GPM) block is designed to

provide a modulated voltage to the gate driver circuitry of a

TFT LCD display. Operation is best understood by referring

to the GPM block diagram in the Block Diagrams section, the

drawing in Figure 2 and the transient waveforms in Figure 3

and Figure 4.

OPERATIONAL AMPLIFIER

Compensation:

The architecture used for the amplifier in the LM3310 re-

quires external compensation on the output. Depending on

the equivalent resistive and capacitive distributed load of the

TFT-LCD panel, external components at the amplifier out-

puts may or may not be necessary. If the capacitance pre-

sented by the load is equal to or greater than an equivalent

distibutive load of 50Ω in series with 4.7nF no external

components are needed as the TFT-LCD panel will act as

compensation itself. Distributed resistive and capacitive

loads enhance stability and increase performance of the

amplifiers. If the capacitance and resistance presented by

the load is less than 50Ω in series with 4.7nF, external

components will be required as the load itself will not ensure

stability. No external compensation in this case will lead to

oscillation of the amplifier and an increase in power con-

sumption. A good choice for compensation in this case is to

add a 50Ω in series with a 4.7nF capacitor from the output of

the amplifier to ground. This allows for driving zero to infinite

capacitance loads with no oscillations, minimal overshoot,

and a higher slew rate than using a single large capacitor.

The high phase margin created by the external compensa-

tion will guarantee stability and good performance for all

conditions.

There are two control signals in the GPM block, VDPM and

VFLK. VDPM is the enable pin for the GPM block. If VDPM

is high, the GPM block is active and will respond to the VFLK

drive signal from the timing controller. However, if VDPM is

low, the GPM block will be disabled and both PMOS

switches P2 and P3 will be turned off. The VGHM node will

be discharged through a 1kΩ resistor and the NMOS switch

N2.

When VDPM is high, typical waveforms for the GPM block

can be seen in Figure 2. The pin VGH is typically driven by

a 2x or 3x charge pump. In most cases, the 2x or 3x charge

pump is a discrete solution driven from the SW pin and the

output of the boost switching regulator. When VFLK is high,

the PMOS switch P2 is turned on and the PMOS switch P3

is turned off. With P2 on, the VGHM pin is pulled to the same

voltage applied to the VGH pin. This provides a high gate

drive voltage, VGHM_MAX, and can source current to the gate

drive circuitry. When VFLK is high, NMOS switch N3 is on

which discharges the capacitor CE.

Layout and Filtering considerations:

When the power supply for the amplifiers (AV_IN) is con-

nected to the output of the switching regulator, the output

ripple of the regulator will produce ripple at the output of the

amplifiers. This can be minimized by directly bypassing the

AV_INpin to ground with a low ESR ceramic capacitor. For

best noise reduction a resistor on the order of 5Ω to 20Ω

from the supply being used to the AV_INpin will create and RC

filter and give you a cleaner supply to the amplifier. The

bypass capacitor should be placed as close to the AV_INpin

as possible and connected directly to the AGND plane.

For best noise immunity all bias and feedback resistors

should be in the low kΩ range due to the high input imped-

ance of the amplifier. It is good practice to use a small

capacitance at the high impedance input terminals as well to

reduce noise susceptibility. All resistors and capacitors

should be placed as close to the input pins as possible.

20133384

FIGURE 2.

Special care should also be taken in routing of the PCB

traces. All traces should be as short and direct as possible.

The output pin trace must never be routed near any trace

going to the positive input. If this happens cross talk from the

output trace to the positive input trace will cause the circuit to

oscillate.

When VFLK is low, the NMOS switch N3 is turned off which

allows current to charge the C_Ecapacitor. This creates a

delay, t_DELAY, given by the following equations:

t_DELAY) 1.265V(C_E+ 7pF)/I_CE

When the voltage on CE reaches about 1.265V and the

VFLK signal is low, the PMOS switch P2 will turn off and the

PMOS switch P3 will turn on connecting resistor R3 to the

VGHM pin through P3. This will discharge the voltage at

VGHM at some rate determined by R3 creating a slope, M_R,

as shown in Figure 2. The VGHM pin is no longer a current

source, it is now sinking current from the gate drive circuitry.

The op-amp is not a three terminal device it has 5 terminals:

positive voltage power pin, AGND, positive input, negative

input, and the output. The op-amp "routes" current from the

power input pin and AGND to the output pin. So in effect an

opamp has not two inputs but four, all of which must be kept

noise free relative to the external circuits which are being

15

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Operation (Continued)

As VGHM is discharged through R3, the comparator con-

nected to the pin V_DDmonitors the VGHM voltage. PMOS

switch P3 will turn off when the following is true:

VGHM_MIN) 10V_XR2/(R1 + R2)

where V_Xis some voltage connected to the resistor divider

on pin V_DD. V_Xis typically connected to the output of the

boost switching regulator. When PMOS switch P3 turns off,

VGHM will be high impedance until the VFLK pin is high

again.

Figure 3 and Figure 4 give typical transient waveforms for

the GPM block. Waveform (1) is the VGHM pin, (2) is the

VFLK and (3) is the VDPM. The output of the boost switching

regulator is operating at 8.5V and there is a 3x discrete

~

charge pump ( 23.5V) supplying the VGH pin. In Figure 3

and Figure 4, the VGHM pin is driving a purely capacitive

load, 4.7nF. The value of resistor R1 is 15kohm, R2 is 1.1kΩ

and R3 is 750Ω. In both transient plots, there is no C_Edelay

capacitor.

20133386

FIGURE 4.

In the GPM block diagram, a signal called “Reset” is shown.

This signal is generated from the V_INunder-voltage lockout,

thermal shutdown, or the SHDN pin. If the V_INsupply voltage

drops below 2.3V, typically, then the GPM block will be

disabled and the VGHM pin will discharge through NMOS

switch N2 and the 1kΩ resistor. This applies also if the

junction temperature of the device exceeds 145˚C or if the

SHDN signal is low. As shown in the block diagram, both

VDPM and VFLK have internal 350kΩ pull down resistors.

This puts both VDPM and VFLK in normally “off” states.

Typical VDPM and VFLK pin currents can be found in the

Typical Performance Characteristics section.

INTRODUCTION TO COMPENSATION (BOOST

CONVERTER)

20133385

FIGURE 3.

20133305

FIGURE 5. (a) Inductor current. (b) Diode current.

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16

Operation (Continued)

The LM3310 is a current mode PWM boost converter. The

signal flow of this control scheme has two feedback loops,

one that senses switch current and one that senses output

voltage.

where fs is the switching frequency, D is the duty cycle, and

R_DSONis the ON resistance of the internal switch taken from

the graph "R_DSONvs. V_IN" in the Typical Performance Char-

acteristics section. This equation is only good for duty cycles

To keep a current programmed control converter stable

above duty cycles of 50%, the inductor must meet certain

criteria. The inductor, along with input and output voltage,

will determine the slope of the current through the inductor

(see Figure 5 (a)). If the slope of the inductor current is too

great, the circuit will be unstable above duty cycles of 50%.

A 10µH inductor is recommended for most 660 kHz applica-

tions, while a 4.7µH inductor may be used for most 1.28 MHz

applications. If the duty cycle is approaching the maximum of

85%, it may be necessary to increase the inductance by as

much as 2X. See Inductor and Diode Selection for more

detailed inductor sizing.

>

greater than 50% (D 0.5), for duty cycles less than 50% the

recommended values may be used. The value given by this

equation is the inductance necessary to supress sub-

harmonic oscillations. In some cases the value given by this

equation may be too small for a given application. In this

case the average inductor current and the inductor current

ripple must be considered.

The corresponding inductor current ripple, average inductor

current, and peak inductor current as shown in Figure 5 (a) is

given by:

The LM3310 provides a compensation pin (V_C) to customize

the voltage loop feedback. It is recommended that a series

combination of R_Cand C_Cbe used for the compensation

network, as shown in the typical application circuit. For any

given application, there exists a unique combination of R_C

and C_Cthat will optimize the performance of the LM3310

circuit in terms of its transient response. The series combi-

nation of R_Cand C_Cintroduces a pole-zero pair according to

the following equations:

Continuous conduction mode occurs when ∆i_Lis less than

the average inductor current and discontinuous conduction

mode occurs when ∆i_Lis greater than the average inductor

current. Care must be taken to make sure that the switch will

not reach its current limit during normal operation. The in-

ductor must also be sized accordingly. It should have a

saturation current rating higher than the peak inductor cur-

rent expected. The output voltage ripple is also affected by

the total ripple current.

where R_Ois the output impedance of the error amplifier,

approximately 900kΩ. For most applications, performance

can be optimized by choosing values within the range 5kΩ ≤

R_C≤ 100kΩ (R_Ccan be up to 200kΩ if C_C2is used, see High

Output Capacitor ESR Compensation) and 68pF ≤ C_C

≤

4.7nF. Refer to the Applications Information section for rec-

ommended values for specific circuits and conditions. Refer

to the Compensation section for other design requirement.

The output diode for a boost regulator must be chosen

correctly depending on the output voltage and the output

current. The typical current waveform for the diode in con-

tinuous conduction mode is shown in Figure 5 (b). The diode

must be rated for a reverse voltage equal to or greater than

the output voltage used. The average current rating must be

greater than the maximum load current expected, and the

peak current rating must be greater than the peak inductor

current. During short circuit testing, or if short circuit condi-

tions are possible in the application, the diode current rating

must exceed the switch current limit. Using Schottky diodes

with lower forward voltage drop will decrease power dissipa-

tion and increase efficiency.

COMPENSATION

This section will present a general design procedure to help

insure a stable and operational circuit. The designs in this

datasheet are optimized for particular requirements. If differ-

ent conversions are required, some of the components may

need to be changed to ensure stability. Below is a set of

general guidelines in designing a stable circuit for continu-

ous conduction operation, in most all cases this will provide

for stability during discontinuous operation as well. The

power components and their effects will be determined first,

then the compensation components will be chosen to pro-

duce stability.

DC GAIN AND OPEN-LOOP GAIN

Since the control stage of the converter forms a complete

feedback loop with the power components, it forms a closed-

loop system that must be stabilized to avoid positive feed-

back and instability. A value for open-loop DC gain will be

required, from which you can calculate, or place, poles and

zeros to determine the crossover frequency and the phase

margin. A high phase margin (greater than 45˚) is desired for

the best stability and transient response. For the purpose of

stabilizing the LM3310, choosing a crossover point well be-

low where the right half plane zero is located will ensure

sufficient phase margin.

INDUCTOR AND DIODE SELECTION

Although the inductor sizes mentioned earlier are fine for

most applications, a more exact value can be calculated. To

ensure stability at duty cycles above 50%, the inductor must

have some minimum value determined by the minimum

input voltage and the maximum output voltage. This equa-

tion is:

17

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ESR is also important because it determines the peak to

peak output voltage ripple according to the approximate

equation:

Operation (Continued)

1

To ensure a bandwidth of

⁄2 or less of the frequency of the

RHP zero, calculate the open-loop DC gain, A_DC. After this

value is known, you can calculate the crossover visually by

placing a −20dB/decade slope at each pole, and a +20dB/

decade slope for each zero. The point at which the gain plot

crosses unity gain, or 0dB, is the crossover frequency. If the

∆V_OUT) 2∆i_LR_ESR(in Volts)

A minimum value of 10µF is recommended and may be

increased to a larger value. After choosing the output capaci-

tor you can determine a pole-zero pair introduced into the

control loop by the following equations:

crossover frequency is less than ¹⁄

the RHP zero, the phase

2

margin should be high enough for stability. The phase mar-

gin can also be improved by adding C_C2as discussed later in

this section. The equation for A_DCis given below with addi-

tional equations required for the calculation:

Where R_Lis the minimum load resistance corresponding to

the maximum load current. The zero created by the ESR of

the output capacitor is generally very high frequency if the

ESR is small. If low ESR capacitors are used it can be

neglected. If higher ESR capacitors are used see the High

Output Capacitor ESR Compensation section. Some suit-

able capacitor vendors include Vishay, Taiyo-Yuden, and

TDK.

RIGHT HALF PLANE ZERO

A current mode control boost regulator has an inherent right

half plane zero (RHP zero). This zero has the effect of a zero

in the gain plot, causing an imposed +20dB/decade on the

rolloff, but has the effect of a pole in the phase, subtracting

another 90˚ in the phase plot. This can cause undesirable

effects if the control loop is influenced by this zero. To ensure

the RHP zero does not cause instability issues, the control

mc ) 0.072fs (in V/s)

loop should be designed to have a bandwidth of less than ¹⁄

2

where R_Lis the minimum load resistance, V_INis the mini-

mum input voltage, g_mis the error amplifier transconduc-

tance found in the Electrical Characteristics table, and R_D

the frequency of the RHP zero. This zero occurs at a fre-

quency of:

-

^SONis the value chosen from the graph "NMOS R_DSONvs.

Input Voltage" in the Typical Performance Characteristics

section.

INPUT AND OUTPUT CAPACITOR SELECTION

where I_LOADis the maximum load current.

The switching action of a boost regulator causes a triangular

voltage waveform at the input. A capacitor is required to

reduce the input ripple and noise for proper operation of the

regulator. The size used is dependant on the application and

board layout. If the regulator will be loaded uniformly, with

very little load changes, and at lower current outputs, the

input capacitor size can often be reduced. The size can also

be reduced if the input of the regulator is very close to the

source output. The size will generally need to be larger for

applications where the regulator is supplying nearly the

maximum rated output or if large load steps are expected. A

minimum value of 10µF should be used for the less stressful

condtions while a 22µF to 47µF capacitor may be required

for higher power and dynamic loads. Larger values and/or

lower ESR may be needed if the application requires very

low ripple on the input source voltage.

SELECTING THE COMPENSATION COMPONENTS

The first step in selecting the compensation components R_C

and C_Cis to set a dominant low frequency pole in the control

loop. Simply choose values for R_Cand C_Cwithin the ranges

given in the Introduction to Compensation section to set this

pole in the area of 10Hz to 500Hz. The frequency of the pole

created is determined by the equation:

where R_Ois the output impedance of the error amplifier,

approximately 900kΩ. Since R_Cis generally much less than

R_O, it does not have much effect on the above equation and

can be neglected until a value is chosen to set the zero f_ZC

.

The choice of output capacitors is also somewhat arbitrary

and depends on the design requirements for output voltage

ripple. It is recommended that low ESR (Equivalent Series

Resistance, denoted R_ESR) capacitors be used such as

ceramic, polymer electrolytic, or low ESR tantalum. Higher

ESR capacitors may be used but will require more compen-

sation which will be explained later on in the section. The

f_ZCis created to cancel out the pole created by the output

capacitor, f_P1. The output capacitor pole will shift with differ-

ent load currents as shown by the equation, so setting the

zero is not exact. Determine the range of f_P1over the ex-

pected loads and then set the zero f_ZCto a point approxi-

mately in the middle. The frequency of this zero is deter-

mined by:

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18

sients. If more detail is required, or the most optimum per-

formance is desired, refer to a more in depth discussion of

compensating current mode DC/DC switching regulators.

Operation (Continued)

POWER DISSIPATION

The output power of the LM3310 is limited by its maximum

power dissipation. The maximum power dissipation is deter-

mined by the formula

Now R_Ccan be chosen with the selected value for C_C.

Check to make sure that the pole f_PCis still in the 10Hz to

500Hz range, change each value slightly if needed to ensure

both component values are in the recommended range.

P_D= (T_jmax- T_A)/θ_JA

where T_jmaxis the maximum specified junction temperature

(125˚C), T_Ais the ambient temperature, and θ_JAis the ther-

mal resistance of the package.

HIGH OUTPUT CAPACITOR ESR COMPENSATION

When using an output capacitor with a high ESR value, or

just to improve the overall phase margin of the control loop,

another pole may be introduced to cancel the zero created

by the ESR. This is accomplished by adding another capaci-

tor, C_C2, directly from the compensation pin V_Cto ground, in

parallel with the series combination of R_Cand C_C. The pole

should be placed at the same frequency as f_Z1, the ESR

zero. The equation for this pole follows:

LAYOUT CONSIDERATIONS

The input bypass capacitor C_IN, as shown in the typical

operating circuit, must be placed close to the IC. This will

reduce copper trace resistance which effects input voltage

ripple of the IC. For additional input voltage filtering, a 100nF

bypass capacitor can be placed in parallel with C_IN, close to

the V_INpin, to shunt any high frequency noise to ground. The

output capacitor, C_OUT, should also be placed close to the

IC. Any copper trace connections for the C_OUTcapacitor can

increase the series resistance, which directly effects output

voltage ripple. The feedback network, resistors R_FB1and

R_FB2, should be kept close to the FB pin, and away from the

inductor, to minimize copper trace connections that can in-

ject noise into the system. R_Eand C_Eshould also be close to

the RE and CE pins to minimize noise in the GPM circuitry.

Trace connections made to the inductor and schottky diode

should be minimized to reduce power dissipation and in-

crease overall efficiency. For more detail on switching power

supply layout considerations see Application Note AN-1149:

Layout Guidelines for Switching Power Supplies.

To ensure this equation is valid, and that C_C2can be used

without negatively impacting the effects of R_Cand C_C, f_PC2

must be greater than 10f_ZC

.

CHECKING THE DESIGN

With all the poles and zeros calculated the crossover fre-

quency can be checked as described in the section DC Gain

and Open-loop Gain. The compensation values can be

changed a little more to optimize performance if desired.

This is best done in the lab on a bench, checking the load

step response with different values until the ringing and

overshoot on the output voltage at the edge of the load steps

is minimal. This should produce a stable, high performance

circuit. For improved transient response, higher values of R_C

should be chosen. This will improve the overall bandwidth

which makes the regulator respond more quickly to tran-

For Op-Amp layout please refer to the Operational Amplifier

section.

Figure 6, Figure 7, and Figure 8 in the Application Informa-

tion section following show the schematic and an example of

a good layout as used in the LM3310/11 evaluation board.

19

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Application Information

20133323

FIGURE 6. Evaluation Board Schematic

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20

Application Information (Continued)

20133324

FIGURE 7. Evaluation Board Layout (top layer)

21

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Application Information (Continued)

20133325

FIGURE 8. Evaluation Board Layout (bottom layer)

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22

Application Information (Continued)

20133329

FIGURE 9. Li-Ion to 8V, 1.28MHz Application

23

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Application Information (Continued)

20133330

FIGURE 10. 5V to 10.5V, 1.28MHz Application

Some recommended Inductors (others may be used)

Manufacturer

Inductor

Contact Information

Coilcraft

DO3316 and DT3316 series

www.coilcraft.com

800-3222645

TDK

SLF10145 series

www.component.tdk.com

847-803-6100

Pulse

P0751 and P0762 series

www.pulseeng.com

www.sumida.com

Sumida

CDRH8D28 and CDRH8D43 series

Some recommended Input and Output Capacitors (others may be used)

Manufacturer

Capacitor

Contact Information

Vishay Sprague

293D, 592D, and 595D series tantalum

www.vishay.com

407-324-4140

Taiyo Yuden

High capacitance MLCC ceramic

www.t-yuden.com

408-573-4150

ESRD seriec Polymer Aluminum Electrolytic

SPV and AFK series V-chip series

High capacitance MLCC ceramic

EEJ-L series tantalum

Cornell Dubilier

Panasonic

www.cde.com

www.panasonic.com

www.national.com

24

Physical Dimensions inches (millimeters) unless otherwise noted

LLP-24 Pin Package (SQA)

For Ordering, Refer to Ordering Information Table

NS Package Number SQA24A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

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型号：	LM3310SQ
厂家：	National Semiconductor
描述：	Step-up PWM DC/DC Converter with Integrated Op-Amp and Gate Pulse Modulation Switch 升压PWM DC / DC转换器，集成运算放大器和门脉冲调制开关转换器开关运算放大器脉冲栅
文件：	总25页 (文件大小：1662K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM3310SQ [NSC]

相关型号：

LM3310SQ/NOPB

LM3310SQ/NOPB

LM3310SQX

LM3310_07

LM3311

LM3311SQ

LM3311SQ-HIOP

LM3311SQ-HIOP

LM3311SQ-HIOP/NOPB

LM3311SQX

LM3311SQX

LM3311SQX-HIOP