LM3311SQX [TI]
2.6A SWITCHING REGULATOR, 1280kHz SWITCHING FREQ-MAX, QCC24, LLP-24;
| 型号： | LM3311SQX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.6A SWITCHING REGULATOR, 1280kHz SWITCHING FREQ-MAX, QCC24, LLP-24 开关 |
| 文件： | 总38页 (文件大小：2046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM3311
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SNVS320G –AUGUST 2005–REVISED APRIL 2013
LM3311 Step-Up PWM DC/DC Converter with Integrated LDO, Op-Amp, and Gate Pulse
Modulation Switch
Check for Samples: LM3311
1
FEATURES
DESCRIPTION
The LM3311 is a step-up DC/DC converter integrated
with an LDO, an Operational Amplifier, and a gate
pulse modulation switch. The boost (step-up)
converter is used to generate an adjustable output
voltage and features a low RDSON internal switch for
maximum efficiency. The operating frequency is
selectable between 660kHz and 1.28MHz allowing for
the use of small external components. An external
soft-start pin enables the user to tailor the soft-start
time to a specific application and limit the inrush
current. The LDO also has an adjustable output
voltage and is stable using ceramic output capacitors.
The Op-Amp is capable of sourcing/sinking 135mA of
current (typical) for the standard version and 200mA
(typical) for the HIOP version. The gate pulse
modulation switch can operate with a VGH voltage of
5V to 30V. The LM3311 is available in a low profile
24-lead WQFN package.
2
•
Boost Converter with a 2A, 0.18Ω Switch
Boost Output Voltage Adjustable up to 20V
Operating Voltage Range of 2.5V to 7V
•
•
•
660kHz/1.28MHz Pin Selectable Switching
Frequency
•
•
•
•
Adjustable Soft-Start Function
Input Undervoltage Protection
Over Temperature Protection
Adjustable Low Dropout Linear Regulator
(LDO)
•
•
Integrated Op-Amp
Integrated Gate Pulse Modulation (GPM)
Switch
•
24-Lead WQFN Package
APPLICATIONS
•
•
TFT Bias Supplies
Portable Applications
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM3311
SNVS320G –AUGUST 2005–REVISED APRIL 2013
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Typical Application Circuit
D
D
3
2
= 2 X
V
V
OUT
OH
C4
C3
L
D
1
V
V
OUT
IN
R1
FREQ
V
SW
V
SHDN
IN
R2
POS
NEG
R
FB1
DD
AV
C
IN
OUT
OUT
FB
SS
C
LM3311
VFLK
VDPM
VGHM
VGH
IN
R
FB2
V
C
AGND
V
RE CE
ADJ LV
IN
PGND
OUT
R
R
C
LDO
Input
LDO
C
SS
ADJ1
Output
R
E
C
E
C
C
R
ADJ2
C1
C2
Connection Diagram
NC
VGHM
VFLK
1
2
3
4
5
6
18
SW
17
16
15
14
13
V
IN
FREQ
LM3311
VDPM
V
C
SS
LV
V
DD
AV
IN
IN
Figure 1. 24-Lead WQFN (Top View)
See RTW0024A Package
θJA=37°C/W
Pin Descriptions
Pin
Name
Function
1
NC
Not internally connected.
2
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Pin Descriptions (continued)
Pin
2
Name
VGHM
VFLK
Function
Output of GPM circuit. This output directly drives the supply for the gate driver circuits.
3
Determines when the TFT LCD is on or off. This is controlled by the timing controller in the LCD
module.
4
5
VDPM
VDD
VDPM pin is the enable signal for the GPM block. Pulling this pin high enables the GPM while
pulling this pin low disables it. VDPM is used for timing sequence control.
Reference input for gate pulse modulation (GPM) circuit. The voltage at VDD is used to set the lower
VGHM voltage. If the GPM function is not used connect VDD to VIN
.
6
7
AVIN
OUT
Op-Amp analog power input.
Output of the Op-Amp.
8
NEG
POS
Negative input terminal of the Op-Amp.
Positive input terminal of the Op-Amp.
9
10
AGND
Analog ground for the step-up regulator, LDO, and Op-Amp. Connect directly to DAP and PGND
beneath the device.
11
12
13
14
15
16
ADJ
VOUT
LVIN
SS
LDO output voltage feedback input.
LDO regulator output.
LDO power input.
Boost converter soft start pin.
VC
Boost compensation network connection. Connected to the output of the voltage error amplifier.
FREQ
Switching frequency select input. Connect this pin to VIN for 1.28MHz operation and AGND for
660kHz operation.
17
18
19
20
21
VIN
SW
Boost converter and GPM power input.
Boost power switch input. Switch connected between SW pin and PGND pin.
Shutdown pin. Active low, pulling this pin low will disable the LM3311.
Boost output voltage feedback input.
SHDN
FB
PGND
Power Ground. Source connection of the step-up regulator NMOS switch and ground for the GPM
circuit. Connect AGND and PGND directly to the DAP beneath the device.
22
23
CE
RE
Connect capacitor from this pin to AGND.
Connect a resistor between RE and PGND.
GPM power supply input. VGH range is 5V to 30V.
24
VGH
DAP
Die Attach Pad. Internally connected to GND. Connect AGND and PGND pins directly to this pad
beneath the device.
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Block Diagrams
Boost Converter
V
IN
17
FREQ
16
SW
18
Current
Sense
V
IN
Dcomp
V
IN
+
-
PWM
Comp
I
+
-
SS
SS
D
REF
FB
20
Softstart
14
EAMP
-
osc
BG
+
LLcomp
-
Driver
V
+
REF
C
S
UVP
Comp
Q
N1
15
R
V
-
IN
UVP
+
REF
BG
REF
TSD
Comp
+
-
Bandgap
BG
Reset
T
SHDN
19
350 kW
AGND
10
PGND
21
AGND
PGND
Figure 2.
4
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GPM Block
2x or 3x Charge
Pump
24
VGH
VDPM
P2
4
VGHM
2
350 kW
PGND
P3
RE
23
V
IN
1 kW
I
CE
CE
22
R
E
+
-
N2
C
E
BG
PGND
PGND
9R
AGND
BG
R1
+
-
V
DD
5
Reset
N3
R
AGND
R2
VFLK
3
AGND
AGND
AGND
10
PGND
21
350 kW
PGND
AGND
PGND
Figure 3.
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LDO
LV
13
IN
Input
Amplifier
BG
-
V
P1
OUT
+
12
SS
11
-
Short Circuit
Comp
ADJ
0.84V
+
AGND
10
Reset
AGND
Figure 4.
Op-Amp
AV
6
IN
Reset
OUT
POS
NEG
9
8
+
7
-
AGND
10
Figure 5.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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SNVS320G –AUGUST 2005–REVISED APRIL 2013
(1)(2)
Absolute Maximum Ratings
VIN
7.5V
21V
SW Voltage
FB Voltage
VIN
(3)
VC Voltage
1.265V ± 0.3V
7.5V
SHDN Voltage
FREQ
VIN
AVIN
14.5V
Amplifier Inputs/Output
LVIN
Rail-to-Rail
7.5V
ADJ Voltage
VOUT
LVIN
LVIN
VGH Voltage
VGHM Voltage
VFLK, VDPM, VDD Voltage
31V
VGH
7.5V
(3)
CE Voltage
1.265 + 0.3V
VGH
RE Voltage
Maximum Junction Temperature
Power Dissipation(4)
Lead Temperature
Vapor Phase (60 sec.)
Infrared (15 sec.)
150°C
Internally Limited
300°C
215°C
220°C
(5)
ESD Susceptibility
Human Body Model
2kV
(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Under normal operation the VC and CE pins may go to voltages above this value. The maximum rating is for the possibility of a voltage
being applied to the pin, however the VC and CE pins should never have a voltage directly applied to them.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts.
The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding
the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
(5) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin per JEDEC standard JESD22-A114.
Operating Conditions
(1)
Operating Junction Temperature Range
Storage Temperature
Supply Voltage
−40°C to +125°C
−65°C to +150°C
2.5V to 7V
20V
Maximum SW Voltage
VGH Voltage Range
5V to 30V
Op-Amp Supply, AVIN
LDO Supply, LVIN
4V to 14V
2.5V to 7V
(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ = −40°C to +125°C). Unless otherwise specified, VIN = LVIN = 2.5V and IL = 0A.
Min
Typ
Max
Symbol
Parameter
Quiescent Current
Conditions
Units
(1)
(2)
(1)
IQ
FB = 2V (Not Switching)
VSHDN = 0V
690
1100
µA
0.5
8.5
0.04
660kHz Switching
1.28MHz Switching
2.1
3.1
2.8
4.0
mA
VFB
Feedback Voltage
1.231
-0.26
2.0
1.263
1.287
V
%VFB/ΔVIN
Feedback Voltage Line
Regulation
2.5V ≤ VIN ≤ 7V
0.089
0.42
%/V
(3)
(4)
ICL
Switch Current Limit
2.6
27
A
nA
(5)
IB
FB Pin Bias Current
160
13.5
1.28
7
ISS
VSS
VIN
gm
SS Pin Current
8.5
1.20
2.5
26
11
µA
V
SS Pin Voltage
1.24
Input Voltage Range
Error Amp Transconductance
Error Amp Voltage Gain
Maximum Duty Cycle
V
ΔI = 5µA
74
69
133
µmho
V/V
AV
DMAX
fS = 660kHz
80
80
91
%
fS = 1.28MHz
89
fS
Switching Frequency
Shutdown Pin Current
FREQ = Ground
440
1.0
660
1.28
8
760
1.5
13.5
2
kHz
MHz
µA
FREQ = VIN
ISHDN
VSHDN = 2.5V
VSHDN = 0.3V
1
IL
Switch Leakage Current
Switch RDSON
VSW = 20V
0.03
0.18
5
µA
Ω
RDSON
ThSHDN
ISW = 500mA
0.35
SHDN Threshold
Output High, VIN = 2.5V to 7V
Output Low, VIN = 2.5V to 7V
On Threshold (Switch On)
Off Threshold (Switch Off)
FREQ = VIN = 2.5V
1.4
2.5
V
0.4
UVP
Undervoltage Protection
Threshold
2.4
2.3
2.7
V
2.1
IFREQ
FREQ Pin Current
13.5
µA
Operational Amplifier
VOS
Input Offset Voltage
Buffer configuration, VO
AVIN/2, no load
=
=
5.7
5.7
200
15
16
mV
nA
Buffer configuration, VO
AVIN/2, no load (HIOP version)
IB
Input Bias Current (POS Pin)
Buffer configuration, VO =
550
(5)
AVIN/2, no load
VOUT Swing
Buffer, RL=2kΩ, VO min.
0.001
7.97
0.03
V
V
Buffer, RL=2kΩ, VO max.
7.9
4
AVIN
Is+
Supply Voltage
Supply Current
14
Buffer, VO = AVIN/2, No Load
1.5
2.5
7.8
mA
Buffer, VO = AVIN/2, No Load
(HIOP version)
9
(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) Duty cycle affects current limit due to ramp generator.
(4) Current limit at 0% duty cycle. See Typical Performance Characteristics section for Switch Current Limit vs. VIN
(5) Bias current flows into pin.
8
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Electrical Characteristics (continued)
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ = −40°C to +125°C). Unless otherwise specified, VIN = LVIN = 2.5V and IL = 0A.
Min
Typ
Max
Symbol
IOUT
Parameter
Output Current
Conditions
Units
(1)
(2)
(1)
Source
Sink
90
138
135
215
205
50
195
175
270
260
105
140
175
mA
Source (HIOP version)
Sink (HIOP version)
(6)
SR
Slew Rate
CL = 10pF
V/µs
MHz
GBW
Gain Bandwidth
-3dB, CL = 100pF
3.3
Gate Pulse Modulation
VFLK
VDPM
VDD(TH)
IVFLK
VFLK Voltage Levels
Rising edge threshold
Falling edge threshold
Rising edge threshold
Falling edge threshold
VGHM = 30V
1.4
1.4
V
V
0.4
VDPM Voltage Levels
VDD Threshold
0.4
2.8
0.4
3
3.3
0.7
11
V
VGHM = 5V
0.5
4.8
1.1
4.8
1.1
59
VFLK Current
VFLK = 1.5V
µA
µA
µA
VFLK = 0.3V
2.5
11
IVDPM
VDPM Current
VDPM = 1.5V
VDPM = 0.3V
2.5
300
35.5
28.5
IVGH
VGH Bias Current
VGH = 30V, VFLK High
VGH = 30V, VFLK Low
20mA Current, VGH = 30V
11
RVGH-VGHM
RVGHM-RE
VGH to VGHM Resistance
VGHM to RE Resistance
14
Ω
20mA Current, VGH = VGHM
= 30V
27
55
RVGHM(OFF)
ICE
VGH Resistance
CE Current
VDPM is Low, VGHM = 2V
CE = 0V
1.2
57
1.7
71
kΩ
µA
V
40
VCE(TH)
CE Voltage Threshold
1.16
1.22
1.30
Low Dropout Linear Regulator (LDO)
LVIN
VADJ
IADJ
Input Voltage Range
ADJ Pin Voltage
2.5
7
V
V
LVIN = 3V and 7V
1.197
1.263
28
1.289
380
(7)
ADJ Pin Current
nA
%VADJ/ΔVIN ADJ Voltage Line Regulation
LVIN = 3V to 7V, LDOOUT
2.8V, no load
=
-2.6
0.032
1.4
8
%
%
%VADJ/ΔIL
LDOOUT Load Regulation
LVIN Quiescent Current
IOUT = 10mA to 300mA, LVIN
3.3V, LDOOUT = 2.8V
=
-11.6
2.931
290
IQL
Device enabled
425
10.5
674
µA
Device shut down
350mA load, LDOOUT = 2.8V
LVIN = 3.3V
VDO
Dropout Voltage
218
409
mV
V
VADJ(LOW)
VADJ Short Circuit Disable
Threshold
0.85
0.9
(6) Input signal is overdriven to force the output to swing rail to rail.
(7) Bias current flows into pin.
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Typical Performance Characteristics
SHDN Pin Current
vs.
SHDN Pin Voltage
SS Pin Current
vs.
Input Voltage
30
25
20
15
10
5
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
T = -40°C
J
T
= 25°C
J
T = 25°C
J
T = -40°C
J
T
J
= 125°C
T
= 125°C
J
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
0.5
1.5
2.5
3.5
4.5
5.5
6.5
INPUT VOLTAGE (V)
SHDN PIN VOLTAGE (V)
Figure 6.
Figure 7.
FREQ Pin Current
vs.
Input Voltage
FB Pin Current
vs.
Temperature
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
60
50
40
30
20
10
0
FB = 1.265V
T
= -40°C
J
T
= 25°C
J
V
= 2.5V
IN
V
T
= 125°C
J
= 7.0V
IN
1.5
-40 -25 -10
5 20 35 50 65 80 95 110 125
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
Figure 8.
Figure 9.
CE Pin Current
vs.
Input Voltage
VDPM Pin Current
vs.
VDPM Pin Voltage
25
20
15
10
5
66.4
64.4
62.4
60.4
58.4
56.4
54.4
52.4
50.4
T = -40°C
J
T
= 25°C
J
T
= 25°C
J
T = 125°C
T
= 125°C
J
J
T
= -40°C
J
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
0.5
1.5
2.5
3.5
4.5
5.5
6.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDPM PIN VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
VFLK Pin Current
vs.
VFLK Pin Voltage
660kHz Switching Quiescent Current
vs.
Input Voltage
25
20
15
10
5
4.0
3.8
T
J
= -40oC
3.6
T
= 25oC
J
3.4
3.2
T = -40°C
J
3.0
2.8
T
= 25°C
J
T
J
= 125oC
2.6
2.4
2.2
T = 125°C
J
2.0
1.8
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
0.5
1.5
2.5
3.5
4.5
5.5
6.5
INPUT VOLTAGE (V)
VFLK PIN VOLTAGE (V)
Figure 12.
Figure 13.
1.28MHz Switching Quiescent Current
660kHz Switching Quiescent Current
vs.
vs.
Input Voltage
Temperature
4.2
6.75
6.25
5.75
5.25
4.75
4.25
3.75
3.25
2.75
T
= 25°C
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
J
V
= 7.0V
IN
T
= -40°C
J
T
= 125°C
J
V
= 2.5V
IN
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
-40 -25 -10
5 20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (oC)
INPUT VOLTAGE (V)
Figure 14.
Figure 15.
1.28MHz Switching Quiescent Current
660kHz Switching Frequency
vs.
vs.
Temperature
Temperature
6.8
610
600
590
580
570
560
550
6.4
6.0
5.6
5.2
4.8
4.4
4.0
3.6
V
= 7.0V
IN
V
= 7.0V
IN
V
= 2.5V
IN
V
= 2.5V
IN
3.2
2.8
-40 -25 -10
5 20 35 50 65 80 95 110 125
-40 -25 -10
5 20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (°C)
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
1.28MHz Switching Frequency
Switch Current Limit
vs.
vs.
Temperature
Input Voltage
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
2.32
2.3
V
= 8V
OUT
2.28
2.26
2.24
2.22
2.2
V
= 7.0V
IN
V
= 2.5V
IN
2.18
2.16
2.14
2.12
V
= 10V
OUT
-40 -25 -10
5 20 35 50 65 80 95 110 125
2.7 3.3 3.9 4.5 5.1 5.7 6.3 6.9
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 18.
Figure 19.
Non-Switching Quiescent Current
Non-Switching Quiescent Current
vs.
vs.
Input Voltage
GPM Disabled
Input Voltage
GPM Enabled
1.20
1.17
1.14
1.11
1.08
1.05
1.02
0.99
0.96
0.93
0.84
0.81
GPM Enabled
T
= -40°C
GPM Disabled
J
T
= -40°C
J
0.78
0.75
0.72
0.69
0.66
T
= 25°C
J
T
= 25°C
J
T
= 125°C
J
T
= 125°C
J
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 20.
Figure 21.
Non-Switching Quiescent Current
Non-Switching Quiescent Current
vs.
vs.
Temperature
GPM Disabled
Temperature
GPM Enabled
0.84
1.23
GPM Enabled
GPM Disabled
1.20
1.17
1.14
1.11
1.08
1.05
1.02
0.99
0.96
0.93
0.81
0.78
0.75
0.72
0.69
0.66
V
= 7.0V
IN
V
= 7.0V
IN
V
= 2.5V
V
IN
= 2.5V
IN
-40 -25 -10
5
20 35 50 65 80 95 110125
-40 -25 -10
5
20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 22.
Figure 23.
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Typical Performance Characteristics (continued)
Power NMOS RDSON
vs.
660kHz Max. Duty Cycle
vs.
Input Voltage
Input Voltage
0.25
0.23
0.21
0.19
0.17
0.15
0.13
0.11
0.09
93.0
92.5
92.0
91.5
91.0
90.5
I
= 1A
SW
T
J
= -40oC
T
= 100°C
A
T
= 25oC
J
T
= 125oC
J
T
= 25°C
A
T
= -40°C
A
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.5
3
3.5
4
4.5
5
5.5
6
6.5 7
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 24.
Figure 25.
1.28MHz Max. Duty Cycle
660kHz Max. Duty Cycle
vs.
vs.
Input Voltage
Temperature
93.0
92.5
92.0
91.5
91.0
90.5
94.0
93.5
93.0
92.5
92.0
91.5
91.0
90.5
90.0
89.5
89.0
T
= -40°C
T
= 25°C
J
V
= 7.0V
J
IN
T
= 125°C
J
V
= 2.5V
IN
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
-40 -25 -10
5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (oC)
INPUT VOLTAGE (V)
Figure 26.
Figure 27.
1.28MHz Max. Duty Cycle
vs.
Temperature
1.28MHz Application Efficiency
95
90
85
80
75
70
65
93.5
V
= 5.5V
V
= 8.5V
IN
OUT
93.0
92.5
92.0
91.5
91.0
90.5
90.0
89.5
89.0
V
= 7.0V
IN
V
= 2.5V
IN
V
IN
=3.3V
V
= 4.2V
V
= 2.5V
IN
IN
0.01
0.10
1.00
-40 -25 -10
5
20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (°C)
LOAD CURRENT (A)
Figure 28.
Figure 29.
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Typical Performance Characteristics (continued)
VGH Pin Bias Current
vs.
1.28MHz Application Efficiency
VGH Pin Voltage
95
16
14
12
10
8
V
OUT
= 10.5V
V
= 5.0V
IN
T
= -40°C
VFLK = low
J
90
85
80
75
70
65
T
J
= 25°C
V
= 3.0V
IN
6
V
=4.2V
IN
4
2
T
= 125°C
J
0
0.01
0.10
1.00
0
4
8
12 16 20 24 28 32
LOAD CURRENT (A)
VGH PIN VOLTAGE (V)
Figure 30.
Figure 31.
VGH Pin Bias Current
vs.
VGH Pin Voltage
VGH-VGHM PMOS RDSON
vs.
VGH Pin Voltage
28
26
24
22
20
18
16
14
12
10
80
I
= 20 mA
VFLK = high
VGHM
70
60
50
40
30
20
10
0
T
= 125°C
J
T
= -40°C
J
T
= 125°C
= 25°C
J
T
= 25°C
J
T
J
T
= -40°C
J
4
8
12
16
20
24
28
32
0
4
8
12 16 20 24 28 32
VGH PIN VOLTAGE (V)
VGH PIN VOLTAGE (V)
Figure 32.
Figure 33.
VGHM-RE PMOS RDSON
vs.
VGHM Pin Voltage
VGHM OFF Resistance
vs.
Temperature
1450
1400
1350
1300
1250
1200
1150
48
43
38
33
28
23
18
VGH=VGHM
= 20 mA
V
=2.5V
IN
I
RE
T
= 125°C
J
T
= 25°C
J
T
= -40°C
J
5
8
10 13 15 18 20 23 25 28 30
VGHM PIN VOLTAGE (V)
Figure 34.
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
Figure 35.
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Typical Performance Characteristics (continued)
LVIN Quiescent Current
vs.
LVIN Quiescent Current
vs.
LVIN Voltage
Temperature
400
390
380
370
360
350
340
330
320
310
420
400
380
360
340
320
300
T
J
= -40oC
LV = 7.0V
IN
T
J
= 25oC
LV = 2.5V
IN
T
= 125oC
J
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
LDO INPUT VOLTAGE (V)
Figure 36.
-40 -25 -10
5
20 35 50 65 80 95 110125
JUNCTION TEMPERATURE (oC)
Figure 37.
LDO Dropout Voltage
vs.
LDO VOUT
vs.
Load Current
Load Current
500
450
400
350
300
250
200
150
100
50
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
V
= 2.8V
LV = 3.3V
OUT
IN
V
= 3.0V
OUT
V
OUT
= 2.5V
V
= 2.8V
= 2.5V
OUT
V
OUT
= 3.0V
V
OUT
0
0
50 100 150 200 250 300 350
75 125 175 225 275 325
0
100 200 300 400 500 600
150 250 350 450 550 650
50
25
LDO OUTPUT CURRENT (mA)
LDO OUTPUT CURRENT (mA)
Figure 38.
Figure 39.
Op-Amp Source Current
Op-Amp Sink Current
vs.
AVIN
vs.
AVIN
(Standard Version)
(Standard Version)
170
160
150
140
130
120
110
100
NEG-POS = 0.2V
POS-NEG = 0.2V
160
150
= -40oC
T
A
= -40oC
T
A
= 25oC
T
= 25oC
T
140
130
120
110
100
A
A
= 125oC
T
= 125oC
T
A
A
4
5
6
7
8
9
10 11 12
4
5
6
7
8
9
10 11 12
OP-AMP INPUT VOLTAGE (V)
OP-AMP INPUT VOLTAGE (V)
Figure 40.
Figure 41.
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Typical Performance Characteristics (continued)
Op-Amp Quiescent Current
Op-Amp Offset Voltage
vs.
AVIN
vs.
AVIN
(Standard Version)
(Standard Version, No Load)
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
-4.8
-4.9
-5.0
-5.1
-5.2
-5.3
-5.4
-5.5
-5.6
-5.7
Unity Gain, POS = AV /2
IN
Unity Gain, POS = AV /2
IN
T
J
= 25oC
= -40oC
T
J
= -40oC
T
J
T
J
= 25oC
J
T
= 125oC
J
T
= 125oC
4
5
6
7
8
9
10 11 12
4
5
6
7
8
9
10 11 12
OP-AMP INPUT VOLTAGE (V)
OP-AMP INPUT VOLTAGE (V)
Figure 42.
Figure 43.
Op-Amp Offset Voltage
vs.
Load Current
(Standard Version)
1.28MHz, 8.5V Application Boost Load Step
210
190
170
150
130
110
90
Unity Gain, POS = AV /2
IN
AV = 8V
IN
AV = 4V
IN
AV = 12V
IN
70
50
30
10
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF
-10
0
20
40
60
80 100 120 140
1) VOUT, 200mV/div, AC
3) ILOAD, 200mA/div, DC
T = 200µs/div
OP-AMP LOAD CURRENT (mA)
Figure 44.
Figure 45.
1.28MHz, 8.5V Application Boost Startup Waveform
1.28MHz, 8.5V Application Boost Startup Waveform
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF, RLOAD = 20Ω, CSS = 100nF
1) VSHDN, 2V/div, DC
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF, RLOAD = 20Ω, CSS = 10nF
1) VSHDN, 2V/div, DC
2) VOUT, 5V/div, DC
2) VOUT, 5V/div, DC
3) IIN, 500mA/div, DC
3) IIN, 500mA/div, DC
T = 1ms/div
T = 200µs/div
Figure 46.
Figure 47.
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Typical Performance Characteristics (continued)
1.28MHz, 8.5V Application Boost Startup Waveform
LDO Load Transient Waveform
VOUT = 8.5V, VIN = 3.3V, COUT = 20µF, RLOAD = 20Ω, CSS = open
LDOOUT = 2.5V, LVIN = 5V, COUT = 2.2µF
1) VSHDN, 2V/div, DC
2) VOUT, 5V/div, DC
3) IIN, 1A/div, DC
2) LDOOUT, 100mV/div, AC
3) ILOAD, 100mA/div, DC
T = 200µs/div
T = 40µs/div
Figure 48.
Figure 49.
LDO Startup Waveform
(LVIN Fast Rising Edge)
LDO Startup Waveform
(LVIN Slow Rising Edge)
LDOOUT = 2.5V, LVIN = 5V, COUT = 2.2µF, ILOAD = 300mA
1) LVIN, 5V/div, DC
LDOOUT = 2.5V, LVIN = 5V, COUT = 2.2µF, ILOAD = 300mA
1) LVIN, 5V/div, DC
2) LDOOUT, 1V/div, DC
2) LDOOUT, 1V/div, DC
T = 100µs/div
T = 4ms/div
Figure 50.
Figure 51.
GPM Transient Waveforms
GPM Transient Waveforms
VGH = 20V, VDPM = 3.3V, CVGHM = 4.7nF, RE = 2.4kΩ, CE = 33pF, VGH = 20V, VDPM = 3.3V, CVGHM = 4.7nF, RE = 750Ω, CE = 33pF,
R1 = 13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 30kHz
1) VFLK, 2V/div, DC
R1 = 13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 64kHz
1) VFLK, 2V/div, DC
3) VGHM, 5V/div, DC
3) VGHM, 5V/div, DC
T = 4µs/div
T = 2µs/div
Figure 52.
Figure 53.
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Typical Performance Characteristics (continued)
GPM Transient Waveforms
GPM Transient Waveforms
VGH = 20V, VDPM = 3.3V, CVGHM = 4.7nF, RE = 2.4kΩ, CE = open, VGH = 20V, VDPM = 3.3V, CVGHM = 4.7nF, RE = 750Ω, CE = open,
R1 = 13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 30kHz
1) VFLK, 2V/div, DC
R1 = 13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 64kHz
1) VFLK, 2V/div, DC
3) VGHM, 5V/div, DC
3) VGHM, 5V/div, DC
T = 4µs/div
T = 2µs/div
Figure 54.
Figure 55.
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OPERATION
L
D
RLOAD
COUT
VIN
PWM
L
X
+
+
L
COUT
COUT
VIN
RLOAD VIN
VOUT
RLOAD
VOUT
-
-
Cycle 1
(a)
Cycle 2
(b)
(a) First Cycle of Operation
(b) Second Cycle Of Operation
Figure 56. Simplified Boost Converter Diagram
CONTINUOUS CONDUCTION MODE
The LM3311 contains a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a
higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady
state), the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 56 (a), the transistor is closed and the diode is reverse biased.
Energy is collected in the inductor and the load current is supplied by COUT
.
The second cycle is shown in Figure 56 (b). During this cycle, the transistor is open and the diode is forward
biased. The energy stored in the inductor is transferred to the load and output capacitor.
The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:
VIN
VIN
VOUT
=
, D' = (1-D) =
VOUT
1-D
where
•
•
D is the duty cycle of the switch
D and D′ will be required for design calculations
(1)
SETTING THE OUTPUT VOLTAGE (BOOST CONVERTER AND LDO)
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in the
Typical Application Circuit. The feedback pin voltage is 1.263V for both the boost regulator and the LDO, so the
ratio of the feedback resistors sets the output voltage according to the following equations:
VOUT - 1.263
W (Boost)
RFB1 = RFB2
x
1.263
(2)
(3)
LDO out - 1.263
1.263
W (LDO)
RADJ1 = RADJ2
x
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SOFT-START CAPACITOR
The LM3311 has a soft-start pin that can be used to limit the inductor inrush current on start-up. The external SS
pin is used to tailor the soft-start for a specific application (see the LINEAR REGULATOR (LDO) section for the
minimum value of CSS). When used, a current source charges the external soft-start capacitor CSS until it reaches
its typical clamp voltage, VSS. The soft-start time can be estimated as:
TSS = CSS*VSS/ISS
(4)
THERMAL SHUTDOWN
The LM3311 includes thermal shutdown. If the die temperature reaches 145°C the device will shut down until it
cools to a safe temperature at which point the device will resume operation. If the adverse condition that is
heating the device is not removed (ambient temperature too high, short circuit conditions, etc...) the device will
continue to cycle on and off to keep the die temperature below 145°C. The thermal shutdown has approximately
20°C of hysteresis. When in thermal shutdown the boost regulator, LDO, Op-Amp, and GPM blocks will all be
disabled.
INPUT UNDER-VOLTAGE PROTECTION
The LM3311 includes input under-voltage protection (UVP). The purpose of the UVP is to protect the device both
during start-up and during normal operation from trying to operate with insufficient input voltage. During start-up
using a ramping input voltage the UVP circuitry ensures that the device does not begin switching until the input
voltage reaches the UVP On threshold. If the input voltage is present and the shutdown pin is pulled high the
UVP circuitry will prevent the device from switching if the input voltage present is lower than the UVP On
threshold. During normal operation the UVP circuitry will disable the device if the input voltage falls below the
UVP Off threshold for any reason. In this case the device will not turn back on until the UVP On threshold voltage
is exceeded.
LINEAR REGULATOR (LDO)
The LM3311 includes a Low Dropout Linear Regulator. The LDO is designed to operate with ceramic input and
output capacitors with values as low as 2.2µF. The efficiency of the LDO is approximately the output voltage
divided by the input voltage. When using higher input voltages special care should be taken to not dissipate too
much power and cause excessive heating of the die. The power dissipated in the LDO section is approximately:
PD(LDO) = (VIN - VOUT)*IOUT
(5)
The LDO has an output undervoltage lockout feature. This feature is to ensure the LDO will shut itself down in
the event of an output overload or short condition. When the output is overloaded the output voltage will fall
causing the ADJ voltage to fall. When the ADJ voltage falls to VADJ(LOW) the LDO will shut off. In this event the
SHDN pin or the input UVP must be cycled to turn the LDO back on.
The LDO output undervoltage lockout is controlled by the SS voltage. The LDO startup time must be less than
the following:
TS = CSS*0.5V/ISS
(6)
When SS is less than 0.5V the output undervoltage lockout is disabled and allows the LDO to start up. When SS
is greater than 0.5V the undervoltage lockout is active. If the LDO feedback voltage is not greater than VADJ(LOW)
when SS reaches 0.5V the LDO may enter an undervoltage lockout condition. In most cases CSS = 10nF or
greater is sufficient. If a supply other than that used to power VIN is used to power LVIN care must be taken to
apply the input voltage to LVIN prior to applying voltage to VIN.
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3311 requires external compensation on the output. Depending
on the equivalent resistive and capacitive distributed load of the TFT-LCD panel, external components at the
amplifier outputs may or may not be necessary. If the capacitance presented by the load is equal to or greater
than an equivalent distibutive load of 50Ω in series with 4.7nF no external components are needed as the TFT-
LCD panel will act as compensation itself. Distributed resistive and capacitive loads enhance stability and
increase performance of the amplifiers. If the capacitance and resistance presented by the load is less than 50Ω
in series with 4.7nF, external components will be required as the load itself will not ensure stability. No external
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compensation in this case will lead to oscillation of the amplifier and an increase in power consumption. A good
choice for compensation in this case is to add a 50Ω in series with a 4.7nF capacitor from the output of the
amplifier to ground. This allows for driving zero to infinite capacitance loads with no oscillations, minimal
overshoot, and a higher slew rate than using a single large capacitor. The high phase margin created by the
external compensation will ensure stability and good performance for all conditions.
Layout and Filtering considerations:
When the power supply for the amplifier (AVIN) is connected to the output of the switching regulator, the output
ripple of the regulator will produce ripple at the output of the amplifiers. This can be minimized by directly
bypassing the AVIN pin to ground with a low ESR ceramic capacitor. For best noise reduction a resistor on the
order of 5Ω to 20Ω from the supply being used to the AVIN pin will create and RC filter and give you a cleaner
supply to the amplifier. The bypass capacitor should be placed as close to the AVIN pin as possible and
connected directly to the AGND plane.
For best noise immunity all bias and feedback resistors should be in the low kΩ range due to the high input
impedance of the amplifier. It is good practice to use a small capacitance at the high impedance input terminals
as well to reduce noise susceptibility. All resistors and capacitors should be placed as close to the input pins as
possible.
Special care should also be taken in routing of the PCB traces. All traces should be as short and direct as
possible. The output pin trace must never be routed near any trace going to the positive input. If this happens
cross talk from the output trace to the positive input trace will cause the circuit to oscillate.
The op-amp is not a three terminal device it has 5 terminals: positive voltage power pin, AGND, positive input,
negative input, and the output. The op-amp "routes" current from the power pin and AGND to the output pin. So
in effect an opamp has not two inputs but four, all of which must be kept noise free relative to the external circuits
which are being driven by the op-amp. The current from the power pins goes through the output pin and into the
load and feedback loop. The current exiting the load and feedback loops then must have a return path back to
the op-amp power supply pins. Ideally this return path must follow the same path as the output pin trace to the
load. Any deviation that makes the loop area larger between the output current path and the return current path
adds to the probability of noise pick up.
GATE PULSE MODULATION
The Gate Pulse Modulation (GPM) block is designed to provide a modulated voltage to the gate driver circuitry of
a TFT LCD display. Operation is best understood by referring to the GPM block diagram in the Block Diagrams
section, the drawing in Figure 57 and the transient waveforms in Figure 58 and Figure 59.
There are two control signals in the GPM block, VDPM and VFLK. VDPM is the enable pin for the GPM block. If
VDPM is high, the GPM block is active and will respond to the VFLK drive signal from the timing controller.
However, if VDPM is low, the GPM block will be disabled and both PMOS switches P2 and P3 will be turned off.
The VGHM node will be discharged through a 1kΩ resistor and the NMOS switch N2.
When VDPM is high, typical waveforms for the GPM block can be seen in Figure 57. The pin VGH is typically
driven by a 2x or 3x charge pump. In most cases, the 2x or 3x charge pump is a discrete solution driven from the
SW pin and the output of the boost switching regulator. When VFLK is high, the PMOS switch P2 is turned on
and the PMOS switch P3 is turned off. With P2 on, the VGHM pin is pulled to the same voltage applied to the
VGH pin. This provides a high gate drive voltage, VGHMMAX, and can source current to the gate drive circuitry.
When VFLK is high, NMOS switch N3 is on which discharges the capacitor CE.
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VGHM
MAX
VGHM
M
R
VGHM
MIN
t
0
VFLK
0
t
t
DELAY
~1.94V
CE
~1.265V
0
t
Figure 57.
When VFLK is low, the NMOS switch N3 is turned off which allows current to charge the CE capacitor. This
creates a delay, tDELAY, given by the following equations:
tDELAY ≊ 1.265V(CE + 15pF)/ICE
(7)
When the voltage on CE reaches about 1.265V and the VFLK signal is low, the PMOS switch P2 will turn off and
the PMOS switch P3 will turn on connecting resistor R3 to the VGHM pin through P3. This will discharge the
voltage at VGHM at some rate determined by R3 creating a slope, MR, as shown in Figure 57. The VGHM pin is
no longer a current source, it is now sinking current from the gate drive circuitry.
As VGHM is discharged through R3, the comparator connected to the pin VDD monitors the VGHM voltage.
PMOS switch P3 will turn off when the following is true:
VGHMMIN ≊ 10VXR2/(R1 + R2)
where
•
VX is some voltage connected to the resistor divider on pin VDD
(8)
VX is typically connected to the output of the boost switching regulator. When PMOS switch P3 turns off, VGHM
will be high impedance until the VFLK pin is high again.
Figure 58 and Figure 59 give typical transient waveforms for the GPM block. Waveform (1) is the VGHM pin, (2)
is the VFLK and (3) is the VDPM. The output of the boost switching regulator is operating at 8.5V and there is a
3x discrete charge pump (~23.5V) supplying the VGH pin. In Figure 58 and Figure 59, the VGHM pin is driving a
purely capacitive load, 4.7nF. The value of resistor R1 is 15kohm, R2 is 1.1kΩ and R3 is 750Ω. In both transient
plots, there is no CE delay capacitor.
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Figure 58. Waveform
Figure 59. Waveform
In the GPM block diagram, a signal called “Reset” is shown. This signal is generated from the VIN under-voltage
lockout, thermal shutdown, or the SHDN pin. If the VIN supply voltage drops below 2.3V, typically, then the GPM
block will be disabled and the VGHM pin will discharge through NMOS switch N2 and the 1kΩ resistor. This
applies also if the junction temperature of the device exceeds 145°C or if the SHDN signal is low. As shown in
the Block Diagrams, both VDPM and VFLK have internal 350kΩ pull down resistors. This puts both VDPM and
VFLK in normally “off” states. Typical VDPM and VFLK pin currents can be found in the Typical Performance
Characteristics section.
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INTRODUCTION TO COMPENSATION (BOOST CONVERTER)
IL (A)
V
VIN - VOUT
IN
L
L
DiL
IL_AVG
t (s)
D*Ts
Ts
(a)
ID (A)
VIN - VOUT
L
ID_AVG
=IOUT_AVG
t (s)
D*Ts
Ts
(b)
(a) Inductor current
(b) Diode current
Figure 60.
The LM3311 is a current mode PWM boost converter. The signal flow of this control scheme has two feedback
loops, one that senses switch current and one that senses output voltage.
To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet
certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through
the inductor (see Figure 60 (a)). If the slope of the inductor current is too great, the circuit will be unstable above
duty cycles of 50%. A 10µH inductor is recommended for most 660 kHz applications, while a 4.7µH inductor may
be used for most 1.28 MHz applications. If the duty cycle is approaching the maximum of 85%, it may be
necessary to increase the inductance by as much as 2X. See INDUCTOR AND DIODE SELECTION for more
detailed inductor sizing.
The LM3311 provides a compensation pin (VC) to customize the voltage loop feedback. It is recommended that a
series combination of RC and CC be used for the compensation network, as shown in the Typical Application
Circuit. For any given application, there exists a unique combination of RC and CC that will optimize the
performance of the LM3311 circuit in terms of its transient response. The series combination of RC and CC
introduces a pole-zero pair according to the following equations:
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1
fZC
=
Hz
2pRCCC
(9)
1
fPC
=
Hz
2p(RC + RO)CC
where
•
RO is the output impedance of the error amplifier, approximately 900kΩ
(10)
For most applications, performance can be optimized by choosing values within the range 5kΩ ≤ RC ≤ 100kΩ (RC
can be higher values if CC2 is used, see HIGH OUTPUT CAPACITOR ESR COMPENSATION) and 68pF ≤ CC ≤
4.7nF. Refer to the Application Information section for recommended values for specific circuits and conditions.
Refer to the COMPENSATION section for other design requirement.
COMPENSATION
This section will present a general design procedure to help insure a stable and operational circuit. The designs
in this datasheet are optimized for particular requirements. If different conversions are required, some of the
components may need to be changed to ensure stability. Below is a set of general guidelines in designing a
stable circuit for continuous conduction operation, in most all cases this will provide for stability during
discontinuous operation as well. The power components and their effects will be determined first, then the
compensation components will be chosen to produce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be
calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value
determined by the minimum input voltage and the maximum output voltage. This equation is:
VINRDSON
D
D'
- 1
(in H)
L >
0.144 fs
where
•
•
•
fs is the switching frequency
D is the duty cycle
RDSON is the ON resistance of the internal power switch
(11)
This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the
recommended values may be used. The value given by this equation is the inductance necessary to supress
sub-harmonic oscillations. In some cases the value given by this equation may be too small for a given
application. In this case the average inductor current and the inductor current ripple must be considered.
The corresponding inductor current ripple, average inductor current, and peak inductor current as shown in
Figure 60 (a) is given by:
VIND
(in Amps)
DiL =
2Lfs
(12)
iL(AVE) ö I
OUT
hD'
(13)
iL(PEAK)
ö
iL(AVE) + DiL
(14)
Continuous conduction mode occurs when ΔiL is less than the average inductor current and discontinuous
conduction mode occurs when ΔiL is greater than the average inductor current. Care must be taken to make sure
that the switch will not reach its current limit during normal operation. The inductor must also be sized
accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output
voltage ripple is also affected by the total ripple current.
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The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output
current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 60 (b). The
diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current
rating must be greater than the maximum load current expected, and the peak current rating must be greater
than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the
application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower
forward voltage drop will decrease power dissipation and increase efficiency.
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete feedback loop with the power components, it forms a
closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC
gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover
frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and
transient response. For the purpose of stabilizing the LM3311, choosing a crossover point well below where the
right half plane zero is located will ensure sufficient phase margin.
To ensure a bandwidth of ½ or less of the frequency of the RHP zero, calculate the open-loop DC gain, ADC
.
After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole,
and a +20dB/decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the
crossover frequency. If the crossover frequency is less than ½ the RHP zero, the phase margin should be high
enough for stability. The phase margin can also be improved by adding CC2 as discussed later in this section.
The equation for ADC is given below with additional equations required for the calculation:
RFB2
gmROD'
{[(wcLeff)// RL]//RL} (in dB)
ADC(DB) = 20log10
(
)
RDSON
RFB1 + RFB2
where
•
•
RL is the minimum load resistance
gm is the error amplifier transconductance found in the Electrical Characteristics table
(15)
(16)
(17)
2fs
nD'
(in rad/s)
@
wc
L
Leff =
(D')2
2mc
m1
(no unit)
n = 1+
(18)
(19)
mc ≊ 0.072fs (in V/s)
VINRDSON
(in V/s)
@
m1
L
•
•
VIN is the minimum input voltage
RDSON is the value chosen from the graph "NMOS RDSON vs. Input Voltage" in the Typical Performance
Characteristics
(20)
INPUT AND OUTPUT CAPACITOR SELECTION
The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is
required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on
the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at
lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of
the regulator is very close to the source output. The size will generally need to be larger for applications where
the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value
of 10µF should be used for the less stressful condtions while a 22µF to 47µF capacitor may be required for
higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very
low ripple on the input source voltage.
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The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output
voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted RESR) capacitors be used
such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require
more compensation which will be explained later on in the section. The ESR is also important because it
determines the peak to peak output voltage ripple according to the approximate equation:
ΔVOUT ≊ 2ΔiLRESR (in Volts)
(21)
A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output
capacitor you can determine a pole-zero pair introduced into the control loop by the following equations:
1
(in Hz)
fP1
=
2p(RESR + RL)COUT
where
•
RL is the minimum load resistance corresponding to the maximum load current
(22)
(23)
1
(in Hz)
fZ1
=
2pRESRCOUT
The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low
ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the HIGH OUTPUT
CAPACITOR ESR COMPENSATION section. Some suitable capacitor vendors include Vishay, Taiyo-Yuden,
and TDK.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be
designed to have a bandwidth of less than ½ the frequency of the RHP zero. This zero occurs at a frequency of:
VOUT(D')2
(in Hz)
RHPzero =
2pILOADL
where
•
ILOAD is the maximum load current
(24)
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in
the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to
Compensation section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is
determined by the equation:
1
(in Hz)
fPC
=
2p(RC + RO)CC
where
•
RO is the output impedance of the error amplifier, approximately 900kΩ
(25)
Since RC is generally much less than RO, it does not have much effect on the above equation and can be
neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output
capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting
the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point
approximately in the middle. The frequency of this zero is determined by:
1
(in Hz)
fZC
=
2pCCRC
(26)
Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure both component values are in the recommended
range.
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HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of
RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole
follows:
1
(in Hz)
fPC2
=
2pCC2(RC //RO)
(27)
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,
fPC2 must be greater than 10fZC
.
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover frequency can be checked as described in the section DC
GAIN AND OPEN-LOOP GAIN. The compensation values can be changed a little more to optimize performance
if desired. This is best done in the lab on a bench, checking the load step response with different values until the
ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a
stable, high performance circuit. For improved transient response, higher values of RC should be chosen. This
will improve the overall bandwidth which makes the regulator respond more quickly to transients. If more detail is
required, or the most optimum performance is desired, refer to a more in depth discussion of compensating
current mode DC/DC switching regulators.
POWER DISSIPATION
The output power of the LM3311 is limited by its maximum power dissipation. The maximum power dissipation is
determined by the formula
PD = (Tjmax - TA)/θJA
where
•
•
•
Tjmax is the maximum specified junction temperature (125°C)
TA is the ambient temperature
θJA is the thermal resistance of the package
(28)
LAYOUT CONSIDERATIONS
The input bypass capacitor CIN, as shown in the Typical Application Circuit, must be placed close to the IC. This
will reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage
filtering, a 100nF bypass capacitor can be placed in parallel with CIN, close to the VIN pin, to shunt any high
frequency noise to ground. The output capacitor, COUT, should also be placed close to the IC. Any copper trace
connections for the COUT capacitor can increase the series resistance, which directly effects output voltage ripple.
The feedback network, resistors RFB1 and RFB2, should be kept close to the FB pin, and away from the inductor,
to minimize copper trace connections that can inject noise into the system. RE and CE should also be close to the
RE and CE pins to minimize noise in the GPM circuitry. Trace connections made to the inductor and schottky
diode should be minimized to reduce power dissipation and increase overall efficiency. For more detail on
switching power supply layout considerations see Application Note AN-1149: Layout Guidelines for Switching
Power Supplies (SNVA021).
The input capacitor, output capacitor, and feedback resistors for the LDO should be placed as close to the device
as possible to minimize noise and increase stability. Keep the feedback traces short and connect RADJ2 directly to
AGND close to the device.
For Op-Amp layout please refer to the OPERATIONAL AMPLIFIER section.
Figure 61, Figure 62, and Figure 63 in the Application Information section following show the schematic and an
example of a good layout as used in the LM3310/11 evaluation board.
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Application Information
VOUTX2
DCP1
DCP2
VOUTX3
-VOUT
DCP3
RC6
CCP3
CCP1
CCP2
CCP4
RC7 CO2
CCP5
L1
D1
V
IN
VOUT
NEG
RVDD1
RVDD2
RAC2
POS
RFB1
FREQ
V
SW
V
SHDN
IN
CAC2
OUT
POS
NEG
DD
COUT
AV
COUT1
COUT2
IN
OUT
VFLK
CIN
FB
SS
LM3311
VFLK
VDPM
VGHM
VGH
CIN1
VDPM
RFB2
VGHM
V
C
VGH
AGND
PGND
CO1
V
RE CE
OUT
ADJ LV
IN
RAC1
CAC1
RC1
V
IN
RE
CSS
CC1
LDOOUT
CLDO
RFB3
CG2 CG1
CC2
CE
RFB4
CADJ
Figure 61. Evaluation Board Schematic
Figure 62. Evaluation Board Layout (top layer)
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Figure 63. Evaluation Board Layout (bottom layer)
D
D
3
2
= 15V
V
OH
Connect to
VGH
C3
1 mF
C4
1 mF
L
10 mH
D
1
V
= 8V
OUT
V
= 2.9V - 4.2V
IN
R1
13k
R
FB1
R2
1.2k
160k
FREQ
V
SW
V
SHDN
IN
POS
NEG
DD
AV
C
IN
OUT
OUT
2 X 10 mF
ceramic
FB
SS
C
LM3311
VFLK
VDPM
VGHM
VGH
IN
22 mF
R
FB2
30k
V
C
AGND
PGND
V
RE CE
ADJ LV
IN
OUT
R
R
30k
C
10 nF
C
LDO
R
E
Output
2.5V
ADJ1
12k
V
IN
SS
C
C2
2.4k
68 pF
C
C
E
C
1 nF
33 pF
R
ADJ2
12k
C2
2.2 mF
C1
2.2 mF
Figure 64. Li-Ion to 8V, 1.28MHz Application
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D
D
3
2
= 20V
V
OH
Connect to
VGH
C3
1 mF
C4
1 mF
L
10 mH
D
1
V
= 10.5V
V
= 5V
OUT
IN
R1
13k
R
FB1
16k
C
33 pF
R2
1.2k
FF
FREQ
V
SW
V
SHDN
IN
POS
NEG
DD
AV
C
IN
OUT
OUT
4 X 10 mF
ceramic
FB
SS
C
LM3311
VFLK
VDPM
VGHM
VGH
IN
22 mF
R
FB2
2.2k
V
C
AGND
PGND
V
RE CE
ADJ LV
IN
OUT
R
R
33k
C
LDO
R
E
C
10 nF
SS
Output
2.5V
ADJ1
12k
V
IN
2.4k
C
C
E
C
100 pF
33 pF
R
ADJ2
12k
C2
2.2 mF
C1
2.2 mF
Figure 65. 5V to 10.5V, 1.28MHz Application
Table 1. Some Recommended Inductors (Others May Be Used)
Manufacturer
Inductor
Contact Information
Coilcraft
DO3316 and DT3316 series
www.coilcraft.com
800-3222645
TDK
SLF10145 series
www.component.tdk.com
847-803-6100
Pulse
P0751 and P0762 series
www.pulseeng.com
www.sumida.com
Sumida
CDRH8D28 and CDRH8D43 series
Table 2. Some Recommended Input And Output Capacitors (Others May Be Used)
Manufacturer
Capacitor
Contact Information
Vishay Sprague
293D, 592D, and 595D series tantalum
www.vishay.com
407-324-4140
Taiyo Yuden
High capacitance MLCC ceramic
www.t-yuden.com
408-573-4150
ESRD seriec Polymer Aluminum Electrolytic
SPV and AFK series V-chip series
Cornell Dubilier
Panasonic
www.cde.com
High capacitance MLCC ceramic
EEJ-L series tantalum
www.panasonic.com
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REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 31
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PACKAGE OPTION ADDENDUM
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23-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
LM3311SQ-HIOP
ACTIVE
WQFN
WQFN
RTW
24
24
TBD
Call TI
CU SN
Call TI
L3311HP
LM3311SQ-HIOP/NOPB
ACTIVE
RTW
1000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
L3311HP
LM3311SQX
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RTW
RTW
RTW
24
24
24
TBD
Call TI
Call TI
CU SN
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
L3311SQ
L3311HP
L3311HP
LM3311SQX-HIOP
TBD
LM3311SQX-HIOP/NOPB
4500
4500
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM3311SQX/NOPB
ACTIVE
WQFN
RTW
24
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L3311SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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23-Sep-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM3311SQ-HIOP/NOPB WQFN
LM3311SQX-HIOP/NOPB WQFN
RTW
RTW
RTW
24
24
24
1000
4500
4500
178.0
330.0
330.0
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
LM3311SQX/NOPB
WQFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM3311SQ-HIOP/NOPB
LM3311SQX-HIOP/NOPB
LM3311SQX/NOPB
WQFN
WQFN
WQFN
RTW
RTW
RTW
24
24
24
1000
4500
4500
203.0
367.0
367.0
190.0
367.0
367.0
41.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
www.ti.com
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