LM3311SQX [NSC]
Step-Up PWM DC/DC Converter with Integrated LDO, Op-Amp, and Gate Pulse Modulation Switch; 升压PWM DC / DC转换器，集成LDO ，运算放大器和门脉冲调制开关
| 型号： | LM3311SQX |
| 厂家： | 
National Semiconductor |
| 描述： | Step-Up PWM DC/DC Converter with Integrated LDO, Op-Amp, and Gate Pulse Modulation Switch |
| 文件： | 总29页 (文件大小：2046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2005
LM3311
Step-Up PWM DC/DC Converter with Integrated LDO,
Op-Amp, and Gate Pulse Modulation Switch
General Description
Features
n Boost converter with a 2A, 0.18Ω switch
n Boost output voltage adjustable up to 20V
n Operating voltage range of 2.5V to 7V
n 660kHz/1.28MHz pin selectable switching frequency
n Adjustable soft-start function
The LM3311 is a step-up DC/DC converter integrated with
an LDO, an Operational Amplifier, and a gate pulse modu-
lation switch. The boost (step-up) converter is used to gen-
erate an adjustable output voltage and features a low RDSON
internal switch for maximum efficiency. The operating fre-
quency is selectable between 660kHz and 1.28MHz allowing
for the use of small external components. An external soft-
start pin enables the user to tailor the soft-start time to a
specific application and limit the inrush current. The LDO
also has an adjustable output voltage and is stable using
ceramic output capacitors. The Op-Amp is capable of
sourcing/sinking 135mA of current (typical). The gate pulse
modulation switch can operate with a VGH voltage of 5V to
30V. The LM3311 is available in a low profile 24-lead LLP
package.
n Input undervoltage protection
n Over temperature protection
n Adjustable low dropout linear regulator (LDO)
n Integrated Op-Amp
n Integrated gate pulse modulation (GPM) switch
n 24-Lead LLP package
Applications
n TFT Bias Supplies
n Portable Applications
Typical Application Circuit
20126331
© 2005 National Semiconductor Corporation
DS201263
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Connection Diagram
20126304
LLP-24 (Top View)
JA=37˚C/W
θ
Ordering Information
Order Number
Spec.
Package
Type
NSC Package Drawing
Supplied As
1000 units/reel
LM3311SQ
LLP-24
SQA24A
SQA24A
SQA24A
SQA24A
tape and reel
4500 units/reel
tape and reel
1000 units/reel
tape and reel
4500 units/reel
tape and reel
LM3311SQX
LM3311SQ
LLP-24
LLP-24
LLP-24
NOPB
NOPB
LM3311SQX
Pin Descriptions
Pin
1
Name
NC
Function
Not internally connected.
2
VGHM
VFLK
Output of GPM circuit. This output directly drives the supply for the gate driver circuits.
Determines when the TFT LCD is on or off. This is controlled by the timing controller in
the LCD module.
3
4
5
VDPM
VDD
VDPM pin is the enable signal for the GPM block. Pulling this pin high enables the GPM
while pulling this pin low disables it. VDPM is used for timing sequence control.
Reference input for gate pulse modulation (GPM) circuit. The voltage at VDD is used to set
the lower VGHM voltage.
6
7
AVIN
OUT
Op-Amp analog power input.
Output of the Op-Amp.
8
NEG
POS
Negative input terminal of the Op-Amp.
9
Positive input terminal of the Op-Amp.
10
AGND
Analog ground for the step-up regulator, LDO, and Op-Amp. Connect directly to DAP and
PGND beneath the device.
11
12
ADJ
LDO output voltage feedback input.
VOUT
LDO regulator output.
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2
Pin Descriptions (Continued)
Pin
13
14
15
Name
LVIN
SS
Function
LDO power input.
Boost converter soft start pin.
VC
Boost compensation network connection. Connected to the output of the voltage error
amplifier.
16
FREQ
Switching frequency select input. Connect this pin to VIN for 1.28MHz operation and
AGND for 660kHz operation.
17
18
19
20
21
VIN
SW
Boost converter and GPM power input.
Boost power switch input. Switch connected between SW pin and PGND pin.
Shutdown pin. Active low, pulling this pin low will disable the LM3311.
Boost output voltage feedback input.
SHDN
FB
PGND
Power Ground. Source connection of the step-up regulator NMOS switch and ground for
the GPM circuit. Connect AGND and PGND directly to the DAP beneath the device.
Connect capacitor from this pin to AGND.
22
23
CE
RE
Connect a resistor between RE and PGND.
24
VGH
GPM power supply input. VGH range is 5V to 30V.
DAP
Die Attach Pad. Internally connected to GND. Connect AGND and PGND pins directly to
this pad beneath the device.
Block Diagrams
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3
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Block Diagrams (Continued)
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Block Diagrams (Continued)
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20126360
5
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Junction
Temperature
150˚C
Power Dissipation(Note 3)
Lead Temperature
Internally Limited
300˚C
VIN
7.5V
21V
Vapor Phase (60 sec.)
Infrared (15 sec.)
215˚C
SW Voltage
FB Voltage
220˚C
VIN
ESD Susceptibility (Note 4)
Human Body Model
VC Voltage (Note 2)
SHDN Voltage
FREQ
1.265V 0.3V
7.5V
2kV
VIN
Operating Conditions
Operating Junction
Temperature Range (Note 5)
Storage Temperature
Supply Voltage
AVIN
12V
Amplifier Inputs/Output
LVIN
Rail-to-Rail
7.5V
−40˚C to +125˚C
−65˚C to +150˚C
2.5V to 7V
20V
ADJ Voltage
VOUT
LVIN
LVIN
Maximum SW Voltage
VGH Voltage Range
Op-Amp Supply, AVIN
LDO Supply, LVIN
VGH Voltage
VGHM Voltage
VFLK, VDPM, VDD Voltage
CE Voltage (Note 2)
RE Voltage
31V
5V to 30V
VGH
4V to 12V
7.5V
2.5V to 7V
1.265 + 0.3V
VGH
Electrical Characteristics
Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera-
ture Range ( TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = LVIN = 2.5V and IL = 0A.
Min
(Note 5)
Typ
(Note 6)
690
Max
(Note 5)
1100
0.5
Symbol
Parameter
Conditions
Units
IQ
Quiescent Current
FB = 2V (Not Switching)
VSHDN = 0V
µA
0.04
8.5
660kHz Switching
1.28MHz Switching
2.1
3.1
2.8
mA
V
4.0
VFB
Feedback Voltage
1.231
-0.26
2.0
1.263
1.287
%VFB/∆VIN Feedback Voltage Line
2.5V ≤ VIN ≤ 7V
0.089
0.42
%/V
Regulation
ICL
Switch Current Limit (Note 7) (Note 8)
2.6
27
A
nA
IB
FB Pin Bias Current (Note 9)
SS Pin Current
160
13.5
1.28
7
ISS
VSS
VIN
gm
8.5
1.20
2.5
26
11
µA
SS Pin Voltage
1.24
V
Input Voltage Range
V
Error Amp Transconductance ∆I = 5µA
74
69
133
µmho
V/V
AV
Error Amp Voltage Gain
DMAX
Maximum Duty Cycle
Switching Frequency
Shutdown Pin Current
fS = 660kHz
80
80
91
%
fS = 1.28MHz
89
fS
FREQ = Ground
FREQ = VIN
440
1.0
660
1.28
8
760
1.5
13.5
2
kHz
MHz
µA
ISHDN
VSHDN = 2.5V
VSHDN = 0.3V
1
IL
Switch Leakage Current
Switch RDSON
VSW = 20V
0.03
0.18
5
µA
Ω
RDSON
ThSHDN
ISW = 500mA
0.35
SHDN Threshold
Output High, VIN = 2.5V to
7V
V
1.4
Output Low, VIN = 2.5V to 7V
0.4
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6
Electrical Characteristics (Continued)
Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera-
ture Range ( TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = LVIN = 2.5V and IL = 0A.
Min
(Note 5)
2.5
Typ
(Note 6)
2.4
Max
(Note 5)
Symbol
UVP
Parameter
Conditions
Units
Undervoltage Protection
Threshold
On Threshold (Switch On)
Off Threshold (Switch Off)
FREQ = VIN = 2.5V
V
2.3
2.1
IFREQ
FREQ Pin Current
2.7
13.5
µA
Electrical Characteristics
Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera-
ture Range ( TJ = −40˚C to +125˚C). Unless otherwise specified VIN = LVIN = 2.5V and AVIN = 8V.
Operational Amplifier
Min
(Note 5)
Typ
(Note 6)
Max
(Note 5)
Symbol
VOS
Parameter
Conditions
Units
mV
nA
Input Offset Voltage
Buffer configuration, VO
AVIN/2, no load
=
=
5.7
15
IB
Input Bias Current (POS Pin) Buffer configuration, VO
AVIN/2, no load (Note 9)
200
550
VOUT Swing
Buffer, RL=2kΩ, VO min.
0.001
7.97
0.03
V
Buffer, RL=2kΩ, VO max.
7.9
4
AVIN
Is+
Supply Voltage
Supply Current
Output Current
12
7.8
V
Buffer, VO = AVIN/2, No Load
1.5
138
135
mA
IOUT
Source
Sink
90
195
175
mA
105
Electrical Characteristics
Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera-
ture Range ( TJ = −40˚C to +125˚C). Unless otherwise specified VIN = LVIN = 2.5V.
Gate Pulse Modulation
Min
(Note 5)
Typ
(Note 6)
Max
(Note 5)
1.4
Symbol
VFLK
Parameter
Conditions
Units
V
VFLK Voltage Levels
Rising edge threshold
Falling edge threshold
Rising edge threshold
Falling edge threshold
VGHM = 30V
0.4
VDPM
VDD(TH)
IVFLK
VDPM Voltage Levels
VDD Threshold
1.4
V
0.4
2.8
0.4
3
3.3
0.7
11
V
VGHM = 5V
0.5
4.8
1.1
4.8
1.1
59
VFLK Current
VFLK = 1.5V
µA
µA
µA
VFLK = 0.3V
2.5
11
IVDPM
IVGH
VDPM Current
VDPM = 1.5V
VDPM = 0.3V
2.5
300
35.5
28.5
VGH Bias Current
VGH = 30V, VFLK High
VGH = 30V, VFLK Low
20mA Current, VGH = 30V
20mA Current, VGH = VGHM
= 30V
11
RVGH-VGHM VGH to VGHM Resistance
RVGHM-RE VGHM to RE Resistance
14
Ω
27
55
RVGHM(OFF) VGH Resistance
VDPM is Low, VGHM = 2V
CE = 0V
1.2
57
1.7
71
kΩ
µA
V
ICE
CE Current
40
VCE(TH)
CE Voltage Threshold
1.16
1.22
1.30
7
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Electrical Characteristics
Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera-
ture Range ( TJ = −40˚C to +125˚C). Unless otherwise specified VIN = LVIN =2.5V.
Low Dropout Linear Regulator (LDO)
Min
(Note 5)
2.5
Typ
(Note 6)
Max
(Note 5)
7
Symbol
Parameter
Conditions
Units
LVIN
VADJ
IADJ
Input Voltage Range
ADJ Pin Voltage
V
V
LVIN = 3V and 7V
1.197
1.263
28
1.289
380
ADJ Pin Current (Note 9)
nA
%VADJ/∆VIN ADJ Voltage Line Regulation LVIN = 3V to 7V, LDOOUT
=
-2.6
0.032
1.4
8
%
%
2.8V, no load
%VADJ/∆IL
LDOOUT Load Regulation
LVIN Quiescent Current
IOUT = 10mA to 300mA, LVIN
-11.6
2.931
290
= 3.3V, LDOOUT = 2.8V
Device enabled
IQL
425
10.5
674
µA
mV
V
Device shut down
350mA load, LDOOUT = 2.8V
LVIN = 3.3V
VDO
Dropout Voltage
VADJ Short Circuit Disable
Threshold
218
409
VADJ(LOW)
0.85
0.9
Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Under normal operation the V and CE pins may go to voltages above this value. The maximum rating is for the possibility of a voltage being applied to
C
the pin, however the V and CE pins should never have a voltage directly applied to them.
C
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T (MAX), the junction-to-ambient thermal resistance, θ
,
JA
J
and the ambient temperature, T . See the Electrical Characteristics table for the thermal resistance of various layouts. The maximum allowable power dissipation
A
at any ambient temperature is calculated using: P (MAX) = (T
− T )/θ . Exceeding the maximum allowable power dissipation will cause excessive die
D
J(MAX)
A JA
temperature, and the regulator will go into thermal shutdown.
Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin per JEDEC standard JESD22-A114.
Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to
calculate Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25˚C and represent the most likely norm.
Note 7: Duty cycle affects current limit due to ramp generator.
Note 8: Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. V
Note 9: Bias current flows into pin.
IN
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Typical Performance Characteristics
SHDN Pin Current vs. SHDN Pin Voltage
SS Pin Current vs. Input Voltage
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20126361
FREQ Pin Current vs. Input Voltage
FB Pin Current vs. Temperature
20126363
20126364
CE Pin Current vs. Input Voltage
VDPM Pin Current vs. VDPM Pin Voltage
20126370
20126365
9
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Typical Performance Characteristics (Continued)
VFLK Pin Current vs. VFLK Pin Voltage
660kHz Switching Quiescent Current vs. Input Voltage
20126387
20126366
1.28MHz Switching Quiescent Current vs. Input Voltage
660kHz Switching Quiescent Current vs. Temperature
20126367
20126388
1.28MHz Switching Quiescent Current vs. Temperature
660kHz Switching Frequency vs. Temperature
20126368
20126389
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Typical Performance Characteristics (Continued)
1.28MHz Switching Frequency vs. Temperature
Switch Current Limit vs. Input Voltage
20126369
20126319
Non-Switching Quiescent Current vs. Input Voltage
GPM Disabled
Non-Switching Quiescent Current vs. Input Voltage
GPM Enabled
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20126372
Non-Switching Quiescent Current vs. Temperature
GPM Disabled
Non-Switching Quiescent Current vs. Temperature
GPM Enabled
20126373
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11
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Typical Performance Characteristics (Continued)
Power NMOS RDSON vs. Input Voltage
660kHz Max. Duty Cycle vs. Input Voltage
20126375
20126391
1.28MHz Max. Duty Cycle vs. Input Voltage
660kHz Max. Duty Cycle vs. Temperature
20126383
20126390
1.28MHz Max. Duty Cycle vs. Temperature
1.28MHz Application Efficiency
20126376
20126382
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Typical Performance Characteristics (Continued)
1.28MHz Application Efficiency
VGH Pin Bias Current vs. VGH Pin Voltage
20126326
20126377
VGH Pin Bias Current vs. VGH Pin Voltage
VGH-VGHM PMOS RDSON vs. VGH Pin Voltage
20126379
20126378
VGHM-RE PMOS RDSON vs. VGHM Pin Voltage
VGHM OFF Resistance vs. Temperature
20126380
20126381
13
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Typical Performance Characteristics (Continued)
LVIN Quiescent Current vs. LVIN Voltage
LVIN Quiescent Current vs. Temperature
20126392
20126393
LDO Dropout Voltage vs. Load Current
LDO VOUT vs. Load Current
20126395
20126394
Op-Amp Source Current vs. AVIN
Op-Amp Sink Current vs. AVIN
20126396
20126397
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Typical Performance Characteristics (Continued)
Op-Amp Quiescent Current vs. AVIN
Op-Amp Offset Voltage Current vs. AVIN (No Load)
20126316
20126317
Op-Amp Offset Voltage Current vs. Load Current
1.28MHz, 8.5V Application Boost Load Step
20126351
V
= 8.5V, V = 3.3V, C
= 20µF
OUT
OUT
IN
1) V
, 200mV/div, AC
OUT
3) I
, 200mA/div, DC
LOAD
T = 200µs/div
20126318
1.28MHz, 8.5V Application Boost Startup Waveform
1.28MHz, 8.5V Application Boost Startup Waveform
20126353
20126352
V
OUT
= 8.5V, V = 3.3V, C
IN
= 20µF, R
= 20Ω, C = 100nF
LOAD SS
V
= 8.5V, V = 3.3V, C
IN
= 20µF, R
= 20Ω, C = 10nF
LOAD SS
OUT
OUT
OUT
1) V
2) V
, 2V/div, DC
1) V
2) V
, 2V/div, DC
SHDN
SHDN
, 5V/div, DC
, 5V/div, DC
OUT
OUT
3) I , 500mA/div, DC
IN
3) I , 500mA/div, DC
IN
T = 1ms/div
T = 200µs/div
15
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Typical Performance Characteristics (Continued)
1.28MHz, 8.5V Application Boost Startup Waveform
LDO Load Transient Waveform
20126354
20126355
V
= 8.5V, V = 3.3V, C
IN
= 20µF, R
= 20Ω, C = open
LOAD SS
LDO
= 2.5V, LV = 5V, C
IN
= 2.2µF
OUT
OUT
OUT
OUT
1) V
2) V
, 2V/div, DC
2) LDO
, 100mV/div, AC
SHDN
OUT
, 5V/div, DC
3) I
, 100mA/div, DC
OUT
LOAD
3) I , 1A/div, DC
IN
T = 200µs/div
T = 40µs/div
LDO Startup Waveform
(LVIN Fast Rising Edge)
LDO Startup Waveform
(LVIN Slow Rising Edge)
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20126308
LDO
= 2.5V, LV = 5V, C
= 2.2µF, I
= 300mA
LDO
= 2.5V, LV = 5V, C
= 2.2µF, I
= 300mA
LOAD
OUT
IN
OUT
LOAD
OUT
IN
OUT
1) LV , 5V/div, DC
1) LV , 5V/div, DC
IN
IN
2) LDO
, 1V/div, DC
2) LDO
, 1V/div, DC
OUT
OUT
T = 100µs/div
T = 4ms/div
GPM Transient Waveforms
GPM Transient Waveforms
20126327
20126328
VGH = 20V, VDPM = 3.3V, C
= 4.7nF, R = 2.4kΩ, C = 33pF, R1 =
VGH = 20V, VDPM = 3.3V, C
= 4.7nF, R = 750Ω, C = 33pF, R1 =
VGHM E E
VGHM
E
E
13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 30kHz
13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 64kHz
1) VFLK, 2V/div, DC
1) VFLK, 2V/div, DC
3) VGHM, 5V/div, DC
3) VGHM, 5V/div, DC
T = 4µs/div
T = 2µs/div
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Typical Performance Characteristics (Continued)
GPM Transient Waveforms
GPM Transient Waveforms
20126398
20126310
VGH = 20V, VDPM = 3.3V, C
= 4.7nF, R = 2.4kΩ, C = open, R1 =
VGH = 20V, VDPM = 3.3V, C
= 4.7nF, R = 750Ω, C = open, R1 =
VGHM E E
VGHM
E
E
13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 30kHz
13kΩ, R2 = 1.2kΩ, VFLK at 50% duty cycle and 64kHz
1) VFLK, 2V/div, DC
1) VFLK, 2V/div, DC
3) VGHM, 5V/div, DC
3) VGHM, 5V/div, DC
T = 4µs/div
T = 2µs/div
17
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Operation
20126302
FIGURE 1. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
CONTINUOUS CONDUCTION MODE
The LM3311 contains a current-mode, PWM boost regulator.
A boost regulator steps the input voltage up to a higher
output voltage. In continuous conduction mode (when the
inductor current never reaches zero at steady state), the
boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 1 (a), the
transistor is closed and the diode is reverse biased. Energy
is collected in the inductor and the load current is supplied by
COUT
.
SOFT-START CAPACITOR
The second cycle is shown in Figure 1 (b). During this cycle,
the transistor is open and the diode is forward biased. The
energy stored in the inductor is transferred to the load and
output capacitor.
The LM3311 has a soft-start pin that can be used to limit the
inductor inrush current on start-up. The external SS pin is
used to tailor the soft-start for a specific application (see the
Linear Regulator (LDO) section for the minimum value of
CSS). When used, a current source charges the external
soft-start capacitor CSS until it reaches its typical clamp
voltage, VSS. The soft-start time can be estimated as:
The ratio of these two cycles determines the output voltage.
The output voltage is defined approximately as:
TSS = CSS*VSS/ISS
THERMAL SHUTDOWN
where D is the duty cycle of the switch, D and D' will be
required for design calculations.
The LM3311 includes thermal shutdown. If the die tempera-
ture reaches 145˚C the device will shut down until it cools to
a safe temperature at which point the device will resume
operation. If the adverse condition that is heating the device
is not removed (ambient temperature too high, short circuit
conditions, etc...) the device will continue to cycle on and off
to keep the die temperature below 145˚C. The thermal shut-
down has approximately 20˚C of hysteresis. When in ther-
mal shutdown the boost regulator, LDO, Op-Amp, and GPM
blocks will all be disabled.
SETTING THE OUTPUT VOLTAGE (BOOST
CONVERTER AND LDO)
The output voltage is set using the feedback pin and a
resistor divider connected to the output as shown in the
typical operating circuit. The feedback pin voltage is 1.263V
for both the boost regulator and the LDO, so the ratio of the
feedback resistors sets the output voltage according to the
following equations:
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oscillation of the amplifier and an increase in power con-
sumption. A good choice for compensation in this case is to
add a 50Ω in series with a 4.7nF capacitor from the output of
the amplifier to ground. This allows for driving zero to infinite
capacitance loads with no oscillations, minimal overshoot,
and a higher slew rate than using a single large capacitor.
The high phase margin created by the external compensa-
tion will guarantee stability and good performance for all
conditions.
Operation (Continued)
INPUT UNDER-VOLTAGE PROTECTION
The LM3311 includes input under-voltage protection (UVP).
The purpose of the UVP is to protect the device both during
start-up and during normal operation from trying to operate
with insufficient input voltage. During start-up using a ramp-
ing input voltage the UVP circuitry ensures that the device
does not begin switching until the input voltage reaches the
UVP On threshold. If the input voltage is present and the
shutdown pin is pulled high the UVP circuitry will prevent the
device from switching if the input voltage present is lower
than the UVP On threshold. During normal operation the
UVP circuitry will disable the device if the input voltage falls
below the UVP Off threshold for any reason. In this case the
device will not turn back on until the UVP On threshold
voltage is exceeded.
Layout and Filtering considerations:
When the power supply for the amplifier (AVIN) is connected
to the output of the switching regulator, the output ripple of
the regulator will produce ripple at the output of the amplifi-
ers. This can be minimized by directly bypassing the AVIN pin
to ground with a low ESR ceramic capacitor. For best noise
reduction a resistor on the order of 5Ω to 20Ω from the
supply being used to the AVIN pin will create and RC filter
and give you a cleaner supply to the amplifier. The bypass
capacitor should be placed as close to the AVIN pin as
possible and connected directly to the AGND plane.
LINEAR REGULATOR (LDO)
The LM3311 includes a Low Dropout Linear Regulator. The
LDO is designed to operate with ceramic input and output
capacitors with values as low as 2.2µF. The efficiency of the
LDO is approximately the output voltage divided by the input
voltage. When using higher input voltages special care
should be taken to not dissipate too much power and cause
excessive heating of the die. The power dissipated in the
LDO section is approximately:
For best noise immunity all bias and feedback resistors
should be in the low kΩ range due to the high input imped-
ance of the amplifier. It is good practice to use a small
capacitance at the high impedance input terminals as well to
reduce noise susceptibility. All resistors and capacitors
should be placed as close to the input pins as possible.
Special care should also be taken in routing of the PCB
traces. All traces should be as short and direct as possible.
The output pin trace must never be routed near any trace
going to the positive input. If this happens cross talk from the
output trace to the positive input trace will cause the circuit to
oscillate.
PD(LDO) = (VIN - VOUT)*IOUT
The LDO has an output undervoltage lockout feature. This
feature is to ensure the LDO will shut itself down in the event
of an output overload or short condition. When the output is
overloaded the output voltage will fall causing the ADJ volt-
age to fall. When the ADJ voltage falls to VADJ(LOW) the LDO
will shut off. In this event the SHDN pin or the input UVP
must be cycled to turn the LDO back on.
The op-amp is not a three terminal device it has 5 terminals:
positive voltage power pin, AGND, positive input, negative
input, and the output. The op-amp "routes" current from the
power pin and AGND to the output pin. So in effect an opamp
has not two inputs but four, all of which must be kept noise
free relative to the external circuits which are being driven by
the op-amp. The current from the power pins goes through
the output pin and into the load and feedback loop. The
current exiting the load and feedback loops then must have
a return path back to the op-amp power supply pins. Ideally
this return path must follow the same path as the output pin
trace to the load. Any deviation that makes the loop area
larger between the output current path and the return current
path adds to the probability of noise pick up.
The LDO output undervoltage lockout is controlled by the SS
voltage. The LDO startup time must be less than the follow-
ing:
TS = CSS*0.5V/ISS
When SS is less than 0.5V the output undervoltage lockout
is disabled and allows the LDO to start up. When SS is
greater than 0.5V the undervoltage lockout is active. If the
LDO feedback voltage is not greater than VADJ(LOW) when
SS reaches 0.5V the LDO may enter an undervoltage lock-
out condition. In most cases CSS = 10nF or greater is suffi-
cient. If a supply other than that used to power VIN is used to
power LVIN care must be taken to apply the input voltage to
GATE PULSE MODULATION
LVIN prior to applying voltage to VIN
.
The Gate Pulse Modulation (GPM) block is designed to
provide a modulated voltage to the gate driver circuitry of a
TFT LCD display. Operation is best understood by referring
to the GPM block diagram in the Block Diagrams section, the
drawing in Figure 2 and the transient waveforms in Figure 3
and Figure 4.
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3311 re-
quires external compensation on the output. Depending on
the equivalent resistive and capacitive distributed load of the
TFT-LCD panel, external components at the amplifier out-
puts may or may not be necessary. If the capacitance pre-
sented by the load is equal to or greater than an equivalent
distibutive load of 50Ω in series with 4.7nF no external
components are needed as the TFT-LCD panel will act as
compensation itself. Distributed resistive and capacitive
loads enhance stability and increase performance of the
amplifiers. If the capacitance and resistance presented by
the load is less than 50Ω in series with 4.7nF, external
components will be required as the load itself will not ensure
stability. No external compensation in this case will lead to
There are two control signals in the GPM block, VDPM and
VFLK. VDPM is the enable pin for the GPM block. If VDPM
is high, the GPM block is active and will respond to the VFLK
drive signal from the timing controller. However, if VDPM is
low, the GPM block will be disabled and both PMOS
switches P2 and P3 will be turned off. The VGHM node will
be discharged through a 1kΩ resistor and the NMOS switch
N2.
When VDPM is high, typical waveforms for the GPM block
can be seen in Figure 2. The pin VGH is typically driven by
a 2x or 3x charge pump. In most cases, the 2x or 3x charge
19
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Operation (Continued)
pump is a discrete solution driven from the SW pin and the
output of the boost switching regulator. When VFLK is high,
the PMOS switch P2 is turned on and the PMOS switch P3
is turned off. With P2 on, the VGHM pin is pulled to the same
voltage applied to the VGH pin. This provides a high gate
drive voltage, VGHMMAX, and can source current to the gate
drive circuitry. When VFLK is high, NMOS switch N3 is on
which discharges the capacitor CE.
20126385
FIGURE 3.
20126384
FIGURE 2.
When VFLK is low, the NMOS switch N3 is turned off which
allows current to charge the CE capacitor. This creates a
delay, tDELAY, given by the following equations:
tDELAY ) 1.265V(CE + 15pF)/ICE
When the voltage on CE reaches about 1.265V and the
VFLK signal is low, the PMOS switch P2 will turn off and the
PMOS switch P3 will turn on connecting resistor R3 to the
VGHM pin through P3. This will discharge the voltage at
VGHM at some rate determined by R3 creating a slope, MR,
as shown in Figure 2. The VGHM pin is no longer a current
source, it is now sinking current from the gate drive circuitry.
As VGHM is discharged through R3, the comparator con-
nected to the pin VDD monitors the VGHM voltage. PMOS
switch P3 will turn off when the following is true:
VGHMMIN ) 10VXR2/(R1 + R2)
where VX is some voltage connected to the resistor divider
on pin VDD. VX is typically connected to the output of the
boost switching regulator. When PMOS switch P3 turns off,
VGHM will be high impedance until the VFLK pin is high
again.
20126386
FIGURE 4.
Figure 3 and Figure 4 give typical transient waveforms for
the GPM block. Waveform (1) is the VGHM pin, (2) is the
VFLK and (3) is the VDPM. The output of the boost switching
regulator is operating at 8.5V and there is a 3x discrete
In the GPM block diagram, a signal called “Reset” is shown.
This signal is generated from the VIN under-voltage lockout,
thermal shutdown, or the SHDN pin. If the VIN supply voltage
drops below 2.3V, typically, then the GPM block will be
disabled and the VGHM pin will discharge through NMOS
switch N2 and the 1kΩ resistor. This applies also if the
junction temperature of the device exceeds 145˚C or if the
SHDN signal is low. As shown in the block diagram, both
VDPM and VFLK have internal 350kΩ pull down resistors.
This puts both VDPM and VFLK in normally “off” states.
Typical VDPM and VFLK pin currents can be found in the
Typical Performance Characteristics section.
~
charge pump ( 23.5V) supplying the VGH pin. In Figure 3
and Figure 4, the VGHM pin is driving a purely capacitive
load, 4.7nF. The value of resistor R1 is 15kohm, R2 is 1.1kΩ
and R3 is 750Ω. In both transient plots, there is no CE delay
capacitor.
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20
RC ≤ 100kΩ (RC can be higher values if CC2 is used, see
High Output Capacitor ESR Compensation) and 68pF ≤ CC
≤ 4.7nF. Refer to the Applications Information section for
recommended values for specific circuits and conditions.
Refer to the Compensation section for other design require-
ment.
Operation (Continued)
INTRODUCTION TO COMPENSATION (BOOST
CONVERTER)
COMPENSATION
This section will present a general design procedure to help
insure a stable and operational circuit. The designs in this
datasheet are optimized for particular requirements. If differ-
ent conversions are required, some of the components may
need to be changed to ensure stability. Below is a set of
general guidelines in designing a stable circuit for continu-
ous conduction operation, in most all cases this will provide
for stability during discontinuous operation as well. The
power components and their effects will be determined first,
then the compensation components will be chosen to pro-
duce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for
most applications, a more exact value can be calculated. To
ensure stability at duty cycles above 50%, the inductor must
have some minimum value determined by the minimum
input voltage and the maximum output voltage. This equa-
tion is:
20126305
FIGURE 5. (a) Inductor current. (b) Diode current.
The LM3311 is a current mode PWM boost converter. The
signal flow of this control scheme has two feedback loops,
one that senses switch current and one that senses output
voltage.
where fs is the switching frequency, D is the duty cycle, and
RDSON is the ON resistance of the internal power switch.
This equation is only good for duty cycles greater than 50%
To keep a current programmed control converter stable
above duty cycles of 50%, the inductor must meet certain
criteria. The inductor, along with input and output voltage,
will determine the slope of the current through the inductor
(see Figure 5 (a)). If the slope of the inductor current is too
great, the circuit will be unstable above duty cycles of 50%.
A 10µH inductor is recommended for most 660 kHz applica-
tions, while a 4.7µH inductor may be used for most 1.28 MHz
applications. If the duty cycle is approaching the maximum of
85%, it may be necessary to increase the inductance by as
much as 2X. See Inductor and Diode Selection for more
detailed inductor sizing.
>
(D 0.5), for duty cycles less than 50% the recommended
values may be used. The value given by this equation is the
inductance necessary to supress sub-harmonic oscillations.
In some cases the value given by this equation may be too
small for a given application. In this case the average induc-
tor current and the inductor current ripple must be consid-
ered.
The corresponding inductor current ripple, average inductor
current, and peak inductor current as shown in Figure 5 (a) is
given by:
The LM3311 provides a compensation pin (VC) to customize
the voltage loop feedback. It is recommended that a series
combination of RC and CC be used for the compensation
network, as shown in the typical application circuit. For any
given application, there exists a unique combination of RC
and CC that will optimize the performance of the LM3311
circuit in terms of its transient response. The series combi-
nation of RC and CC introduces a pole-zero pair according to
the following equations:
Continuous conduction mode occurs when ∆iL is less than
the average inductor current and discontinuous conduction
mode occurs when ∆iL is greater than the average inductor
current. Care must be taken to make sure that the switch will
not reach its current limit during normal operation. The in-
ductor must also be sized accordingly. It should have a
saturation current rating higher than the peak inductor cur-
rent expected. The output voltage ripple is also affected by
the total ripple current.
where RO is the output impedance of the error amplifier,
approximately 900kΩ. For most applications, performance
can be optimized by choosing values within the range 5kΩ ≤
21
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INPUT AND OUTPUT CAPACITOR SELECTION
Operation (Continued)
The switching action of a boost regulator causes a triangular
voltage waveform at the input. A capacitor is required to
reduce the input ripple and noise for proper operation of the
regulator. The size used is dependant on the application and
board layout. If the regulator will be loaded uniformly, with
very little load changes, and at lower current outputs, the
input capacitor size can often be reduced. The size can also
be reduced if the input of the regulator is very close to the
source output. The size will generally need to be larger for
applications where the regulator is supplying nearly the
maximum rated output or if large load steps are expected. A
minimum value of 10µF should be used for the less stressful
condtions while a 22µF to 47µF capacitor may be required
for higher power and dynamic loads. Larger values and/or
lower ESR may be needed if the application requires very
low ripple on the input source voltage.
The output diode for a boost regulator must be chosen
correctly depending on the output voltage and the output
current. The typical current waveform for the diode in con-
tinuous conduction mode is shown in Figure 5 (b). The diode
must be rated for a reverse voltage equal to or greater than
the output voltage used. The average current rating must be
greater than the maximum load current expected, and the
peak current rating must be greater than the peak inductor
current. During short circuit testing, or if short circuit condi-
tions are possible in the application, the diode current rating
must exceed the switch current limit. Using Schottky diodes
with lower forward voltage drop will decrease power dissipa-
tion and increase efficiency.
DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete
feedback loop with the power components, it forms a closed-
loop system that must be stabilized to avoid positive feed-
back and instability. A value for open-loop DC gain will be
required, from which you can calculate, or place, poles and
zeros to determine the crossover frequency and the phase
margin. A high phase margin (greater than 45˚) is desired for
the best stability and transient response. For the purpose of
stabilizing the LM3311, choosing a crossover point well be-
low where the right half plane zero is located will ensure
sufficient phase margin.
The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted RESR) capacitors be used such as
ceramic, polymer electrolytic, or low ESR tantalum. Higher
ESR capacitors may be used but will require more compen-
sation which will be explained later on in the section. The
ESR is also important because it determines the peak to
peak output voltage ripple according to the approximate
equation:
∆VOUT ) 2∆iLRESR (in Volts)
1
To ensure a bandwidth of
⁄2 or less of the frequency of the
A minimum value of 10µF is recommended and may be
increased to a larger value. After choosing the output capaci-
tor you can determine a pole-zero pair introduced into the
control loop by the following equations:
RHP zero, calculate the open-loop DC gain, ADC. After this
value is known, you can calculate the crossover visually by
placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than 1⁄
the RHP zero, the phase
2
margin should be high enough for stability. The phase mar-
gin can also be improved by adding CC2 as discussed later in
this section. The equation for ADC is given below with addi-
tional equations required for the calculation:
Where RL is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be
neglected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section. Some suit-
able capacitor vendors include Vishay, Taiyo-Yuden, and
TDK.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90˚ in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
mc ) 0.072fs (in V/s)
loop should be designed to have a bandwidth of less than 1⁄
2
the frequency of the RHP zero. This zero occurs at a fre-
quency of:
where RL is the minimum load resistance, VIN is the mini-
mum input voltage, gm is the error amplifier transconduc-
tance found in the Electrical Characteristics table, and RD
-
SON is the value chosen from the graph "NMOS RDSON vs.
Input Voltage" in the Typical Performance Characteristics
section.
where ILOAD is the maximum load current.
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22
and Open-loop Gain. The compensation values can be
changed a little more to optimize performance if desired.
This is best done in the lab on a bench, checking the load
step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of RC
should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to tran-
sients. If more detail is required, or the most optimum per-
formance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
Operation (Continued)
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC
and CC is to set a dominant low frequency pole in the control
loop. Simply choose values for RC and CC within the ranges
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
POWER DISSIPATION
where RO is the output impedance of the error amplifier,
approximately 900kΩ. Since RC is generally much less than
RO, it does not have much effect on the above equation and
The output power of the LM3311 is limited by its maximum
power dissipation. The maximum power dissipation is deter-
mined by the formula
can be neglected until a value is chosen to set the zero fZC
.
PD = (Tjmax - TA)/θJA
fZC is created to cancel out the pole created by the output
capacitor, fP1. The output capacitor pole will shift with differ-
ent load currents as shown by the equation, so setting the
zero is not exact. Determine the range of fP1 over the ex-
pected loads and then set the zero fZC to a point approxi-
mately in the middle. The frequency of this zero is deter-
mined by:
where Tjmax is the maximum specified junction temperature
(125˚C), TA is the ambient temperature, and θJA is the ther-
mal resistance of the package.
LAYOUT CONSIDERATIONS
The input bypass capacitor CIN, as shown in the typical
operating circuit, must be placed close to the IC. This will
reduce copper trace resistance which effects input voltage
ripple of the IC. For additional input voltage filtering, a 100nF
bypass capacitor can be placed in parallel with CIN, close to
the VIN pin, to shunt any high frequency noise to ground. The
output capacitor, COUT, should also be placed close to the
IC. Any copper trace connections for the COUT capacitor can
increase the series resistance, which directly effects output
voltage ripple. The feedback network, resistors RFB1 and
RFB2, should be kept close to the FB pin, and away from the
inductor, to minimize copper trace connections that can in-
ject noise into the system. RE and CE should also be close to
the RE and CE pins to minimize noise in the GPM circuitry.
Trace connections made to the inductor and schottky diode
should be minimized to reduce power dissipation and in-
crease overall efficiency. For more detail on switching power
supply layout considerations see Application Note AN-1149:
Layout Guidelines for Switching Power Supplies.
Now RC can be chosen with the selected value for CC.
Check to make sure that the pole fPC is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, CC2, directly from the compensation pin VC to ground, in
parallel with the series combination of RC and CC. The pole
should be placed at the same frequency as fZ1, the ESR
zero. The equation for this pole follows:
The input capacitor, output capacitor, and feedback resistors
for the LDO should be placed as close to the device as
possible to minimize noise and increase stability. Keep the
feedback traces short and connect RADJ2 directly to AGND
close to the device.
To ensure this equation is valid, and that CC2 can be used
without negatively impacting the effects of RC and CC, fPC2
For Op-Amp layout please refer to the Operational Amplifier
section.
must be greater than 10fZC
.
Figure 6, Figure 7, and Figure 8 in the Application Informa-
tion section following show the schematic and an example of
a good layout as used in the LM3310/11 evaluation board.
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover fre-
quency can be checked as described in the section DC Gain
23
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Application Information
20126323
FIGURE 6. Evaluation Board Schematic
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24
Application Information (Continued)
20126324
FIGURE 7. Evaluation Board Layout (top layer)
25
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Application Information (Continued)
20126325
FIGURE 8. Evaluation Board Layout (bottom layer)
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26
Application Information (Continued)
20126329
FIGURE 9. Li-Ion to 8V, 1.28MHz Application
27
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Application Information (Continued)
20126330
FIGURE 10. 5V to 10.5V, 1.28MHz Application
Some recommended Inductors (others may be used)
Manufacturer
Inductor
Contact Information
Coilcraft
DO3316 and DT3316 series
www.coilcraft.com
800-3222645
TDK
SLF10145 series
www.component.tdk.com
847-803-6100
Pulse
P0751 and P0762 series
www.pulseeng.com
www.sumida.com
Sumida
CDRH8D28 and CDRH8D43 series
Some recommended Input and Output Capacitors (others may be used)
Manufacturer
Capacitor
Contact Information
Vishay Sprague
293D, 592D, and 595D series tantalum
www.vishay.com
407-324-4140
Taiyo Yuden
High capacitance MLCC ceramic
www.t-yuden.com
408-573-4150
ESRD seriec Polymer Aluminum Electrolytic
SPV and AFK series V-chip series
High capacitance MLCC ceramic
EEJ-L series tantalum
Cornell Dubilier
Panasonic
www.cde.com
www.panasonic.com
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28
Physical Dimensions inches (millimeters) unless otherwise noted
LLP-24 Pin Package (SQA)
For Ordering, Refer to Ordering Information Table
NS Package Number SQA24A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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(b) support or sustain life, and whose failure to perform when
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