74LVX163SJX [NSC]
Low Voltage Synchronous Binary Counter with Synchronous Clear; 低压同步二进制计数器，同步清除
| 型号： | 74LVX163SJX |
| 厂家： | 
National Semiconductor |
| 描述： | Low Voltage Synchronous Binary Counter with Synchronous Clear |
| 文件： | 总8页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1996
74LVX163
Low Voltage Synchronous Binary Counter with
Synchronous Clear
General Description
The LVX163 is a synchronous modulo-16 binary counter.
This device is synchronously presettable for application in
programmable dividers and has two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
multistage counters. The CLK input is active on the rising
edge. Both PE and CLR inputs are active on low logic lev-
els. Presetting is synchronous to rising edge of CLK and the
Clear function of the LVX163 is synchronous to CLK. Two
enable inputs (ENP and ENT) and Carry Output are provid-
ed to enable easy cascading of counters, which facilitates
easy implementation of n-bit counters without using external
gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
Y
Input voltage level translation from 5V to 3V
Y
Ideal for low power/low noise 3.3V applications
Y
Available in SOIC JEDEC, SOIC EIAJ, and TSSOP
packages
Y
Guaranteed simultaneous switching noise and dynamic
threshold performance
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Assignment for
TSSOP and SOIC
TL/F/12157–1
TL/F/12157–3
TL/F/12157–2
Pin
SOIC JEDEC
SOIC EIAJ
TSSOP
Description
Names
Order Number
74LVX163M
74LVX163SJ
74LVX163MTC
74LVX163MTCX
CEP
CET
CP
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
74LVX163MX
74LVX163SJX
See NS Package
Number
M16A
M16D
MTC16
MR
Synchronous Master Reset Input
Parallel Data Inputs
P
0
–P
3
PE
Parallel Enable Inputs
Flip-Flop Outputs
Q
–Q
3
0
TC
Terminal Count Output
C
1996 National Semiconductor Corporation
TL/F/12157
RRD-B30M17/Printed in U. S. A.
http://www.national.com
Functional Description
The LVX163 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs occur as a result
of, and synchronous with, the LOW-to-HIGH transition of
the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: synchronous
reset, parallel load, count-up and hold. Four control inputsÐ
Synchronous Reset (MR), Parallel Enable (PE), Count En-
able Parallel (CEP) and Count Enable Trickle (CET)Ðdeter-
mine the mode of operation, as shown in the Mode Select
Table. A LOW signal on MR overrides counting and parallel
loading and allows all outputs to go LOW on the next rising
edge of CP. A LOW signal on PE overrides counting and
nous reset for flip-flops, registers or counters. When the
Output Enable (OE) is LOW, the parallel data outputs O –
0
are active and follow the flip-flop Q outputs. A HIGH
O
signal on OE forces O –O to the High Z state but does not
3
0
3
prevent counting, loading or resetting.
e
Logic Equations: Count Enable
CEP CET PE
#
#
CET
e
TC
Q
Q
Q
Q
#
#
#
#
3
0
1
2
Mode Select Table
Action on the Rising
MR
PE
CET
CEP
Clock Edge ( L )
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)
Load (Pn x Q )
n
allows information on the Parallel Data (P ) inputs to be
n
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
loaded into the flip-flops on the next rising edge of CP. With
PE and MR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
X
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
The LVX163 uses D-type edge-triggered flip-flops and
changing the MR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
X
State Diagram
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC de-
lays of the intermediate stages, plus the CET to CP setup
time of the last stage. This total delay plus setup time sets
the upper limit on clock frequency. For faster clock rates,
the carry lookahead connections shown in Figure 2 are rec-
ommended. In this scheme the ripple delay through the in-
termediate stages commences with the same clock that
causes the first stage to tick over from max to min in the Up
mode, or min to max in the Down mode, to start its final
cycle. Since this final cycle takes 16 clocks to complete,
there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock
period is the CP to TC delay of the first stage plus the CEP
to CP setup time of the last stage. The TC output is subject
to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
TL/F/12157–4
TL/F/12157–5
FIGURE 1
TL/F/12157–6
FIGURE 2
http://www.national.com
2
Block Diagram
3
http://www.national.com
Absolute Maximum Ratings (Note)
b
a
0.5V to 7.0V
Supply Voltage (V
)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
CC
DC Input Diode Current (I
e b
)
IK
b
V
I
0.5V
20 mA
b
DC Input Voltage (V )
I
0.5V to 7V
DC Output Diode Current (I
)
OK
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
e
V
CC
0.5V
b
a
DC Output Voltage (V
DC Output Source
)
0.5V to V
CC
0.5V
25 mA
50 mA
O
Recommended Operating
Conditions
g
or Sink Current (I
)
O
Supply Voltage (V
)
CC
2.0V to 3.6V
0V to 5.5V
DC V
or Ground Current
)
CC
(I or I
Input Voltage (V )
I
g
CC GND
Output Voltage (V
)
0V to V
CC
b
a
65 C to 150 C
O
Storage Temperature (T
)
§
§
180 mW
STG
b
a
40 C to 85 C
§
0 ns/V to 100 ns/V
Operating Temperature (T )
A
§
Power Dissipation
Input Rise and Fall Time (D /D )
t
v
DC Electrical Characteristics
74LVX163
74LVX163
e
T
A
e a
Symbol
Parameter
V
CC
Units
Conditions
T
25 C
§
A
b
a
40 C to 85 C
§
§
Min
Typ
Max
Min
Max
V
V
V
V
High Level
Input
Voltage
2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
IH
V
V
V
Low Level
Input
Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
IL
e
e
e b
e b
e b
High Level
Output
Voltage
2.0
3.0
3.0
1.9
2.9
2.0
3.0
1.9
2.9
V
V
V
V
or V
or V
I
I
I
50 mA
50 mA
4 mA
OH
OL
IN
IL
IH
OH
OH
OH
2.58
2.48
e
e
e
Low Level
Output
Voltage
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.1
0.1
I
I
I
50 mA
IN
IL
IH
OL
OL
OL
V
50 mA
0.36
0.44
4 mA
e
e
g
g
1.0
I
I
Input
Leakage
Current
3.6
0.1
mA
V
V
5.5V or GND
IN
IN
Quiescent
Supply
Current
3.6
2.0
20.0
mA
V
CC
or GND
CC
IN
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4
Noise Characteristics
LVX163
V
CC
e
Symbol
Parameter
T
A
25 C
§
Units
C (pF)
L
(V)
Typ
Limits
0.5
V
V
V
V
*
*
Quiet Output Maximum
50
OLP
3.3
3.3
3.3
3.3
0.2
V
V
V
V
Dynamic V
OL
Quiet Output Minimum
Dynamic V
50
50
50
OLV
b
b
0.5
0.2
OL
*
Minimum High Level
IHD
2.0
0.8
Dynamic Input Voltage
*
Maximum Low Level
ILD
Dynamic Input Voltage
*Parameter guaranteed by design.
AC Electrical Characteristics
LVX163
LVX163
e b
a
V
T
A
40 C
CC
§
to 85 C
e
Symbol
Parameter
Units
Conditions
T
A
25 C
§
(V)
§
Min
Typ
9.0
Max
14.0
17.0
12.8
16.3
14.3
18.5
13.6
17.1
18.0
21.0
17.2
20.7
13.5
16.5
12.3
15.8
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
65
Max
16.0
19.0
15.0
18.5
16.7
20.5
16.0
19.5
21.0
24.0
20.0
23.5
15.0
18.5
14.5
18.0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
t
t
,
,
,
,
Propagation Delay
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
PLH
2.7
ns
ns
Time (CP–Q )
n
PHL
11.3
8.3
g
3.3 0.3
10.8
9.5
t
t
Propagation Delay
PLH
PHL
2.7
ns
Time (CP–TC, Count)
12.5
8.7
g
3.3 0.3
ns
11.2
11.4
14.0
11.0
13.5
8.6
t
t
Propagation Delay
PLH
PHL
2.7
ns
Time (CP–TC, Load)
g
3.3 0.3
ns
t
t
Propagation Delay
Time (CET–TC)
PLH
PHL
2.7
ns
11.0
7.5
g
3.3 0.3
ns
10.5
115
80
f
Maximum Clock
Frequency
75
50
80
55
max
2.7
MHz
MHz
45
130
85
70
g
3.3 0.3
50
e
CC
C
C
Input Capacitance
4
10
10
pF
pF
V
Open
IN
Power Dissipation
Capacitance
(Note 1)
PD
23
Note 1: C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I
e
a
I
CC
(opr)
C
PD
* V
* f
IN
.
CC
CC
When the outputs drive a capacitive load, total current consumption is the sum of C , and DI
PD
which is obtained from the following formula:
CC
C
C
C
C
C
QO
2
Q1
Q2
Q3
TC
e
a
a
a
a
DI
CC
F
CP
V
#
CC
4
8
16
16
#
J
C
–C and C are the capacitances at Q0–Q3 and TC, respectively. F is the input frequency of the CP.
TC
Q0
Q3
CP
5
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AC Operating Requirements
LVX163
LVX163
e b
40 C
V
T
§
CC
A
e
Symbol
Parameter
T
25 C
§
Units
Conditions
A
a
to 85 C
(V)
§
Guaranteed Minimum
t
t
t
t
t
t
t
t
Minimum Setup Time
2.7
5.5
5.5
6.5
6.5
S
S
S
S
H
H
H
H
ns
ns
ns
ns
ns
ns
ns
ns
ns
g
3.3 0.3
(P –CP)
n
Minimum Setup Time
(PE–CP)
2.7
8.0
8.0
9.5
9.5
g
3.3 0.3
Minimum Setup Time
(CEP or CET–CP)
2.7
7.5
7.5
9.0
9.0
g
3.3 0.3
Minimum Setup Time
(MR–CP)
2.7
4.0
4.0
4.0
4.0
g
3.3 0.3
Minimum Hold Time
2.7
1.0
1.0
1.0
1.0
g
3.3 0.3
(P –CP)
n
Minimum Hold Time
(PE–CP)
2.7
1.0
1.0
1.0
1.0
g
3.3 0.3
Minimum Hold Time
(CEP or CET–CP)
2.7
1.0
1.0
1.0
1.0
g
3.3 0.3
Minimum Hold Time
(MR–CP)
2.7
1.5
1.5
1.5
1.5
g
3.3 0.3
t
t
(L)
Minimum Pulse Width
CP (Count)
2.7
5.0
5.0
5.0
5.0
W
g
3.3 0.3
(H)
W
Ordering Information
The device number is used to form part of a simplified purchasing code, where the package type and temperature range are
defined as follows:
TL/F/12157–8
http://www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Molded JEDEC SOIC
Order Number 74LVX163M
NS Package Number M16A
16-Lead Molded EIAJ SOIC
Order Number 74LVX163SJ
NS Package Number M16D
7
http://www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Molded JEDEC Type 1 TSSOP
Order Number 74LVX163MTC
NS Package Number MTC16
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be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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