DP7172 [NIDEC]
256-Position SPI;
| 型号： | DP7172 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | 256-Position SPI |
| 文件： | 总11页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7172
256-Position SPI
Compatible Digital
Potentiometer
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MARKING DIAGRAM
ADYM
AEYM
Features
1
1
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AD = 50 k
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AE = 100 k
Y = Production Year
Y = (Last Digit)
M = Production Month
M = (1 ï 9, A, B, C)
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A
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B
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Typical Applications
GND
CLK
CS
SDI
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ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
¢
2009 NIDEC COPAL ELECTRONICS CORP.
1
Publication Order Number:
May, 2009 ï Rev. 0
DP7172/D
DP7172
V
DD
CS
SDI
CLK
SPI
A
INTERFACE
W
B
WIPER
REGISTER
GND
Figure 1. Functional Block Diagram
Table 1. ORDERING INFORMATION
Part Number
Resistance
Temperature Range
Package
Shipping
DP7172TBIï50-GT3
DP7172TBIï00-GT3
50 k
3000/Tape & Reel
3000/Tape & Reel
SOTï23ï8
(PbïFree)
ï40oC to 85oC
100 k
Table 2. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
2
3
4
5
6
7
8
W
Resistor·s Wiper Terminal.
Positive Power Supply.
Digital Ground.
V
DD
GND
CLK
SDI
CS
B
Serial Clock Input. Positive edge triggered.
Serial Data Input.
Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register.
Bottom Terminal of resistive element.
A
Top Terminal of resistive element.
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1)
Rating
Value
Unit
V
DD
to GND
ï0.3 to 6.5
V
V , V , V to GND
V
DD
A
B
W
I
p20
0 to 6.5
ï40 to +85
150
mA
V
MAX
Digital Inputs and Output Voltage to GND
Operating Temperature Range
oC
oC
oC
oC
Maximum Junction Temperature (T
Storage Temperature
)
JMAX
ï65 to +150
300
Lead Temperature (Soldering, 10 sec)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and
maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
2
DP7172
Table 4. ELECTRICAL CHARACTERISTICS: 50 k and 100 k Versions
V
DD
= 5 V (10%, or 3 V (10%; V = V ; V = 0 V; –40$C < T < +85$C; unless otherwise noted.
A
DD
B
A
Typ
(Note 2)
Parameter
Test Conditions
Symbol
Min
Max
Unit
DC CHARACTERISTICS — RHEOSTAT MODE
Resistor Differential Nonlinearity (Note 3)
Resistor Integral Nonlinearity (Note 3)
Nominal Resistor Tolerance (Note 4)
R
R
, V = no connection
RïDNL
RïINL
ï1
ï2
(0.1
(0.4
+1
+2
LSB
LSB
WB
A
, V = no connection
WB
A
TA = 25$C
R
AB
ï20
+20
%
Resistance Temperature Coefficient
Wiper Resistance
V
AB
= V , Wiper = no connection
R
/ T
100
50
ppm/$C
DD
AB
V
DD
V
DD
= 5 V
= 3 V
R
120
250
W
100
DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE
Resolution
N
8
Bits
LSB
Differential Nonlinearity (Note 5)
Integral Nonlinearity (Note 5)
DNL
INL
ï1
ï1
(0.1
(0.4
100
ï1
+1
+1
LSB
Voltage Divider Temperature Coefficient
FullïScale Error
Code = 0x80
V / T
W
ppm/$C
LSB
Code = 0xFF
Code = 0x00
V
ï3
0
3
WFSE
WZSE
ZeroïScale Error
V
0
1
LSB
RESISTOR TERMINALS
Voltage Range (Note 6)
Capacitance (Note 7) A, B
V
GND
V
DD
V
A,B,W
f = 1 MHz, measured to GND,
Code = 0 x 80
C
45
60
1
pF
A,B
Capacitance (Note 7) W
f = 1 MHz, measured to GND,
Code = 0 x 80
C
W
pF
nA
CommonïMode Leakage (Note 7)
DIGITAL INPUTS
V = V = V /2
I
CM
A
B
DD
Input Logic High
V
DD
V
DD
V
DD
V
DD
= 5 V
V
0.7 x V
0.7 x V
V
V
IH
DD
Input Logic Low
= 5 V
= 3 V
= 3 V
V
0.3V
0.3V
IL
DD
Input Logic High
V
IH
V
DD
Input Logic Low
V
V
IL
DD
Input Current
V
IN
= 0 V or 5 V
I
IL
(1
A
Input Capacitance (Note 7)
POWER SUPPLIES
Power Supply Range
Supply Current
C
5
pF
IL
VDD RANGE
2.7
5.5
2
V
A
V
IH
= 5 V or V = 0 V
I
DD
0.3
IL
Power Dissipation (Note 8)
Power Supply Sensitivity
V
= 5 V or V = 0 V, V = 5 V
P
DISS
0.2
mW
%/%
IH
IL
DD
V
DD
= +5 V (10%, Code = Midscale
PSS
(0.05
2. Typical specifications represent average readings at +25$C and V = 5 V.
DD
3. Resistor position nonlinearity error RïINL is the deviation from an ideal value measured between the maximum resistance and the minim-
um resistance wiper positions. RïDNL measures the relative step change from ideal between successive tap positions. Parts are guaran-
teed monotonic.
4. V = V , Wiper (V ) = no connect.
AB
DD
W
5. INL and DNL are measured at VW with the DP configured as a potentiometer divider similar to a voltage output D/A converter. V = V
A
DD
and V = 0 V. DNL specification limits of (1 LSB maximum are guaranteed monotonic operating conditions.
B
6. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
7. Guaranteed by design and not subject to production test.
8. PDISS is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.
DD
DD
9. All dynamic characteristics use V = 5 V.
DD
3
DP7172
Table 4. ELECTRICAL CHARACTERISTICS: 50 k and 100 k Versions (continued)
V
DD
= 5 V (10%, or 3 V (10%; V = V ; V = 0 V; –40$C < T < +85$C; unless otherwise noted.
A
DD
B
A
Typ
(Note 2)
Parameter
DYNAMIC CHARACTERISTICS (Notes 7 and 9)
Test Conditions
Symbol
Min
Max
Unit
Bandwidth –3 dB
R
AB
= 50 k / 100 k , Code = 0x80
BW
100/40
0.05
kHz
%
Total Harmonic Distortion
V =1 V rms, V = 0 V,
THD
W
A
B
f = 1 kHz, R = 10 k
AB
V
W
Settling Time (50 k /100 k
)
V = 5 V, V = 0 V, (1 LSB error band
t
S
2
s
A
B
2. Typical specifications represent average readings at +25$C and V = 5 V.
DD
3. Resistor position nonlinearity error RïINL is the deviation from an ideal value measured between the maximum resistance and the minim-
um resistance wiper positions. RïDNL measures the relative step change from ideal between successive tap positions. Parts are guaran-
teed monotonic.
4. V = V , Wiper (V ) = no connect.
AB
DD
W
5. INL and DNL are measured at VW with the DP configured as a potentiometer divider similar to a voltage output D/A converter. V = V
A
DD
and V = 0 V. DNL specification limits of (1 LSB maximum are guaranteed monotonic operating conditions.
B
6. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
7. Guaranteed by design and not subject to production test.
8. PDISS is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.
DD
DD
9. All dynamic characteristics use V = 5 V.
DD
Table 5. TIMING CHARACTERISTICS: 50 k and 100 k Versions
V
DD
= 5 V ( 10%, or 3 V ( 10%; V = V ; V = 0 V; –40$C < T < +85$C; unless otherwise noted.
A
DD
B
A
Typ
(Note 10)
Parameter
Test Conditions
Symbol
Min
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS (Notes 11 and 12) (Specifications Apply to All Parts)
Clock Frequency
f
25
MHz
ns
CLK
Input Clock Pulse width
Data Setup Time
Clock level high or low
t
, t
20
5
CH CL
t
ns
DS
DH
Data Hold Time
t
5
ns
CS Setup Time
T
15
40
0
ns
CSS
CSW
CSH0
CSH1
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
T
ns
T
T
ns
0
ns
T
10
ns
CS1
10.Typical specifications represent average readings at +25$C and V = 5 V.
DD
11. Guaranteed by design and not subject to production test.
12.See timing diagram for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of 3 V) and timed
R
F
from a voltage level of 1.5 V.
4
DP7172
SPI Interface
Table 6. DP7172 SERIAL DAT$ïWORD FORMAT
B7
B6
B5
B4
B3
B2
B1
B0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
7
0
2
2
CS
1
2
3
4
5
6
7
8
CLK
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
SDI
V1
V
OUT
V2
Figure 2. DP7172 SPI Interface Timing Diagram (V A = 5 V, VB = 0 V, VW = VOUT
)
1
SDI
Dx
Dx
(DATA IN)
0
1
0
t
DS
t
t
t
DH
CH
CS1
CLK
t
CSH1
t
t
CL
CSHO
t
CSS
1
0
CS
t
CSW
t
S
V
W
(1 LSB
VOUT
V
W0
Figure 3. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT
)
5
DP7172
TYPICAL CHARACTERISTICS
0.03
0.02
0.01
0
0.1
0
ï0.1
ï0.2
ï0.3
DNL
INL
ï0.01
ï0.02
ï0.03
ï0.4
ï0.5
ï0.04
ï0.05
0
32
64
96
128
TAP
160
192
224 256
0
32
64
96
128
160
192
224 256
TAP
Figure 4. Differential NonïLinearity,
CC = 5.6 V
Figure 5. Integral NonïLinearity,
V
VCC = 5.6 V
120
100
80
6
5
4
3
2
5.6 V
5.0 V
V
= 2.6 V
CC
4.0 V
3.3 V
60
3.3 V
5.6 V
40
V
= 2.6 V
CC
20
0
1
0
4.0 V
0
50
100
150
200
250
0
52
104
156
208
260
TAP
TAP
Figure 6. Wiper Resistance at Room
Temperature
Figure 7. Wiper Voltage
0.4
0.2
102.15
102.10
102.05
102.00
101.95
101.90
101.85
0
101.80
101.75
ï0.2
ï50
ï20
10
40
70
100
ï50
ï20
10
40
70
100
TEMPERATURE ($C)
TEMPERATURE ($C)
Figure 8. Change in EndïtoïEnd Resistance
Figure 9. EndïtoïEnd Resistance vs.
Temperature
6
DP7172
TYPICAL CHARACTERISTICS
400
CS
350
T = 90$C
T = ï45$C
300
250
200
W
T = 25$C
150
100
2
3
4
5
6
V
(V)
Figure 10. Wiper·s Transition from Position
0xFF to Position 0x00 Relative to the CS
Disable, VCC = 5 V
CC
Figure 11. Standby Current
0
ï6
30
25
20
15
10
V
= 5 V
CC
ï12
ï18
V
CC
= 5 V
V
CC
= 3 V
V
CC
= 3 V
ï24
ï30
ï36
5
0
1
10
100
1000
1
10
100
1000
f (KHz)
f (KHz)
Figure 12. Gain vs. Bandwidth (Tap 0x80)
Figure 13. PSRR
7
DP7172
A
Basic Operation
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Figure 14. DP7172 Equivalent DP Circuit
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Programming: Variable Resistor
Rheostat Mode
D
RWB
RAB RW
(eq. 1)
256
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W
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256
D
RWA(D)
RAB RW
(eq. 2)
256
8
DP7172
Terminal Voltage Operating Range
For R = 100 k and the B terminal open circuited, the
AB
The DP7172 V
and GND power supply define the
following output resistance R will be set for the indicated
DD
WA
limits for proper 3ïterminal digital potentiometer operation.
Wiper register codes.
Signals or potentials applied to terminals A, B or the wiper
Table 8. CODES AND CORRESPONDING RWA
RESISTANCE FOR RAB = 100 k , VDD = 5 V
must remain inside the span of V
and GND. Signals
DD
which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
D (Dec.)
R
WA
( )
Output State
255
128
1
441
Full Scale
Midscale
1 LSB
V
DD
50,050
99,659
100,050
0
Zero Scale
W, A, B
LOGIC
Typical device to device resistance matching is lot
dependent and may vary by up to (20%.
DP7172
SPI Compatible 3ïWire Serial Bus
Control of DP7172 is through a ꢍïZLUH SPI compatible
digital interface (SDI, CS, and CLK).
The CLK input is risingïedge sensitive and requires crisp
transitions to avoid clocking incorrect data into the serial
input register. When CS is low, the clock loads data into the
serial register on each positive clock edge (Figure 1). Each
8ïbit serial word must be loaded starting with the MSB. The
format of the word is shown in Table 6.
GND
Figure 16.
Powerïup Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 15), it is
Data loaded into '3ꢆꢉꢆꢀ·V ꢏïELW serial input register is
transferred to the internal Wiper register when the CS line
returns to logic high. Extra MSB bits are ignored.
recommended that V /GND be powered before applying
DD
any voltage to terminals A, B, and W. The ideal powerïup
sequence is: GND, V , digital inputs, and then V
. The
DD
A
A/B/W
order of powering V , V , V , and the digital inputs is not
B
W
ESD Protection
important as long as they are powered after V /GND.
DD
Digital
Power Supply Bypassing
LOGIC
Input
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01 F to
0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
GND
Potentiometer
V
DD
V
DD
+
C
C
1
3
DP7172
0.1
F
10
F
GND
GND
Figure 15. ESD Protection Networks
Figure 17. Power Supply Bypassing
9
DP7172
PACKAGE DIMENSIONS
SOTï23, 8 Lead
SYMBOL
MIN
NOM
MAX
1.45
0.15
1.30
0.80
0.38
0.22
A
A1
A2
A3
b
0.90
0.00
0.90
0.60
0.28
0.08
1.10
E1
E
c
D
2.90 BSC
2.80 BSC
1.60 BSC
E
E1
e
b
e
L
0.65 BSC
0.45
PIN #1 IDENTIFICATION
0.30
0.60
TOP VIEW
L1
0.60 REF
0.25 REF
L2
Q
0°
8°
D
A2
A
c
A3
A1
L1
L
L2
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
DP7172/D
10
NIDEC COPAL ELECTRONICS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
NIDEC COPAL ELECTRONICS CORP. product s are not de signe d, int e nde d, or aut horize d for use as compone nt s in syst e ms int e nde d for surgical implant int o t he body, or
ot he r applicat ions int e nde d t o support or sust ain life , or for any ot he r applicat ion in which t he failure of t he NIDEC COPAL ELECTRONICS CORP. product could cre at e a
sit uat ion where personal injury or deat h may occur.
NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s
labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.
NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e
t ypical semiconduct or applicat ions and may not be complet e.
NIDEC COPAL ELECTRONICS CORP.
Japan Head Office
Nishi-Shinjuku, Kimuraya Bldg.,
7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023
Phone: +81-3-3364-7055
Fax: +81-3-3364-7098
www.nidec-copal-electronics.com
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