DP7269 [NIDEC]
Dual Digital Potentiometers;
| 型号： | DP7269 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | Dual Digital Potentiometers |
| 文件： | 总16页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7269
Dual Digital Potentiometers
(DP) with 256 Taps and 2-wire Interface
FEATURES
DESCRIPTION
Four linear taper digital potentiometers
The DP7269 is two digital potentiometers
(DPs) integrated with control logic and 18 bytes
256 resistor taps per potentiometer
of NVRAM memory. Each DP consists of
a
End to end resistance 50k or 100k
series of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
registers.
Potentiometer control and memory access via
2-wire interface (I2C like)
Low wiper resistance, typically 100
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and TSSOP packages
Industrial temperature range
The DP7269 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40ºC to 85ºC
industrial operating temperature ranges and offered in
a 24-lead SOIC and TSSOP package.
For Ordering Information details, see page 15.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
R
H0
R
H1
NC
A0
1
2
3
4
5
6
7
8
9
24 A3
WIPER
CONTROL
REGISTERS
2-WIRE BUS
INTERFACE
SCL
SDA
23 SCL
22 NC
21 NC
20 NC
19 NC
18 GND
17 RW1
16 RH1
15 RL1
14 A1
R
R
W0
NC
NC
NC
NC
VCC
RLO
RHO
W1
WP
A0
A1
A2
A3
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
R
L0
R
L1
RWO 10
A2 11
¯¯¯
WP
12
13 SDA
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2123 Rev. D
DP7269
PIN DESCRIPTIONS
PIN DESCRIPTION
SCL: Serial Clock
Pin #
1
Name Function
The DP7269 serial clock input pin is used to
clock all data transfers into or out of the
device.
NC
A0
No Connect
2
Device Address, LSB
No Connect
SDA: Serial Data
3
NC
NC
NC
NC
VCC
RL0
RH0
RW0
A2
The DP7269 bidirectional serial data pin is
used to transfer data into and out of the
device. The SDA pin is an open drain output
and can be wire-Ored with the other open
drain or open collector I/Os.
4
No Connect
5
No Connect
6
No Connect
7
Supply Voltage
8
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
A0, A1, A2, A3: Device Address Inputs
9
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate
communication with the DP7269.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
¯¯¯
WP
Write Protection
SDA
A1
Serial Data Input/Output
Device Address
RH, RL: Resistor End Points
The two sets of RH and RL pins are equivalent
to the terminal connections on a mechanical
potentiometer.
RL1
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
RH1
RW1
GND
NC
RW: Wiper
The RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
No Connect
NC
No Connect
¯¯¯
WP: Write Protect Input
NC
No Connect
¯¯¯
The WP pin when tied low prevents non-
NC
No Connect
volatile writes to the data register (change of
wiper control register is allowed) and when
tied high or left floating normal read/write
operations are allowed. See Write Protection
on page 7 for more details.
SCL
A3
Bus Serial Clock
Device Address
DEVICE OPERATION
The DP7269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and
eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the
output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected
to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or
written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional
instructions allow data to be transferred between the wiper control registers and each respective potentiometer's
non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2123 Rev. D
2
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC + 2.0
-2.0 to +7.0
1.0
Units
ºC
Temperature Under Bias
Storage Temperature
°C
V
(1) (2)
Voltage on Any Pin with Respect to VSS
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25ºC)
Lead Soldering Temperature (10secs)
Wiper Current
W
300
ºC
6
mA
RECOMMENDED OPERATING CONDITIONS
Parameters
VCC
Ratings
+2.5 to +6
-40 to +85
Units
V
Industrial Temperature
°C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol Parameter
Test Conditions
Units
Min
Typ.
100
50
Max
RPOT
RPOT
Potentiometer Resistance (100k)
k
k
Potentiometer Resistance (50k)
Potentiometer Resistance
Tolerance
RPOT Matching
20
1
%
%
mW
mA
Power Rating
25°C, each pot
50
IW
RW
Wiper Current
3
Wiper Resistance
IW = 3mA @ VCC = 3V
IW = 3mA @ VCC = 5V
VSS = 0V
200
100
300
150
VCC
RW
Wiper Resistance
VTERM
Voltage on any RH or RL Pin
Resolution
Absolute Linearity (5)
Relative Linearity (6)
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
VSS
V
0.4
%
(8)
Rw(n)(actual)-R(n)(expected)
1
LSB (7)
LSB (7)
ppm/ºC
ppm/ºC
pF
(8)
Rw(n+1)-[Rw(n)+LSB]
0.2
TCRPOT
TCRATIO
(4)
(4)
(4)
300
20
CH/CL/CW Potentiometer Capacitances
fc Frequency Response
10/10/25
0.4
(4)
RPOT = 50k
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = RTOT / 255 or (RH - RL) / 255, single pot
(8) n = 0, 1, 2, ..., 255
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
3
Doc. No. MD-2123 Rev. D
DP7269
D.C. OPERATING CHARACTERISTICS
V
CC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter Test Conditions
SCL = 400kHz, SDA = Open
VCC = 6V, Inputs = GND
SCK = 400kHz, SDA Open
Min
Max
Units
f
ICC1
ICC2
Power Supply Current
1
mA
Power Supply Current
Non-volatile WRITE
f
5
mA
VCC = 6V, Input = GND
VIN = GND or VCC, SDA = Open
VIN = GND to VCC
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
5
10
µA
µA
µA
V
ILO
VOUT = GND to VCC
10
VIL
VIH
VOL1
-1
VCC x 0.3
Input High Voltage
VCC x 0.7 VCC + 1.0
0.4
V
Output Low Voltage (VCC = 3.0V) IOL = 3mA
V
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol Test
Conditions
Max
8
Units
pF
(1)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
VI/O = 0V
VIN = 0V
(1)
¯¯¯
CIN
6
pF
A.C. CHARACTERISTICS
2.5V - 6.0V
Symbol Parameter
Units
kHz
ns
Min
Max
400
200
1
fSCL
TI(1)
tAA
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
µs
(1)
tBUF
Time the bus must be free before a new transmission can start
Start Condition Hold Time
1.2
0.6
1.2
0.6
0.6
0
µs
tHD:STA
tLOW
µs
Clock Low Period
µs
tHIGH
Clock High Period
µs
tSU:STA
tHD:DAT
tSU:DAT
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
µs
ns
Data in Setup Time
50
ns
(1)
tR
SDA and SCL Rise Time
0.3
µs
(1)
tF
SDA and SCL Fall Time
300
ns
tSU:STO
tDH
Stop Condition Setup Time
Data Out Hold Time
0.6
µs
100
ns
Note:
This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2123 Rev. D
4
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
POWER UP TIMING (1)(2)
Symbol Parameter
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
DP TIMING
Symbol Parameter
tWRPO Wiper Response Time After Power Supply Stable
tWRL Wiper Response Time After Instruction Issued
Max
10
Units
µs
10
µs
WRITE CYCLE LIMITS (3)
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
V
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
(1)
ILTH
100
mA
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Figure 1. Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2123 Rev. D
DP7269
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
When the DP7269 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the DP7269 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
DP7269 will be considered a slave device in all
applications.
Write Operations
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of DP7269. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The DP7269
acknowledges once more and the Master generates
the STOP condition, at which time if a nonvolatile data
register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The DP7269 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
Acknowledge Polling
DEVICE ADDRESSING
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the DP7269 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the DP7269 is still
busy with the write operation, no ACK will be returned.
If the DP7269 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the DP7269 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
After the Master sends a START condition and the
slave address byte, the DP7269 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
¯¯¯
data registers. If the WP pin is tied to LOW, the data
registers are protected and become read only.
¯¯¯
Similarly, the WP pin going low after start will interrupt
Acknowledge
¯¯¯
a nonvolatile write to data registers, while the WP pin
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
going low after an internal write cycle has stated will
have no effect on any write operation (see also
DP7409 or DP7259). The DP7269 will accept both
slave addresses and instructions, but the data registers
are protected from programming by the device’s failure
to send an acknowledge after data is received.
The DP7269 responds with an acknowledge after
receiving a START condition and its slave address. If
Doc. No. MD-2123 Rev. D
6
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
START
ADDRESS
CONDITION
CONDITION
Figure 3. Start/Stop Condition
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. Acknowledge Condition
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
DP7269
0
1
0
1
A3 A2 A1 A0
*
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
7
Doc. No. MD-2123 Rev. D
DP7269
inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
INSTRUCTION AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
SLAVE ADDRESS BYTE
The next byte sent to the DP7269 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I3 - I0. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
The first byte sent to the DP7269 from the
master/processor is called the Slave/DP Address
Byte. The most significant four bits of the slave
address are a device type identifier. These bits for the
DP7269 are fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the DP7269 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A3 - A0
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
0
1
Figure 6. Write Timing
S
SLAVE/DP
ADDRESS
INSTRUCTION
T
A
R
T
S
T
BYTE
BUS ACTIVITY:
MASTER
Register
O
P
Pot1 WCR
Address
DR1 WCRDATA
Fixed
Variable
op code
Address
SDA LINE
S
P
A
C
K
A
A
C
K
C
K
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
A3
A2
A1
A0
1
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
Doc. No. MD-2123 Rev. D
8
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 10ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The DP7269 contains two 8-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of
256 switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be
written by the host via Write Wiper Control Register
instruction; it may be written by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction, it can be modified
one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in the
WCR
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
The Wiper Control Register is a volatile register that
loses its contents when the DP7269 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Read Data Register – read the contents of the
selected Data Register
— Write Data Register – write a new value to the
Data Registers (DR)
selected Data Register
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
Table 3. Instruction Set
Instruction Set
I3 I2 I1 I0 R1 R0 WCR1/P1 WCR0/P0
Instruction
Read Wiper Control
Register
Write Wiper Control
Register
Operation
Read the contents of the Wiper
Control Register pointed to by P1-P0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
0
0
Read the contents of the Data
Register pointed to by P1-P0 and R1-
R0
Read Data Register
1/0 1/0
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
Transfer the contents of the Data
Register pointed to by P1-P0 and R1-
R0 to its associated Wiper Control
Register
Write Data Register
1
1
1
1
0
0
0
1
1/0 1/0
1/0 1/0
1/0
1/0
1/0
1/0
XFR Data Register to
Wiper Control Register
Transfer the contents of the Wiper
Control Register pointed to by P1-P0
to the Data Register pointed to by R1-
R0
Transfer the contents of the Data
Registers pointed to by R1-R0 of both
pots to their respective Wiper Control
Registers
Transfer the contents of both Wiper
Control Registers to their respective
data Registers pointed to by R1-R0 of
both pots
Enable Increment/decrement of the
Control Latch pointed to by P1-P0
XFR Wiper Control
Register to Data
Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
1/0
0
1/0
0
Gang XFR Data
Registers to Wiper
Control Registers
Gang XFR Wiper
Control Registers to
Data Register
0
0
Increment/Decrement
Wiper Control Register
0
0
1/0
1/0
Note: 1/0 = data is one or zero
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
9
Doc. No. MD-2123 Rev. D
DP7269
— Gang XFR Data Register to Wiper Control
Register
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWR. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
two potentiometers and one of its associated
registers; or the transfer can occur between both
potentiometers and one associated register.
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Gang XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
DP7269; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is differ-
ent from the other commands. Once the command is
issued and the DP7269 has responded with an ac-
knowledge, the master can clock the selected wiper
up and/or down in one segment steps; thereby
providing a fine tuning capability to the host. For each
SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0
1
0
1
ID3 ID2 ID1 ID0
S
A2 A1 A0
S
T
A
R
T
A3
A I3 I2 I1
I0
R1 R0 P1 P0
A
C
K
C
K
T
O
P
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Device ID
Address
Figure 8. Three-Byte Instruction Sequence
SDA
0
1
0
1
S
T
A
R
T
I3
ID3 ID2
ID0
A
C
K
I2
I1
P1 P0
I0 R1 R0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
ID1
A3 A2 A1 A0
O
P
Internal
Address
Device ID
WCR[7:0]
or
Instruction
Opcode
Data
Pot/WCR
Register Address
Address
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
SDA
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0
I3
I2
I0
R1 R0 P1 P0
S
T
A
R
T
A
C
K
A
C
K
I
I
D
E
C
1
S
I
D
N
C
1
N
C
2
T
O
P
N
C
n
E
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Data
Register
Address
Doc. No. MD-2123 Rev. D
10
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRL
SCL
SDA
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
1 0 0 1 0 0 P P
1 0
A
C
K
DATA
7 6 5 4 3 2 1 0
A S
T
A
R
T
C
K
C T
K O
P
0 1 0 1 A A A A
3 2 1 0
Write Wiper Control Register (WCR)
S DEVICE ADDRESSES A INSTRUCTION
A
C
K
DATA
7 6 5 4 3 2 1 0
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
1 0 1 0 0 0 P P
1 0
Read Data Register (DR)
S
T
A
R
T
DEVICE ADDRESSES A
INSTRUCTION
1 0 1 1 R R P P
1 0 1 0
A
C
K
DATA
7 6 5 4 3 2 1 0
A S
C T
K O
P
C
K
0 1 0 1 A A A A
3 2 1 0
Write Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
1 1 0 0 R R P P
1 0 1 0
A
C
K
DATA
7 6 5 4 3 2 1 0
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2123 Rev. D
DP7269
INSTRUCTION FORMAT (CONTINUED)
Gang Transfer Data Register (DR) to Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
0 0 0 1 R R 0 0
1 0
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
Gang Transfer Wiper Control Register (WCR) to Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
1 0 0 0 R R 0 0
1 0
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
Transfer Wiper Control Register (WCR) to Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
1 1 1 0 R R P P
1 0 1 0
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
Transfer Data Register (DR) to Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
1 1 0 1 R R P P
1 0 1 0
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
0 0 1 0 0 0 P P
1 0
A
C
K
DATA
A S
C T
K O
P
T
A
R
T
C
K
0 1 0 1 A A A A
3 2 1 0
I
/
I
/
I
/
I
/
. . .
D D
D D
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2123 Rev. D
12
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead 300mils (W)
SYMBOL
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
A
A1
A2
b
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
b
e
L
Q
PIN#1 IDENTIFICATION
Q1
5°
15°
TOP VIEW
h
D
h
Q1
A2
Q
A
Q1
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-013.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
13
Doc. No. MD-2123 Rev. D
DP7269
TSSOP 24-LEAD 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
Q1
0.50
0°
0.70
8°
e
TOP VIEW
D
c
A2
A1
A
Q1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-153.
Doc. No. MD-2123 Rev. D
14
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7269
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
DP
7269
W
I
-00
- T1
Package
W: SOIC
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
Resistance
50: 50k
00: 100k
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Company ID
Product Number
7269
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The device used in the above example is a DP7269WI-00-T1 (SOIC, Industrial Temperature, 100k, Tape & Reel).
Ordering Part Number
DP7269WI-50
DP7269WI-00
DP7269YI-50
DP7269YI-00
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
15
Doc. No. MD-2123 Rev. D
REVISION HISTORY
Date
Revision Description
18-Nov-03
06-May-04
A
B
Initial Issue
Added TSSOP package in all areas
Updated Functional Diagram
Updated Pin Descriptions
Updated notes in Absolute Max Ratings
Updated Potentiometer Characteristics table
Updated DC Characteristics table
Added Wiper Timing table
Updated Write Cycle Limits table
Changed Figure 3 drawing to Start/Stop Condition from Start/Stop Timing
Changed Figure 4 title to Acknowledge Condition (from Acknowledge Timing)
Updated Table 3 Gang XFR Operation information
Corrected Instruction Format for Gang Transfer Data Register (DR) to Wiper Control
Register (WCR)
Updated Example of Ordering Information
Update Package Outline Drawings
Added MD- to document number
Update Potentiometer Characteristics table
Update D.C. Operating Characteristics table
Update Wiper Timing table
16-Oct-07
17-Oct-08
C
D
NIDEC COPAL ELECTRONICS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
NIDEC COPAL ELECTRONICS CORP. product s are not de signe d, int e nde d, or aut horize d for use as compone nt s in syst e ms int e nde d for surgical implant int o t he body, or
ot he r applicat ions int e nde d t o support or sust ain life , or for any ot he r applicat ion in which t he failure of t he NIDEC COPAL ELECTRONICS CORP. product could cre at e a
sit uat ion where personal injury or deat h may occur.
NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s
labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.
NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e
t ypical semiconduct or applicat ions and may not be complet e.
NIDEC COPAL ELECTRONICS CORP.
Japan Head Office
Nishi-Shinjuku, Kimuraya Bldg.,
7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023
Phone: +81-3-3364-7055
Fax: +81-3-3364-7098
Document No: MD-2123
Revision:
D
www.nidec-copal-electronics.com
Issue date:
10/17/08
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