74LVC1G175GV-Q100 [NEXPERIA]
Single D-type flip-flop with reset; positive-edge trigger;![74LVC1G175GV-Q100](http://pdffile.icpdf.com/pdf2/p00337/img/icpdf/74LVC1G175-Q_2072014_icpdf.jpg)
型号: | 74LVC1G175GV-Q100 |
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描述: | Single D-type flip-flop with reset; positive-edge trigger |
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74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
Rev. 3 — 3 October 2019
Product data sheet
1. General description
The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop
with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master
reset (MR) is an asynchronous active LOW input and operates independently of the clock input.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for
partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the
damaging backflow current through the device when it is powered down. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
•
•
•
•
•
•
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
SOT363
SOT457
74LVC1G175GW-Q100 -40 °C to +125 °C
74LVC1G175GV-Q100 -40 °C to +125 °C
SC-88
SC-74
plastic surface-mounted package; 6 leads
plastic surface-mounted package
(SC-74; TSOP6); 6 leads
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
4. Marking
Table 2. Marking
Type number
Marking code [1]
74LVC1G175GW-Q100
74LVC1G175GV-Q100
YT
V75
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6
MR
3
1
1
3
CP
D
4
FF
4
Q
D
Q
CP
6
MR
001aaa468
001aaa469
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
CP
C
C
Q
C
C
C
C
C
C
C
D
C
MR
001aaa466
Fig. 3. Logic diagram
6. Pinning information
6.1. Pinning
74LVC1G175-Q100
1
2
3
6
5
4
CP
GND
D
MR
V
CC
Q
aaa-009630
Fig. 4. Pin configuration SOT363 (SC-88) and SOT457 (SC-74)
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
2 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
CP
GND
D
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
2
3
data input
Q
4
output Q
VCC
MR
5
supply voltage
6
master reset input (active LOW)
7. Functional description
Table 4. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH CP transition; X = don’t care.
Operating mode
Input
MR
L
Output
CP
X
D
X
h
l
Q
L
Reset (clear)
Load ‘1’
H
↑
H
L
Load ‘0’
H
↑
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+6.5
±50
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
[1]
[1]
-0.5
-0.5
-
VCC + 0.5 V
Power-down mode; VCC = 0 V
VO = 0 V to VCC
+6.5
±50
100
-
V
IO
output current
mA
mA
mA
mW
°C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
-100
-
total power dissipation
storage temperature
Tamb = -40 °C to +125 °C
[2]
250
+150
-65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT363 (TSSOP6) packages: Ptot derates linearly with 3.7 mW/K above 83 °C.
For SOT457 (TSOP6) packages: Ptot derates linearly with 4.1 mW/K above 89 °C.
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
3 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
1.65
-
-
-
-
-
-
-
0
0
5.5
V
VO
Active mode
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
-
+125
20
°C
ns/V
ns/V
Δt/ΔV
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
10
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = -40 °C to +85 °C
VIH
HIGH-level input
voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-level input
voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = -100 μA; VCC = 1.65 V to 5.5 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -24 mA; VCC = 3.0 V
IO = -32 mA; VCC = 4.5 V
VI = VIH or VIL
VCC - 0.1
1.2
-
-
-
-
-
-
-
V
V
V
V
V
V
1.54
2.15
2.50
2.62
4.11
1.9
2.2
2.3
3.8
VOL
LOW-level output
voltage
IO = 100 μA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
V
V
V
V
V
V
0.07
0.12
0.17
0.33
0.39
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
4 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
Symbol Parameter
Conditions
Min
Typ [1]
±0.1
Max
±1
Unit
μA
II
input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND
[2]
-
-
IOFF
power-off leakage
current
VCC = 0 V; VI or VO = 5.5 V
±0.1
±2
μA
ICC
ΔICC
CI
supply current
VCC = 1.65 V to 5.5 V; IO = 0 A;
VI = 5.5 V or GND
-
-
-
0.1
5
4
500
-
μA
μA
pF
additional supply
current
VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V;
IO = 0 A
[2]
input capacitance
VCC = 3.3 V; VI = GND to VCC
2.5
Tamb = -40 °C to +125 °C
VIH
HIGH-level input
voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-level input
voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = -100 μA; VCC = 1.65 V to 5.5 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -24 mA; VCC = 3.0 V
IO = -32 mA; VCC = 4.5 V
VI = VIH or VIL
VCC - 0.1
0.95
1.7
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
1.9
2.0
3.4
VOL
LOW-level output
voltage
IO = 100 μA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
±1
V
V
V
V
V
V
II
input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND
μA
μA
IOFF
power-off leakage
current
VCC = 0 V; VI or VO = 5.5 V
±2
ICC
supply current
VCC = 1.65 V to 5.5 V; IO = 0 A;
VI = 5.5 V or GND
-
-
-
-
4
μA
μA
ΔICC
additional supply
current
VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V;
IO = 0 A
500
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
5 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.
Symbol Parameter
Conditions
-40 °C to +85 °C
Typ [1]
-40 °C to +125 °C Unit
Min
Max
Min
Max
tpd
propagation
delay
CP to Q; see Fig. 5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[2]
1.5
1.0
1.0
1.0
1.0
4.9
3.1
3.2
3.1
2.2
13.4
7.1
7.1
5.7
4.0
1.5
1.0
1.0
0.5
0.5
17
9.0
9.0
7.5
5.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR to Q; see Fig. 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
4.3
2.8
3.0
2.5
2.0
12.9
7.0
7.0
5.8
4.1
1.5
1.0
1.0
0.5
0.5
17
9.0
9.0
7.5
5.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CP HIGH or LOW; see Fig. 5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tW
pulse width
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR LOW; see Fig. 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.3
-
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.6
-
trec
recovery time MR; see Fig. 6
VCC = 1.65 V to 1.95 V
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
-
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
D to CP; see Fig. 5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.4
-
tsu
set-up time
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.5
-
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
6 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
Symbol Parameter
Conditions
-40 °C to +85 °C
Typ [1]
-40 °C to +125 °C Unit
Min
Max
Min
Max
th
hold time
D to CP; see Fig. 5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
-
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CP; see Fig. 5
0.2
-
fmax
maximum
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
175
175
175
200
-
125
-
-
-
-
-
-
80
175
175
175
200
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
pF
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = GND to VCC; VCC = 3.3 V [3]
300
-
CPD
power
14
dissipation
capacitance
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
11.1. Waveforms
V
I
V
D input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
Q output
M
V
001aaa465
OL
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 5. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up,
the CP to D hold times, and the maximum clock pulse frequency
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
7 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
V
I
V
MR input
M
GND
t
t
rec
W
V
I
CP input
Q output
V
M
GND
t
PHL
V
OH
V
M
V
OL
001aaa464
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width,
and the MR to CP recovery time
Table 9. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 7. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
8 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
12. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
w
M B
p
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
p
c
D
e
e
H
L
Q
v
w
y
E
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig. 8. Package outline SOT363 (SC-88)
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
9 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
Plastic, surface-mounted package (SC-74; TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
E
v
M
A
6
5
4
Q
A
pin 1
index
A
1
c
L
p
1
2
3
detail X
b
p
e
w
M B
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
A
A
b
c
D
E
e
H
E
L
p
Q
v
w
y
1
p
max 1.1
nom
0.1
0.40 0.26 3.1 1.7
3.0 0.6 0.33
2.5 0.2 0.23
mm
0.95
0.2 0.2 0.1
0.9 0.013 0.25 0.10 2.7 1.3
min
sot457_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
SC-74
06-03-16
18-11-27
SOT457
Fig. 9. Package outline SOT457 (SC-74)
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
10 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
20191003 Product data sheet
Change notice Supersedes
- 74LVC1G175_Q100 v.2
74LVC1G175_Q100 v.3
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 5: Derating values for Ptot total power dissipation updated.
Package outline drawing SOT457 (SC-74) updated.
74LVC1G175_Q100 v.2
Modifications:
20161209
Table 7: The maximum limits for leakage current and supply current have changed.
20131115 Product data sheet
Product data sheet
-
74LVC1G175_Q100 v.1
•
74LVC1G175_Q100 v.1
-
-
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
11 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
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Qualification
Production
This document contains data from
the preliminary specification.
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and products using Nexperia products, and Nexperia accepts no liability for
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Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
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Nexperia does not accept any liability related to any default, damage, costs
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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operation of the device at these or any other conditions above those
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Characteristics sections of this document is not warranted. Constant or
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Export control — This document as well as the item(s) described herein
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Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
12 / 13
Nexperia
74LVC1G175-Q100
Single D-type flip-flop with reset; positive-edge trigger
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................6
11.1. Waveforms................................................................. 7
12. Package outline.......................................................... 9
13. Abbreviations............................................................11
14. Revision history........................................................11
15. Legal information......................................................12
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 3 October 2019
©
74LVC1G175_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 3 — 3 October 2019
13 / 13
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