74LVC1G175GW [NXP]
Single D-type flip-flop with reset; positive-edge trigger; 单一的D- FL型IP- FL运带复位;正边沿触发
| 型号： | 74LVC1G175GW |
| 厂家： | 
NXP |
| 描述： | Single D-type flip-flop with reset; positive-edge trigger |
| 文件： | 总17页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 — 18 October 2004
Product data sheet
1. General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ 5 V tolerant inputs for interfacing with 5 V logic
■ High noise immunity
■ Complies with JEDEC standard:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8B/JESD36 (2.7 V to 3.6 V).
■ ±24 mA output drive (VCC = 3.0 V)
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tPHL, tPLH propagation delay
CP to Q
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
1.0
3.1
5.7
ns
propagation delay
MR to Q
1.0
2.5
5.8
-
ns
fmax
maximum clock
frequency
175
300
MHz
CI
input capacitance
-
-
2.5
14
-
-
pF
pF
[1] [2]
CPD
power dissipation
capacitance
VCC = 3.3 V
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G175GW
74LVC1G175GV
74LVC1G175GM
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
SC-74
XSON6
plastic surface mounted package; 6 leads
plastic surface mounted package; 6 leads
SOT363
SOT457
SOT886
plastic extremely thin small outline package; no
leads; 6 terminals; body 1 × 1.45 × 0.5 mm
5. Functional diagram
6
1
C1
MR
D
3
1
3
4
1D
4
6
R
FF
Q
CP
001aaa469
001aaa468
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
2 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
CP
C
Q
C
C
C
C
C
C
C
C
C
D
MR
001aaa466
Fig 3. Logic diagram.
6. Pinning information
6.1 Pinning
175
CP
1
2
3
6
5
4
MR
V
CP
1
2
3
6
MR
V
GND
D
GND
D
175
5
4
CC
CC
Q
Q
001aaa467
001aab657
Transparent top view
Fig 4. Pin configuration SC-88 and SC-74.
Fig 5. Pin configuration XSON6.
6.2 Pin description
Table 3:
Pin description
Symbol
CP
Pin
1
Description
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
GND
D
2
3
data input
Q
4
flip-flop output
VCC
MR
5
supply voltage
6
master reset input (active LOW)
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
3 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Operating mode
Input
MR
L
Output
CP
X
D
X
h
l
Q
L
Reset (clear)
Load ‘1’
H
↑
H
L
Load ‘0’
H
↑
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH CP transition;
X = don’t care.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+6.5
−50
Unit
V
VCC
IIK
supply voltage
input diode current
input voltage
−0.5
VI < 0 V
-
mA
V
[1]
VI
−0.5
+6.5
±50
IOK
VO
output diode current VO > VCC or VO < 0 V
-
mA
[1] [2]
[1] [2]
output voltage
active mode
−0.5
VCC + 0.5 V
Power-down mode
−0.5
+6.5
±50
V
IO
output diode current VO = 0 V to VCC
-
mA
mA
°C
ICC, IGND VCC or GND current
-
±100
+150
250
Tstg
Ptot
storage temperature
power dissipation
−65
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
Conditions
Min
Max Unit
VCC
VI
supply voltage
input voltage
output voltage
1.65 5.5
V
V
V
V
0
0
0
5.5
VCC
5.5
VO
active mode
Power-down mode; VCC = 0 V
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
4 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
Table 6:
Recommended operating conditions …continued
Conditions
Symbol Parameter
Min
−40
0
Max Unit
Tamb
tr, tf
ambient temperature
+125 °C
input rise and fall times
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
20
10
ns/V
ns/V
0
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
VCC = 2.7 V to 3.6 V
2.0
VCC = 4.5 V to 5.5 V
0.7 × VCC
VIL
LOW-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1
-
-
-
-
-
-
-
V
V
V
V
V
V
1.2
1.9
2.2
2.3
3.8
1.54
2.15
2.50
2.62
4.11
VOL
LOW-level output
voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
±5
V
0.07
0.12
0.17
0.33
0.39
±0.1
±0.1
V
V
V
V
V
ILI
input leakage current
µA
µA
Ioff
power OFF leakage
current
±10
ICC
∆ICC
CI
quiescent supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
0.1
5
10
500
-
µA
µA
pF
V
additional quiescent
supply current per pin
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
V
input capacitance
2.5
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
5 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
VIL
LOW-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
-
0.35 × VCC
0.7
VCC = 2.7 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
VOL
LOW-level output
voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VI = 5.5 V or GND; VCC = 5.5 V
VI or VO = 5.5 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
±20
V
V
V
V
V
V
ILI
input leakage current
µA
µA
Ioff
power OFF leakage
current
±20
ICC
quiescent supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
40
µA
µA
V
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
5000
V
[1] All typical values are measured at Tamb = 25 °C.
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
6 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; see Figure 8
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C[1]
tPHL, tPLH propagation delay CP to Q
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
4.9
3.1
3.2
3.1
2.2
13.4
7.1
7.1
5.7
4.0
ns
ns
ns
ns
ns
[2]
[2]
[2]
[2]
[2]
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
propagation delay MR to Q see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
1.0
1.0
4.3
2.8
3.0
2.5
2.0
12.9
7.0
7.0
5.8
4.1
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
tW
clock pulse width HIGH or
LOW
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
1.3
-
master reset pulse width
LOW
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
1.6
-
trem
removal time master reset
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
0.4
-
tsu
set-up time D to CP
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.5
-
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
7 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
Table 8:
Dynamic characteristics …continued
GND = 0 V; see Figure 8
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
th
hold time D to CP
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
-
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
0.2
-
fmax
maximum clock pulse
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
125
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
pF
175
175
175
200
-
-
-
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 3.3 V
300
-
[3] [4]
CPD
power dissipation
capacitance
14
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay CP to Q
see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
0.5
0.5
-
-
-
-
-
17
ns
ns
ns
ns
ns
9.0
9.0
7.5
5.5
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
propagation delay MR to Q see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.0
1.0
0.5
0.5
-
-
-
-
-
17
ns
ns
ns
ns
ns
9.0
9.0
7.5
5.5
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
tW
clock pulse width HIGH or
LOW
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 7
master reset pulse width
LOW
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
8 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
Table 8:
Dynamic characteristics …continued
GND = 0 V; see Figure 8
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
trem
removal time master reset
see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
tsu
set-up time D to CP
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
th
hold time D to CP
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 6
fmax
maximum clock pulse
frequency
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
80
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
175
175
175
200
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[4] The condition is VI = GND to VCC
.
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
9 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
12. Waveforms
V
I
V
M
D input
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
Q output
M
V
001aaa465
OL
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 6. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the
D to CP set-up, the CP to D hold times and the maximum clock pulse frequency.
Table 9:
Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
1.5 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 × VCC
0.5 × VCC
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
10 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
V
I
V
M
MR input
GND
t
t
rem
W
V
I
CP input
Q output
V
M
GND
t
PHL
V
OH
V
M
V
OL
001aaa464
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The master reset (MR) input to output (Q) propagation delays, the master reset
pulse width and the MR to CP removal time.
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse
generator.
Fig 8. Load circuitry for switching times.
Table 10: Test data
Supply voltage Input
VCC VI
1.65 V to 1.95 V VCC
Load
CL
VEXT
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
2.3 V to 2.7 V
2.7 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
open
GND
2.7 V
2.7 V
VCC
open
GND
3.0 V to 3.6 V
4.5 V to 5.5 V
open
GND
6 V
open
GND
2 × VCC
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
11 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
13. Package outline
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT363
SC-88
Fig 9. Package outline SOT363 (SC-88).
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
12 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
Plastic surface mounted package; 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-74
97-02-28
01-05-04
SOT457
Fig 10. Package outline SOT457 (SC-74).
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
13 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 11. Package outline SOT886 (XSON6).
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
14 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
14. Revision history
Table 11: Revision history
Document ID
74LVC1G175_2
Modifications
Release date Data sheet status
20041018 Product data sheet
Change notice
Doc. number
Supersedes
-
9397 750 13762 74LVC1G175_1
• Package outline. Marking code and ESD data added.
20040318 Product data sheet
74LVC1G175_1
-
9397 750 12973
-
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
15 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13762
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
16 of 17
74LVC1G175
Philips Semiconductors
Single D-type flip-flop with reset; positive-edge trigger
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information . . . . . . . . . . . . . . . . . . . . 16
9
10
11
12
13
14
15
16
17
18
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 18 October 2004
Document number: 9397 750 13762
Published in The Netherlands
相关型号：
74LVC1G175GW-Q100H
74LVC1G175-Q100 - Single D-type flip-flop with reset; positive-edge trigger TSSOP 6-Pin
NXP
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