74ALVCH16952DGG [NEXPERIA]
16-bit registered transceiver; 3-stateProduction;
| 型号： | 74ALVCH16952DGG |
| 厂家： | 
Nexperia |
| 描述： | 16-bit registered transceiver; 3-stateProduction |
| 文件： | 总14页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVCH16952
16-bit registered transceiver; 3-state
Rev. 3 — 9 January 2018
Product data sheet
1 General description
The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting
registered transceiver. Two 8-bit back to back registers store data flowing in both
directions between two bidirectional buses. Data applied to the inputs is entered and
stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock
enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but
is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow
from A inputs to B outputs is the same as for B inputs to A outputs.
2 Features and benefits
• CMOS low-power consumption
• Multibyte flow-through pinout architecture
• Low inductance, multiple center power and ground pins for minimum noise and ground
bounce
• Direct interface with TTL levels
• Output drive capability 50 Ω transmission lines at 85 °C
• Complies with JEDEC standard JESD8-B
3 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Temperature range
Name
Description
Version
74ALVCH16952DGG -40 °C to +85 °C
TSSOP56
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
SOT364-1
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
4 Functional diagram
5
52
51
49
48
47
45
44
43
15
16
17
19
20
22
23
24
42
1A0
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B0
6
41
1A1
2B1
8
40
1A2
2B2
9
38
1A3
2B3
10
37
1A4
2B4
12
36
1A5
2B5
13
34
1A6
2B6
14
33
1A7
2B7
56
1
29 28
3
54
2
55
26 31 27 30
1OEBA
2OEBA
2OEAB
2CEAB
2CEBA
2CPAB
2CPBA
1OEAB
1CEAB
1CEBA
1CPAB
1CPBA
001aae552
Figure 1.ꢀLogic symbol
56
1EN3
1OEBA
1CEBA
1CPBA
1OEAB
1CEAB
54
55
1
G1
1C5
EN4
G2
3
2
2C6
EN9
G7
1CPAB
2OEBA
2CEBA
29
31
30
28
26
27
7C11
EN10
G8
2CPBA
2OEAB
2CEAB
8C12
2CPAB
5
52
1A0
1B0
3
5D
4
6D
6
8
9
51
49
48
47
45
44
43
42
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
10
12
13
14
15
V
CC
9
11D
10
12D
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
data input
to internal circuit
001aae550
001aad245
Figure 2.ꢀIEC logic symbol
Figure 3.ꢀBus hold circuit
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
2 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
CEAB
CPAB
OEAB
CEBA
CPBA
OEBA
Q
A0
D
CP
Q
D
B0
CP
8 IDENTICAL CHANNELS
TO 7 OTHER CHANNELS
001aae549
Figure 4.ꢀSchematic diagram (one section)
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
3 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
5 Pinning information
5.1 Pinning
74ALVCH16952
1
56
1OEAB
1CPAB
1CEAB
GND
1OEBA
1CPBA
1CEBA
GND
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
4
5
1A0
1B0
6
1A1
1B1
7
V
CC
V
CC
8
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A1
2A2
GND
2A3
2A4
2A5
1B2
1B3
1B4
GND
1B5
1B6
1B7
2B0
2B1
2B2
GND
2B3
2B4
2B5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
CC
V
CC
2A6
2A7
2B6
2B7
GND
GND
2CEAB
2CPAB
2OEAB
2CEBA
2CPBA
2OEBA
001aae551
Figure 5.ꢀPin configuration
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
4 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
5.2 Pin description
Table 2.ꢀPin description
Symbol
Pin
Description
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
1OEAB, 1OEBA, 2OEAB, 2OEBA
5, 6, 8, 9, 10, 12, 13, 14
52, 51, 49, 48, 47, 45, 44, 43
15, 16, 17, 19, 20, 21, 23, 24
42, 41, 40, 38, 37, 36, 34, 33
1, 56, 28, 29
data inputs or outputs
data inputs or outputs
data inputs or outputs
data inputs or outputs
output enable input (active LOW)
clock enable input (active LOW)
1CEAB, 1CEBA, 2CEAB, 2CEBA
3, 54, 26, 31
1CPAB, 1CPBA, 2CPAB, 2CPBA
2, 55, 27, 30
clock pulse input
(LOW-to-HIGH, edge-triggered)
GND
VCC
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
ground (0 V)
supply voltage
6 Functional description
Table 3.ꢀFunction table [1]
Operating mode
Control
nOEAB,
Input
Internal
nQn
Output
A to B,
B to A
nCEAB,
nCEBA
nCPAB,
nAn,
nBn
nBn,
nAn
nOEBA
nCPBA
Hold
L
L
H
L
X
↑
X
L
NC
L
NC
L
Load and output enable
H
L
H
H
Z
Load and output disable
H
L
↑
L
H
H
Z
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH clock transition;
X = don’t care;
Z = high impedance OFF-state;
NC = no change.
74ALVCH16952
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
5 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
7 Limiting values
Table 4.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-0.5
-0.5
-
Max
+4.6
+4.6
Unit
V
VCC
VI
supply voltage
input voltage
[1]
[1]
[1]
control pins
data inputs
V
VCC + 0.5 V
VCC + 0.5 V
VO
IIK
output voltage
input clamping current
output clamping current
output current
VI < 0 V
-50
±50
±50
100
-
mA
IOK
IO
VO > VCC or VO < 0 V
VO = 0 V to VCC
-
mA
mA
mA
mA
°C
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
600
[2]
Tamb = -40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 package: Ptot derates linearly with 8 mW/K above 55 °C.
8 Recommended operating conditions
Table 5.ꢀRecommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
maximum speed performance
CL = 30 pF
2.3
3.0
0
-
-
-
-
-
-
-
2.7
3.6
VCC
VCC
+85
20
V
CL = 50 pF
V
VI
input voltage
V
VO
output voltage
0
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
operating in free-air
VCC = 2.3 V to 3.0 V
VCC = 3.0 V to 3.6 V
-40
0
°C
ns/V
ns/V
0
10
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
6 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
9 Static characteristics
Table 6.ꢀStatic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = -40 °C to +85 °C
Unit
Min
Typ [1]
Max
VIH
VIL
HIGH-level input
voltage
VCC = 2.3 V to 2.7 V
1.7
2.0
-
1.2
-
V
V
V
V
VCC = 2.7 V to 3.6 V
1.5
-
LOW-level input
voltage
VCC = 2.3 V to 2.7 V
1.2
0.7
0.8
VCC = 2.7 V to 3.6 V
-
1.5
VOH
HIGH-level output
voltage
VI = VIH or VIL
VCC = 2.3 V to 3.6 V; IO = -100 μA
VCC = 2.3 V; IO = -6 mA
VCC = 2.3 V; IO = -12 mA
VCC = 2.7 V; IO = -12 mA
VCC = 3.0 V; IO = -12 mA
VCC = 3.0 V; IO = -24 mA
VI = VIH or VIL
VCC - 0.2
VCC
-
-
-
-
-
-
V
V
V
V
V
V
VCC - 0.3 VCC - 0.08
VCC - 0.6 VCC - 0.26
VCC - 0.5 VCC - 0.14
VCC - 0.6 VCC - 0.09
VCC - 1.0 VCC - 0.28
VOL
LOW-level output
voltage
VCC = 2.3 V to 3.6 V; IO = 100 μA
VCC = 2.3 V; IO = 6 mA
VCC = 2.3 V; IO = 12 mA
VCC = 2.7 V; IO = 12 mA
VCC = 3.0 V; IO = 24 mA
-
-
-
-
-
-
-
GND
0.07
0.15
0.14
0.27
0.1
0.20
0.40
0.70
0.40
0.55
5
V
V
V
V
V
II
input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND
μA
μA
IOZ
OFF-state output
current
VCC = 2.7 V to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
0.1
10
ICC
supply current
VCC = 2.3 V to 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
0.2
40
μA
μA
ΔICC
IBHL
additional supply
current
VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A
150
750
bus hold LOW
sustaining current
VCC = 2.3 V; VI = 0.7 V
VCC = 3.0 V; VI = 0.8 V
VCC = 2.3 V; VI = 1.7 V
VCC = 3.0 V; VI = 2.0 V
VCC = 3.6 V
45
75
-
150
-
-
-
-
-
-
μA
μA
μA
μA
μA
IBHH
bus hold HIGH
sustaining current
-45
-75
500
-175
-
IBHLO
IBHHO
Ci
bus hold LOW
overdrive current
bus hold HIGH
overdrive current
VCC = 3.6 V
-500
-
-
-
-
μA
pF
input capacitance
3.0
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
7 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
10 Dynamic characteristics
Table 7.ꢀDynamic characteristics
Voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C; For test circuit, see Figure 9.
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
[2]
[3]
[4]
tpd
ten
tdis
tw
propagation delay nCPBA to nAn; nCPAB to nBn; see Figure 6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
3.2
-
4.1
4.6
3.9
ns
ns
ns
VCC = 3.0 V to 3.6 V
3.2
enable time
disable time
pulse width
set-up time
nOEBA to nAn; nOEAB to nBn; see Figure 8
VCC = 2.3 V to 2.7 V
1.0
1.0
1.0
-
-
-
5.4
5.3
4.4
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
nOEBA to nAn; nOEAB to nBn; see Figure 8
VCC = 2.3 V to 2.7 V
1.0
1.4
1.1
-
-
-
5.3
4.4
4.0
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
nCPAB; nCPBA; HIGH or LOW; see Figure 6
VCC = 2.3 V to 2.7 V
3.3
3.3
3.3
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tsu
nAn to nCPAB or nBn to nCPBA; see Figure 7
VCC = 2.3 V to 2.7 V
1.7
1.9
1.5
-
-
-
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
nCEAB to nCPAB or nCEBA to nCPBA;
see Figure 7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.2
1.0
1.0
-
-
-
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nAn to nCPAB or nBn to nCPBA; see Figure 7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
th
hold time
0.6
0.6
0.8
-
-
-
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nCEAB to nCPAB or nCEBA to nCPBA;
see Figure 7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.1
0.9
1.1
-
-
-
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
8 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
fmax
maximum
frequency
CP; see Figure 6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
150
150
150
-
350
350
350
30
-
-
-
-
MHz
MHz
MHz
pF
VCC = 3.0 V to 3.6 V
[5]
CPD
power dissipation per driver; VI = GND to VCC
capacitance
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V
[2] tpd is the same as tPHL and tPLH
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPHZ and tPLZ
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD x VCC2 x fi x N +∑(CL x VCC2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL x VCC2 x fo) = sum of outputs.
10.1 Waveforms and test circuit
1/f
max
V
I
input nCPBA
or nCPAB
V
V
V
M
M
M
0 V
OH
t
t
W
W
t
t
PLH
PHL
V
output
nAn or nBn
V
V
M
M
V
OL
001aae956
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 6.ꢀPropagation delay clock input (nCPAB, nCPBA) to output (nBn, nAn), clock pulse width and maximum
clock pulse frequency
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
9 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
V
I
input nAn or nBn
nCEAB
V
M
nCEBA
0 V
t
t
h
h
t
t
su
su
V
I
input nCPAB
or nCPBA
V
M
0 V
001aae547
Measurements points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 7.ꢀSetup and hold times
V
I
input nOEAB
nOEBA
GND
V
M
t
t
PZL
PLZ
V
CC
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
PHZ
t
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aae548
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 8.ꢀ3-state enable and disable time
Table 8.ꢀMeasurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
2.3 V to 2.7 V
2.7 V
VCC
0.5 V
1.5 V
1.5 V
0.5 V
1.5 V
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.3 V
VOH - 0.3 V
2.7 V
2.7 V
3.0 V to 3.6 V
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
10 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Figure 9.ꢀTest circuit for measuring switching times
Table 9.ꢀTest data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
2.3 V to 2.7 V
2.7 V
VCC
≤ 2.0 ns
2.5 ns
2.5 ns
30 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
open
GND
3.0 V to 3.6 V
open
GND
74ALVCH16952
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© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
11 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
11 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.08
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Figure 10.ꢀPackage outline SOT364-1 (TSSOP56)
74ALVCH16952
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
12 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
12 Abbreviations
Table 10.ꢀAbbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
TTL
Transistor-Transistor Logic
13 Revision history
Table 11.ꢀRevision history
Document ID
Release date
20180109
Data sheet status
Change notice
Supersedes
74ALVCH16952 v.3
Modifications:
Product data sheet
-
74ALVCH16952 v.2
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74ALVCH16952 v.2
Modifications:
20060427
Product data sheet
-
74ALVCH16952 v.1
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors
• The symbol of pin numbers 15, 16, 17, 19, 20, 21, 23 and 24 is rectified
74ALVCH16952 v.1
19980901
Preliminary specification
-
-
74ALVCH16952
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 9 January 2018
13 / 14
Nexperia
74ALVCH16952
16-bit registered transceiver; 3-state
Contents
1
General description ............................................ 1
2
3
4
5
5.1
5.2
6
7
8
Features and benefits .........................................1
Ordering information .......................................... 1
Functional diagram .............................................2
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................5
Functional description ........................................5
Limiting values ....................................................6
Recommended operating conditions ................6
Static characteristics ..........................................7
Dynamic characteristics .....................................8
Waveforms and test circuit ................................9
Package outline .................................................12
Abbreviations .................................................... 13
Revision history ................................................ 13
9
10
10.1
11
12
13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 9 January 2018
Document identifier: 74ALVCH16952
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