74ALVCH2245 [FAIRCHILD]
Low Voltage Bidirectional Transceiver with Bushold and 26з Series Resistors in B Outputs; 低电压双向收发器与Bushold和26з系列电阻在B输出
| 型号： | 74ALVCH2245 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Bidirectional Transceiver with Bushold and 26з Series Resistors in B Outputs |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2002
Revised January 2002
74ALVCH2245
Low Voltage Bidirectional Transceiver with Bushold
and 26Ω Series Resistors in B Outputs
General Description
Features
The ALVCH2245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The T/R input determines the direction
of data flow. The OE input disables both the A and B Ports
■ 1.65V to 3.6V VCC supply operation
■ 3.6V tolerant control inputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
by placing them in
a high impedance state. The
■ 26Ω series resistors in B Port outputs
■ tPD (A to B)
ALVCH2245 data inputs include active bushold circuitry,
eliminating the need for external pull-up resistors to hold
unused or floating data inputs at a valid logic level.
4.9 ns max for 3.0V to 3.6V VCC
6.1 ns max for 2.3V to 2.7V VCC
9.8 ns max for 1.65V to 1.95V VCC
The 74ALVCH2245 is designed for low voltage (1.65V to
3.6V) VCC applications. The ALVCH2245 is also designed
with 26Ω series resistance in the B Port outputs. This
design reduces line noise in applications such as memory
address drivers, clock drivers, and bus transceivers trans-
mitters
■ Uses patented Quiet Series noise/EMI reduction
circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
The 74ALVCH2245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
74ALVCH2245WM
74ALVCH2245MTC
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MTC20
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2002 Fairchild Semiconductor Corporation
ds500716
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Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
OE
Output Enable Input (Active LOW)
Transmit/Receive Input
OE T/R
T/R
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
A0–A7
B0–B7
Side A Bushold Inputs or 3-STATE Outputs
Side B Bushold Inputs or 3-STATE Outputs
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO) (Note 2)
−0.5V to VCC +0.5V
Operating
1.65V to 3.6V
0V to VCC
DC Input Diode Current (IIK
)
Input Voltage
VI < 0V
−50 mA
−50 mA
±50 mA
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
0V to VCC
DC Output Diode Current (IOK
O < 0V
DC Output Source/Sink Current
(IOH/IOL
)
−40°C to +85°C
V
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
)
DC VCC or GND Current per
Supply Pin (ICC or GND)
±100 mA
Storage Temperature Range (TSTG
)
−65°C to +150°C
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
2.7 - 3.6
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
1.65 - 3.6
1.65
1.7
2.0
V
VIL
LOW Level Input Voltage
0.35 x VCC
0.7
V
0.8
VOH
HIGH Level Output Voltage
A Outputs
I
I
I
I
OH = −100 µA
OH = −4 mA
OH = −6 mA
OH = −12 mA
VCC - 0.2
1.2
2.0
1.7
2.2
2.4
2
2.3
2.3
2.7
3.0
IOH = −24 mA
IOH = −100 µA
IOH = −2 mA
IOH = −4 mA
IOH = −6 mA
3.0
V
HIGH Level Output Voltage
B Outputs
1.65 - 3.6
1.65
VCC - 0.2
1.2
1.9
1.7
2.4
2
2.3
2.3
3.0
I
I
I
I
I
I
OH = −8 mA
OH = −12 mA
OL = 100 µA
OL = 4 mA
2.7
3.0
2
VOL
LOW Level Output Voltage
A Outputs
1.65 - 3.6
1.65
0.2
0.45
0.4
OL = 6 mA
2.3
OL = 12 mA
2.3
0.7
2.7
0.4
I
I
I
I
I
OL = 24 mA
OL = 100 µA
OL = 2 mA
OL = 4 mA
OL = 6 mA
3.0
0.55
0.2
LOW Level Output Voltage
B Outputs
1.65 - 3.6
1.65
V
0.45
0.4
2.3
2.3
0.55
0.55
0.6
3.0
I
I
OL = 8 mA
2.7
OL = 12 mA
3.0
0.8
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
1.65 - 3.6
±5.0
µA
3
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DC Electrical Characteristics (Continued)
VCC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
1.65
1.65
2.3
II(HOLD)
Bushold Input Maximum
Drive Hold Current
VIN = 0.58V
VIN = 1.07V
VIN = 0.7V
VIN = 1.7V
VIN = 0.8V
VIN = 2.0V
25
−25
45
2.3
−45
75
µA
3.0
3.0
−75
0 < VO ≤ 3.6V
3.6
±500
±10
40
IOZ
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
0 ≤ VO ≤ 3.6V, VI = VIH or VIL
VI = VCC or GND, IO = 0
1.65 - 3.6
3.6
µA
µA
µA
ICC
∆ICC
VIH = VCC − 0.6V
2.7 - 3.6
750
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
CL = 50 pF
CL = 30 pF
Symbol
Parameter
Units
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5 ± 0.2V
VCC = 1.8V ± 0.15V
Min
Max
Min
Max
Min
Max
Min
Max
t
PHL, tPLH
Propagation Delay
1.1
4.9
1.3
6.1
0.8
0.8
0.8
0.8
0.8
0.8
5.6
1.5
9.8
A to B
ns
ns
ns
Propagation Delay
B to A
1.1
1.1
1.1
1.1
1.1
4.0
5.5
5.0
4.7
4.1
1.3
1.3
1.3
1.3
1.3
4.7
7.1
6.1
5.2
4.5
4.2
6.6
5.6
4.7
4.0
1.5
1.5
1.5
1.5
1.5
8.4
9.8
9.8
8.5
7.2
tPZL, tPZH
Output Enable Time
A to B
Output Enable Time
B to A
tPLZ, tPHZ
Output Disable Time
A to B
Output Disable Time
B to A
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
Units
VCC
Typical
CIN
CIO
CPD
Input Capacitance
Input, Output Capacitance
Power Dissipation Capacitance
VI = 0V or VCC
3.3
3.3
3.3
2.5
6
7
pF
pF
VO = 0V or VCC
Outputs Enabled f = 10 MHz, CL = 50 pF
20
20
pF
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4
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
SWITCH
Open
VL
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; ZO = 50Ω)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5 ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.3V
V
OL + 0.15V
OH − 0.15V
VCC*2
VOL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.3V
V
V
OH − 0.15V
VL
6V
6V
VCC*2
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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