UPD75P316B [NEC]

4-BIT SINGLE-CHIP MICROCOMPUTER; 4位单片机


型号：	UPD75P316B
厂家：	NEC
描述：	4-BIT SINGLE-CHIP MICROCOMPUTER 4位单片机计算机
文件：	总42页 (文件大小：368K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD75P316A

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The µPD75P316A is a product of the µPD75316 with on-chip ROM having been replaced with the one-time PROM

or EPROM.

It is most suitable for test production during system development and for production in small amounts since it

can operate under the same supply voltage as mask products.

The one-time PROM product is capable of writing only once and is effective for production of many kinds of sets

in small quantities and early startup. The EPROM product allows program writing and rewriting, and is therefore

suitable for system evaluation. The on-chip RAM has twice the capacity of the µPD75316/75P316, enabling large

amounts of data to be processed.

Details of functions are described in the User's Manual shown below. Be sure to read in design.

µPD75308 User's Manual : IEM-5016

FEATURES

• Compatible (excluding mask option) with the mask products

• Memory capacity

• Program memory (PROM) : 16256 × 8 bits

• Data memory (RAM)

: 1024 × 4 bits

• Low-voltage operation capability: 2.7 to 6.0 V

ORDERING INFORMATION

Ordering Code

µPD75P316AGF-3B9

µPD75P316AK

Package

On-Chip ROM

One-time PROM

EPROM

80-pin plastic QFP (14 × 20 mm)

80-pin ceramic WQFN (LCC with window)

QUALITY GRADE

Ordering Code

Package

Quality Grade

Standard

µPD75P316AGF-3B9

µPD75P316AK

80-pin plastic QFP (14 × 20 mm)

80-pin ceramic WQFN (LCC with window)

Standard

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

In descriptions common to one-time PROM products and EPROM products in this document, the term "PROM" is

used.

The information in this document is subject to change without notice.

Document No. IC-2524A

The mark ★ shows major revised points.

(O. D. No. IC-7950B)

Date Published October 1993 P

Printed in Japan

µPD75P316A

PIN CONFIGURATION (Top View)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

P70/KR4

S12

S13

S14

S15

S16

S17

P63/KR3

P62/KR2

P61/KR1

P60/KR0

S18

S19

S20

S21

S22

XT2

XT1

S23

P33 (MD3)

P32 (MD2)

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

S31/BP7

COM0

P31/SYNC (MD1)

P30/LCDCL (MD0)

P23/BUZ

P22/PCL

P21

P20/PTO0

P13/TI0

P12/INT2

P11/INT1

COM1

COM2

COM3

P10/INT0

P03/SI/SB1

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

BASIC

INTERVAL

TIMER

PORT0

P00-P03

INTBT

PROGRAM

COUNTER (14)

PORT1

PORT2

PORT3

PORT4

P10-P13

P20-P23

SP(8)

ALU

TIMER/EVENT

COUNTER

TI0/P13

PTO0/P20

P30-P33

/MD0-MD3

INTT0

BANK

P40-P43

P50-P53

P60-P63

P70-P73

WATCH

TIMER

BUZ/P23

PORT5

PORT6

PORT7

GENERAL REG.

PROGRAM

MEMORY

INTW

LCD

DECODE

AND

CONTROL

(PROM)

SI/SB1/P03

SO/SB0/P02

SCK/P01

DATA

MEMORY

(RAM)

SERIAL BUS

INTERFACE

16256 × 8 BITS

1024 × 4 BITS

INTCSI

S0-S23

INT0/P10

INT1/P11

INT2/P12

S24/BP0

–S31/BP7

INTERRUPT

CONTROL

LCD

CONTROL-

LER

COM0–COM3

INT4/P00

KR0/P60

–KR7/P73

/ 2^N

/DRIVER

VLC0–VLC2

SYSTEM CLOCK

GENERATOR

CLOCK

OUTPUT

CONTROL

CLOCK

DIVIDER

STAND BY

CONTROL

CPU

CLOCK

BIT SEQ.

BUFFER (16)

SUB

MAIN

LCD

BIAS

LCDCL/P30

SYNC/P31

PCL/P22

XT1

XT2

X1 X2

VPP

RESET

µPD75P316A

CONTENTS

1. PIN FUNCTIONS ......................................................................................................................................... 5

1.1 PORT PINS ........................................................................................................................................................... 5

1.2 OTHER PINS ......................................................................................................................................................... 7

1.3 PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9

1.4 CAUTION ON USING P00/INT4 PIN AND RESET PIN .................................................................................. 11

★

2. DIFFERENCES BETWEEN PRODUCTS IN SERIES ............................................................................... 11

3. DATA MEMORY (RAM) ............................................................................................................................ 13

4. PROGRAM MEMORY WRITE AND VERIFY........................................................................................... 15

4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 15

4.2 PROGRAM MEMORY WRITING PROCEDURE ...............................................................................................16

4.3 PROGRAM MEMORY READING PROCEDURE...............................................................................................17

4.4 ERASURE METHOD ..........................................................................................................................................18

5. ELECTRICAL SPECIFICATIONS ...............................................................................................................19

6. PACKAGE INFORMATION .......................................................................................................................35

7. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 37

APPENDIX A. DEVELOPMENT TOOLS.........................................................................................................38

APPENDIX B. RELATED DOCUMENTS ........................................................................................................39

★

µPD75P316A

1. PIN FUNCTIONS

1.1 PORT PINS (1/2)

Dual-

Function Pin

I/O Circuit

Type*1

Pin Name

Afer Reset

Function

Input/Output

8-Bit I/O

P00

P01

Input

INT4

SCK

4-bit input port (PORT0)

Internal pull-up resistor specification by soft-

ware is possible for P01 to P03 as a 3-bit unit.

Input/output

F - A

F - B

M - C

Input

P02

SO/SB0

SI/SB1

INT0

P03

With noise elimination circuit

P10

P11

INT1

4-bit input port (PORT1)

Internal pull-up resistor specification by soft-

ware is possible as a 4-bit unit.

Input

B - C

E - B

P12

INT2

P13

TI0

P20

PTO0

P21

—

4-bit input/output port (PORT2)

Internal pull-up resistor specification by soft-

ware is possible as a 4-bit unit.

Input/output

P22

PCL

P23

BUZ

P30 *2

P31 *2

P32 *2

P33 *2

LCDCL MD0

SYNC MD1

MD2

Programmable 4-bit input/output port (PORT3)

Input/output settable bit-wise.

Internal pull-up resistor specification by soft-

ware is possible as a 4-bit unit.

MD3

N-ch open-drain 4-bit input/output port (PORT

4).

Data input/output pins for program memory

(PROM) write/verify (low-order 4 bits).

P40 to P43*2

P50 to P53 *2

Input/output

—

High impedance

M - A

N-ch open-drain 4-bit input/output port (PORT 5)

Data input/output pins for program memory

(PROM) write/verify (high-order 4 bits).

P60

P61

P62

P63

P70

P71

P72

P73

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

Programmable 4-bit input/output port (PORT6).

Input/output settable bit-wise.

Internal pull-up resistor specification by soft-

ware is possible as a 4-bit unit.

Input/output

Input

F - A

4-bit input/output port (PORT7).

Internal pull-up resistor specification by soft-

ware is possible as a 4-bit unit.

F - A

: Indicates a Schmitt-triggered input.

2 . Direct LED drive capability.

µPD75P316A

1.1 PORT PINS (2/2)

Dual-

Function Pin

I/O Circuit

TYPE

Pin Name

Input/Output

Output

Function

8-Bit I/O

After Reset

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

S24

S25

S26

S27

S28

S29

S30

S31

1-bit output port (BIT PORT)

Dual-function as segment output pins.

G - C

Output

For BP0 to BP7, VLC1 is selected as the input source. The output level depends on BP0 to BP7 and the VLC1 external

circuit, however.

µPD75P316A

1.2 OTHER PINS

Dual-

Function Pin

I/O Circuit

Pin Name

After Reset

Function

Input/Output

Type *1

B - C

E - B

—

Input

output

P13

P20

P22

External event pulse input pin for timer/event counter.

Timer/event counter output pin

Clock output pin

TI0

PTO0

PCL

Input

Input/output

E - B

Fixed frequency output pin (for buzzer or system clock

trimming)

Input/output

P23

P01

P02

Input

BUZ

E - B

Serial clock input/output pin

F - A

Input

SCK

Serial data output pin

Serial bus input/output pin

SO/SB0

F - B

M - C

Serial data input pin

Serial bus input/output pin

Input

—

SI/SB1

INT4

Input/output

Input

P03

P00

Edge-detected vectored interrupt input pin (rising or falling

edge detection).

INT0

INT1

P10

P11

Edge-detected vectored interrupt input pin (detection edge

selectable)

Input

B - C

—

Input

Input/output

Output

B - C

F - A

G - A

G - C

G - B

—

Edge-detected testable input pin (rising edge detection)

Testable Input/output pins (parallel falling edge detection)

Segment signal output pins

INT2

P12

Input

KR0 to KR3

KR4 to KR7

S0 to S23

S24 to S31

COM0 to COM3

P60 to P63

P70 to P73

—

Output

BP0 to 7

—

Segment signal output pins

Output

Common signal output pins

LC0 to VLC2

—

LCD drive power supply pins

—

BIAS

—

External split cutting output pin

High impedance

Input

—

LCDCL*2

SYNC*2

Input/output

P30

External extension driver drive clock output pin

External extension driver synchronization clock output pin

E - B

P31

Input/output

Input

—

E - B

—

Main system clock oscillation crystal/ceramic connection

pins. When an external clock is used, the clock is input to

X1 and the inverted clock to X2.

X1, X2

—

Subsystem clock oscillation crystal connection pins

When an external clock is used, the clock is input to XT1 and

the inverted clock to XT2. XT1 can be used as a 1-bit input

(test) pin.

—

Input

—

XT1, XT2

—

Input

System reset input pin (low-level active).

RESET

—

Mode selection pin for program memory (PROM) write/

verify.

Input/output

P30 to P33

Input

MD0 to MD3

E - B

Programvoltageapplicationpinforprogrammemory(PROM)

write/verify . Connected to V_DDin normal operation. Applies

+12.5 V in program memory write/verify.

—

Positive power supply pin

GND potential pin

—

µPD75P316A

: Indicates a Schmitt-triggered input.

2. Pins provided for future system expansion. Currently used only as pins 30 and 31.

3. V^LCXshown below can be selected for display outputs.

S0 to S31: VLC1, COM0 to COM2: VLC2 , COM3: VLC0

However, display output levels depend on the display output and VLCX external circuit.

µPD75P316A

1.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuits of each pin of the µPD75P316A are shown by in abbreviated form.

TYPE A (For TYPE E-B)

TYPE D (For TYPE E-B, F-A)

V^DD

data

P-ch

OUT

P-ch

output

disable

N-ch

Push-pull output that can be made high-impedance

output (P-ch and N-ch OFF)

CMOS standard input buffer

TYPE B

TYPE E-B

VDD

P.U.R.

enable

P-ch

data

IN/OUT

Type D

Type A

output

disable

P.U.R.

Pull-Up Resistor

Schmitt trigger input with hysteresis characteristic

TYPE B-C

TYPE F-A

VDD

P.U.R.

enable

P-ch

P.U.R.

enable

P-ch

data

IN/OUT

Type D

Type B

output

disable

P.U.R. : Pull-Up Resistor

P.U.R.

Pull-Up Resistor

Schmitt trigger input with hysteresis characteristic

µPD75P316A

TYPE F-B

TYPE G-C

V^DD

P.U.R.

P-ch

VDD

P.U.R.

enable

P-ch

VDD

LC0

output

disable

(P)

P-ch

LC1

IN/OUT

P-ch

data

SEG

output

disable

OUT

N-ch

data/Bit Port data

N-ch

output

disable

(N)

LC2

N-ch

P.U.R.

Pull-Up Resistor

TYPE G-A

TYPE M-A

IN/OUT

LC0

P-ch

data

N-ch

(+10 V

Withstand

Voltage)

LC1

output

disable

P-ch

SEG

data

OUT

N-ch

VLC2

N-ch

Middle-High Voltage Input Buffer

(+10 V Withstand Voltage)

TYPE G-B

TYPE M-C

VDD

LC0

P-ch

P.U.R.

P-ch

IN/OUT

VLC1

P.U.R.

enable

N-ch

P-ch

OUT

data

N-ch

COM

data

output

disable

N-ch P-ch

VLC2

N-ch

P.U.R.

Pull-Up Resistor

µPD75P316A

1.4 CAUTION ON USING P00/INT4 PIN AND RESET PIN

★

The P00/INT4 and RESET pins have a test mode setting function (IC test only) which tests internal operations of

the µPD75P316A in addition to those functions given in 1.1 and 1.2.

The test mode is set when voltage greater than VDD is applied to either pin. Therefore, even during normal

operation, the test mode is engaged when noise greater than V^DDis added, thus causing interference with normal

operation.

For example, this problem may occure if the P00/INT4 and RESET pins wiring is too long, causing line noise.

To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the

exterior add-on components shown in the Figures below.

• Connect a condenser between the VDD and the pin.

• Connect a diode with low V^Fbetween the VDD

and the pin.

VDD

Diode with

Small V

VDD

P00/INT4, RESET

2. DIFFERENCES BETWEEN PRODUCTS IN SERIES

The µPD75P316A is a product of the µPD75316 with on-chip mask ROM having been replaced with the one-time

PROM or EPROM. If you use PROM for debugging the applied system or trial manufacturing, and proceed to use

masked ROM products for mass production, do so only with a full understanding of their differences beforehand.

Also, µPD75P316A functions are an extension of those of theµPD75P316. Table 2-1 shows the differences between

the series products. All products have the same functions except as indicated in this table.

For the details of the CPU functions and the built-in hardware, please refer to the µPD75308 User's Manual (IEM-

5016).

Table 2-1 Differences between Products in Series

Product Name

Comparison Item

µPD75304/75306/75308

µPD75312/75316

µPD75304B/75306B/75308B µPD75312B/75316B

µPD75P308

µPD75P316

µPD75P316A

µPD75P316B*1

Mask ROM

4K/6K/8K

Mask ROM

12K/16K

Mask ROM

4K/6K/8K

Mask ROM

12K/16K

One-time PROM,EPROM One-time PROM

8K 16K

One-time PROM,EPROM One-time PROM

16K 16K

ROM(× 8 bits)

RAM(× 4 bits)

Mask option

512

1024

512

1024

Port 4, 5 pull-up resistor incorporated

LCD driving power supplying split resistor

P30/MD0 to P33/MD3

No. 50 to 53

P30 to P33

connection

No. 57

Masked ROM products and PROM products have different current dissipation and operating temperature range *2. For details, refer to the electrical specifications of

respective data sheet.

Electrical specifications

Power supply voltage range

★

2.7 to 6.0 V

2.0 to 6.0 V

2.0 to 5.5 V

5 V ±5 %

2.7 to 6.0 V

2.0 to 5.5 V

Operating temperature

range

Under

investigation

–40 to +85 °C

–10 to +70 °C

–40 to +85 °C

• 80-pin plastic QFP (14 × 20)

• 80-pin plastic QFP

QFP (■14)

• 80-pin plastic QFP

(14 × 20)

• 80-pin plastic TQFP

(■12)

• 80-pin plastic

QFP (■14)

• 80-pin plastic

TQFP (■12)

• 80-pin plastic

QFP (14 × 20)

• 80-pin plastic

QFP (14 × 20)

• 80-pin ceramic

WQFN (LCC with

window)

• 80 pin plastic

QFP (■14)

• 80 pin plastic

TQFP (■12)

QFP (14 × 20)

• 80-pin ceramic

WQFN (LCC with

window)

Package

µPD75P316

µPD75P316A

µPD75P316B

On-chip PROM product

Others

µPD75P308

µPD75P316B

––––

★

Masked ROM products and PROM products have different noise endurance limits and noise radiation due to differing circuit scales and mask layouts.

1. The µPD75P316B is under development.

2. The µPD75P316A is the same as the mask ROM products.

Note

PROM and masked ROM have different noise endurance limits and noise radiation. When considering replacement of masked ROM products after trial manufacturing

with PROM products, sufficient evaluation of CS products (not ES products) with masked ROM products should be performed.

★

µPD75P316A

3. DATA MEMORY (RAM)

Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area.

The data memory consists of memory banks 0 to 3 with each bank consisting of 256 words × 4 bits.

Peripheral hardware has been assigned to the area of memory bank 15.

(1) Data area

The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt execution

stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the memory content

for a long time by battery backup, etc. The data area is operated by memory manipulation instructions.

The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 × 4 bits each. Bank 0 has been mapped

as a data area but is also available as a general register area (000H to 007H) and a stack area (000H to 0FFH) (banks

1, 2 and 3 are available only as a data area).

In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory manipulation

instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruction, an even

address should be specified.

(a) General register area

The general register area can be operated either by general register operation instructions or by memory

manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers which

is not used in the program is available as a data area or a stack area.

(b) Stack area

The stack area is set by an instruction. It is available as a subroutine execution or interrupt service execution

save area.

(2) Peripheral hardware area

The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15.

It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware, however,

the operable bit unit differs from one address to another. An address to which peripheral hardware has not been

assigned is inaccessible since no data memory is built in.

µPD75P316A

µPD78012

Fig. 3-1 Data Memory Map

Data Memory

Memory Bank

000H

General

(8 × 4)

007H

008H

Stack

Area

256 × 4

0FFH

100H

Data Area

Static RAM

(1024 × 4)

256 × 4

1FFH

200H

2FFH

300H

256 × 4

3FFH

Not On-Chip

F80H

FFFH

128 × 4

Peripheral Hardware Area

µPD75P316A

4. PROGRAM MEMORY WRITE AND VERIFY

The ROM built into the µPD75P316A is a 16256 × 8-bit electrically writable one-time PROM. The table below shows

the pins used to program this PROM. There is no address input; instead, a method to update the address by the

clock input via the X1 pin is adopted.

Pin Name

Function

Voltage applecation pin for program memory write/verify

(normally VDD potential).

VPP

Address update clock inputs for program memory write/

verify. Inverse of X1 pin signal is input to X2 pin.

X1, X2

Operating mode selection pins for program memory write/

verify.

MD0 to MD3

8-bit data input/output pins for progrm memory write/

verify.

P40 to P43 (low-order 4 bits)

P50 to P53 (high-order 4 bits)

Supply voltage application pin.

VDD

Applies 2.7 to 6.0 V in normal operation, and 6 V for

program memory write/verify.

Note 1. A lightshield cover film should be applied to the µPD75P316AK provided

with an erasure window, except when erasing the EPROM.

2. The one-time PROM version of µPD75P316AGF is not provided with an

erasure window, and therefore UV erasure is not possible.

4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES

The µPD75P316A assumes the program memory write/verify mode when +6 V and +12.5 V are applied

respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin

setting in this mode. All the remaining pins are at the V^SSpotential by the pull-down resistor.

Operating Mode Setting

Operating Mode

VPP

VDD

MD1 MD2 MD3

MD0

Program memory address zero-clear

Write mode

+12.5 V

+6 V

Verify mode

Program inhibit mode

×: L or H

µPD75P316A

µPD78012

4.2 PROGRAM MEMORY WRITING PROCEDURE

The program memory writing procedure is shown below. High-speed write is possible.

(1) Pull down a pin which is not used to V^SSvia the resistor. The X1 pin is at the low level.

(2) Supply 5 V to the VDD and VPP pins.

(3) 10 µs wait.

(4) The program memory address 0 clear mode.

(5) Supply 6 V and 12.5 V respectively to V^DDand VPP.

(6) The program inhibit mode.

(7) Write data in the 1-ms write mode.

(8) The program inhibit mode.

(9) The verify mode. If written, proceed to (10); if not written, repeat (7) to (9).

(10) (Number of times written in (7) to (9): X) × 1-ms additional write.

(11) The program inhibit mode.

(12) Update (+1) the program memory address by inputting 4 pulses to the X1 pin.

(13) Repeat (7) to (12) up to the last address.

(14) The program memory address 0 clear mode.

(15) Change the V^DDand VPP pins voltage to 5 V.

(16) Power off.

The diagram below shows the procedure of the above (2) to (12).

Repeated X Times

Address

Increment

Additional

Write

Verify

DD + 1

P40-P43

P50-P53

Data Output

Data Input

MD0

(P30)

MD1

(P31)

MD2

(P32)

MD3

(P33)

µPD75P316A

4.3 PROGRAM MEMORY READING PROCEDURE

The µPD75P316A can read the content of the program memory in the following procedure. It reads in the verify

mode.

(1) Pull down a pin which is not used to V^SSvia the resistor. The X1 pin is at the low level.

(2) Supply 5 V to the V^DDand VPP pins.

(3) 10 µs wait.

(4) The program memory address 0 clear mode.

(5) Supply 6 V and 12.5 V respectively to V^DDand VPP.

(6) The program inhibit mode.

(7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at

the period of inputting 4 pulses.

(8) The program inhibit mode.

(9) The program memory address 0 clear mode.

(10) Change the V^DDand VPP pins voltage to 5 V.

(11) Power off.

The diagram below shows the procedure of the above (2) to (9).

VPP

VDD

VDD + 1

VDD

V^DD

P40-P43

P50-P53

Data Output

MD0

(P30)

"L"

MD1

(P31)

MD2

(P32)

MD3

(P33)

µPD75P316A

µPD78012

4.4 ERASING METHOD (µPD75P316AK ONLY)

The content of the data programmed in the µPD75P316A is erased as ultraviolet rays are irradiated to the window

in the upper part.

The erasable ultraviolet-ray wavelength is about 250 nm.

The dose required for complete erasure is 15 W•s/cm²(ultraviolet-ray intensity × erasure time). If a commercially

available ultraviolet-ray lamp (wavelength 254 nm, intensity 12 mW/cm²) is used, it takes about 15 to 20 minutes

to erase.

Note 1. The content may be erased if exposed to direct sunlight or fluorescent lamp light for a long time. To

protect the content, the window in the upper part should be masked with a lightshield cover film.

NEC attaches such a lightshield cover film to each UV EPROM product.

2. When erasing, the distance between the ultraviolet-ray lamp and the µPD75P316A should be kept

normally within 2.5 cm.

Remarks It may take longer to erase if the ultraviolet-ray lamp has deteriorated or if the package window is dirty

and so on.

µPD75P316A

5. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)

PARAMETER

SYMBOL

TEST CONDITIONS

Open-drain

RATING

UNIT

VDD

–0.3 to +7.0

–0.3 to +13.5

–0.3 to VDD +0.3

Power supply voltage

VPP

Except ports 4, 5

VI1

Input voltage

V^I2

Ports 4, 5

–0.3 to +11

–0.3 to V^DD+0.3

Output voltage

–15

°C

1 pin

Output current high

IOH

–30

All pins

Peak value

1 pin

100

Effective value

Peak value

Output current low

Total of ports 0, 2, 3, 5

Total of ports 4, 6, 7

I^OL*

Effective value

Peak value

100

Effective value

Operating temperature

Storage temperature

Topt

Tstg

–40 to +85

–65 to +150

°C

Calculate the effective value with the formula [Effective value] = [Peak value] × √duty.

CAPACITANCE (Ta = 25 °C, VDD = 0 V)

MAX.

UNIT

PARAMETER

Input capacitance

Output capacitance

SYMBOL

CIN

TEST CONDITIONS

MIN.

TYP.

f = 1 MHz

Unmeasured pin returned to 0 V

COUT

Input /output

capacitance

CIO

µPD75P316A

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

RECOMMENDED CIRCUIT

PARAMETER

TEST CONDITIONS

MIN.

1.0

TYP.

UNIT

MHz

RESONATOR

MAX.

Oscillator frequency

(fX) *1

5.0*3

Ceramic

resonator

After VDD reaches the

Oscillation stabilization minimum value in the

time *2

oscillation voltage

range

Oscillator frequency

(f^X) *1

1.0

5.0*3

4.19

MHz

Crystal

resonator

V^DD= 4.5 to 6.0 V

Oscillation stabilization

time *2

VDD

X1 input frequency

(fX) *1

5.0*3

MHz

1.0

External

clock

X1 high and low level

widths (tXH, tXL)

100

500

µPD74HCU04

1. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution

time.

2. Time required for oscillation to become stabilized after V^DDreaches MIN. of the oscillation voltage range or

after STOP mode release.

3. When the oscillator frequency is 4.19 MHz < f ≤ 5.0 MHz, do not select PPC = 0011 as instruction execution

time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 µs, with the result that specified MIN.

value 0.95 µs can not be observed.

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

TYP.

RESONATOR RECOMMENDED CIRCUIT

MAX.

PARAMETER

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

UNIT

kHz

Oscillator frequency

(fXT)

32.768

XT1

XT2

Crystal

resonator

1.0

Oscillation stabilization

time*

VDD

XT1 input frequency

(fXT)

kHz

100

External

clock

XT1 high and low level

widths (tXTH, tXTL)

µs

µPD75P316A

Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or after

STOP made release.

Note When the main system clock and subsystem clock oscillation circuit are used, the area enclosed by dotted

line in the figure should be wired as follows to prevent influence from the wiring capacitance, etc..

• Wiring should be as short as possible.

• Do not cross other signal lines.

Do not place the circuit closed to a line in which varying high current flows.

• The connecting point of oscillation circuit capacitor should always be the same potential as V^DD. Do

not connect it to the power supply pattern in which high current flows.

• Do not pick up a signal from the oscillation circuit.

The subsystem clock oscillation circuit is designed to be low amplification circuit for low dissipation

current, thus misoperation due to noise occurs more often than with the main system clock oscillation

circuit. Therefore, when the subsystem clock is used, care is needed especially for the wiring procedure.

µPD75P316A

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/2)

PARAMETER

SYMBOL

VIH1

TEST CONDITIONS

Ports 2 and 3

MIN.

0.7 VDD

0.8 VDD

0.7 VDD

VDD –0.5

TYP.

MAX.

VDD

UNIT

VIH2

Ports 0, 1, 6, 7, RESET

Ports 4 and 5

VDD

Input voltage

high

VIH3

Open-drain

VIH4

VIL1

X1, X2, XT1

VDD

Ports 2, 3, 4 and 5

Ports 0, 1, 6, 7, RESET

X1, X2, XT1

0.3 VDD

0.2 VDD

0.4

Input voltage

low

VIL2

VIL3

VDD = 4.5 to

6.0 V

IOH = –1 mA

Ports

0, 2, 3, 6, 7,

BIAS

VDD –1.0

VDD –0.5

VDD –2.0

VDD –1.0

VOH1

V0H2

Output voltage

high

IOH = -100 µA

VDD = 4.5 to

6.0 V

IOH = –100 µA

BP0 to BP7

(with 2 IOH

outputs)

IOH = –30 µA

Ports 3, 4 and 5

V^DD= 4.5 to

6.0 V

0.4

2.0

IOL = 15 mA

Ports

0, 2, 3, 4, 5, 6

and 7

VDD = 4.5 to

6.0 V

I^OL= 1.6 mA

0.4

0.5

VOL1

Output voltage

low

IOL = 400 µA

Open-drain

pull-up

resistor ≥ 1 kΩ

SB0, 1

0.2 V^DD

VDD = 4.5 to

6.0 V

I^OL= 100 µA

1.0

BP0 to BP7 (with 2

IOL outputs)

VOL2

I^OL= 50 µA

Other than

below

µA

ILIH1

ILIH2

VIN = VDD

VIN = 10 V

VIN = 0 V

X1, X2, XT1

Input leakage

current high

Ports 4 and 5

(when open-

drain)

µA

ILIH3

Other than

below

µA

ILIL1

ILIL2

-3

Input leakage

current low

X1, X2, XT1

-20

µPD75P316A

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/2)

PARAMETER

SYMBOL

TEST CONDITIONS

Other than

MIN.

TYP.

MAX.

UNIT

µA

ILOH1

VOUT = VDD

below

Output leakage

current high

Ports 4 and 5

(when open-

drain)

µA

I^LOH2

VOUT = 10 V

VOUT = 0 V

Output leakage

current low

ILOL

–3

V^DD= 5.0 V

kΩ

Ports 0, 1, 2, 3, 6

and 7 (Except P00)

VIN = 0 V

±10%

On-chip pull-up

resistor

RL1

VDD = 3.0 V

300

kΩ

±10%

LCD drive voltage

VDD

2.5

V^LCD

LCD output

voltage

deviation*1

(common)

VLCD0 = VLCD

VLCD1 =

VLCD × 2/3

VLCD2 = VLCD

× 1/3

IO = ±5 µA

IO = ±5µA

VODC

±0.2

LCD output

voltage

deviation*1

(segment)

2.7 V ≤ VLCD

≤ VDD

VODC

V^DD= 5 V

±10%*4

4.5

0.9

IDD1

VDD = 3 V

±10%*5

4.19 MHz*3 crystal

oscillation C1=C2

22 pF

HALT V^DD=

mode 5 V

±10%

700

2100

µA

IDD2

V^DD=

3 V

±10%

300

100

900

300

µA

Ope-

V^DD=

3 V

Supply current*2

IDD3

IDD4

rating

mode

±10%

32 kHz*6

crystal oscillation

HALT VDD =

mode 3 V

±10%

µA

VDD = 5 V±10%

0.5

0.1

µA

XT1 =

0 V STOP mode

IDD5

VDD =

3 V±10%

Ta = 25°C

0.1

µA

32 kHz

crystal oscillation

STOP mode

I^DD6

VDD = 3 V ±10%*7

µPD75P316A

1. The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n = 0, 1,

2) and output voltage.

2. Current flowing in the internal pull-up resistor and LCD split resistor are not included.

3. Includes when the subsystem clock is oscillated.

4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode.

5. When the PCC is set to 0000 and operated in low-speed mode.

6. When operated by the subsystem clock with the system clock control register (SCC) set to 1011 and the main

system clock stops.

7. When the STOP instruction is executed during the main system clock operation and the subsystem clock is

oscillated.

µPD75P316A

AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

TYP.

MAX. UNIT

0.95

3.8

µs

Operation with main

system clock

CPU clock cycle time

(minimum instruction

execution time = 1

machine cycle )*1

tCY

Operation with

114

122

125

µs

subsystem clock

MHZ

kHz

µs

VDD = 4.5 to 6.0 V

fTI

TI0 input frequency

275

0.48

t^TIH,

TI0 input high and low-

level widths

tTIL

1.8

µs

INT0

tINTH,

Interrupt input high and

low-level widths

INT1, 2, 4

KR0–7

t^INTL

µs

RESET low-level width

tRSL

CY VS

* 1. CPU clock (Φ) cycle time is determined by oscillator

frequencyoftheconnectedresonator, systemclock

control register (SCC) and processor clock control

voltage V^DDvs • cycle time tCY in main system clock

operation is shown below.

(Main System Clock in Operation)

2. It becomes 2t^CYor 128/f by interrupt mode register

(IM0) setting.

0.5

Power Supply Voltage V^DD[V]

µPD75P316A

Serial Transfer Operation

2-wire and 3-wire serial I/O mode (SCK...Internal clock output)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

1600

TYP.

MAX. UNIT

tKCY1

SCK cycle time

3800

tKL1

tKH1

tSIK1

tKSI1

V^DD= 4.5 to 6.0 V

tKCY1/2–50

tKCY1/2–150

150

SCK high and low level

widths

SI setup time (to SCK↑)

SI hold time (from SCK↑)

400

V^DD= 4.5 to 6.0 V

250

SO output delay time

from SCK↓

R^L= 1 k Ω, CL = 100 pF*

tKSO1

1000

and C

are SO output line load resistance and load capacitance, respectively.

2-wire and 3-wire serial I/O mode (SCK...External clock input)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

800

TYP.

MAX. UNIT

SCK cycle time

tKCY2

3200

400

tKL2

tKH2

tSIK2

tKSI2

VDD = 4.5 to 6.0 V

SCK high and low level

widths

1600

100

SI setup time (to SCK↑)

SI hold time (from SCK↑)

400

V^DD= 4.5 to 6.0 V

300

SO output delay time

from SCK↓

tKSO2

RL = 1 k Ω, CL = 100 pF*

1000

and C are SO output line load resistance and load capacitance, respectively.

µPD75P316A

SBI mode (SCK...Internal clock output (master))

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

1600

3800

tKCY3/2–50

tKCY3/2–150

150

TYP.

MAX. UNIT

SCK cycle time

tKCY3

tKL3

tKH3

tSIK3

tKSI3

VDD = 4.5 to 6.0 V

SCK high and low level

widths

SB0andSB1setuptime(toSCK↑)

SB0andSB1holdtime (fromSCK↑)

tKCY3/2

VDD = 4.5 to 6.0 V

250

SB0 and SB1 output

delay time from SCK↓

tKSO3

RL = 1 k Ω, CL = 100 pF*

1000

SB0, SB1↓ from SCK↑

SCK from SB0, SB1↓

t^KCY3

tKSB

tSBK

tSBL

tSBH

tKCY3

t^KCY3

SB0andSB1low-levelwidths

SB0andSB1high-levelwidths

t^KCY3

and C are SO output line load resistance and load capacitance, respectively.

SBI mode (SCK...External clock input (slave))

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

800

3200

400

TYP.

MAX. UNIT

SCK cycle time

tKCY4

tKL4

tKH4

tSIK4

tKSI4

VDD = 4.5 to 6.0 V

SCK high and low level

widths

1600

100

tKCY3/2

SB0andSB1setuptime(toSCK↑)

SB0andSB1holdtime (fromSCK↑)

VDD = 4.5 to 6.0 V

300

SB0 and SB1 output

delay time from SCK↓

tKSO4

RL = 1 k Ω, CL = 100 pF*

1000

SB0, SB1↓ from SCK↑

SCK from SB0, SB1↓

tKCY4

tKSB

tSBK

tSBL

tSBH

SB0andSB1low-levelwidths

SB0andSB1high-levelwidths

and C are SO output line load resistance and load capacitance, respectively.

µPD75P316A

AC Timing Test Points (Except X1 and XT1 Inputs)

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

Test Points

Clock Timing

1/fX

tXL

tXH

X1 Input

V_DD- 0.5 V

0.4 V

1/fXT

XTL

tXTH

XT1 Input

VDD - 0.5 V

0.4 V

TI0 Timing

1/fT1

TIL

tTIH

TI0

µPD75P316A

Serial Transfer Timing

3-wire serial I/O mode:

KCY1

KH1

tKL1

SCK

tSIK1

tKSI1

Input Data

tKSO1

Output Data

2-wire serial I/O mode:

KCY2

KL2

KH2

SCK

SIK2

KS12

SB0,1

KSO2

µPD75P316A

Serial Transfer Timing

Bus release signal transfer:

KCY3,4

KL3,4

KH3,4

SCK

SIK3,4

tKSB

SBL

SBH

tSBK

KSI3,4

SB0,1

KSO3,4

Command signal transfer:

KCY3,4

KL3,4

KH3,4

SCK

SIK3,4

KSB

tSBK

tKSI3,4

SB0,1

KSO3,4

Interrupt Input Timing

INTL

INTH

INT0,1,2,4

KR0-7

RESET Input Timing

tRSL

RESET

µPD75P316A

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40

to +85 °C)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

2.0

TYP.

0.1

MAX.

6.0

UNIT

VDDDR

IDDDR

tSREL

Data retention power supply voltage

Data retention power supply current *1

Release signal set time

VDDDR = 2.0 V

µA

µs

Release by RESET

2¹⁷/fX

Oscillation stabilization wait

tWAIT

time *2

Release by interrupt request

* 1. Current to the internal pull-up resistor is not included.

2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation

start.

3. According to the setting of the basic interval timer mode register (BTM) (see below).

Wait Time

BTM3

BTM2

BTM1

BTM0

(Values at f^XX= 4.19 MHz in parentheses)

2²⁰/fXX (approx. 250 ms)

—

2¹⁷/fXX (approx. 31.3 ms)

2¹⁵/fXX (approx. 7.82 ms)

2¹³/fXX (approx. 1.95 ms)

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

Operating Mode

STOP Mode

Data Retention Mode

VDD

tSREL

VDDDR

STOP Instruction Execution

RESET

WAIT

µPD75P316A

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT Mode

Operating Mode

STOP Mode

Data Retention Mode

VDD

SREL

VDDDR

STOP Instruction Execution

Standby Release Signal

(Interrupt Request)

WAIT

DC PROGRAMMING CHARACTERISTICS (Ta = –25 to ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)

MAX.

UNIT

TYP.

TEST CONDITIONS

Except X1, X2

MIN.

PARAMETER

SYMBOL

0.7 VDD

VIH1

VDD

Input voltage high

VDD –0.5

VIH2

VIL1

VIL2

X1, X2

Except X1, X2

0.3 VDD

0.4

Input voltage low

X1, X2

Input leakage current

Output voltage high

µA

ILI

VIN = VIL or VIH

IOH = –1mA

VDD –1.0

VOH

Output voltage low

0.4

VOL

IDD

IOL = 1.6 mA

VDD power supply current

V^PPpower supply current

IPP

MD0 = VIL, MD1 = VIH

Note 1. VPP including overshoot should not exceed +13.5 V.

2. V^DDshould be applied before VPP and should be cut after VPP

µPD75P316A

AC PROGRAMMING CHARACTERISTICS (Ta = 25 to ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)

TEST CONDITIONS

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Address setup time*2 (to MD0 ↓)

µs

t^AS

tAS

tM1S

tOES

MD1 setup time (to MD0 ↓)

Data setup time (to MD0 ↓)

tDS

Address hold time*2 (from MD0 ↑)

Data hold time (to MD0 ↑)

tAH

tDH

tAH

tDH

µs

Data output float delay time from MD0 ↑

VPP setup time (to MD3 ↑)

tDF

130

µs

tVPS

tVDS

tPW

tVPS

tVCS

tPW

tOPW

tCES

µs

VDD setup time (to MD3 ↑)

µs

1.05

21.0

0.95

1.0

Initial program pulse width

Additional program pulse width

MD1 setup time (to MD1 ↑)

tOPW

tMOS

Data output delay time from MD0 ↓

MD1 hold time (from MD0 ↑)

MD1 recovery time (from MD0 ↓)

Program counter reset time

tDV

MD0 = MD1 = V^IL

µs

tM1H

tM1R

tOEH

tOR

tM1H + tM1R ≥ 50 µs

tPCR

–

µs

X1 input high/low level width

X1 input frequency

tXH, tXL

0.125

4.19

MHz

µs

–

Initial mode set time

µs

tM3S

tM3H

MD3 setup time (to MD1 ↑)

MD3 hold time (from MD1 ↓)

MD3 setup time (to MD0 ↓)

–

µs

tM3SR

When reading program memory

tDAD

tHAD

tACC

tOH

Data output delay time from address*2

Data output hold time from address*2

130

µs

tM3HR

tDFR

MD3 hold time (from MD0 ↑)

–

Data output float delay time from MD3 ↓

When reading program memory

1. Symbol of the corresponding µPD27C256A.

2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not

connected to pins.

µPD75P316A

Program Memory Write Timing

tVPS

VDD

tVDS

VDD + 1

VDD

tXH

P40 – P43

P50 –P53

Data Input

Data Output

tAS

MD0

MOS

OPW

tM1R

tPW

MD1

MD2

PCR

M1S

tM1H

M3H

M3S

MD3

Program Memory Read Timing

tVPS

VPP

VDD

tVDS

DD + 1

VDD

DAD

tHAD

P40 – P43

P50 –P53

Data Output

tDFR

tDV

tM3HR

MD0

MD1

MD2

tPCR

M3SR

MD3

µPD75P316A

6. PACKAGE INFORMATION

80 PIN PLASTIC QFP (14×20)

detail of lead end

P80GF-80-3B9-2

NOTE

ITEM

MILLIMETERS

INCHES

Each lead centerline is located within 0.15

mm (0.006 inch) of its true position (T.P.) at

maximum material condition.

23.6 0.4

0.929 0.016

+0.009

20.0 0.2

0.795

–0.008

+0.009

14.0 0.2

0.551

–0.008

0.693 0.016

17.6 0.4

1.0

0.8

0.039

0.031

+0.004

0.35 0.10

0.014

–0.005

0.15

0.006

0.8 (T.P.)

0.031 (T.P.)

+0.008

1.8 0.2

0.071

–0.009

+0.009

0.031

0.8 0.2

–0.008

+0.10

+0.004

0.15

0.006

–0.05

–0.003

0.15

2.7

0.006

0.106

0.1 0.1

0.004 0.004

3.0 MAX.

0.119 MAX.

µPD75P316A

80 PIN CERAMIC WQFN

X80KW-80A-1

NOTE

ITEM

MILLIMETERS

INCHES

Each lead centerline is located within 0.08

mm (0.003 inch) of its true position (T.P.) at

maximum material condition.

+0.017

20.0 0.4

0.787

–0.016

19.0

13.2

0.748

0.520

14.2 0.4

0.559 0.016

1.64

0.065

2.14

0.084

4.064 MAX.

0.160 MAX.

0.51 0.10

0.020 0.004

0.08

0.003

0.8 (T.P.)

0.031 (T.P.)

+0.009

1.0 0.2

0.039

–0.008

C 0.5

0.8

C 0.020

0.031

1.1

0.043

R 3.0

12.0

R 0.118

0.472

+0.008

0.75 0.2

0.030

–0.009

µPD75P316A

7. RECOMMENDED SOLDERING CONDITIONS

The µPD75P316A should be soldered and mounted under the conditions recommended in the table below.

For detail of recommended soldering conditions, refer to the information document “Semiconductor Device

Mount Manual” (IEI-1207).

For soldering methods and conditions other than those recommended below, contact our salesman.

Table 7-1 Surface Mounting Type Soldering Conditions

µPD75P316AGF-3B9 : 80-pin plastic QFP (14 × 20 mm)

Recommended

Solderring Method

Wave soldering

Solderring Conditions

Condition Symbol

Solder bath temperature: 260 °C or below. , Duration: 10 sec. max.

Number of times: Once, Time limit: 7 days*(thereafter 20 hours prebaking required

at 125 °C)

WS60-207-1

Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above),

Number of times: Once, Time limit: 7 days*(thereafter 20 hours prebaking required

at 125 °C)

Infrared reflow

IR30-207-1

Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above),

Number of times: Once, Time limit: 7 days* (thereafter 20 hours prebaking required

at 125 °C)

VPS

VP15-207-1

–––

Pin part heating

Pin part temperature: 300 °C or below , Duration: 3 sec. max. (per device side)

For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65 % RH.

Note Use more than one soldering method should be avoided (except in the case of pin part heating).

For Your Information

Products to improve the recommended soldering conditions are available.

(Improvements : Extension of the infrared reflow peak temperature to 235 °C, doubled frequency, increased

life, etc.)

For further details, consult our sales personnel.

µPD75P316A

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD75P316A.

IE-75000-R*1

In-circuit emulator for use with the 75X series

IE-75001-R

IE-75000-R-EM*2

Emulation board for use with the IE-75000-R and the IE-75001-R

EP-75308GF-R

Emulation probe for use with the µPD75P308GF 80-pin conversion socket EV-9200G-80

included

EV-9200G-80

PG-1500

PROM programmer

PA-75P308GF

PA-75P308K

Connect to PG-1500 with PROM programmer adapter for use with the µPD75P308GF

Connect to PG-1500 with PROM programmer adapter for use wtih the µPD75P308K

IE-control program

Host machine

PG-1500 controller

• PC-9800 series (MS-DOS Ver. 3.30 to Ver.5.00A *3)

• IBM PC/AT (PC DOS Ver. 3.1)

RA75X relocatable assembler

1. Maintenance product

2. Not a built-in component in the IE-75001-R

3. Ver. 5.00/5.00A has a task swaping function, which cannot be used with this software.

Remarks Refer to the 75X Series Selection Guide (IF-151) for third-party development tools.

µPD75P316A

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

User's Manual

Document Number

IEM-5016

Instruction Application Table

75X Series Selection Guide

IEM-994

IF-151

Development Tools Documents

Document Name

IE-75000-R/IE-75001-R User's Manual

IE-75000-R-EM User's Manual

EP-75308GF-R User's Manual

Document Number

EEU-846

EEU-673

EEU-689

EEU-651

EEU-731

EEU-730

EEU-704

PG-1500 User's Manual

Operation Volume

Language Volume

RA75X Assembler Package User's Manual

PG-1500 Controller User's Manual

UPD75P316B [NEC]

相关型号：

UPD75P316BGC-3B9

UPD75P316BGK-BE9

UPD75P316BKK-T

UPD75P316GF

UPD75P316GF3B9

UPD75P3216

UPD75P3216GT

UPD75P3216GT

UPD75P3216GT-A

UPD75P328

UPD75P328GC

UPD75P328GC-3B9