UPD75P3216GT_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD75P3216

4-BIT SINGLE-CHIP MICROCONTROLLER

The µPD75P3216 replaces the µPD753208’s internal mask ROM with a one-time PROM, and features expanded

ROM capacity.

Because the µPD75P3216 supports programming by users, it is suitable for use in prototype testing for system

development using the µPD753204, 753206, or 753208, and for use in small-lot production.

The functions are explained in detail in the following user’s manual. Be sure to read this manual when

designing your system.

µPD753208 User’s Manual: U10158E

FEATURES

• Compatible with µPD753208

• Memory capacity:

•

PROM : 16384 × 8 bits

•

RAM : 512 × 4 bits

• Can operate in same power supply voltage range as the mask version µPD753208

V^DD= 1.8 to 5.5 V

•

• LCD controller/driver

ORDERING INFORMATION

Part Number

Package

48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)

µPD75P3216GT

Caution Mask-option pull-up resistors are not provided in this device.

The information in this document is subject to change without notice.

The mark

shows major revised points.

Document No. U10241EJ1V0DS00 (1st edition)

Date Published January 1997 N

Printed in Japan

1997

1995

'

©

µPD75P3216

FUNCTION OUTLINE

Parameter

Function

Instruction execution time

• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock)

• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock)

Internal memory

PROM 16384 × 8 bits

RAM

512 × 4 bits

General-purpose register

• 4-bit operation: 8 × 4 banks

• 8-bit operation: 4 × 4 banks

Input/

CMOS input

6

Connecting on-chip pull-up resistors can be specified by software: 5

output

port

CMOS input/output

20 Connecting on-chip pull-up resistors can be specified by software: 20

Also used for segment pins: 8

N-ch open-drain I/O

Total

4

13-V withstand

30

LCD controller/driver

• Segment selection:

4/8/12 segments (can be changed to CMOS input/

output port in 4-time units; max. 8)

• Display mode selection: Static

1/2 duty (1/2 bias)

1/3 duty (1/2 bias)

1/3 duty (1/3 bias)

1/4 duty (1/3 bias)

Timer

5 channels

• 8-bit timer/event counter: 1 channel

• 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier

generator, timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface

• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

• 2-wire serial I/O mode

• SBI mode

Bit sequential buffer (BSB)

Clock output (PCL)

16 bits

•

Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)

Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)

Buzzer output (BUZ)

• 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)

• 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)

Vectored interrupts

Test input

External: 2, Internal: 5

External: 1, Internal: 1

System clock oscillator

Standby function

Power supply voltage

Package

Ceramic or crystal oscillator for system clock oscillation

STOP/HALT mode

VDD = 1.8 to 5.5 V

48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)

2

µPD75P3216

CONTENTS

1. PIN CONFIGURATION (Top View) .................................................................................................... 4

2. BLOCK DIAGRAM .............................................................................................................................. 5

3. PIN FUNCTIONS ................................................................................................................................. 6

3.1 Port Pins ...................................................................................................................................................... 6

3.2 Non-port Pins .............................................................................................................................................. 7

3.3 Equivalent Circuits for Pins...................................................................................................................... 8

3.4 Recommended Connection of Unused Pins ........................................................................................ 10

4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................ 11

4.1 Difference between Mk I Mode and Mk II Mode ................................................................................... 11

4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................. 12

5. Differences between µPD75P3216 and µPD753204, 753206, and 753208 ................................13

6. MEMORY CONFIGURATION ........................................................................................................... 14

7. INSTRUCTION SET........................................................................................................................... 16

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................25

8.1 Operation Modes for Program Memory Write/Verify........................................................................... 25

8.2 Program Memory Write Procedure ........................................................................................................ 26

8.3 Program Memory Read Procedure ........................................................................................................ 27

8.4 One-time PROM Screening ..................................................................................................................... 28

9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 29

10. CHARACTERISTIC CURVE (REFERENCE VALUE) ...................................................................... 42

11. PACKAGE DRAWINGS .................................................................................................................... 44

12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 45

APPENDIX A. µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST ...........................................46

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 48

APPENDIX C. RELATED DOCUMENTS............................................................................................... 52

3

µPD75P3216

1. PIN CONFIGURATION (Top View)

•

48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)

µPD75P3216GT

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

COM0

COM1

COM2

COM3

S12

S13

S14

S15

P93/S16

P92/S17

P91/S18

P90/S19

P83/S20

P82/S21

P81/S22

P80/S23

P23

P22/PCL/PTO2

P21/PTO1

P20/PTO0

P13/TI0

P10/INT0

P03/SI/SB1

P02/SO/SB0

P01/SCK

P00/INT4

BIAS

V

LC0

LC1

LC2

9

P30/LCDCL/MD0

P31/SYNC/MD1

P32/MD2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P33/MD3

V

SS

P50/D4

P51/D5

P52/D6

P53/D7

P60/KR0/D0

P61/KR1/D1

P62/KR2/D2

P63/KR3/D3

VDD

RESET

X1

X2

Note

PP

V

Note Be sure to connect VPP to VDD directly in normal operation mode.

PIN IDENTIFICATIONS

PCL

: Programmable Clock

BIAS

BUZ

: LCD Power Supply Bias Control

: Buzzer Clock

PTO0-PTO2 : Programmable Timer Output 0 to 2

RESET

S12-S23

SB0, SB1

SCK

: Reset Input

COM0-COM3 : Common Output 0 to 3

: Segment Output 12 to 23

: Serial Bus 0, 1

D0-D7

: Data Bus 0 to 7

: External Vectored Interrupt 0, 4

: Key Return 0 to 3

: LCD Clock

: Mode Selection 0 to 3

: Port0

INT0, INT4

KR0-KR3

LCDCL

: Serial Clock

SI

: Serial Input

SO

: Serial Output

MD0-MD3

P00-P03

P10, P13

P20-P23

P30-P33

P50-P53

P60-P63

P80-P83

P90-P93

SYNC

TI0

: LCD Synchronization

: Timer Input 0

: Port1

V^DD

: Positive Power Supply

: LCD Power Supply 0 to 2

: Programming Power Supply

: Ground

: Port2

VLC0-VLC2

V^PP

: Port3

: Port5

VSS

: Port6

X1, X2

: System Clock Oscillation 1, 2

: Port8

: Port9

4

µPD75P3216

2. BLOCK DIAGRAM

WATCH

BUZ/P23

TIMER

INTW fLCD

PORT0

PORT1

PORT2

PORT3

PORT5

PORT6

PORT8

PORT9

4

2

4

P00-P03

P10, P13

P20-P23

BASIC

INTERVAL

TIMER/

WATCHDOG

TIMER

SP (8)

PROGRAM

COUNTER

CY

ALU

INTBT

SBS

8-BIT

TIMER/EVENT

COUNTER #0

TI0/P13

P30/MD0-

P33/MD3

BANK

PTO0/P20

INTT0 TOUT

P50/D4-

P53/D7

INTT1

GENERAL

REG.

P60/D0-

P63/D3

8-BIT

TIMER

CASCADED

COUNTER #1 16-BIT

PTO1/P21

TOUT

TIMER

COUNTER

8-BIT

TIMER

COUNTER #2

PROM

PROGRAM

MEMORY

P80-P83

P90-P93

DECODE

AND

CONTROL

PTO2/

PCL/P22

DATA

MEMORY

(RAM)

16384 × 8 BITS

INTT2

SI/SB1/P03

SO/SB0/P02

SCK/P01

CLOCKED

SERIAL

INTERFACE

512 × 4 BITS

4

S12-S15

INTCSI TOUT

S16/P93-

S19/P90

INT0/P10

INT4/P00

LCD

CONTROLLER/

DRIVER

S20/P83-

S23/P80

INTERRUPT

CONTROL

fx/2^N

CPU CLOCK Φ

fLCD

KR0/P60-

KR3/P63

COM0-COM3

4

CLOCK

OUTPUT

CONTROL

SYSTEM

CLOCK

DIVIDER

STANDBY

CONTROL

CLOCK

VLC0

GENERATOR

BIT SEQ.

BUFFER (16)

VLC1

VLC2

BIAS

LCDCL/P30

SYNC/P31

X1 X2

PCL/PTO2/P22

Vpp VDD VSS RESET

5

µPD75P3216

3. PIN FUNCTIONS

3.1 Port Pins

8-bit

I/O

Status

After Reset Type^{Note 1}

I/O Circuit

Pin Name

P00

I/O

Shared by

Function

Input INT4

×

Input

This is a 4-bit input port (PORT0).

P01 to P03 are 3-bit pins for which an internal

pull-up resistor can be connected by software.

P01

P02

P03

P10

I/O

SCK

<F>-A

<F>-B

<M>-C

-C

SO/SB0

SI/SB1

Input INT0

×

Input

This is a 1-bit input port (PORT1).

These are 1-bit pins for which an internal pull-up

resistor can be connected by software.

P10/INT0 can select noise elimination circuit.

P13

TI0

This is a 4-bit I/O port (PORT2).

P20

P21

P22

P23

P30

P31

P32

P33

P50

P51

P52

P53

I/O

PTO0

PTO1

PCL/PTO2

BUZ

E-B

M-E

These are 4-bit pins for which an internal pull-up

resistor can be connected by software.

This is a programmable 4-bit I/O port (PORT3).

Input and output in single-bit units can be specified.

When set for 4-bit units, an internal pull-up resistor

can be connected by software.

LCDCL/MD0

SYNC/MD1

MD2

×

Input

MD3

Note 2

D4

High

This is an N-ch open-drain 4-bit I/O port (PORT5).

When set to open-drain, voltage is 13 V.

Also functions as data I/O pin (upper 4 bits)

for program memory (PROM) write/verify.

D5

impedance

D6

D7

This is a programmable 4-bit I/O port (PORT6).

Input and output in single-bit units can be specified.

When set for 4-bit units, an internal pull-up resistor

can be connected by software.

P60

P61

P62

I/O

KR0/D0

KR1/D1

KR2/D2

×

Input

<F>-A

Also functions as data I/O pin (lower 4 bits) for

program memory (PROM) write/verify.

P63

P80

P81

P82

P83

P90

P91

P92

P93

KR3/D3

S23

I/O

Input

H

This is a 4-bit I/O port (PORT8).

When set for 4-bit units, an internal pull-up resistor

can be connected by software.

S22

S21

S20

S19

This is a programmable 4-bit I/O port (PORT9).

When set for 4-bit units, an internal pull-up resistor

can be connected by software.

S18

S17

S16

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.

2. Low level input current leakage increases when input instructions or bit manipulation instructions are

executed.

6

µPD75P3216

3.2 Non-port Pins

Status

After Reset Type^{Note 1}

I/O Circuit

Pin Name

TI0

I/O

Shared by

Function

Input P13

Output P20

P21

External event pulse input to timer/event counter

Timer/event counter output

Input

-C

E-B

PTO0

PTO1

PTO2

PCL

Timer counter output

P22/PCL

P22/PTO2

P23

Clock output

BUZ

Any frequency output (for buzzer or system clock trimming)

Serial clock I/O

SCK

I/O

P01

Input

<F>-A

<F>-B

SO/SB0

P02

Serial data output

Serial data bus I/O

SI/SB1

INT4

P03

Serial data input

<M>-C

Serial data bus I/O

Input P00

Input P10

Edge detection vectored interrupt input

(detecting both rising and falling edges)

Input

INT0

Edge detection vectored interrupt input

(detected edge is selectable). INT0/P10

can select noise elimination circuit

-C

Noise elimination

circuit/asynch

is selectable

KR0 to KR3

X1

Input P60/D0-P63/D3

Falling edge detection testable input

Input

—

<F>-A

—

Ceramic/crystal oscillation circuit connection for system

clock. If using an external clock, input to X1 and input

inverted phase to X2.

Input

—

X2

—

RESET

Input

—

System reset input

—

<F>-A

M-E

MD0 to MD3

D0 to D3

D4 to D7

VPP

Input P30 to P33

Mode selection for program memory (PROM) write/verify

Input

I/O

P60/KR0-P63/KR3 Data bus pin for program memory (PROM) write/verify.

P50 to P53

—

Programmable power supply voltage for program memory

(PROM) write/verify.

—

For normal operation, connect directly to V^DD.

Apply +12.5 V for PROM write/verify.

VDD

—

Positive power supply

Ground

—

VSS

S12 to S15

S16 to S19

S20 to S23

Output

Segment signal output

Note 2

Input

G-A

H

Output P93 to P90

P83 to P80

COM0 to COM3 Output

—

Common signal output

Note 2

—

G-B

—

VLC0 to VLC2

BIAS

—

Power source for LCD drive

Output

Output for external split resistor cut

Note 3

Input

—

Note 4

LCDCL

Output P30/MD0

P31/MD1

Clock output for driving external expansion driver

Clock output for synchronization of external expansion driver

E-B

Note 4

SYNC

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.

2. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.

S12 to S15: V^LC1, COM1 to COM2: VLC2, COM3: VLC0

3. When the split resistor is incorporated

: Low level

When the split resistor is not incorporated: High impedance

4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

7

µPD75P3216

3.3 Equivalent Circuits for Pins

The equivalent circuits for the µPD75P3216’s pins are shown in abbreviated form below.

TYPE A

TYPE D

VDD

Data

P-ch

OUT

P-ch

IN

Output

disable

N-ch

Push-pull output that can be set to high impedance output

(with both P-ch and N-ch OFF).

CMOS standard input buffer

TYPE B

TYPE E-B

VDD

P.U.R.

P-ch

P.U.R.

enable

IN

Data

IN/OUT

Type D

Output

disable

Type A

Schmitt trigger input with hysteresis characteristics.

P.U.R. : Pull-Up Resistor

TYPE B-C

TYPE F-A

VDD

P.U.R.

P-ch

P.U.R.

enable

P.U.R.

enable

P-ch

Data

IN/OUT

Type D

Output

disable

IN

Type B

P.U.R. : Pull-Up Resistor

(Continued)

8

µPD75P3216

(Continued)

TYPE F-B

TYPE H

VDD

P.U.R.

P-ch

P.U.R.

enable

Output

disable

(P)

V

DD

IN/OUT

SEG

data

Type G-A

Type E-B

P-ch

IN/OUT

Data

Output

disable

N-ch

Data

Output

disable

(N)

Output

disable

P.U.R. : Pull-Up Resistor

TYPE G-A

TYPE M-C

VDD

V^LC0

P.U.R.

P-ch

IN/OUT

VLC1

P.U.R.

enable

P-ch N-ch

OUT

Data

N-ch

SEG

data

Output

disable

N-ch

VLC2

N-ch

P.U.R. : Pull-Up Resistor

TYPE G-B

TYPE M-E

IN/OUT

V

LC0

LC1

data

N-ch

(+13 V)

output

disable

VDD

P-ch N-ch

input

instruction

P-ch

P.U.R.^Note

OUT

COM

data

Voltage

control

circuit

N-ch P-ch

V

LC2

(+13 V)

N-ch

Note This pull-up resistor is effective only when an input

instruction is executed (when the pin level is low,

current flows from V^DDto the pin).

9

µPD75P3216

3.4 Recommended Connection of Unused Pins

Recommended Connection

P00/INT4

Connect to Vss or VDD

P01/SCK

Connect to Vss or VDD through a resistor individually

P02/SO/SB0

P03/SI/SB1

P10/INT0

Connect to Vss

Connect to Vss or VDD

P13/TI0

P20/PTO0

Input status : connect to Vss or VDD through a resistor individually

Output status: open

P21/PTO1

P22/PTO2/PCL

P23/BUZ

P30/MD0/LCDCL

P31/MD1/SYNC

P32/MD2

P33/MD3

P50/D4 to P53/D7

Connect to Vss

P60/KR0/D0 to P63/KR3/D3 Input status : connect to Vss or VDD through a resistor individually

Output status: open

S12 to S15

Open

COM0 to COM3

S16/P93 to S19/P90

S20/P83 to S23/P80

VLC0 to VLC2

Input status : connect to Vss or VDD through a resistor individually

Output status: open

Connect to Vss

BIAS

Connect to Vss only when VLC0 to VLC2 are all not used.

In other cases, leave open.

VPP

Be sure to connect VDD directly.

10

µPD75P3216

4. Mk I AND Mk II MODE SELECTION FUNCTION

Setting a stack bank selection (SBS) register for the µPD75P3216 enables the program memory to be switched

between Mk I mode and Mk II mode. This function is applicable when using theµPD75P3216 to evaluate the µPD753204,

753206, or 753208.

When the SBS bit 3 is set to 1: sets Mk I mode (supports Mk I mode for µPD753204, 753206, and 753208)

When the SBS bit 3 is set to 0: sets Mk II mode (supports Mk II mode for µPD753204, 753206, and 753208)

4.1 Difference between Mk I Mode and Mk II Mode

Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3216.

Table 4-1. Difference between Mk I Mode and Mk II Mode

Item

Mk I Mode

Mk II Mode

Program counter

PC13-0

16384

512 × 4

Program memory (bytes)

Data memory (bits)

Stack

Stack bank

Selectable via memory banks 0, 1

No. of stack bytes

2 bytes

None

3 bytes

Instruction

BRA !addr1 instruction

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

Provided

Instruction

3 machine cycles

2 machine cycles

4 machine cycles

3 machine cycles

execution time

Supported mask ROMs

When set to Mk I mode:

When set to Mk II mode:

µPD753204, 753206, and 753208

Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This

mode enhances the software compatibility with products which have more than 16K bytes.

When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call

instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore,

when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine

cycle. Therefore, when more importance is attached to RAM utilization or throughput than software

compatibility, use the Mk I mode.

11

µPD75P3216

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for

doing this.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be

sure to initialize the stack bank selection register to 100XB^Noteat the beginning of the program. When using the Mk II

mode, be sure to initialize it to 000XB^Note

.

Note Set the desired value for X.

Figure 4-1. Format of Stack Bank Selection Register

Address

3

2

1

0

Symbol

F84H SBS3 SBS2 SBS1 SBS0 SBS

Stack area specification

0

1

0

1

0

1

Memory bank 0

Memory bank 1

Setting prohibited

0

Be sure to enter “0” for bit 2.

Mode selection specification

0

1

Mk II mode

Mk I mode

Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When

using instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the

instructions.

2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after

RESET input and after setting the stack bank selection register.

12

µPD75P3216

5. DIFFERENCES BETWEEN µPD75P3216 AND µPD753204, 753206, AND 753208

The µPD75P3216 replaces the internal mask ROM in the µPD753204, 753206, and 753208 with a one-time PROM

andfeaturesexpandedROMcapacity. TheµPD75P3216’sMkImodesupportstheMkImodeintheµPD753204,753206,

and 753208 and the µPD75P3216’s Mk II mode supports the Mk II mode in the µPD753204, 753206, and 753208.

Table 5-1 lists differences among the µPD75P3216 and the µPD753204, 753206, and 753208. Be sure to check the

differences among these products before using them with PROMs for debugging or prototype testing of application

systems or, later, when using them with a mask ROM for full-scale production.

For details on the CPU functions and internal hardware, refer to µPD753208 User’s Manual (U10158E).

Table 5-1. Differences between µPD75P3216 and µPD753204, 753206, and 753208

Item

µPD753204

12 bits

µPD753206

13 bits

µPD753208

µPD75P3216

14 bits

Program counter

Program memory (bytes)

Mask ROM

4096

Mask ROM

6144

Mask ROM

8192

One-time PROM

16384

Data memory (× 4 bits)

512

Mask options

Pull-up resistor for

Yes (specifiable)

No (off chip)

port 5

Note

Waiting time in

RESET

Yes (selectable from 2¹⁷/fX and 2¹⁵/fX)

No

(Fixed to 2¹⁵/fX ms)

Pin configuration Pin 9 to 12

Pin 14 to 17

P30 to P33

P30/MD0-P33/MD3

P50/D4-P53/D7

P50 to P53

Pin 18 to 20

P60/KR0 to P63/KR3

P60/KR0/D0-

P63/KR3/D3

Pin 25

IC

VPP

Other

Noise resistance and noise radiation may differ due to the different circuit sizes and

mask layouts.

Note 2¹⁷/fX = 21.8 ms (@6.0 MHz), 31.3 ms (@4.19 MHz)

2¹⁵/fX = 5.46 ms (@6.0 MHz), 7.81 ms (@4.19 MHz)

Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask

ROM versions from the PROM version in a process between prototype development and full

production, be sure to fully evaluate the mask ROM version’s CS (not ES).

13

µPD75P3216

6. MEMORY CONFIGURATION

Figure 6-1. Program Memory Map

7

6

5

0

0000H MBE RBE Internal reset start address (upper 6 bits)

Internal reset start address (lower 8 bits)

0002H MBE RBE INTBT/INT4 start address (upper 6 bits)

INTBT/INT4 start address (lower 8 bits)

CALLF

!faddr instruction

entry address

0004H MBE RBE INT0 start address (upper 6 bits)

INT0 start address (lower 8 bits)

0006H

BRCB

!caddr instruction

branch address

0008H MBE RBE INTCSI start address (upper 6 bits)

INTCSI start address (lower 8 bits)

Branch addresses for

the following instructions

• BR !addr

• CALL !addr

• BRA !addr1^Note

• CALLA !addr1^Note

• MOVT BCDE

• MOVT BCXA

000AH MBE RBE INTT0 start address (upper 6 bits)

INTT0 start address (lower 8 bits)

000CH MBE RBE INTT1/INTT2 start address (upper 6 bits)

INTT1/INTT2 start address (lower 8 bits)

Branch/call

address

0020H

by GETI

Reference table for GETI instruction

007FH

0080H

BR $addr instruction

relative branch address

(–15 to –1,

+2 to +16)

07FFH

0800H

0FFFH

1000H

BRCB

!caddr instruction

branch address

1FFFH

2000H

BRCB

!caddr instruction

branch address

2FFFH

3000H

BRCB

!caddr instruction

branch address

3FFFH

Note Can be used only in Mk II mode.

Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to

branch to addresses with changes in the PC’s lower 8 bits only.

14

µPD75P3216

Figure 6-2. Data Memory Map

Data memory

Memory bank

000H

General-purpose register area

(32 × 4)

01FH

020H

0

256 × 4

(224 × 4)

Stack area ^Note

Data area

static RAM

(512 × 4)

0FFH

100H

256 × 4

(236 × 4)

1EBH

1ECH

1

Display data memory (12 × 4)

(12 × 4)

(8 × 4)

1F7H

1F8H

1FFH

F80H

Not incorporated

128 × 4

15

Peripheral hardware area

FFFH

Note Memory bank 0 or 1 can be selected as the stack area.

15

µPD75P3216

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the

instruction’s operand representations (for further description, refer to RA75X Assembler Package User’s Manual

–Language (EEU-1343)). When there are several codes, select and use just one. Codes that consist of upper-case

letters and + or – symbols are key words that should be entered as they are.

For immediate data, enter an appropriate numerical value or label.

Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer

to µPD753208 User’s Manual (U10158E)). The number of labels that can be entered for fmem and pmem are

restricted.

Representation

reg

Coding Format

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

XA, BC, DE, HL

BC, DE, HL

reg1

rp

rp1

rp2

BC, DE

rp’

XA, BC, DE, HL, XA’, BC’, DE’, HL’

BC, DE, HL, XA’, BC’, DE’, HL’

HL, HL+, HL–, DE, DL

rp’1

rpa

rpa1

n4

DE, DL

4-bit immediate data or label

8-bit immediate data or label

n8

Note

mem

bit

8-bit immediate data or label

2-bit immediate data or label

fmem

pmem

addr

addr1

caddr

faddr

taddr

PORTn

IEXXX

RBn

MBn

FB0H to FBFH, FF0H to FFFH immediate data or label

FC0H to FFFH immediate data or label

0000H to 3FFFH immediate data or label

0000H to 3FFFH immediate data or label (Mk II mode only)

12-bit immediate data or label

11-bit immediate data or label

20H to 7FH immediate data (however, bit0 = 0) or label

PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9

IEBT, IECSI, IET0, IET1, IET2, IE0, IE2, IE4, IEW

RB0 to RB3

MB0, MB1, MB15

Note When processing 8-bit data, only even-numbered addresses can be specified.

16

µPD75P3216

(2) Operation legend

A

: A register; 4-bit accumulator

B

: B register

C

: C register

D

: D register

E

: E register

H

: H register

L

: L register

X

: X register

XA

BC

DE

HL

XA’

BC’

DE’

HL’

PC

SP

CY

PSW

MBE

RBE

: Register pair (XA); 8-bit accumulator

: Register pair (BC)

: Register pair (DE)

: Register pair (HL)

: Expansion register pair (XA’)

: Expansion register pair (BC’)

: Expansion register pair (DE’)

: Expansion register pair (HL’)

: Program counter

: Stack pointer

: Carry flag; bit accumulator

: Program status word

: Memory bank enable flag

: Register bank enable flag

PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)

IME

IPS

: Interrupt master enable flag

: Interrupt priority selection register

IEXXX : Interrupt enable flag

RBS

MBS

PCC

.

: Register bank selection register

: Memory bank selection register

: Processor clock control register

: Delimiter for address and bit

: Addressed data

(XX)

XXH

: Hexadecimal data

17

µPD75P3216

(3) Description of symbols used in addressing area

MB = MBE • MBS

*1

MBS = 0, 1, 15

MB = 0

*2

*3

MBE = 0

: MB = 0 (000H to 07FH)

MB = 15 (F80H to FFFH)

: MB = MBS

Data memory

addressing

MBE = 1

MBS = 0, 1, 15

MB = 15, fmem = FB0H to FBFH, FF0H to FFFH

MB = 15, pmem = FC0H to FFFH

*4

*5

*6

addr = 0000H to 3FFFH

addr, addr1 = (Current PC) – 15 to (Current PC) – 1

(Current PC) +2 to (Current PC) +16

*7

caddr = 0000H to 0FFFH (PC13

1000H to 1FFFH (PC13

2000H to 2FFFH (PC13

3000H to 3FFFH (PC13

,

12 = 00B) or

12 = 01B) or

12 = 10B) or

12 = 11B)

Program memory

addressing

*8

faddr = 0000H to 07FFH

taddr = 0020H to 007FH

*9

*10

*11

addr1 = 0000H to 3FFFH (Mk II mode only)

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies

as shown below.

•

No skip ....................................................................S = 0

Skipped instruction is 1-byte or 2-byte instruction .. S = 1

Skipped instruction is 3-byte instruction^Note........... S = 2

Note

3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

One machine cycle equals one cycle (= tCY) of the CPU clock F. Use the PCC setting to select among four cycle

times.

18

µPD75P3216

Instruction

Group

No. of Machine

Bytes Cycle

Addressing

Skip

Mnemonic

MOV

Operand

A, #n4

Operation

Area

Condition

Transfer

1

2

1

2

1

2

1

2

1

2

1

2

1

A←n4

String-effect A

reg1, #n4

XA, #n8

reg1←n4

XA←n8

HL←n8

rp2←n8

A←(HL)

String-effect A

String-effect B

HL, #n8

rp2, #n8

A, @HL

*1

*2

*1

*3

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

@HL, A

2+S A←(HL), then L←L+1

2+S A←(HL), then L←L–1

L=0

L=FH

1

2

1

2

1

A←(rpa1)

XA←(HL)

(HL)←A

@HL, XA

A, mem

(HL)←XA

A←(mem)

XA←(mem)

(mem)←A

(mem)←XA

A←reg

XA, mem

mem, A

mem, XA

A, reg

XA, rp’

XA←rp’

reg1, A

reg1←A

rp’1, XA

rp’1←XA

A↔(HL)

XCH

A, @HL

*1

*2

*1

*3

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

A, mem

2+S A↔(HL), then L←L+1

2+S A↔(HL), then L←L–1

L=0

L=FH

1

2

1

2

3

A↔(rpa1)

XA↔(HL)

A↔(mem)

XA, mem

A, reg1

XA↔(mem)

A↔reg1

XA, rp’

XA↔rp’

Table

MOVT

XA, @PCDE

XA, @PCXA

XA, @BCDE

XA, @BCXA

XA←(PC13-8+DE)ROM

XA←(PC13-8+XA)ROM

XA←(B2-0+BCDE)ROM

XA←(B2-0+BCXA)ROM

reference

Note

*6

Note Only the lower 2 bits in the B register are valid.

19

µPD75P3216

Instruction

Group

No. of Machine

Bytes Cycle

Addressing

Area

Skip

Mnemonic

MOV1

Operand

Operation

CY←(fmem.bit)

Condition

Bit transfer

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

fmem.bit, CY

pmem.@L, CY

@H+mem.bit, CY

A, #n4

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

*4

*5

*1

*4

*5

*1

CY←(pmem7-2+L3-2.bit(L1-0))

CY←(H+mem3-0.bit)

(fmem.bit)←CY

(pmem7-2+L3-2.bit(L1-0))←CY

(H+mem3-0.bit)←CY

Arithmetic

ADDS

1+S A←A+n4

carry

XA, #n8

A, @HL

XA, rp’

2+S XA←XA+n8

1+S A←A+(HL)

2+S XA←XA+rp’

2+S rp’1←rp’1+XA

carry

*1

rp’1, XA

A, @HL

XA, rp’

ADDC

SUBS

SUBC

AND

1

2

A, CY←A+(HL)+CY

XA, CY←XA+rp’+CY

rp’1, CY←rp’1+XA+CY

rp’1, XA

A, @HL

XA, rp’

1+S A←A–(HL)

2+S XA←XA–rp’

2+S rp’1←rp’1–XA

borrow

rp’1, XA

A, @HL

XA, rp’

1

2

1

2

1

2

1

2

1

2

A, CY←A–(HL)–CY

XA, CY←XA–rp’–CY

rp’1, CY←rp’1–XA–CY

A←A n4

rp’1, XA

A, #n4

A, @HL

XA, rp’

A←A (HL)

*1

XA←XA rp’

rp’1, XA

A, #n4

rp’1←rp’1 XA

A←A n4

OR

A, @HL

XA, rp’

A←A (HL)

XA←XA rp’

rp’1, XA

A, #n4

rp’1←rp’1 XA

A←A n4

XOR

A, @HL

XA, rp’

A←A (HL)

XA←XA rp’

rp’1, XA

A

rp’1←rp’1 XA

CY←A0, A3←CY, An-1←An

A←A

Accumulator

manipulation

RORC

NOT

A

INCS

reg

1+S reg←reg+1

1+S rp1←rp1+1

2+S (HL)←(HL)+1

2+S (mem)←(mem)+1

1+S reg←reg–1

2+S rp’←rp’–1

reg=0

Increment/

decrement

rp1

rp1=00H

(HL)=0

@HL

*1

*3

mem

(mem)=0

reg=FH

rp’=FFH

DECS

reg

rp’

20

µPD75P3216

Instruction

Group

No. of Machine

Bytes Cycle

Addressing

Skip

Mnemonic

SKE

Operand

reg, #n4

Operation

Area

Condition

Comparison

2

1

2

1

2

2+S Skip if reg=n4

reg=n4

@HL, #n4

A, @HL

2+S Skip if(HL)=n4

1+S Skip if A=(HL)

2+S Skip if XA=(HL)

2+S Skip if A=reg

2+S Skip if XA=rp’

*1

(HL)=n4

A=(HL)

XA=(HL)

A=reg

XA, @HL

A, reg

XA, rp’

XA=rp’

Carry flag

SET1

CLR1

SKT

CY

1

CY←1

CY←0

manipulation

CY

1+S Skip if CY=1

CY=1

NOT1

SET1

CY

1

2

CY←CY

Memory bit

mem.bit

(mem.bit)←1

(fmem.bit)←1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

manipulation

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

(pmem7-2+L3-2.bit(L1-0))←1

(H+mem3-0.bit)←1

(mem.bit)←0

CLR1

SKT

fmem.bit

(fmem.bit)←0

pmem.@L

@H+mem.bit

mem.bit

(pmem7-2+L3-2.bit(L1-0))←0

(H+mem3-0.bit)←0

2+S Skip if(mem.bit)=1

(mem.bit)=1

fmem.bit

2+S Skip if(fmem.bit)=1

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

(mem.bit)=0

pmem.@L

@H+mem.bit

mem.bit

2+S Skip if(pmem7-2+L3-2.bit(L1-0))=1

2+S Skip if(H+mem3-0.bit)=1

2+S Skip if(mem.bit)=0

SKF

fmem.bit

2+S Skip if(fmem.bit)=0

(fmem.bit)=0

(pmem.@L)=0

(@H+mem.bit)=0

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

pmem.@L

@H+mem.bit

fmem.bit

2+S Skip if(pmem7-2+L3-2.bit(L1-0))=0

2+S Skip if(H+mem3-0.bit)=0

2+S Skip if(fmem.bit)=1 and clear

2+S Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear

2+S Skip if(H+mem3-0.bit)=1 and clear

SKTCLR

AND1

OR1

pmem.@L

@H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

2

CY←CY (fmem.bit)

CY←CY (pmem7-2+L3-2.bit(L1-0))

CY←CY (H+mem3-0.bit)

CY←CY (fmem.bit)

CY←CY (pmem7-2+L3-2.bit(L1-0))

CY←CY (H+mem3-0.bit)

CY←CY (fmem.bit)

XOR1

CY←CY (pmem7-2+L3-2.bit(L1-0))

CY←CY (H+mem3-0.bit)

21

µPD75P3216

Instruction

Group

No. of Machine

Bytes Cycle

Addressing

Area

Skip

Mnemonic

Operand

addr

Operation

Condition

Note

Branch

BR

—

PC13-0←addr

*6

Use the assembler to select the

most appropriate instruction

among the following.

• BR !addr

• BRCB !caddr

• BR $addr

addr1

—

PC13-0←addr1

*11

Use the assembler to select

the most appropriate instruction

among the following.

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

!addr

3

1

2

3

2

3

2

3

2

PC13-0←addr

*6

*7

$addr

$addr1

PCDE

PCXA

BCDE

BCXA

!addr1

!caddr

PC13-0←addr

PC13-0←addr1

PC13-0←PC13-8+DE

PC13-0←PC13-8+XA

PC13-0←BCDE

*6

PC13-0←BCXA

Note

BRA

PC13-0←addr1

*11

*8

BRCB

PC13-0←PC13, 12+caddr11-0

Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

22

µPD75P3216

Instruction

Group

No. of Machine

Bytes Cycle

Addressing

Skip

Mnemonic

Operand

!addr1

Operation

Area

Condition

Note

Subroutine

CALLA

3

(SP–6)(SP–3)(SP–4)←PC11-0

(SP–5)←0, 0, PC13, 12

stack control

(SP–2)

←X, X, MBE, RBE

PC13–0

←

addr1, SP SP–6

←

Note

CALL

!addr

3

4

(SP–4)(SP–1)(SP–2)

(SP–3) MBE, RBE, PC13, 12

addr, SP SP–4

←

PC11-0

*6

←

PC13–0

←

(SP–6)(SP–3)(SP–4)←PC11-0

(SP–5)←0, 0, PC13, 12

(SP–2)

←X, X, MBE, RBE

PC13-0

←

addr, SP SP–6

←

Note

CALLF

!faddr

2

1

2

3

(SP–4)(SP–1)(SP–2)

(SP–3) MBE, RBE, PC13, 12

PC13-0←000+faddr, SP←SP–4

←

PC11-0

*9

←

(SP–6)(SP–3)(SP–4)←PC11-0

(SP–5)←0, 0, PC13, 12

(SP–2)←X, X, MBE, RBE

PC13-0←000+faddr, SP←SP–6

Note

RET

3

MBE, RBE, PC13, 12←(SP+1)

PC11-0←(SP)(SP+3)(SP+2)

SP←SP+4

X, X, MBE, RBE←(SP+4)

PC11-0←(SP)(SP+3)(SP+2)

MBE, 0, PC13, 12←(SP+1)

SP←SP+6

Note

RETS

3+S MBE, RBE, PC13, 12←(SP+1)

PC11-0←(SP)(SP+3)(SP+2)

SP←SP+4

Unconditional

then skip unconditionally

X, X, MBE, RBE←(SP+4)

PC11-0←(SP)(SP+3)(SP+2)

0, 0, PC13, 12←(SP+1)

SP←SP+6

then skip unconditionally

Note

RETI

1

3

MBE, RBE, PC13, 12←(SP+1)

PC11-0←(SP)(SP+3)(SP+2)

PSW←(SP+4)(SP+5), SP←SP+6

0, 0, PC13, 12←(SP+1)

PC11-0←(SP)(SP+3)(SP+2)

PSW←(SP+4)(SP+5), SP←SP+6

PUSH

POP

rp

1

2

1

2

1

2

1

2

(SP–1)(SP–2)←rp, SP←SP–2

BS

rp

(SP–1)

rp←(SP+1)(SP), SP←SP+2

MBS←(SP+1), RBS←(SP), SP←SP+2

←MBS, (SP–2)←RBS, SP←SP–2

BS

Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

23

µPD75P3216

Instruction

Group

No. of Machine

Bytes Cycle

Addressing

Area

Skip

Mnemonic

EI

Operand

Operation

Condition

Interrupt

control

2

1

2

1

2

1

2

3

IME(IPS.3)←1

IEXXX←1

IEXXX

DI

IME(IPS.3)←0

IEXXX←0

IEXXX

Note 1

I/O

IN

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

A←PORTn

(n=0-3, 5, 6, 8, 9)

XA←PORTn+1, PORTn(n=8)

Note 1

OUT

PORTn←A

(n=2-3, 5, 6, 8, 9)

PORTn+1, PORTn←XA(n=8)

Set HALT Mode(PCC.2←1)

Set STOP Mode(PCC.3←1)

No Operation

CPU control

Special

HALT

STOP

NOP

SEL

RBn

MBn

RBS←n (n=0-3)

MBS←n (n=0, 1, 15)

• When using TBR instruction

GETI^{Note 2, 3}taddr

*10

PC13-0←(taddr)5-0+(taddr+1)

- - - - - - - - - - - - - - - - - - - - - - - - - - -

• When using TCALL instruction

- - - - - - - - - - - -

(SP–4)(SP–1)(SP–2)←PC11-0

(SP+1)

←MBE, RBE, PC13, 12

PC13-0←(taddr)5-0+(taddr+1)

SP←SP–4

- - - - - - - - - - - - - - - - - - - - - - - - - - -

• When using instruction other than

- - - - - - - - - - - -

Determined by

TBR or TCALL

referenced

instruction

Execute (taddr)(taddr+1) instructions

• When using TBR instruction

PC13-0←(taddr)5-0+(taddr+1)

1

3

*10

- - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

4

• When using TCALL instruction

(SP–6)(SP–3)(SP–4)

←PC11-0

(SP–2)←X, X, MBE, RBE

PC13-0←(taddr)5-0+(taddr+1)

SP←SP–6

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - -

Determined by

3

• When using instruction other than

TBR or TCALL

referenced

instruction

Execute (taddr)(taddr+1) instructions

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBE to 15.

2. TBR and TCALL instructions are assembler directives for the GETI instruction’s table definitions.

3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

24

µPD75P3216

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory contained in the µPD75P3216 is a 16384 × 8-bit one-time PROM that can be electrically written

one time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the

X1 pin is used instead of address input as a method for updating addresses.

Function

VPP

Pin where program voltage is applied during program

memory write/verify (usually VDD potential)

X1, X2

Clock input pins for address updating during program

memory write/verify. Input the X1 pin’s inverted signal to

the X2 pin.

MD0 to MD3

Operation mode selection pin for program memory write/

verify

D0/P60/KR0-D3/P63/KR3 (lower 4 bits) 8-bit data I/O pins for program memory write/verify

D4/P50-D7/P53 (upper 4 bits)

VDD

Pin where power supply voltage is applied. Applies 1.8 to

5.5 V in normal operation mode and +6 V for program

memory write/verify.

Caution Pins not used for program memory write/verify should be connected to Vss.

8.1 Operation Modes for Program Memory Write/Verify

When +6 V is applied to the V^DDpin and +12.5 V to the VPP pin, the µPD75P3216 enters the program memory write/

verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.

Operation Mode Specification

Operation Mode

VPP

VDD

MD0 MD1

MD2 MD3

+12.5 V

+6 V

H

L

H

L

H

L

Zero-clear program memory address

Write mode

H

L

Verify mode

H

X

Program inhibit mode

X: L or H

25

µPD75P3216

8.2 Program Memory Write Procedure

Program memory can be written at high speed using the following procedure.

(1) Pull down unused pins to Vss through resistors. Set the X1 pin low.

(2) Supply 5 V to the V^DDand VPP pins.

(3) Wait 10 µs.

(4) Select the zero-clear program memory address mode.

(5) Supply 6 V to the V^DDand 12.5 V to the VPP pins.

(6) Write data in the 1 ms write mode.

(7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7).

(8) (X : number of write operations from steps (6) and (7)) × 1 ms additional write.

(9) Apply four pulses to the X1 pin to increment the program memory address by one.

(10) Repeat steps (6) to (9) until the end address is reached.

(11) Select the zero-clear program memory address mode.

(12) Return the V^DDand VPP pins back to 5 V.

(13) Turn off the power.

The following figure shows steps (2) to (9).

X repetitions

Address

increment

Additional

write

Write

Verify

VPP

VDD

VPP

VDD + 1

VDD

X1

D0/P60/KR0-

D3/P63/KR3

Data

output

Data input

D4/P50-

D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

26

µPD75P3216

8.3 Program Memory Read Procedure

The µPD75P3216 can read program memory contents using the following procedure.

(1) Pull down unused pins to V^SSthrough resistors. Set the X1 pin low.

(2) Supply 5 V to the VDD and VPP pins.

(3) Wait 10 µs.

(4) Select the zero-clear program memory address mode.

(5) Supply 6 V to the V^DDand 12.5 V to the VPP pins.

(6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one

address.

(7) Select the zero-clear program memory address mode.

(8) Return the V^DDand VPP pins back to 5 V.

(9) Turn off the power.

The following figure shows steps (2) to (9).

V

PP

VPP

V

DD

VDD + 1

V

DD

VDD

X1

D0/P60/KR0-

D3/P63/KR3

Data output

D4/P50-

D7/P53

MD0/P30

“L”

MD1/P31

MD2/P32

MD3/P33

27

µPD75P3216

8.4 One-time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends

that after the required data is written and the PROM is stored under the temperature and time conditions shown below,

the PROM should be verified via a screening.

Storage Temperature

125 ˚C

Storage Time

24 hours

28

µPD75P3216

9. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)

Parameter

Supply voltage

Symbol

VDD

VPP

VI1

Test Conditions

Rating

Unit

V

–0.3 to +7.0

–0.3 to +13.5

–0.3 to VDD + 0.3

–0.3 to +14

–0.3 to VDD + 0.3

–10

PROM supply voltage

Input voltage

V

Except port 5

V

VI2

Port 5

N-ch open-drain

V

Output voltage

VO

V

Output current, high

IOH

Per pin

mA

˚C

Total for all pins

Per pin

–30

Output current, low

IOL

TA

30

Total for all pins

220

Operating ambient

temperature

–40 to +85^Note

Storage temperature

Tstg

–65 to +150

˚C

Note When LCD is driven in normal mode: TA = –10 to +85 ˚C

Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding

the ratings could cause parmanent damage. The parameters apply independently. The device

should be operated within the limits specified under DC and AC Characteristics.

CAPACITANCE (T^A= 25 ˚C, VDD = 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

CIN

Test Conditions

MIN.

TYP.

MAX.

15

Unit

pF

f = 1 MHz

Unmeasured pins returned to 0 V.

COUT

C^IO

15

pF

15

pF

29

µPD75P3216

SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Resonator

Ceramic

Recommended Constant

Parameter

Test Conditions

MIN. TYP. MAX.

Unit

Note 2

Oscillator

1.0

6.0

MHz

X2

X1

resonator

frequency (fx) ^{Note 1}

Oscillation

C1

C2

After VDD reaches oscil-

4

ms

MHz

ms

stabilization time ^{Note 3}lation voltage range MIN.

V

DD

Note 2

Crystal

Oscillator

1.0

6.0

X2

X1

resonator

frequency (fx) ^{Note 1}

C1

C2

Oscillation

VDD = 4.5 to 5.5 V

10

30

stabilization time ^{Note 3}

V

DD

Note 2

External

clock

X1 input

1.0

6.0

MHz

ns

frequency (fx) ^{Note 1}

X1 input

X1

X2

83.3

500

high/low level width

(tXH, tXL)

Notes 1. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the

instruction execution time, refer to the AC characteristics.

2. When the oscillator frequency is 4.19 MHz < fx ≤ 6.0 MHz, setting the processor clock control register

(PCC) to 0011 results in 1 machine cycle being less than the required 0.95 µs. Therefore, set PCC

to a value other than 0011.

3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing

the STOP mode.

Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should be

carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V^SS.

• Do not ground it to the ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

30

µPD75P3216

DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN. TYP. MAX.

Unit

mA

V

Output current, low

IOL

Per pin

15

150

Total for all pins

Ports 2, 3, 8, 9

Input voltage, high

VIH1

VIH2

VIH3

2.7 ≤ VDD ≤ 5.5 V 0.7VDD

1.8 ≤ VDD < 2.7 V 0.9VDD

2.7 ≤ VDD ≤ 5.5 V 0.8VDD

1.8 ≤ VDD < 2.7 V 0.9VDD

VDD

V

Ports 0, 1, 6, RESET

VDD

V

VDD

V

Port 5

N-ch open-drain 2.7 ≤ VDD ≤ 5.5 V 0.7VDD

1.8 ≤ VDD < 2.7 V 0.9VDD

VDD – 0.1

13

V

13

V

VI14

VIL1

X1

VDD

V

Input voltage, low

Ports 2, 3, 5, 8, 9

2.7 ≤ VDD ≤ 5.5 V

1.8 ≤ VDD < 2.7 V

2.7 ≤ VDD ≤ 5.5 V

1.8 ≤ VDD < 2.7 V

0

0.3VDD

0.1VDD

0.2VDD

0.1VDD

0.1

V

0

V

VIL2

Ports 0, 1, 6, RESET

X1

0

V

0

V

VIL3

VOH

VOL1

V

Output voltage, high

Output voltage, low

SCK, SO, ports 2, 3, 6, 8, 9 IOH = –1 mA

SCK, SO, ports 2, 3, 5, 6, 8, 9 IOL = 15 mA,

VDD – 0.5

V

0.2

2.0

V

VDD = 4.5 to 5.5 V

IOL = 1.6 mA

0.4

0.2VDD

3

V

VOL2

ILIH1

ILIH2

ILIH3

ILIL1

ILIL2

ILIL3

SB0, SB1

N-ch open-drain pull-up resistor ≥ 1 kΩ

Other pins than X1

X1

V

Input leakage

current, high

VIN = VDD

µA

20

VIN = 13 V

VIN = 0 V

Port 5 (N-ch open-drain)

Other pins than port 5 and X1

X1

20

Input leakage

current, low

–3

–20

–3

Port 5 (N-ch open-drain) When an

input instruction is not executed

Port 5 (N-ch

–30

µA

open-drain)

When an input

instruction

VDD = 5.0 V

VDD = 3.0 V

–10

–3

–27

–8

µA

is executed

Output leakage

current, high

ILOH1

ILOH2

ILOL

VOUT = VDD

VOUT = 13 V

VOUT = 0 V

SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9

Port 5 (N-ch open-drain)

3

µA

20

–3

Output leakage

current, low

Pull-up resistor

RL

VIN = 0 V

Ports 0, 1, 2, 3, 6, 8, 9

(Excluding P00 pin)

50

100

200

kΩ

31

µPD75P3216

DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN. TYP. MAX.

Unit

V

LCD drive voltage

VLCD

VAC0 = 0

VAC0 = 1

TA = –40 to +85 °C

TA = –10 to +85 °C

2.7

2.2

1.8

VDD

4

V

VAC current

IVAC

VAC0 = 1, VDD = 2.0 V ± 10%

1

µA

V

LCD output voltage

deviation ^{Note 1}(common)

LCD output voltage

deviation ^{Note 1}(segment)

Supply current ^{Note 2}

VODC

lo = ±1 µA

lo = ±0.5 µA

6.0 MHz

VLCD0 = VLCD

0

±0.2

VLCD1 = VLCD × 2/3

VODS

IDD1

VLCD2 = VLCD × 1/3

2.2 V ≤ VLCD ≤ VDD

VDD = 5.0 V ± 10%

±0.2

V

Note 1

Note 3

Note 4

2.6

0.47

0.72

0.27

1.9

7.8

1.4

2.1

0.8

5.7

1.1

2.0

0.7

10

mA

µA

Crystal oscillation VDD = 3.0 V ± 10%

IDD2

IDD1

IDD2

IDD5

C1 = C2 = 22 pF

HALT mode VDD = 5.0 V ± 10%

VDD = 3.0 V ± 10%

4.19 MHz

VDD = 5.0 V ± 10% ^{Note 3}

Crystal oscillation VDD = 3.0 V ± 10% ^{Note 4}

0.36

0.7

C1 = C2 = 22 pF

HALT mode VDD = 5.0 V ± 10%

VDD = 3.0 V ± 10%

0.23

0.05

0.02

Note 5

STOP mode

VDD = 5.0 V ± 10%

DD = 3.0 V

±10%

V

5

µA

T^A= 25˚C

3

µA

Notes 1. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the

segment and common outputs (V^LCDn; n = 0, 1, 2).

2. Not including current flowing in on-chip pull-up resistors.

3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-

speed mode.

4. When PCC is set to 0000 and the device is operated in the low-speed mode.

5. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1

µA.

32

µPD75P3216

AC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

MIN. TYP. MAX.

Unit

µs

CPU clock cycle

tCY

VDD = 2.7 to 5.5 V

0.67

0.95

0

64

1

Note 1

time

µs

TI0 input frequency

fTI

MHz

kHz

µs

0

275

TI0 input

tTIH, tTIL

0.48

1.8

Note 2

10

high/low-level width

Interrupt input high/

low-level width

µs

tINTH, tINTL INT0

IM02 = 0

IM02 = 1

µs

INT4

10

µs

KR0 to KR3

10

µs

RESET low level width

tRSL

10

µs

Notes 1. Thecycletime(minimuminstruction

execution time) of the CPU clock

(Φ) is determined by the oscillation

frequency of the connected

resonator (and external clock) and

theprocessorclockcontrolregister

(PCC). The figure at the right

indicates the cycle time t^CYversus

supply voltage VDD characteristic.

2. 2tCY or 128/fx is set by setting the

interrupt mode register (IM0).

t

CY vs VDD

64

30

6

5

Guaranteed Operation

Range

µ

4

3

1

0.5

0

1

2

3

4

5

6

Supply Voltage V^DD[V]

33

µPD75P3216

SERIAL TRANSFER OPERATION

2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T^A= –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

VDD = 2.7 to 5.5 V

MIN.

1300

3800

tKCY1/2–50

tKCY1/2–150

150

TYP.

MAX.

Unit

ns

SCK cycle time

tKCY1

SCK high/low-level

width

tKL1, tKH1

tSIK1

VDD = 2.7 to 5.5 V

RL = 1 kΩ,

SI^{Note 1}setup time

(to SCK↑)

500

SI^{Note 1}hold time

(from SCK↑)

tKSI1

400

600

SO^{Note 1}output delay time

from SCK↓

tKSO1

VDD = 2.7 to 5.5 V

0

250

Note 2

C^L= 100 pF

0

1000

Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.

2. RL and CL are the load resistance and load capacitance of the SO output lines.

2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (T^A= –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

VDD = 2.7 to 5.5 V

MIN.

800

3200

400

1600

100

150

400

600

0

TYP.

MAX.

Unit

ns

SCK cycle time

tKCY2

SCK high/low-level

width

tKL2, tKH2

tSIK2

VDD = 2.7 to 5.5 V

RL = 1 kΩ,

SI^{Note 1}setup time

(to SCK↑)

SI^{Note 1}hold time

(from SCK↑)

tKSI2

SO^{Note 1}output delay time

from SCK↓

tKSO2

VDD = 2.7 to 5.5 V

300

Note 2

CL = 100 pF

0

1000

Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.

2. RL and CL are the load resistance and load capacitance of the SO output lines.

34

µPD75P3216

SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

VDD = 2.7 to 5.5 V

MIN.

1300

3800

tKCY3/2–50

tKCY3/2–150

150

TYP.

MAX.

Unit

ns

SCK cycle time

tKCY3

SCK high/low-level

width

tKL3, tKH3

tSIK3

VDD = 2.7 to 5.5 V

SB0, 1 setup time

(to SCK↑)

500

SB0, 1 hold time (from SCK↑)

SB0, 1 output delay

time from SCK↓

tKSI3

VDD = 2.7 to 5.5 V

RL = 1 kΩ,^Note

CL = 100 pF

tKCY3/2

0

tKSO3

VDD = 2.7 to 5.5 V

250

0

1000

SB0, 1↓ from SCK↑

SCK↓ from SB0, 1↑

SB0, 1 low-level width

SB0, 1 high-level width

tKSB

tSBK

tSBL

t^SBH

tKCY3

Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines.

SBI Mode (SCK...External clock input (slave)): (T^A= –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Test Conditions

VDD = 2.7 to 5.5 V

MIN.

800

3200

400

1600

100

150

tKCY4/2

0

TYP.

MAX.

Unit

ns

SCK cycle time

tKCY4

SCK high/low-level

width

tKL4, tKH4

tSIK4

VDD = 2.7 to 5.5 V

SB0, 1 setup time

(to SCK↑)

SB0, 1 hold time (from SCK↑)

SB0, 1 output delay

time from SCK↓

tKSI4

VDD = 2.7 to 5.5 V

RL = 1 kΩ,^Note

CL = 100 pF

tKSO4

VDD = 2.7 to 5.5 V

300

0

1000

SB0, 1↓ from SCK↑

SCK↓ from SB0, 1↑

SB0, 1 low-level width

SB0, 1 high-level width

tKSB

tSBK

tSBL

tSBH

tKCY4

Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines.

35

µPD75P3216

AC Timing Test Point (Excluding X1 Input)

VIH (MIN.)

V^IL(MAX.)

V^IH(MIN.)

V^IL(MAX.)

VOH (MIN.)

V^OL(MAX.)

V^OH(MIN.)

V^OL(MAX.)

Clock Timing

1/f

X

t

XL

t

XH

V

DD–0.1 V

X1 Input

0.1 V

TI0 Timing

1/f^TI

t

TIL

t

TIH

TI0

36

µPD75P3216

Serial Transfer Timing

3-wire serial I/O mode

t

KCY1, 2

t

KL1, 2

t

KH1, 2

SCK

t

SIK1, 2

t

KSI1, 2

SI

Input Data

t

KSO1, 2

SO

Output Data

2-wire serial I/O mode

t

KCY1, 2

t

KL1, 2

t

KH1, 2

SCK

t

SIK1, 2

t

KSI1, 2

SB0, 1

t

KSO1, 2

37

µPD75P3216

Serial Transfer Timing

Bus release signal transfer

t

KCY3, 4

t

KL3, 4

t

KH3, 4

SCK

t

SIK3, 4

t

KSI3, 4

t

KSB

t

SBL

t

SBH

t

SBK

SB0, 1

t

KSO3, 4

Command signal transfer

t

KCY3, 4

t

KL3, 4

t

KH3, 4

SCK

t

SIK3, 4

t

KSB

t

SBK

t

KSI3, 4

SB0, 1

t

KSO3, 4

Interrupt input timing

t

INTL

t

INTH

INTP0, 4

KR0 to 3

RESET input timing

t

RSL

RESET

38

µPD75P3216

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

(T^A= –40 to +85 ˚C)

Parameter

Symbol

tSREL

Test Conditions

MIN. TYP. MAX.

Unit

µs

Release signal set time

Oscillation stabilization

wait time ^{Note 1}

0

tWAIT

Release by RESET

Release by interrupt

2¹⁵/fX

ms

Note 2

Notes 1. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent

unstable operation at the oscillation start.

2. Depends on the basic interval timer mode register (BTM) settings (See the table below).

BTM3

BTM2

BTM1

BTM0

Wait Time

When fx = 4.19-MHz operation

When fx = 6.0-MHz operation

2²⁰/fx (approx. 175 ms)

2¹⁷/fx (approx. 21.8 ms)

2¹⁵/fx (approx. 5.46 ms)

2¹³/fx (approx. 1.37 ms)

—

0

1

0

1

0

1

0

1

2²⁰/fx (approx. 250 ms)

2¹⁷/fx (approx. 31.3 ms)

2¹⁵/fx (approx. 7.81 ms)

2¹³/fx (approx. 1.95 ms)

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

Operating Mode

STOP Mode

Data Retention Mode

V

DD

V

DDDR

t

SREL

STOP Instruction Execution

RESET

t

WAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT Mode

Operating Mode

STOP Mode

Data Retention Mode

V

DD

V

DDDR

t

SREL

STOP Instruction Execution

Standby Release Signal

(Interrupt Request)

t

WAIT

39

µPD75P3216

DC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0V)

Parameter

Symbol

Test Conditions

Other than X1, X2 pins

X1, X2

MIN.

0.7 VDD

VDD – 0.5

0

TYP.

MAX.

VDD

Unit

V

Input voltage, high

VIH1

VIH2

VIL1

VIL2

ILI

VDD

V

Input voltage, low

Other than X1, X2 pins

X1, X2

0.3 VDD

0.4

V

0

V

Input leakage current

Output voltage, high

Output voltage, low

VDD supply current

VPP supply current

VIN = VIL or VIH

IOH = – 1 mA

10

µA

V

VOH

VOL

IDD

VDD – 1.0

IOL = 1.6 mA

0.4

30

V

mA

IPP

MD0 = VIL, MD1 = VIH

Cautions 1. Keep VPP to within +13.5 V, including overshoot.

2. Apply V^DDbefore VPP and turn it off after VPP.

AC Programming Characteristics (T^A= 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

Parameter

Symbol

Note 1

Test Conditions

MIN.

2

TYP.

MAX.

Unit

Note 2

Address setup time

tAS

µs

(vs. MD0 ↓)

MD1 setup time (vs. MD0 ↓)

Data setup time (vs. MD0 ↓)

tM1S

tDS

tOES

tDS

2

µs

Note 2

Address hold time

tAH

(vs. MD0 ↑)

Data hold time (vs. MD0 ↑)

tDH

tDF

tDH

tDF

2

0

µs

MD0 ↑ → data output float

130

ns

delay time

VPP setup time (vs. MD3 ↑)

VDD setup time (vs. MD3 ↑)

Initial program pulse width

tVPS

tVDS

tPW

tVPS

tVCS

tPW

tOPW

tCES

tDV

tOEH

tOR

—

2

µs

0.95

2

1.0

1.05

21.0

ms

µs

Additional program pulse width tOPW

MD0 setup time (vs. MD1 ↑)

MD0 ↓ → data output delay time tDV

tM0S

MD0 = MD1 = VIL

1

µs

MD1 hold time (vs. MD0 ↑)

MD1 recovery time (vs. MD0 ↓)

Program counter reset time

X1 input high-, low-level width

X1 input frequency

tM1H

tM1H + tM1R ≥ 50 µs

2

µs

tM1R

tPCR

tXH, tXL

fX

µs

10

µs

—

0.125

µs

—

4.19

MHz

µs

Initial mode set time

t1

—

2

MD3 setup time (vs. MD1 ↑)

MD3 hold time (vs. MD1 ↓)

tM3S

tM3H

tM3SR

—

µs

—

µs

MD3 setup time (vs. MD0 ↓)

—

When program memory is read

µs

Note 2

Address

→ data output tDAD

tACC

2

µs

delay time

Note 2

Address

→ data output tHAD

tOH

When program memory is read

0

2

130

ns

hold time

MD3 hold time (vs. MD0 ↑)

tM3HR

tDFR

—

When program memory is read

µs

MD3 ↓ → data output float

2

delay time

Notes 1. Symbol of corresponding µPD27C256A

2. The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not

connected to a pin.

40

µPD75P3216

Program Memory Write Timing

t

VPS

V

PP

VPP

V

DD

VDS

V

DD

DD+1

V

t

XH

V

DD

X1

D0/P60/KR0-

D3/P63/KR3

D4/P50-

t

XL

Data input

Data output

Data input

D7/P53

t

DS

t

DS

t

^DHtAH

t

AS

t

I

t

DH

t

DV

t

DF

MD0/P30

MD1/P31

t

PW

t

M1R

t

M0S

t

OPW

t

PCR

t

M1S

t

M1H

MD2/P32

MD3/P33

t

M3S

t

M3H

Program Memory Read Timing

t

VPS

V

PP

VPP

VDD

t

VDS

VDD+1

VDD

t

XH

V

DD

X1

t

XL

t

DAD

t

HAD

D0/P60/KR0-

D3/P63/KR3

D4/P50-

Data output

D7/P53

t

DV

t

DFR

t

I

t

M3HR

MD0/P30

MD1/P31

t

PCR

MD2/P32

MD3/P33

t

M3SR

41

µPD75P3216

10. CHARACTERISTIC CURVE (REFERENCE VALUE)

I

DD vs VDD (System clock : 6.0 MHz Crystal resonator)

(TA = 25 °C)

10

5.0

PCC = 0011

PCC = 0010

PCC = 0001

PCC = 0000

HALT mode

1.0

0.5

0.1

0.05

0.01

0.005

X1

X2

Crystal

resonator

6.0 MHz

22 pF

V

DD

0.001

0

1

2

3

4

5

6

7

8

Supply Voltage V^DD(V)

42

µPD75P3216

IDD vs VDD (System clock : 4.19 MHz Crystal resonator)

(T^A= 25 °C)

10

5.0

PCC = 0011

PCC = 0010

PCC = 0001

1.0

0.5

PCC = 0000

HALT mode

0.1

0.05

0.01

0.005

X1

X2

Crystal

resonator

4.19 MHz

22 pF

V^DD

0.001

0

1

2

3

4

5

6

7

8

Supply Voltage VDD (V)

43

µPD75P3216

11. PACKAGE DRAWINGS

48 PIN PLASTIC SHRINK SOP (375 m il)

48

25

detail of lead end

1

24

A

H

I

J

N

C

L

B

D

M

P48GT-65-375B-1

NOTE

ITEM

A

B

MILLIMETERS

16.21 MAX.

0.63 MAX.

INCHES

0.639 MAX.

0.025 MAX.

Each lead centerline is located within 0.10

mm (0.004 inch) of its true position (T.P.) at

maximum material condition.

C

0.65 (T.P.)

0.026 (T.P.)

+0.004

±

0.012

D

E

0.30 0.10

–0.005

±

0.125 0.075

0.005 0.003

F

2.0 MAX.

0.079 MAX.

±

G

H

I

1.7 0.1

0.067 0.004

+0.012

–0.013

±

10.0 0.3

0.394

±

8.0 0.2

0.315 0.008

+0.009

–0.008

±

0.039

J

1.0 0.2

+0.10

+0.004

0.15

0.006

K

L

–0.05

–0.002

+0.008

–0.009

±

0.5 0.2

0.020

M

N

0.10

0.004

44

µPD75P3216

12. RECOMMENDED SOLDERING CONDITIONS

The µPD75P3216 should be soldered and mounted under the conditions recommended in the table below.

For details of recommended soldering conditions, refer to the information document “Semiconductor Device

Mounting Technology Manual” (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.

Table 12-1. Surface Mounting Type Soldering Conditions

µPD75P3216GT: 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)

Soldering

Soldering Conditions

Symbol

Method

Infrared rays

reflow

Peak package's surface temperature: 235 ˚C, Reflow time: 30 seconds or less

(at 210 ˚C or higher), Number of reflow processes: Twice max.

Number of days: 7^Note(after that, prebaking is necessary at 125 °C for 10 hours)

IR35-107-2

Products other than those supplied in thermal-resistant tray (magazine, taping, and non-

thermal-resistant tray) cannot be baked in their packs.

VPS

Peak package's surface temperature: 215 ˚C, Reflow time: 40 seconds or less

(at 200 ˚C or higher), Number of reflow processes: Twice max.

Number of days: 7^Note(after that, prebaking is necessary at 125 °C for 10 hours)

VP15-107-2

Products other than those supplied in thermal-resistant tray (magazine, taping, and non-

thermal-resistant tray) cannot be baked in their packs.

Wave soldering

Partial heating

Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less, Number of

flow process: 1, Preheating temperature: 120 ˚C or below (Package surface temperature)

Number of days: 7^Note(after that, prebaking is necessary at 125 °C for 10 hours)

WS60-107-1

—

Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side)

Note The number of days during which the product can be stored at 25 °C, 65 % RH max. after the dry pack

has been opened.

Caution Use of more than one soldering method should be avoided (except for partial heating).

45

µPD75P3216

APPENDIX A. µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST

Parameter

Program memory

µPD753108

µPD753208

µPD75P3216

Mask ROM

0000H-1FFFH

(8192 × 8 bits)

One-time PROM

0000H-3FFFH

(16384 × 8 bits)

Data memory

000H-1FFH

(512 × 4 bits)

CPU

75XL CPU

Instruction

When main system

clock is selected

•

0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation)

0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation)

execution

time

When subsystem

clock is selected

122 µs (@ 32.768-kHz

None

operation)

I/O port

CMOS input

8 (on-chip pull-up resistors can

be specified by software: 7)

6 (on-chip pull-up resistors can be specified by software: 5)

CMOS input/output

20 (on-chip pull-up resistors can be specified by software)

N-ch open drain

input/output

4 (on-chip pull-up resistors can be specified by software,

withstand voltage is 13 V)

4 (no mask option, withstand

voltage is 13 V)

Total

32

30

LCD controller/driver

Segment selection: 16/20/24

(can be changed to CMOS

input/output port in 4 time-

unit; max. 8)

Segment selection: 4/8/12 segments

(can be changed to CMOS input/output port in 4 time-unit;

max. 8)

Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),

1/4 duty (1/3 bias)

On-chip split resistor for LCD driver can be specified by

using mask option.

No on-chip split resistor for

LCD driver

Timer

5 channels

• 8-bit timer/event

• 8-bit timer counter: 2 channels

counter: 3 channels

(Can be used as 16-bit

timer/event counter, carrier

generator, timer with gate)

• Basic interval timer/

watchdog timer: 1 channel

• Watch timer: 1 channel

(Can be used as 16-bit timer counter, carrier generator,

timer with gate)

• 8-bit timer/event counter: 1 channel

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Clock output (PCL)

Buzzer output (BUZ)

• Φ, 524, 262, 65.5 kHz

(Main system clock: @ 4.19-MHz operation)

• Φ, 750, 375, 93.8 kHz

(Main system clock: @ 6.0-MHz operation)

• 2, 4, 32 kHz

(Main system clock: @

4.19-MHz operation or sub-

system clock: @ 32.768-kHz

operation)

(Main system clock: @ 4.19-MHz operation)

• 2.93, 5.86, 46.9 kHz

(Main system clock: @ 6.0-MHz operation)

• 2.86, 5.72, 45.8 kHz

(Main system clock: @

6.0-MHz operation)

Serial interface

3 modes are available

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit

• 2-wire serial I/O mode

• SBI mode

SCC register

Contained

None

SOS register

Vectored interrupt

External: 3, internal: 5

External: 2, internal: 5

46

µPD75P3216

Parameter

µPD753108

External: 1, internal: 1

VDD = 1.8 to 5.5 V

µPD753208

µPD75P3216

Test input

Operation supply voltage

Operating ambient temperature

Package

TA = –40 to +85°C

• 64-pin plastic QFP

(14 × 14 mm)

• 48-pin plastic shrink SOP

(375 mil, 0.65-mm pitch)

• 64-pin plastic QFP

(12 × 12 mm)

47

µPD75P3216

APPENDIX B. DEVELOPMENT TOOLS

The following development tools have been provided for system development using the µPD75P3216.

In the 75XL series, relocatable assemblers common to the series can be used in combination with the device files for

each product type.

RA75X relocatable assembler

Host machine

Part No. (name)

OS

Supply medium

3.5” 2HD

PC-9800 Series

MS-DOS^TM

µS5A13RA75X

µS5A10RA75X

Ver.3.30 to

5” 2HD

Note

Ver.6.2

IBM PC/AT^TM

or compatible

Refer to “OS for

3.5” 2HC

5” 2HC

µS7B13RA75X

µS7B10RA75X

IBM PCs”

Device file

Host machine

Part No. (name)

OS

Supply medium

3.5” 2HD

PC-9800 Series

MS-DOS^TM

Ver.3.30 to

µS5A13DF753208

µS5A10DF753208

5” 2HD

Note

Ver.6.2

IBM PC/AT

Refer to “OS for

3.5” 2HC

5” 2HC

µS7B13DF753208

µS7B10DF753208

or compatible

IBM PCs”

Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described

above.

48

µPD75P3216

PROM Write Tools

Hardware

PG-1500

This is a PROM programmer that can program single-chip microcomputer with PROM in

stand alone mode or under control of host machine when connected with supplied

accessory board and optional programmer adapter.

It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.

PA-75P3216GT

This is a PROM programmer adapter for the µPD75P3216GT.

It can be used when connected to a PG-1500.

Software

PG-1500 controller

Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500

on host machine.

Host machine

Part No. (name)

OS

Supply medium

3.5” 2HD

PC-9800 Series

MS-DOS

µS5A13PG1500

µS5A10PG1500

Ver.3.30 to

5” 2HD

Ver.6.2^Note

Refer to “OS for

IBM PCs”

IBM PC/AT

3.5” 2HD

5” 2HC

µS7B13PG1500

µS7B10PG1500

or compatible

Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described

above.

49

µPD75P3216

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3216.

Various system configurations using these in-circuit emulators are listed below.

Hardware IE-75000-R^{Note 1}

The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging

during development of application systems using the 75X or 75XL Series products.

For development of the µPD753208 subseries, the IE-75000-R is used with optional

emulation board (IE-75300-R-EM) and emulation probe (EP-753208GT-R).

Highly efficient debugging can be performed when connected to host machine and PROM

programmer.

The IE-75000-R includes a connected emulation board (IE-75000-R-EM).

IE-75001-R

The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging

during development of application systems using the 75X or 75XL Series products.

The IE-75001-R is used in combination with optional emulation board (IE-75300-R-EM) and

emulation probe (EP-753208GT-R).

Highly efficient debugging can be performed when connected to host machine and PROM

programmer.

IE-75300-R-EM

EP-753208GT-R

This is an emulation board for evaluating application systems using the µPD75P3216.

It is used in combination with the IE-75000-R or IE-75001-R.

This is an emulation probe for the µPD75P3216GK.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-

EM.

EV-9500GT-48 It includes a flexible board (EV-9500GT-48) to facilitate connections with target system.

Software

IE control program

This program can control the IE-75000-R or IE-75001-R on a host machine when connected

to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.

Host machine

Part No. (name)

OS

Supply medium

3.5” 2HD

PC-9800 Series

MS-DOS

µS5A13IE75X

µS5A10IE75X

Ver.3.30 to

5” 2HD

Ver.6.2^{Note 2}

Refer to “OS for

IBM PCs”

IBM PC/AT

3.5” 2HC

5” 2HC

µS7B13IE75X

µS7B10IE75X

or compatible

Notes 1. This is a maintenance product.

2. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described

above.

2. The generic name for the µPD753204, 753206, 753208, and 75P3216 is the µPD753208 subseries.

50

µPD75P3216

OS for IBM PCs

The following operating systems for the IBM PC are supported.

OS

Version

PC DOS^TM

Ver.5.02 to Ver.6.3

Note

J6.1/V

to J6.3/V

MS-DOS

Ver.5.0 to Ver.6.22

Note

5.0/V

to 6.2/V

Note

IBM DOS^TM

J5.02/V

Note Only English version is supported.

Caution Ver. 5.0 or later include a task swapping function, but this software is not able to use that function.

51

µPD75P3216

APPENDIX C. RELATED DOCUMENTS

Some of the related documents are preliminary but are not marked as such.

Device related documents

Document Number

Japanese English

U10166J U10166E

U10241J

Document Name

µPD753204, 753206, 753208 preliminary product information

µPD75P3216 data sheet

This document

U10158E

µPD753208 user’s manual

U10158J

U10453J

75XL series selection guide

U10453E

Development tool related documents

Document Number

Japanese English

EEU-1416

Document Name

Hardware

Software

IE-75000-R/IE-75001-R user’s manual

IE-75300-R-EM user’s manual

EP-753208GT-R user’s manual

PG-1500 user’s manual

EEU-846

U11354J

U10739J

EEU-651

EEU-731

EEU-730

EEU-704

U11354E

U10739E

EEU-1335

EEU-1346

EEU-1363

EEU-1291

RA75X assembler package user’s manual

Operation

Language

PG-1500 controller user’s manual

PC-9800 series

(MS-DOS) base

IBM PC series

(PC DOS) base

EEU-5008

U10540E


型号：	UPD75P3216GT
厂家：	NEC
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