UPD75P336GC-3B9 [NEC]
4-BIT SINGLE-CHIP MICROCOMPUTER; 4位单片机
| 型号： | UPD75P336GC-3B9 |
| 厂家： | 
NEC |
| 描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 文件： | 总56页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P336
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P336 is a version of the µPD75336 in which the on-chip mask ROM is replaced by one-time
PROM.
As the µPD75P336 is user-programmable, it is suitable for preproduction in system development, and for
short-run and multiple device-production.
Detailed function description, etc. are described in the following User's manual. Be sure to read it when
designing. µPD75336 User's Manual: IEU-725
FEATURES
• µPD75336 compatible
• Memory capacity:
• PROM : 16256 × 8 bits
• RAM : 768 × 4 bits
• Operable over same supply voltage range as mask ROM µPD75336
• VDD = 2.7 to 6.0 V
• On-chip 8-bits resolution A/D converter (successive approximation type)
• On-chip LCD controller/driver
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
µPD75P336GC-3B9
µPD75P336GK-BE9
80-pin plastic QFP (
80-pin plastic TQFP (fine pitch)( 12mm)
14mm)
Standard
Standard
★
Note Pull-up resistor cannot be incorporated by mask option.
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-2980A
The mark ★ shows major revised points.
(O. D. No. IC-8371A)
Date Published October 1993P
Printed in Japan
© NEC Corporation 1993
AN0-AN7*
A/D
CONVERT-
ER
8
AVREF
AVSS
PORT0
PORT 1
P00-P03
P10-P13
P20-P23
4
4
BASIC
INTERVAL
TIMER
INTBT
PROGRAM
COUNTER
(15)
SP(8)
PORT 2
PORT 3
PORT 4
PORT 5
4
4
4
4
CY
TIMER/EVENT
COUNTER
#0
TI0/P13
PTO0/P20
ALU
P30-P33
/MD0-MD3
INTT0
P40-P43
P50-P53
BANK
TIMER/EVENT
COUNTER
#1
TI1/P80
PTO1/P21
INTT1
PORT 6
4
P60-P63
GENERAL REG.
WATCH
TIMER
BUZ/P23
PROGRAM
MEMORY
(ROM)
DECODE
AND
CONTROL
PORT 7
PORT 8
4
4
P70-P73
P80-P83
16256 × 8 BITS
DATA
MEMORY
(RAM)
INTW
fLCD
SI/SB1/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
768 × 4 BITS
12
8
S12-S23
INTCSI
S24/BP0
–S31/BP7
INT0/P10
INT1/P11
INT2/P12
LCD
CONTROL-
LER
INTER-
RUPT
CONTROL
4
COM0–COM3
f
/ 2N
X
SYSTEM CLOCK
GENERATOR
CLOCK
OUTPUT
CONTROL
INT4/P00
KR0/P60
–KR3/P63
KR4/P70
–KR7/P73
3
CLOCK
DIVIDER
STAND BY
CONTROL
/DRIVER
VLC0–VLC2
CPU
CLOCK
SUB
MAIN
8
BIAS
LCDCL/P30
SYNC/P31
fLCD
µ
BIT SEQ.
BUFFER (16)
PCL/P22
XT1
XT2
X1 X2
V
SS
V
PP
V
DD
RESET
*
AN6/P82, AN7/P83
µPD75P336
PIN CONFIGURATION (Top View)
● 80-pin plastic QFP (■14mm)
● 80-pin plastic TQFP (fine pitch) (■12mm)
★
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
AN2
AN1
AN0
S31/BP7
S30/BP6
S29/BP5
S28/BP4
S27/BP3
S26/BP2
60
59
58
P83/AN7
57
56
55
54
53
52
P82/AN6
P81
P80/TI1
P33/MD3
P32/MD2
µ
µ
S25/BP1
S24/BP0
S23
S22
S21
S20
S19
S18
S17
S16
10
11
12
13
14
15
16
17
18
19
20
51
50
49
48
47
46
45
44
43
42
41
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
S15
S14
S13
P10/INT0
P03/SI/SB1
S12
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
*
In normal operation, VPP should be connected to VDD directly.
3
µPD75P336
PIN NAME
P00 to 03 : Port 0
P10 to 13 : Port 1
P20 to 23 : Port 2
P30 to 33 : Port 3
P40 to 43 : Port 4
P50 to 53 : Port 5
P60 to 63 : Port 6
P70 to 73 : Port 7
P80 to 83 : Port 8
BP0 to 7 : Bit Port
KR0 to 7 : Key Return
SB0, 1
RESET
: Serial Bus 0,1
: Reset Input
S12 to 31 : Segment Output 12 to 31
COM0 to 3 : Common Output 0 to 3
VLC0 to 2
BIAS
LCDCL
SYNC
TI0, 1
PTO0, 1
BUZ
: LCD Power Supply 0 to 2
: LCD Power Supply Bias Control
: LCD Clock
: LCD Synchronization
: Timer Input 0, 1
: Programmable Timer Output 0, 1
: Buzzer Clock
AVREF
AVSS
: Analog Reference
: Analog Ground
PCL
: Programmable Clock
INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
AN0 to 7 : Analog Input 0 to 7
INT2
X1, 2
XT1, 2
VDD
: External Test Interrupt 2
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
: Positive Power Supply
: Ground
SCK
SI
SO
: Serial Clock
: Serial Input
: Serial Output
MD0 to 3 : Mode Selection
VPP : Programming/Verifying
Power Supply
VSS
4
µPD75P336
CONTENTS
1. PIN FUNCTIONS ......................................................................................................................................... 6
1.1 PORT PINS............................................................................................................................................................. 6
1.2 OTHER PINS .......................................................................................................................................................... 8
1.3 PIN INPUT/OUTPUT CIRCUITS...........................................................................................................................10
2. DIFFERENCES BETWEEN µPD75P336 AND µPD75336 ......................................................................... 13
2.1 PROGRAM MEMORY (PROM) 16256 WORDS × 8 BITS ..................................................................................14
2.2 DATA MEMORY (RAM) 768 WORDS × 4 BITS..................................................................................................15
3. INSTRUCTION SET AND INSTRUCTION OPERATIONS ....................................................................... 16
4. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS.................................. 25
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES...........................................................................26
4.2 PROGRAM MEMORY WRITE PROCEDURE .......................................................................................................27
4.3 PROGRAM MEMORY READ PROCEDURE.........................................................................................................28
5. ELECTRICAL SPECIFICATIONS ................................................................................................................ 29
6. PACKAGE INFORMATION ........................................................................................................................ 48
7. RECOMMENDED SOLDERING CONDITIONS ......................................................................................... 50
APPENDIX A. LIST OF FUNCTIONS.............................................................................................................. 51
APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 52
5
µPD75P336
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Dual-
Function Pin
I/O Circuit
Type *1
Pin Name
After Reset
Input
Input/Output
Function
8-bit I/O
P00
P01
Input
INT4
SCK
B
4-bit input port (PORT0)
Input/output
Input/output
Input/output
F
F
- A
- B
Internal pull-up resistor specification by
software is possible for P01 to P03 as a 3-bit
unit.
×
P02
SO/SB0
SI/SB1
INT0
P03
M - C
With noise elimination circuit
P10
P11
INT1
Input
4-bit input port (PORT1)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
×
×
×
Input
Input
Input
B - C
P12
INT2
P13
TI0
P20
PTO0
PTO1
PCL
P21
4-bit input/output port (PORT2)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input/output
Input/output
E - B
P22
P23
BUZ
P30 *2
P31 *2
P32 *2
P33 *2
LCDCL MD0
Programmable 4-bit input/output port (PORT3)
SYNC MD1 Input/output settable bit-wise.
Internal pull-up resistor specification by
E - B
MD2
software is possible as a 4-bit unit.
MD3
N-ch open-drain 4-bit input/output port (PORT
4).
Data input/output pins for program memory
(PROM) write/verify (low-order 4 bits).
P40 to P43 *2
P50 to P53 *2
Input/output
Input/output
—
—
Input
Input
M - B
M - B
N-ch open-drain 4-bit input/output port (PORT
5)
Data input/output pins for program memory
(PROM) write/verify (high-order 4 bits).
P60
P61
P62
P63
P70
P71
P72
P73
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input/output
Input/output
Input
Input
F - A
4-bit input/output port (PORT7).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
F
- A
*
1.
: Indicates a Schmitt-triggered input.
2. Direct LED drive capability.
6
µPD75P336
1.1 PORT PINS (2/2)
Dual-
Function Pin
I/O Circuit
Pin Name
Input/Output
Input/output
Function
8-bit I/O
After Reset
Type
E - E
E - B
P80
P81
P82
P83
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
TI1
—
4-bit input/output port (PORT8).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input
×
AN6
AN7
S24
S25
S26
S27
S28
S29
S30
S31
Y - B
Output
Output
1-bit output port (BIT PORT)
Dual function as segment output pins.
×
G - C
*
*
VLCX shown below can be selected for the display outputs.
S12 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0
However, display output levels depend on the display outputs and VLCX external circuit.
7
µPD75P336
1.2 OTHER PINS (1/2)
I/O Circuit
Type *
Dual-
Function Pin
Pin Name
Function
After Reset
Input/Output
Input
TI0
TI1
P13
P80
P20
P21
P22
B
B
- C
- E
Input
External event pulse input pin for timer/event counter.
PTO0
PTO1
PCL
output
output
Input
Input
Timer/event counter output pin
Clock output pin
E - B
E - B
E - B
Frequency output pin (for buzzer or system clock
trimming)
Input
Input
BUZ
SCK
output
P23
P01
Input/output
Serial clock input/output pin
F
- A
- B
Serial data output pin
Input
Input
Input
SO/SB0
SI/SB1
INT4
Input/output
Input/output
Input
P02
P03
P00
F
Serial bus input/output pin
Serial data input pin
M - C
B
Serial bus input/output pin
Edge-detected vectored interrupt input pin (both rising
and falling edge detection valid).
INT0
INT1
P10
P11
Edge-detected vectored
interrupt input pin (detected
edge selectable)
Clocked
Input
Input
Input
Input
B
- C
- C
Asynchronous
Edge-detected testable input pin
(rising edge detection)
INT2
P12
B
Asynchronous
Input
Input
Input
Input
KR0 to KR3
KR4 to KR7
P60 to P63
P70 to P73
Parallel falling edge detected testable input pins.
Parallel falling edge detected testable input pins.
F
F
- A
- A
Main system clock oscillation crystal/ceramic resonator
inputs. When an external clock is used, the clock is
input to X1 and the inverted clock to X2.
—
—
—
—
X1, X2
—
—
—
Subsystem clock oscillation crystal reasonator inputs
When an external clock is used, the clock is input to XT1
and the inverted clock toXT2. XT1 can be used as a 1-
bit input (test) pin.
XT1, XT2
––
B
Input
—
RESET
—
System reset input pin.
Mode selection pin for program memory (PROM) write/
verify.
Input
MD0 to MD3
Input/output
P30 to P33
E - B
—
Program voltage application pin for program memory
(PROM) write/verify. Applies +12.5 V in program
memory write/verify.
PP
V
—
—
—
Directly connected to VDD in normal operation.
—
—
—
—
VDD
VSS
—
—
Positive power supply pin
GND potential pin
—
—
*
: indicates a Schmitt-triggered input.
8
µPD75P336
1.2 OTHER PINS (2/2)
Dual-
Function Pin
I/O Circuit
Type
Function
Segment signal output pins
Input/Output
After Reset
Pin Name
S12 to S23
S24 to S31
COM0 to COM3
VLC0 to VLC2
BIAS
*2
*2
*2
—
Output
Output
Output
Input
—
BP0 to 7
—
G - A
G - C
G - B
—
Segment signal output pins
Common signal output pins
LCD drive power supply pins
—
External split cutting output pin
External extension driver drive clock output pin
High impedance
Input
Output
Output
—
—
LCDCL*1
P30
E - B
E - B
External extension driver synchronization drive clock
output pin
Input
P31
SYNC *1
Output
AN0 to AN5
AN6
—
P82
P83
—
Y
A/D converter analog signal input pins
Input
Input
Y
- B
AN7
AVREF
A/D converter reference voltage input pin
A/D converter GND potential pin
—
—
Z
Input
—
AVSS
—
Z
*
1. Pins provided for future system expansion. Currently used only as pins 30 and 31.
2. VLCX shown below can be selected for the display outputs.
S12 to S31: VLC1, COM0 to COM2: VLC2, COM3:VLC0
However, display output levels depend on the display outputs and VLCX external circuit.
9
µPD75P336
1.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuits for each of the pin µPD75P336 are shown below in partially simplified form.
TYPE A (For TYPE E-B)
TYPE D (For TYPE E-B, F-A)
V
DD
VDD
data
P-ch
P-ch
OUT
IN
output
disable
N-ch
N-ch
Push-Pull Output that can be Made High-Impedance
Output (P-ch and N-ch OFF)
CMOS Standard Input Buffer
TYPE B
TYPE E-B
VDD
P.U.R.
output
disable
P-ch
IN
data
IN/OUT
Type D
output
disable
Type A
P.U.R.
:
Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
TYPE B-C
VDD
TYPE E-E
P.U.R.
P.U.R.
enable
VDD
P-ch
P.U.R.
data
IN/OUT
Type D
output
disable
P.U.R.
enable
P-ch
Type A
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R.
:
Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
10
µPD75P336
TYPE F-A
TYPE G-B
VDD
V
LC0
LC1
P.U.R.
P-ch
P.U.R.
enable
V
P-ch
N-ch
P-ch
data
IN/OUT
Type D
Type B
output
disable
OUT
COM
data
N-ch P-ch
VLC2
N-ch
P.U.R.
:
Pull-Up Resistor
TYPE F-B
TYPE G-C
V
DD
P.U.R.
P-ch
VDD
P.U.R.
enable
P-ch
V
LC0
V
DD
output
disable
(P)
P-ch
V
LC1
IN/OUT
P-ch
data
SEG
OUT
N-ch
output
disable
data/Bit Port data
N-ch
output
disable
(N)
V
LC2
N-ch
P.U.R.
:
Pull-Up Resistor
TYPE G-A
TYPE M-B
IN/OUT
V
LC0
P-ch
data
VLC1
N-ch
P-ch
output
disable
SEG
data
OUT
N-ch
VLC2
Middle-High Voltage Input Buffer
N-ch
11
µPD75P336
V
DD
TYPE M-C
TYPE Y-B
V
DD
P.U.R.
P-ch
P.U.R
enable
P-ch
P.U.R.
enable
IN/OUT
data
IN/OUT
Type D
output
disable
data
N-ch
output
disable
Type A
Type Y
P.U.R.
:
Pull-Up Resistor
P.U.R:Pull-Up Resistor
TYPE Y
TYPE Z
IN
VDD
IN
P-ch
N-ch
+
-
Sampl-
ing C
VDD
AVSS
Reference Voltage
AVSS
Reference Voltage
(From Series Resistance
Voltage Tap)
input
AVSS
enable
12
µPD75P336
2. DIFFERENCES BETWEEN µPD75P336 AND µPD75336
Parameter
Program memory
µPD75336
Mask ROM 16256 × 8 bits
768 × 4 bits
µPD75P336
One-time PROM 16256 × 8 bits
768 × 4 bits
Data memory
Incorporation specifiable by mask
option
Ports 4, 5 pull-up resistor
No
No
LCD drive power supply split
resistor
Incorporation specifiable by mask
option
Subsystem clock oscillation
feedback resistor
Incorporation specifiable by mask
option
Incorporated
VPP
Pin 69
IC
13
µPD75P336
2.1 PROGRAM MEMORY (PROM) ..... 16256 WORDS × 8 BITS
The program memory consists of 16256-byte PROM. The program memory map is shown in Fig. 2-1.
Fig. 2-1 Program Memory Map
7
6
0
0000H
0002H
Internal Reset Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
MBE RBE
I
NTBT/INT4 Start Address (High-Order 6 Bits)
(Low-Order 8 Bits)
MBE RBE
0004H MBE
INT0 Start Address
INT1 Start Address
INTCSI Start Address
INTT0 Start Address
(High-Order 6 Bits)
(Low-Order 8 Bits)
(High-Order 6 Bits)
(Low-Order 8 Bits)
(High-Order 6 Bits)
(Low-Order 8 Bits)
(High-Order 6 Bits)
(Low-Order 8 Bits)
RBE
RBE
RBE
RBE
RBE
CALLF
!faddr
Instruction
Entry
MBE
MBE
0006H
0008H
Address
BRCB !caddr
Instruction
Branch
000AH MBE
Address
BR !addr
Instruction
Branch Address
000CH
MBE
INTT1 Start Address
(High-Order 6 Bits)
(Low-Order 8 Bits)
CALL !addr
Instruction
Branch Address
≈
≈
0020H
Branch/Call
Address, by
GETI
GETI Instruction Reference Table
007FH
0080H
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
≈
≈
≈
07FFH
0800H
+2 to +16)
≈
0FFFH
1000H
BRCB !caddr
Instruction
Branch Address
≈
≈
≈
≈
1FFFH
2000H
BRCB !caddr
Instruction
Branch Address
2FFFH
3000H
BRCB !caddr
Instruction
Branch Address
≈
≈
3F7FH
14
µPD75P336
Remarks In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to addresses
with the low-order 8 bits only of the PC modified.
2.2 DATA MEMORY (RAM) .......768 WORDS × 4 BITS
The configuration of the data memory is shown in Fig. 2-2. The data memory comprises a data area and peripheral
hardware area, the data area comprises 768 × 4-bit static RAM.
Fig. 2-2 Data Memory Map
Data Memory
000H
General
Register Area
(32 × 4)
01FH
020H
Stack Area
Memory Bank 0
256 × 4
0FFH
100H
Data Area
Static RAM
768 × 4
Memory Bank 1
256 × 4
(20 × 4)
1EBH
1ECH
Display Data
Memory Area
1FFH
200H
Memory Bank 2
256 × 4
2FFH
Not On-Chip
F80H
FFFH
Memory Bank 15
128 × 4
Peripheral Hardware Area
15
µPD75P336
3. INSTRUCTION SET AND INSTRUCTION OPERATIONS
(1) Operand identifier and description
Operand identifiers and description method operands are written in the operand column for each instruction in
accordance with the description method for the operand identifier for that instruction (refer to "RA75X Assembler
Package User's Manual Language Volume (EEU-730)" for details). Where multiple items are included in the
description method, one of those elements should be selected. Uppercase letters and the symbols + and – are
keywords and should be written as they are.
In the case of immediate data, an appropriate number or label is written.
Description Method
X, A, B, C, D, E, H, L
Descriptor
reg
X, B, C, D, E, H, L
reg1
rp
XA, BC, DE, HL
BC, DE, HL
rp1
BC, DE
rp2
XA, BC, DE, HL, XA', BC', DE' HL'
BC, DE, HL, XA', BC', DE', HL'
HL, HL+, HL–, DE, DL
DE, DL
rp'
rp'1
rpa
rpa1
n4
4-bit immediate date or label
8-bit immediate date or label
8-bit immediate date or label*
2-bit immediate date or label
n8
mem
bit
fmem
pmem
FB0H to FBFH, FF0H to FFFH immediate data or label
FC0H to FFFH immediate data or label
0000H to 3F7FH immediate data or label
12-bit immediate date or label
11-bit immediate date or label
20H to 7FH immediate date (bit 0 = 0) or label
PORT0 to PORT8
addr
caddr
faddr
taddr
PORTn
IE×××
RBn
IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW
RB0 to RB3
MB0, MB1, MB2, MB15
MBn
*
In 8-bit data processing, only an even address can be specified.
16
µPD75P336
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register; 4-bit accumulator
: C register; 4-bit accumulator
: D register; 4-bit accumulator
: E register; 4-bit accumulator
: H register; 4-bit accumulator
: L register; 4-bit accumulator
: X register; 4-bit accumulator
: Register pair (XA); 8-bit accumulator
: Register pair (BC); 8-bit accumulator
: Register pair (DE); 8-bit accumulator
: Register pair (HL); 8-bit accumulator
: Extended register pair (XA')
: Extended register pair (BC')
: Extended register pair (DE')
: Extended register pair (HL')
: Program counter
C
D
E
H
L
X
XA
BC
DE
HL
XA'
BC'
DE'
HL'
PC
SP
: Stack pointer
CY
: Carry flag; bit accumulator
: Program status word
PSW
MBE
RBE
PORTn
IME
IPS
IE×××
RBS
MBS
PCC
.
: Memory bank enable flag
:
Register bank enable flag
: Portn (n = 0 to 8)
: Interrupt master enable flag
: Interrupt priority selection register
: Interrupt enable flag
: Register bank selection register
: Memory bank selection register
: Processor clock control register
: Address, bit delimiter
(××)
××H
: Contents addressed by ××
: Hexadecimal data
17
µPD75P336
(3) Description of addressing area field symbols
*1
*2
MB = MBE • MBS
MB = 0
MBS = 0, 1, 2, 15
MBE = 0 : MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
Data Memory
Addressing
*3
MBE = 1 : MB = MBS (MBS = 0, 1, 2, 15)
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*4
*5
*6
MB = 15, pmem = FC0H to FFFH
addr = 0000H to 3F7FH
addr = (Current PC) –15 to (Current PC) –1
(Current PC) + 2 to (Current PC) + 16
*7
caddr = 0000H to 0FFFH (PC13,12 = 00B) or
1000H to 1FFFH (PC13,12 = 01B) or
2000H to 2FFFH (PC13,12 = 10B) or
3000H to 3FFFH (PC13,12 = 11B)
Program Memory
Addressing
*8
*9
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
*10
Remarks 1. MB indicates the accessible memory bank.
2. MB=0 irrespective of MBE and MBS in *2.
3. MB=15 irrespective of MBE and MBS in *4 and *5.
4. *6 to *10 indicate accessible area.
(4) Explanation of machine cycle column
"S" indicates the number of machine cycles required when an instruction with a skip function performs a
skip operation. The value of "s" is as follows:
• When a skip is not performed ....................................................................................................................... S = 0
• When the skipped instruction is a 1-byte or 2-byte instruction ................................................................ S = 1
• When the skipped instruction is a 3-byte instruction (BR !addr or CALL !addr)................................... S = 2
Note A GETI instruction is skipped in one machine cycle.
One machine cycle is equivalent to one cycle (=tCY)of the CPU clock cycle Φ : any of four times can be
selected according to the PCC setting.
18
µPD75P336
Mne-
Address-
ing Area
Operand
Operation
Skip Condition
Stack A
monic
A, #n4
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
1
2
2
2
2
1
A ← n4
reg1, #n4
XA, #n8
HL, #n8
reg1 ← n4
XA ← n8
HL ← n8
rp2 ← n8
A ← (HL)
Stack A
Stack B
rp2, #n8
A, @HL
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
@HL, A
2 + S A ← (HL), then L← L + 1
2 + S A ← (HL), then L← L – 1
L = 0
L = FH
1
2
1
2
2
2
2
2
2
2
2
2
1
A ← (rpa1)
XA ← (HL)
(HL) ← A
MOV
@HL, XA
A, mem
XA, mem
mem, A
mem, XA
A, reg
(HL) ← XA
A ← (mem)
XA ← (mem)
(mem) ← A
(mem) ← XA
A ← reg
XA, rp'
XA ← rp'
reg1, A
reg1 ← A
rp'1, XA
A, @HL
rp'1 ← XA
A ↔ (HL)
*1
*1
*1
*2
*1
*3
*3
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
A, mem
XA, mem
A,reg1
2 + S A ↔ (HL), then L← L + 1
2 + S A ↔ (HL), then L← L –1
L = 0
L = FH
1
2
2
2
1
2
3
3
A ↔ (rpa1)
XCH
XA ↔ (HL)
A ↔ (mem)
XA ↔ (mem)
A ↔ reg1
XA, rp'
XA ↔ rp'
XA, @PCDE
XA, @PCXA
XA ← (PC13–8 + DE)ROM
XA ← (PC13–8 + XA)ROM
MOVT
Note 1. Instruction Group
2. Table reference
19
µPD75P336
Mne-
Address-
ing Area
Operand
Operation
Skip Condition
monic
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
fmem.bit, CY
pmem.@L, CY
@H + mem.bit, CY
A, #n4
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
2
*4
*5
*1
*4
*5
*1
CY ← (fmem.bit)
2
CY ← (pmem7–2 + L3–2.bit (L1–0))
CY ← (H + mem3-0.bit)
(fmem.bit)← CY
(pmem7–2 + L3–2.bit (L1–0)) ← CY
(H + mem3-0.bit) ← CY
A ← A + n4
2
MOV1
2
2
2
carry
1 + S
XA, #n8
carry
carry
carry
carry
2 + S
XA ← XA + n8
A, @HL
1 + S
ADDS
*1
*1
*1
*1
A ← A + (HL)
XA, rp'
2 + S
XA ← XA + rp'
rp'1, XA
A, @HL
2 + S
rp'1← rp'1 + XA
A, CY ← A + (HL) + CY
XA, CY ← XA + rp' + CY
rp'1, CY ← rp'1 + XA + CY
A ← A − (HL)
1
XA, rp'
2
ADDC
SUBS
rp'1, XA
A, @HL
2
borrow
borrow
borrow
1 + S
XA, rp'
2 + S
XA ← XA − rp'
rp'1, XA
A, @HL
2 + S
rp'1← rp'1 − XA
A , CY← A − (HL) − CY
XA, CY← XA − rp' − CY
rp'1, CY ← rp'1 − XA − CY
A←A n4
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
XA, rp'
SBUC
AND
rp'1, XA
A, #n4
A, @HL
*1
*1
*1
A←A (HL)
XA, rp'
XA ← XA rp'
rp'1, XA
A, #n4
rp'1← rp'1 XA
A←A n4
A, @HL
A←A (HL)
OR
XA, rp'
XA ← XA rp'
rp'1, XA
A, #n4
rp'1← rp'1 XA
A←A n4
A, @HL
A←A (HL)
XOR
XA, rp'
XA ← XA rp'
rp'1, XA
rp'1← rp'1 XA
Note Instruction Group
20
µPD75P336
Mne-
Address-
ing Area
Operand
Operation
Skip Condition
monic
RORC
NOT
A
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
1
2
CY ← A0, A3 ← CY, An–1 ← An
A ← A
A
reg
rp1
1 + S reg ← reg + 1
1 + S rp1 ← rp1 + 1
2 + S (HL) ← (HL) + 1
2 + S (mem) ← (mem) + 1
1 + S reg ← reg – 1
2 + S rp' ← rp' – 1
reg = 0
INCS
rp1 = 00H
(HL) = 0
@HL
*1
*3
mem
reg
(mem) = 0
reg = FH
rp' = FFH
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
DECS
rp'
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp'
CY
2 + S Skip if reg = n4
2 + S Skip if (HL) = n4
1 + S Skip if A = (HL)
2 + S Skip if XA = (HL)
2 + S Skip if A = reg
2 + S Skip if XA = rp'
*1
*1
*1
SKE
XA = rp'
1
1
CY ← 1
CY ← 0
SET1
CLR1
SKT
CY
CY
1 + S Skip if CY = 1
CY ← CY
CY = 1
NOT1
CY
1
Note 1. Instruction Group
2. Accumulator operation
3. Increment and decrement
4. Carry flag manipulation
21
µPD75P336
Address-
ing Area
Mne-
Operand
Operation
Skip Condition
monic
mem.bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
(mem.bit) ← 1
(fmem.bit) ← 1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
SET1
CLR1
SKT
fmem.bit
pmem.@L
(pmem7–2 + L3–2.bit (L1–0)) ← 1
(H + mem3–0.bit) ← 1
(mem.bit) ← 0
@H + mem.bit
mem.bit
fmem.bit
(fmem.bit) ← 0
pmem.@L
(pmem7–2 + L3–2.bit (L1–0)) ← 0
(H + mem3–0.bit) ← 0
@H + mem.bit
mem.bit
2 + S Skip if (mem.bit) = 1
(mem.bit) = 1
fmem.bit
2 + S Skip if (fmem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0
pmem.@L
2 + S Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1
2 + S Skip if (H + mem3–0.bit) = 1
2 + S Skip if (mem.bit) = 0
@H + mem.bit
mem.bit
SKF
fmem.bit
2 + S Skip if (fmem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
pmem.@L
2 + S Skip if (pmem7–2 + L3–2.bit (L1–0))= 0
2 + S Skip if (H + mem3–0.bit) = 0
2 + S Skip if (fmem.bit) = 1 and clear
2 + S Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1 and clear
2 + S Skip if (H + mem3–0.bit) = 1 and clear
@H + mem.bit
fmem.bit
pmem.@L
SKTCLR
AND1
OR1
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
2
2
2
2
2
2
2
2
2
CY ← CY (fmem.bit)
CY ← CY
CY ← CY
(pmem7–2 + L3–2.bit (L1–0))
(H + mem3-0.bit)
CY ← CY (fmem.bit)
CY ← CY
CY ← CY
(pmem7–2 + L3–2.bit (L1–0))
(H + mem3-0.bit)
CY ← CY (fmem.bit)
XOR1
BR
CY ← CY
CY ← CY
(pmem7–2 + L3–2.bit (L1–0))
(H + mem3-0.bit)
PC13–0 ← addr
(The assembler selects the optimum instruction
from among the BRCB !caddr, and BR $addr
instructions.)
addr
—
—
*6
BR
PC13–0 ← addr
*6
*8
*7
3
3
!addr
!caddr
BRCB
BR
PC13–0 ← PC 13.12 + caddr11–0
PC13–0 ← addr
2
1
2
2
2
3
$addr
PCDE
PC13–0 ← PC 13-8 + DE
PC13–0 ← PC 13-8 + XA
BR
2
3
PCXA
Note Instruction Group
22
µPD75P336
Address-
ing Area
Mne-
Operand
Operation
Skip Condition
monic
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, PC13.12
PC13–0 ← addr, SP ← SP – 4
*6
*9
3
2
1
3
2
3
CALL
CALLF
RET
!addr
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, PC13.12
!faddr
PC13–0 ← 000 + faddr, SP ← SP – 4
MBE, RBE, PC13.12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
MBE, RBE, PC13.12 ← (SP + 1)
PC11–0 ← (SP) (SP + 3) (SP + 2)
SP ← SP + 4
1
1
3 + S
Unconditional
RETS
RETI
the skip unconditionally
×, ×, PC13.12 ← (SP + 1)
3
PC11–0 ← (SP) (SP + 3) (SP + 2)
PSW ← (SP + 4) (SP + 5), SP ← SP + 6
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
(SP – 1) (SP – 2) ← rp, SP ← SP – 2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
rp ← (SP + 1) (SP), SP ← SP + 2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
IME (IPS.3) ← 1
rp
PUSH
POP
EI
BS
rp
BS
IE × × × ← 1
IE× × ×
IME (IPS.3) ← 0
DI
IE × × × ← 0
IE× × ×
A ← PORTn
(n = 0–8)
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
IN*1
OUT*1
XA ← PORTn+1, PORTn
PORTn ← A
(n = 4, 6)
(n = 2–8)
(n =4, 6)
*10
PORTn+1, PORTn ← XA
Set HALT Mode (PCC.2 ← 1)
Set STOP Mode (PCC.3 ← 1)
No Operation
HALT
STOP
NOP
RBS ← n
(n = 0–3)
RBn
SEL
MBS ← n
(n = 0,1,2,15)
MBn
• TBR Instruction
PC13–0 ← (taddr) 5–0 + (taddr + 1)
-----------------------------------------------------------------------
-----------------------------
• TCALL Instruction
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, PC13, 12
PC13–0 ← (taddr) 5–0 ← (taddr + 1)
1
3
GETI*2 taddr
SP ← SP – 4
-----------------------------------------------------------------------
• Other than TBR and TCALL Instruction
-----------------------------
Conforms to
Execution of an instruction addressed at
(taddr) and (taddr + 1)
referenced
instruction.
23
µPD75P336
*
1. At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance.
2. TBR and TCALL instructions are assembler pseudo-instructions for table definition.
Note 1. Instruction Group
2. Interruput control
3. CPU control
24
µPD75P336
4. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS
The program memory incorporated in the µPD75P336 is 32640 × 8-bit electrically writable one-time PROM.
Write/verify operations on this one-time PROM are executed using the pins shown in the table below.
Address updating is performed by means of clock input from the X1 pin rather than by address input.
Pin Name
Function
Voltage applecation pin for program memory write/verify
(normally VDD potential).
PP
V
Address update clock inputs for program memory write/verify.
Inverse of X1 pin signal is input to X2 pin.
X1, X2
MD0 to MD3
Operating mode selection pin for program memory write/verify.
8-bit data input/output pins for progrm memory write/verify.
P40 to P43 (low-order 4 bits)
P50 to P53 (high-order 4 bits)
Supply voltage application pin.
VDD
Applies 2.7 to 6.0 V in normal operation, and 6 V for program
memory write/verify.
Note 1. Pins not used in a program memory write/verify operation are handled as follows:
• Pins other than XT2.......... Connect to VSS with a pull-down resistor
• XT2 pins ............................. Leave open
2. Since the µPD75P336 is not provided with an erase window, program memory contents cannot be
erased with ultra-violet light.
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P336 enters the program memory write/
verify mode. This mode comprises one of the operating modes shown below according to the setting of pins MD0
to MD3.
Operating Mode Setting
Operating Mode
VPP
VDD
MD1
MD2 MD3
MD0
L
H
L
H
H
H
H
L
H
H
H
L
Program memory address zero-clear
Write mode
+12.5 V
+6V
L
Verify mode
X
H
Program inhibit mode
H
X: L or H
25
µPD75P336
4.2 PROGRAM MEMORY WRITE PROCEDURE
The procedure for writing to program memory is as shown below, allowing high-speed writing.
(1) Unused pins are connected to VSS with a pull-down resistor. The X1 pin is driven low.
(2) 5 V is supplied to the VDD and VPP pins.
(3) 10 µs wait.
(4) Program memory address zero-clear mode.
(5) 6 V is supplied to VDD, 12.5 V to VPP.
(6) Program inhibit mode.
(7) Data is written in 1 ms write mode.
(8) Program inhibit mode.
(9) Verify mode. If write is successful go to (10), otherwise repeat (7) to (9).
(10) (Number of times written in (7) to (9): X) × 1 ms additional writes.
(11) Program inhibit mode.
(12) Program memory address is updated (+1) by inputting 4 pulses to the X1 pin.
(13) Steps (7) to (12) are repeated until the last address.
(14) Program memory address zero-clear mode.
(15) VDD / VPP pin voltage is changed to 5 V.
(16) Power-off.
Steps (2) to (12) of this procedure are shown in the figure below.
Repeated X Times
Address
Increment
Additional
Write
Write
Verify
V
V
PP
V
PP
DD
V
DD + 1
V
DD
VDD
X1
P40-P43
P50-P53
Data Output
Data Input
Data Input
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
26
µPD75P336
4.3 PROGRAM MEMORY READ PROCEDURE
µPD75P336 program memory contents can be read using the following procedure.
(1) Unused pins are connected to VSS with a pull-down resistor. The X1 pin is driven low.
(2) 5 V is supplied to the VDD and VPP pins.
(3) 10 µs wait.
(4) Program memory address zero-clear mode.
(5) 6 V supplied to VDD, and 12.5 V to VPP.
(6) Program inhibit mode.
(7) Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per
4-pulse-input cycle.
(8) Program inhibit mode.
(9) Program memory address zero-clear mode.
(10) VDD / VPP pin voltage is changed to 5 V.
(11) Power-off.
Steps (2) to (9) of this procedure are shown in the figure below.
VPP
VPP
VDD
VDD + 1
VDD
V
DD
X1
P40-P43
P50-P53
Data Output
Data Output
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
27
µPD75P336
P336
µPD75304B
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
SYMBOL
TEST CONDITIONS
Open-drain
RATING
UNIT
–0.3 to +7.0
VDD
V
V
★
Power supply voltage
VPP
–0.3 to +13.5
–0.3 to VDD +0.3
V
Except ports 4, 5
VI1
VI2
Input voltage
Ports 4, 5
–0.3 to +11
V
Output voltage
–0.3 to VDD +0.3
VO
IOH
V
–15
mA
mA
mA
mA
mA
mA
mA
mA
°C
1 pin
Output current high
–30
All pins
30
Peak value
1 pin
15
100
Effective value
Peak value
Output current low
Total of ports 0, 2, 3, 5, 18
Total of ports 4, 6, 7
IOL*
60
Effective value
Peak value
100
60
Effective value
Operating temperature
Storage temperature
Topt
Tstg
–40 to +85
–65 to +150
°C
*
Rms value is calculated from [effective value] = [peak value] × √duty
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
I/O capacitance
SYMBOL
CIN
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
pF
15
15
15
f = 1 MHz
Unmeasured pins returned to 0 V.
COUT
pF
CIO
pF
28
µPD75P336
P336
µPD75304B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
TEST
CONDITIONS
RECOMMENDED
CONSTANT
ESONATOR
PARAMETER
MIN.
1.0
TYP.
MAX.
UNIT
MHz
Oscillator
frequency (fx)*1
5.0*3
X1
X1
Ceramic
resonator
After VDD
reached the
MIN. of the
oscillator
voltage
Oscillation
stabilization
time*2
4
ms
C1
C2
VDD
range.
Oscillator
frequency (fx)*1
1.0
4.19
5.0*3
10
MHz
ms
X1
X1
Crystal
resonator
VDD = 4.5
to 6.0 V
Oscillation
stabilization
time*2
C1
C2
30
ms
VDD
X1 input
frequency (fx)*1
1.0
5.0*3
MHz
ns
X1
X2
External
clock
X1 input
high-/low-level
width (tXH, tXL)
100
500
µPD74HCU04
*
1. Shows the oscillator characteristics only. For the instruction execution time, see the AC characteristics.
2. Time necessary for oscillation to stabilize after VDD applied or STOP mode released.
3. When the oscillator frequency is “4.19 MHz < fX ≤ 5.0 MHz”, it is impossible to select of “PCC = 0011” with
1 machine cycle of less than 0.95 µs as instruction execution time.
29
µPD75P336
P336
µPD75304B
(Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS
RECOMMENDED
TEST
RESONATOR
PARAMETER
MIN.
32
TYP.
MAX.
UNIT
CONSTANT
CONDITIONS
Oscillator
frequency (fXT)
32.768
1.0
35
2
kHz
s
XT1
XT2
VDD = 4.5
to 6.0 V
Crystal
R
resonator
Oscillation
stabilization time
C3
C4
10
s
VDD
XT1 input
frequency (fXT)
32
5
100
15
kHz
XT1
XT2
External
clock
Leave
Open
XT1 input high-/
low-level width
(tXTH,tXTL)
µs
Note When the main system clock and subsystem clock oscillation circuit are used, area inside doted lines in
the figure should be wired as follows to prevent influence from the wiring capacitance, etc..
• Wiring should be as short as possible.
• Do not cross other signal lines, and do not place the oscillator close to line in which varying high
current flows.
• Potential at the oscillator capacitor connecting point should always be the same as VDD. Do not
connect to the power supply pattern in which high current flows.
• Do not fetch signals from the oscillator.
In the subsystem clock oscillator, which is designed to be a circuit with low amplification ratio to suppress
consumption current, misoperation due to noise occurs more often than in the main system clock
oscillator. Therefore, when using the subsystem clock, special care should be taken in the wiring method.
30
µPD75P336
P336
µPD75304B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/3)
PARAMETER
SYMBOL
TEST CONDITIONS
Ports 2, 3, 8
Ports 0, 1, 6, 7, RESET
MIN.
TYP.
MAX.
UNIT
VDD
VDD
0.7 VDD
V
V
V
V
V
V
V
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
0.8 VDD
Input voltage
high
10
0.7 VDD
Ports 4 and 5
Open-drain
VDD
X1, X2, XT1
VDD –0.5
0.3 VDD
0.2 VDD
0.4
0
0
0
Ports 2, 3, 4, 5, 8
Ports 0, 1, 6, 7 RESET
Input voltage
low
X1, X2, XT1
VDD = 4.5 to
6.0 V
IOH = –1 mA
V
V
V
V
VDD –1.0
VDD –0.5
VDD –2.0
VDD –1.0
Ports
0, 2, 3, 6, 7, 8
BIAS
VOH1
VOH2
IOH = –100 µA
Output voltage
high
VDD = 4.5 to
6.0 V
IOH = –100 µA
BP0 to BP7
(IOH 2 outputs)
IOH = –50 µA
31
µPD75P336
P336
µPD75304B
DC CHARACTERISTICS
(Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (2/3)
PARAMETER
SYMBOL
TEST CONDITIONS
Ports 3, 4, 5
MIN.
TYP.
0.4
MAX.
UNIT
V
VDD = 4.5 to
6.0 V
2.0
IOL = 15 mA
Ports
0, 2, 3, 4, 5, 6
7, 8
VDD = 4.5 to
6.0 V
0.4
0.5
V
V
V
VOL1
IOL = 1.6 mA
Output voltage
low
IOL = 400 µA
Open-drain
pull-up
0.2 VDD
SB0, 1
resistor ≥ 1 kΩ
VDD = 4.5 to
6.0 V
IOL = 100 µA
1.0
1.0
V
V
BP0 to BP7
(IOL 2 outputs)
VOL2
IOL = 50 µA
Other than
below
ILIH1
ILIH2
ILIH3
3
µA
µA
VIN = VDD
X1, X2, XT1
20
Input leakage
current high
Ports 4, 5
(when open-
drain)
20
µA
VIN = 10 V
Other than
below
–3
µA
µA
ILIL1
ILIL2
Input leakage
current low
VIN = 0 V
X1, X2, XT1
–20
Other than
below
3
µA
µA
ILOH1
ILOH2
VOUT = VDD
Output leakage
current high
Ports 4 and 5
(when open-
drain)
20
VOUT = 10 V
Output leakage
current low
–3
80
µA
kΩ
ILOL
RL1
VOUT = 0 V
VDD = 5.0 V
15
30
2.5
40
±10%
Ports 0, 1, 2, 3, 6
7, 8 (Except P00)
VIN = 0 V
Built-in Pull-up
resistor
VDD = 3.0 V
300
kΩ
±10%
LCD drive voltage
VDD
V
VLCD
32
µPD75P336
P336
µPD75304B
DC CHARACTERISTICS
(Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (3/3)
SYMBOL
VODC
TEST CONDITION
MIN.
0
TYP.
PARAMETER
UNIT
V
MAX.
LCD output
voltage
deviation*1
(common)
VLCD0 = VLCD
VLCD1 =
IO = ±5 µA
IO = ±1 µA
±0.2V
VLCD × 2/3
VLCD2 =
VLCD × 1/3
2.7 V ≤ VLCD
≤ VDD
LCD output
voltage
deviation*1
(segment)
VODS
V
±0.2V
0
VDD = 5 V
±10 %*4
15
3
5
1
mA
mA
IDD1
VDD = 3 V
±10 %*5
4.19 MHz
crystal
oscillation
C1= C2 = 22 pF*3
VDD =
5 V
±10 %
500
1500
µA
HALT
mode
IDD2
VDD =
3 V
±10 %
900
300
60
300
100
20
µA
µA
Power supply
current
*2
VDD =
3 V
±10 %
Operat-
IDD3
IDD4
ing
mode
32 kHz
crystal
oscillation*6
VDD =
3 V
±10 %
HALT
mode
µA
µA
VDD = 5 V ±10 %
0.5
0.1
0.1
20
10
XT1 = 0 V
STOP mode
IDD5
VDD =
3 V
±10 %
µA
µA
Ta =
25 °C
5
*
1. The voltage deviation means a difference between the ideal value of segment or common output (VLCDn;
n = 0, 1, 2) and the output voltage.
2. Current flowing in the built-in pull-up resistor and the LCD split resistor is not include.
3. Including the case where the subsystem clock is operating.
4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode.
5. When PCC is set to 0000 and operated in the low-speed mode.
6. The case where the system clock control register (SCC) is set to 1001, the main system clock oscillatio stopped
and the device is operated on the subsystem clock.
33
µPD75P336
P336
µPD75304B
A/D CONVERTER CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
SYMBOL
TEST CONDITION
MIN.
8
TYP.
8
PARAMETER
Resolution
UNIT
bit
MAX.
8
–10 ≤ Ta ≤
±1.5
±2.0
+ 85 oC
2.5 V ≤ AVREF ≤ VDD
AVREF ≥ 0.6 VDD
–40 ≤ Ta <
o
–10 C
Absolute
–10 ≤
accuracy*1
Ta ≤
±1.5
±2.0
±3.0
LSB
+ 85 oC
tCY ≥
1.91 µs
–40 ≤
2.5 V ≤ AVREF ≤ VDD
AVREF < 0.6 VDD
Ta ≤
– 10 oC
–40 ≤
Ta ≤
tCY <
1.91 µs
+ 85 oC
s
s
Conversion time
Sampling time
tCONV
*2
*3
168/fx
44x
tSAMP
Analog input
voltage
AVSS
AVREF
V
VIAN
Analog input
impedance
RAN
IREF
MΩ
1000
1.0
AVREF current
2.0
mA
*
1. Absolute accuracy excluding quantization (±1/2LSB) error.
2. Time up to end of conversion (EOC = 1) after execution of the conversion start instruction.
(40.1 µs: fx = 4.19 MHz operation)
3. Time up to end of sampling after execution of the conversion start instruction.
(10.5 µs: fx = 4.19 MHz operation)
34
µPD75P336
P336
µPD75304B
(Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
AC CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
0.95
3.8
TYP.
MAX.
UNIT
µs
Operated
by main
system
VDD = 4.5
to 6.0 V
64
64
CPU clock cycle
time (minimum
instruction
tCY
clock
µs
execution time = 1
machine cycle)*1
Operated
by subsystem
clock
114
122
125
µs
VDD = 4.5 to 6.0 V
0
0
1
MHz
kHz
µs
TI0, 1 input
frequency
fTI
275
tTIH,
tTIL
VDD = 4.5 to 6.0 V
0.48
1.8
*2
10
10
TI0, 1 input high/
low level width
µs
INT0
µs
tINTH,
tINTL
Interrupt input high/
low level width
INT1, 2, 4
KR0 to KR7
µs
µs
RESET low
level width
tRSL
10
µs
t
cy vs VDD
* 1. The CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator
and the system clock control register (SCC) and
the processor clock control register (PCC). The
figure below shows the main system clock opera-
tion power supply voltage VDD vs cycle time tCY
characteristics.
(Operating on Main System Clock)
70
64
30
6
5
Operating Guaranteed
Range
4
3
2. Becomes 2tCY or 128/fX depending on the
interrupt mode register (IM0) setting.
µ
2
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
35
µPD75P336
P336
µPD75304B
SERIAL TRANSFER OPERATION
2-wired and 3-wired serial I/O modes (SCK ... Internal clock output)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
1600
TYP.
MAX.
UNIT
ns
tKCY1
SCK cycle time
3800
ns
ns
tKCY1
/2-50
VDD = 4.5 to 6.0 V
tKL1
tKH1
SCK high/low
level width
tKCY1
/2-150
ns
ns
ns
SI setup time
(to SCK↑)
150
400
tSIK1
tKSI1
SI hold time
(from SCK↑)
VDD = 4.5
to 6.0 V
ns
ns
SO output
delay time
from SCK↓
250
RL = 1 kΩ ,
CL = 100 pF*
tKSO1
1000
2-wired and 3-wired serial I/O modes (SCK ... External clock input)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
UNIT
ns
tKCY2
SCK cycle time
3200
400
ns
ns
ns
VDD = 4.5 to 6.0 V
SCK high/low
level width
tKL2
tKH2
1600
SI setup time
(to SCK↑)
tSIK2
tKSI2
100
400
ns
SI hold time
(from SCK ↑)
ns
ns
VDD = 4.5
to 6.0 V
300
SO output
delay time
from SCK↓
RL = 1 kΩ,
CL = 100 pF*
tKSO2
1000
ns
*
RL and CL are the SO output line load resistance and load capacitance, respectively.
36
µPD75P336
P336
µPD75304B
SBI mode (SCK ... Internal clock output (master))
PARAMETER
UNIT
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
TYP.
MAX.
MIN.
1600
ns
ns
tKCY3
SCK cycle time
3800
tKCY3
/2-50
ns
tKL3
tKH3
VDD = 4.5 to 6.0 V
SCK high/low
level width
tKCY3
/2-150
ns
ns
SB0,1 setup time
(to SCK↑)
150
tSIK3
tKSI3
SB0,1 hold time
(from SCK↑)
ns
tKCY3/2
SB0,1 output
VDD = 4.5 to 6.0 V
250
ns
ns
0
0
RL = 1 kΩ ,
CL = 100 pF*
tKSO3
delay time
from SCK↓
1000
SB0,1 ↓
from SCK↑
tKSB
tSBK
tKCY3
tKCY3
tKCY3
ns
ns
ns
SCK from SB0, 1 ↓
SB0,1 low
level width
tSBL
tSBH
SB0,1 high
level width
tKCY3
ns
*
RL and CL are the SB0 and SB1 output line load resistance and load capacitance, respectively.
37
µPD75P336
P336
µPD75304B
SBI mode (SCK ... External clock input (slave))
PARAMETER
UNIT
SYMBOL
TYP.
MAX.
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
800
ns
ns
tKCY4
SCK cycle time
3200
400
ns
tKL4
tKH4
VDD = 4.5 to 6.0 V
SCK high/low
level width
ns
ns
ns
1600
SB0,1 setup time
(to SCK↑)
tSIK4
tKSI4
100
SB0,1 hold time
(from SCK↑)
tKCY4/2
0
0
SB0,1 output
VDD = 4.5 to 6.0 V
300
ns
ns
RL = 1 kΩ ,
CL = 100 pF*
tKSO4
tKSB
delay time
from SCK↓
1000
SB0,1 ↓
from SCK↑
tKCY4
ns
ns
SCK↓ from SB0, 1 ↓
tSBK
tKCY4
tKCY4
SB0,1 low
level width
ns
ns
tSBL
tSBH
SB0,1 high
level width
tKCY4
*
RL and CL are the SB0 and SB1 output line load resistance and load capacitance, respectively.
38
µPD75P336
P336
µPD75304B
AC Timing Test Point(Exculuding X1 and XT1 Inputs)
0.8 VDD
0.8 VDD
0.2 VDD
Test Points
0.2 VDD
Clock Timings
1/fX
t
XL
tXH
VDD -0.5 V
0.4 V
X1 Input
1/fXT
t
XTL
t
XTH
VDD -0.5 V
0.4 V
XT1 Input
TI0 Timing
1/fTI
t
TIL
tTIH
TI0
39
µPD75P336
P336
µPD75304B
Serial Transfer Timing
3-wired serial I/O mode:
t
KCY1
tKL1
tKH1
SCK
tSIK1
t
KSI1
Input Data
SI
tKSO1
SO
Output Data
2-wired serial I/O mode:
t
KCY2
t
KL2
t
KH2
SCK
tSIK2
t
KSI2
SB0,1
tKSO2
40
µPD75P336
P336
µPD75304B
Serial Transfer Timing
Bus release signal transfer:
t
KCY3,4
t
KL3,4
t
KH3,4
SCK
t
SIK3,4
t
KSB
tSBL
t
SBH
t
SBK
tKSI3,4
SB0,1
tKSO3,4
Command signal transfer:
tKCY3,4
t
KL3,4
tKH3,4
SCK
t
SIK3,4
tKSB
tSBK
t
KSI3,4
SB0,1
tKSO3,4
Interrupt Input Timing
tINTL
t
INTH
INT0,1,2,4
KR0-7
RESET Input Timing
t
RSL
RESET
41
µPD75P336
P336
µPD75304B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DAT RETENTION CHARACTERISTICS (Ta = –40 to 85 °C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
2.0
TYP.
MAX.
6.0
UNIT
V
Data retention
supply voltage
VDDDR
Data retention
supply current*1
VDDDR = 2.0 V
0.1
10
µA
µs
IDDDR
tSREL
tWAIT
Release signal
set time
0
Oscillation
stabilization
wait time*2
Release by RESET
217/fx
ms
ms
Release by interrupt request
*3
*
1. Current flng in the built-in pull-up resistor is not included.
2. The oscillation stabilization wait time is the time CPU operation is stopped to prevent unstable operation at
start of oscillation.
3. Depends on the basic interval timer mode register (BTM) setting (table below).
Waite Time
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at fxx = 4.19 MHz)
—
—
—
—
0
0
1
1
0
1
0
1
0
1
1
1
220/fxx (approx. 250 ms)
217/fxx (approx. 31.3 ms)
215/fxx (approx. 7.82 ms)
213/fxx (approx. 1.95 ms)
42
µPD75P336
P336
µPD75304B
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
V
DD
V
DDDR
t
SREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
V
DD
VDDDR
t
SREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
t
WAIT
43
µPD75P336
P336
µPD75304B
D/C PROGRAMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
MAX.
PARAMETER
MIN.
UNIT
SYMBOL
TEST CONDITION
Except X1, X2
TYP.
VDD
0.7VDD
V
V
V
VIH1
VIH2
VIL1
VIL2
VL1
Input voltage
high
VDD -0.5
X1, X2
VDD
Except X1, X2
0.3VDD
0
0
Input voltage
low
0.4
10
V
X1, X2
Input leakage
current
µA
VIN = VIL or VIH
Output voltage
high
VDD -1.0
IOH = –1 mA
IOL = 1.6 mA
V
VOH
VOL
Output voltage
low
0.4
30
V
VDD power supply
current
IDD
IPP
mA
mA
VPP power supply
current
30
MD0 = VIL , MD1 = VIH
* 1. VPP must not exceed +13.5 V including overshoot.
2. VDD should be applied before VPP and cut after VPP.
A/D PROGRAMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) (1/2)
UNIT
µs
PARAMETER
MAX.
SYMBOL
TYP.
TEST CONDITION
MIN.
2
*1
Address setup time *2
(to MD0↓)
tAS
tAS
MD1 setup time
µs
tMIS
tDS
tAH
tDH
tOES
tDS
tAH
tDH
2
2
(to MD0↓)
Data setup time
µs
(to MD0↓)
Address hold time *2
(from MD0↑)
µs
µs
µs
2
Data hold time
2
0
2
2
(from MD0↑)
Data output float
130
tDF
tDF
delay time from MD0↑
VPP setup time
tVPS
tVPS
µs
µs
(to MD3↑)
VDD setup time
tVDS
tPW
tVCS
tPW
(to MD3↑)
Initial program
pulse width
ms
1.05
0.95
1.0
*
1. Symbol of the corresponding µPD27C256.
2. The internal address signal is incremented (+1) at the rising edge of the forth X1 input. The signal is not
connected to pins.
44
µPD75P336
P336
µPD75304B
A/D PROGRAMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) (2/2)
UNIT
ms
PARAMETER
MAX.
21.0
SYMBOL
TYP.
TEST CONDITION
MIN.
0.95
*1
Additional program
pulse width
tOPW
tOPW
MD0 setup time
µs
tMOS
tDV
tCES
tDV
2
(to MD1↑)
Data output delay time
µs
1
MD0 = MD1 = VIL
from MD0↓
MD1 hold time
tM1H
tM1R
tOEH
tOR
µs
µs
µs
2
(from MD0↑)
tM1H + tM1R ≥ 50 µs
MD1 recover time
2
(from MD0↓)
Program conuter
reset time
10
tPCR
X1 input
0.125
tXH, tXL
µs
high/low width
X1 input frequency
Initial mode set time
fx
tI
MHz
4.19
µs
µs
2
2
MD3 setup time
tM3S
(to MD1↑)
MD3 hold time
tM3H
tM3SR
tDAD
2
2
µs
µs
(to MD1↓)
MD3 setup time
Program memory read
(to MD0 ↓)
Data output delay time
tACC
µs
µs
µs
µs
2
Program memory read
Program memory read
from address *2
Data output hold time
0
2
130
tHAD
tM3HR
tDFR
tOH
from address *2
MD3 hold time
Program memory read
Program memory read
(from MD0↑)
Data output float
delay time from MD3 ↓
2
*
1. Symbol of the corresponding µPD27C256.
2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not
connected to pins.
45
µPD75P336
P336
µPD75304B
Program Memory Write Timing mode:
tVPS
VPP
VPP
VDD
tVDS
VDD + 1
VDD
tXH
VDD
X1
tXL
P40-P43
P50-P53
Data Output
Data Input
Data Input
Data Input
tDH
tDS
tI
tDS
tAS
tAH
tOH
tDV
tDF
MD0
tPW
tM1R
tM0S
tOPW
MD1
MD2
tPCR
tM1S
tM1H
tM3H
tM3S
MD3
Program Memory Read Timing mode:
tVPS
V
V
PP
VPP
DD
tVDS
V
DD + 1
VDD
V
DD
t
XH
X1
tXL
t
DAD
tHAD
P40-P43
P50-P53
Data Output
Data Output
tDFR
tDV
tI
tM3HR
MD0
MD1
MD2
tPCR
t
M3SR
MD3
46
µPD75P336
6. PACKAGE INFORMATION
★
80 PIN PLASTIC QFP ( 14)
A
B
60
61
41
40
detail of lead end
21
20
80
1
G
M
I
H
J
K
N
L
S80GC-65-3B9-3
INCHES
NOTE
ITEM
A
MILLIMETERS
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
±
±
17.2 0.4
0.677 0.016
+0.009
±
B
14.0 0.2
0.551
–0.008
+0.009
±
C
14.0 0.2
0.551
–0.008
±
±
D
F
0.677 0.016
17.2 0.4
0.8
0.8
0.031
G
H
I
0.031
+0.004
±
0.30 0.10
0.012
–0.005
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
±
±
K
1.6 0.2
0.063 0.008
+0.009
±
0.031
L
0.8 0.2
–0.008
+0.10
+0.004
0.15
M
N
P
0.006
–0.05
–0.003
0.10
2.7
0.004
0.106
±
Q
S
0.1 0.1
±
0.004 0.004
3.0 MAX.
0.119 MAX.
47
µPD75P336
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
A
B
60
41
61
40
detail of lead end
80
21
1
20
G
M
I
J
H
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
0.551
A
B
C
D
14.0±0.2
12.0±0.2
12.0±0.2
14.0±0.2
–0.008
+0.009
0.472
–0.008
+0.009
0.472
–0.008
+0.009
0.551
–0.008
F
1.25
1.25
0.049
0.049
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.055
M
0.145
0.006±0.002
–0.045
N
P
Q
R
S
0.10
1.05
0.004
0.041
0.05±0.05
5°±5°
0.002±0.002
5°±5°
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-4
48
µPD75P336
7. RECOMMENDED SOLDERING CONDITIONS
★
This product should be soldered and mounted under the conditions in the table below.
For detail of recommended soldering conditions, refer to the information document"Surface Mount Technology
Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 7-1 Soldering Conditions
(1) µPD75P336GC-3B9 : 80-pin plastic QFP ( 14mm)
Recommended
Solderring Method
Wave soldering
Solderring Conditions
Condition Symbol
Solder bath temperature: 260 °C. max., Duration: 10 sec. max.,
Number of times: Once,
WS60-202-1
Time limit: 2 days* (thereafter 20 hours prebaking required at 125 °C)
Preheat temperature: 120 °C max. (package surface temperature)
Package Peak temperature: 230 °C, Duration: 30 sec. max., (at 210 °C or above),
Number of times: Once,
IR30-202-1
VP15-202-1
Infrared reflow
Time limit: 2 days* (thereafter 20 hours prebaking required at 125 °C)
Package Peak temperature: 215 °C, Duration: 40 sec. max., (at 200 °C or above),
Number of times: Once,
VPS reflow
Time limit: 2 days* (thereafter 20 hours prebaking required at 125 °C)
Pin part temperature: 300 °C or below,
Pin part heating
Duration: 3 sec. max. (per device side)
(2) µPD75P336GK-BE9 : 80-pin plastic TQFP (fine pitch) ( 12mm)
Recommended
Solderring Method
Infrared reflow
Solderring Conditions
Condition Symbol
Package Peak temperature: 235 °C, Duration: 30 sec. max., (at 210 °C or above),
Number of times: Once,
IR35-101-1
VP15-101-1
Time limit: 1 day* (thereafter 10 hours prebaking required at 125 °C)
Package Peak temperature: 215 °C, Duration: 40 sec. max., (at 200 °C or above),
Number of times: Once,
VPS reflow
Time limit: 1 day* (thereafter 10 hours prebaking required at 125 °C)
Pin part temperature: 300 °C or below,
Pin part heating
Duration: 3 sec. max. (per device side)
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65 % RH.
Note Use of more than one soldering method should be avoided (except in the case of pin part heating).
49
µPD75P336
P336
µPD75304B
µPD75304B
APPENDIX A. LIST OF FUNCTIONS
Name
µPD75P336
µPD75328
µPD75336
Item
75X-Standard
8064 (mask ROM)
512
CPU core
75X-High End
16256 (PROM)
ROM (bytes)
16256 (mask ROM)
RAM ( × 4 bits)
General registers
768
4 bits × 8 × 1 bank
4 bits × 8 × 4 banks
Main system
0.95 µs, 1.91 µs, 15.3 µs
0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs
clock
(at 4.19 MHz operation)
Instruction
cycle
(at 4.19 MHz operation)
122 µs (at 32.768 KHz operation)
Subsystem clock
CMOS input
8
20
8
Internal pull-up resistor specifiable by software
Dual function as segment pins
CMOS input/output
Input/
output
ports
44
CMOS output
8 (10 V withstand
voltage, mask option
pull-up capability)
8 (10 V, withstand voltage
mask option pull-up
capability)
N-ch open-drain
input/output
Same as at left
(but no pull-up resistor)
LCD controller/driver
Max.20 × 4 segment drive, variable duty: static, 1/2, 1/3, 1/4
•
8-bit resolution × 6-ch
(successive approxima-
tion type)
•
•
8-bit resolution × 8-ch (successive approximation
type)
A/D converter
•
Low-voltage operation
capability: VDD = 3.5 to
6.0 V
Low-voltage operation capability: VDD = 2.7 to 6.0 V
•
•
•
Basic interval timer × 1
Timer/event counter × 1
Watch timer × 1
•
•
•
Basic interval timer × 1
Timer/event counter × 2
Watch timer × 1
Timer/counter
Serial Interface
•
•
NEC standard serial interface (SBI)
Clocked serial interface
Vectored interrupt
Test input
External: 3 Internal: 3
External: 1 Internal: 1
External: 3 Internal: 4
External: 1 Internal: 1
Clock output (PCL)
Buzzer output (BUZ)
Φ, 524kHz, 262kHz, 65.5kHz (at 4.19MHz operation)
2kHz, 4kHz, 32kHz
2kHz
Transfer, addition/subtraction, increment/decrement,
comparison
8-bit data processing
Operating voltage
Transfer
VDD = 2.7 - 6.0 V
80-pin plastic QFP ( 14 mm)
Package
80-pin plastic TQFP (fine pitch) ( 12mm)
★
On-chip PROM product
µPD75P336
—
µPD75P328
50
µPD75P336
µPD75P336
P336
µPD75304B
PD75304B
APPENDIX B. DEVELOPMENT TOOLS
The following support tools are available for system development using the µPD75P336.
Language Processor
OS
Ordering Code (Product Name)
Host Machine
Supply Medium
MS-DOS™
Ver. 3.30
to
µS5A13RA75X
µS5A10RA75X
3.5-inch 2HD
5-inch 2HD
PC-9800
series
RA75X relocatable
assembler
Ver. 5.00A*
PC DOS™
(Ver. 3.1)
5-inch 2HC
IBM PC/AT
µS7B10RA75X
Remarks Assembler operation is only guaranteed for the host machines and operating systems quoted above.
PROM Write Tools
PROM programmer which enables a single-chip microcomputer with on-chip PROM to be
programmed in stand-alone mode or by operations from a host machine by connection of the
PG-1500
supplied board and a separately available programmer adapter.
Typical PROMs from 256K bits to 4M bits can also be programmed.
PA-75P328GC
PA-75P336GK
PROM programmer adapter for the µPD75P336GC, used connected to the PG-1500.
PROM program adapter for the µPD75P336GK, used connect to the PG-1500.
Controls the PG-1500 on the host machine, with the PG-1500 and host machine connected via a
serial or parallel interface.
Ordering Code (Product Name)
µS5A13PG1500
Host Machine
Supply Medium
3.5-inch 2HD
5-inch 2HD
OS
PG-1500
controller
MS-DOS
Ver. 3.30
to
PC-9800
series
★
★
µS5A10PG1500
Ver. 5.00A*
PC DOS
µS7B10PG1500
5-inch 2HC
IBM PC/AT
(Ver. 3.1)
*
The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software.
Remarks PG-1500 controller operation is only guaranteed for the host machines and operating systems quoted
above.
51
µPD75P336
P336
µPD75304B
µPD75304B
Debugging Tools
The IE-75000-R is an in-circuit emulator which corresponds to the 75X series. For µPD75P336
development the IE-75000-R is used in conjunction with an emulation probe.
IE-75000-R*1
Efficient debugging is possible by connection to a host machine and PROM programmer.
Emulation board for the IE-75000-R and IE-75001-R. Incorporated in the IE-75000-R. Used in
IE-75000-R-EM
conjunction with the IE-75000-R or IE-75001-R to perform µPD75P336 evaluation.
The IE-75001-R is an in-circuit emulator which corresponds to 75X series. For µPD75P336
development the IE-75001-R is used in conjunction with an emulation board IE-75000-R-EM*2
and emulation probe. Efficient debugging is possible by connection to a host machine and
PROM programer.
IE-75001-R
Emulation probe for µPD75P336GC. Used connect with the IE-75000-R or IE-75001-R, IE-75000-R-
EP-75338GC-R
EV-9200G-80
EM.
An 80-pin LCC socket (EV-9200GC-80) is also available to simplify connection to the user system.
Emulation probe for µPD75336GK. Used connected with the IE-75000-R or IE-75001-R, IE-75000-R-
EM. An 80-pin conversion adapter (EV-9500GK-80 is also available to simplify connection to the
user system.
EP-75336GK-R
EV-9500GK-80
Connects the IE-75000-R or IE-75001-R to the host machine via by RS-232-C and contronix I/F and
controls the IE-75000-R or IE-75001-R on the host machine.
Host Machine
Ordering Code (Product Name)
Supply Medium
3.5-inch 2HD
OS
µS5A13IE75X
MS-DOS
Ver. 3.30
to
IE control
program
PC-9800
series
µS5A10IE75X
µS7B10IE75X
5-inch 2HD
5-inch 2HC
Ver. 5.00A*3
PC DOS
IBM PC/AT
(Ver. 3.1)
*
1. Maintenance product
2. IE-75000-R-EM sold sparately
3. The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software.
★
Remarks Operations of the IE control program is only guaranteed for the host machines and operating systems
quoted above.
52
Development Tools Configuration ★
In-Circuit Emulator
IE-75000-R
Emulation Probe
IE-75001-R*1
Centronics I/F
EP-75336GC-R
EP-75336GK-R
RS-232-C
IE-75000-R-EM
IE
Control
Program
Host Machine
*2
PC-9800 Series
IBM PC/AT
User System
(Symbolic Debugging
Possible)
PG-1500
Controller
Pruducts
Incorporating
PROM
PROM Programmer
PG-1500
µPD75P336GC
µPD75P336GK
+
Relocatable
Assembler
*
1. The IE-75001-R does not incorporate the IE-75000-R-EM
(Available separately.)
Programmer Adapter
PA-75P328GC
PA-75P336GK
2. EV-9200GC-80
EV-9500GK-80
µ
µ
µ
µ
µ
µ
µ
µPD75P336
P336
µPD75304B
µPD75304B
54
µPD75P336
µPD75P336
P336
µPD75304B
PD75304B
55
µPD75P336
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation.
PC DOS and PC/AT is a trademark of IBM Corporation.
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NEC
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