UPD75P316BKK-T [NEC]
4-BIT SINGLE-CHIP MICROCOMPUTER; 4位单片机
| 型号： | UPD75P316BKK-T |
| 厂家： | 
NEC |
| 描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 文件： | 总46页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P316B
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P316B is a product of the µPD75316B with its built-in ROM having been replaced with the one-
time PROM.
It is most suitable for test production during system development and for production in small amounts since
it can operate under the same supply voltage as mask products.
The one-time PROM product is capable of writing only once and is effective for production of many kinds of
sets in small quantities and early startup.
The EPROM product allows programs to be written and rewritten, making it ideal for system evaluation.
Functions are described in detail in the following User'S Manual, which should be read when carrying out
design work.
µPD75308 User's Manual: IEM-5016
FEATURES
• Compatible (excluding mask option) with the µPD75312B/75316B (mask products)
• Memory capacity
• Program memory (PROM) : 16256 × 8 bits
• Data memory (RAM)
: 1024 × 4 bits
• Ideal for small set as camera, etc.
ORDERING INFORMATION
Ordering Code
Package
Internal ROM
One-time PROM
One-time PROM
EPROM
Quality Grade
Standard
µPD75P316BGC-3B9
µPD75P316BGK-BE9
µPD75P316BKK-T*
80-pin plastic QFP (■14 mm)
80-pin plastic QFP (fine pitch) (■12 mm)
80-pin ceramic WQNF (LCC with window)
Standard
Not applicable
(for function evaluation)
*
Under Development
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The µPD75P316B EPROM product does not provide a level of reliability suitable for use as a
volume production product for customers' devices. The EPROM product should be used solely for
function evaluation in experiments or preproduction.
In descriptions common to one-time PROM products and EPROM products in this document, the term
"PROM" is used.
The information in this document is subject to change without notice.
Document No. IC-3189
The mark ★ shows the major revised points.
(O.D. No. IC-8696)
Date Published January 1994P
Printed in Japan
© NEC Corporation 1994
µPD75P316B
PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (■14 mm)
• 80-pin plastic TQFP (fine pitch)(■12 mm)
• 80-pin ceramic WQFN (LCC with window)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
P60/KR0
S12
S13
S14
S15
S16
S17
60
59
58
X2
X1
VPP*
57
56
55
54
53
52
XT2
XT1
VDD
µ
µ
µ
S18
S19
P33/MD3
P32/MD2
S20
S21
10
11
12
13
14
15
16
17
18
19
20
51
50
49
48
47
46
45
44
43
42
41
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
S22
S23
P22/PCL
S24/BP0
S25/BP1
S26/BP2
S27/BP3
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
S28/BP4
S29/BP5
S30/BP6
S31/BP7
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
*
In normal operation, VPP input should be the VDD level.
P00-03
P10-13
P20-23
P30-33
P40-43
P50-53
P60-63
P70-73
BP0-7
KR0-7
SCK
: Port 0
VLC0-2
BIAS
LCDCL
SYNC
TI0
: LCD Power Supply 0-2
: LCD Power Supply Bias Control
: LCD Clock
: Port 1
: Port 2
: Port 3
: LCD Synchronization
: Timer Input 0
: Port 4
: Port 5
PTO0
BUZ
: Programmable Timer Output 0
: Buzzer Clock
: Port 6
: Port 7
PCL
: Programmable Clock
: Bit Port
INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
: Key Return
: Serial Clock
: Serial Input
: Serial Output
: Serial Bus 0, 1
: Reset Input
: Segment Output 0-31
INT2
X1, 2
XT1, 2
MD0-3
VDD
: External Test Input 2
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
: Mode Selection
SI
SO
SB0, 1
RESET
S0-31
: Positive Power Supply
: Ground
VSS
VPP
: Programing/Verifying Power
COM0-3 : Common Output 0-3
2
BASIC
INTERVAL
TIMER
PORT0
P00-P03
4
INTBT
PROGRAM
COUNTER (14)
PORT1
PORT2
PORT3
PORT4
P10-P13
P20-P23
4
4
4
4
SP(8)
CY
ALU
TIMER/EVENT
COUNTER
#0
TI0/P13
PTO0/P20
P30-P33
/MD0-MD3
INTT0
BANK
P40-P43
P50-P53
P60-P63
P70-P73
WATCH
TIMER
BUZ/P23
PORT5
PORT6
PORT7
4
4
4
GENERAL REG.
PROGRAM
MEMORY
INTW
f
LCD
DECODE
AND
CONTROL
(PROM)
SI/SB1/P03
SO/SB0/P02
SCK/P01
DATA
MEMORY
(RAM)
SERIAL BUS
INTERFACE
16256 × 8 BITS
1024 × 4 BITS
INTCSI
24
8
S0-S23
INT0/P10
INT1/P11
INT2/P12
S24/BP0
–S31/BP7
INTERRUPT
CONTROL
LCD
CONTROL-
LER
4
COM0–COM3
INT4/P00
KR0/P60
–KR7/P73
f
/ 2N
X
8
3
/DRIVER
VLC0–VLC2
SYSTEM CLOCK
GENERATOR
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
STAND BY
CONTROL
CPU
CLOCK
BIT SEQ.
BUFFER (16)
SUB
MAIN
f
LCD
BIAS
µ
LCDCL/P30
SYNC/P31
PCL/P22
XT1
XT2
X1 X2
V
SS
V
PP
V
DD
RESET
µPD75P316B
CONTENTS
1. PIN FUNCTIONS ......................................................................................................................................... 5
1.1 PORT PINS ........................................................................................................................................................... 5
1.2 OTHER PINS ......................................................................................................................................................... 7
1.3 PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9
2. DIFFERENCES BETWEEN PRODUCTS IN SERIES ................................................................................11
3. DATA MEMORY (RAM) ............................................................................................................................ 12
4. PROGRAM MEMORY WRITE AND VERIFY............................................................................................ 14
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 14
4.2 PROGRAM MEMORY WRITING PROCEDURE ...............................................................................................15
4.3 PROGRAM MEMORY READING PROCEDURE...............................................................................................16
4.4 ERASURE PROCEDURE(µPD75P316BKK-T-ONLY) ........................................................................................17
5. ELECTRICAL SPECIFICATIONS ............................................................................................................... 18
6. PACKAGE INFORMATION ....................................................................................................................... 39
7. RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 42
APPENDIX A. DEVELOPMENT TOOLS......................................................................................................... 43
APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 44
4
µPD75P316B
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Dual-Function
Pin
I/O Circuit
Type*1
Pin Name
Afer Reset
Input/Output
Function
8-bit I/O
P00
P01
Input
INT4
SCK
B
4-bit input port (PORT0)
Input/output
Input/output
Input/output
F
F
- A
- B
Internal pull-up resistor specification by
software is possible for P01 to P03 as a 3-bit
unit.
×
Input
Input
Input
Input
P02
SO/SB0
SI/SB1
INT0
P03
M - C
With noise elimination circuit
P10
P11
INT1
4-bit input port (PORT1)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input
×
×
×
B - C
P12
INT2
P13
TI0
P20
PTO0
P21
—
4-bit input/output port (PORT2)
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input/output
Input/output
E - B
P22
PCL
P23
BUZ
P30 *2
P31 *2
P32 *2
P33 *2
LCDCL MD0
SYNC MD1
MD2
Programmable 4-bit input/output port (PORT3)
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
E - B
MD3
N-ch open-drain 4-bit input/output port (PORT
4).
Data input/output pins for program memory
(PROM) write/verify (low-order 4 bits).
P40 to P43*2
P50 to P53 *2
Input/output
Input/output
—
—
High impedance
High impedance
M - A
M - A
N-ch open-drain 4-bit input/output port (PORT
5)
Data input/output pins for program memory
(PROM) write/verify (high-order 4 bits).
P60
P61
P62
P63
P70
P71
P72
P73
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
Input/output
Input/output
Input
Input
F - A
4-bit input/output port (PORT7).
Internal pull-up resistor specification by
software is possible as a 4-bit unit.
F
- A
* 1.
: Indicates a Schmitt-triggered input.
2 . Direct LED drive capability.
5
µPD75P316B
1.1 PORT PINS (2/2)
Dual-
Function Pin
I/O Circuit
TYPE
Pin Name
Input/Output
Output
Function
8-bit I/O
After Reset
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
S24
S25
S26
S27
S28
S29
S30
S31
★
1-bit output port (BIT PORT)
Dual-function as segment output pins.
×
*
G - C
Output
*
For BP0 to BP7, VLC1 is selected as the input source. The output level depends on BP0 to BP7 and the
VLC1 external circuit, however.
6
µPD75P316B
1.2 OTHER PINS
Dual-
Function Pin
I/O Circuit
Type *1
Pin Name
After Reset
Function
Input/Output
—
Input
output
P13
P20
P22
B
- C
External event pulse input pin for timer/event counter.
Timer/event counter output pin
Clock output pin
TI0
PTO0
PCL
Input
Input
E - B
E - B
Input/output
Fixed frequency output pin (for buzzer or system clock
trimming)
Input/output
Input/output
Input/output
P23
P01
P02
Input
BUZ
E - B
Serial clock input/output pin
F
- A
- B
Input
Input
SCK
Serial data output pin
Serial bus input/output pin
SO/SB0
F
Serial data input pin
Serial bus input/output pin
M - C
B
Input
—
SI/SB1
INT4
Input/output
Input
P03
P00
Edge-detected vectored interrupt input pin (rising or
falling edge detection).
INT0
INT1
P10
P11
Edge-detected vectored interrupt input pin (detection
edge selectable)
Input
B
- C
—
—
Input
Input/output
Input/output
Output
B
F
F
- C
- A
- A
Edge-detected testable input pin (rising edge detection)
Testable Input/output pins (parallel falling edge detection)
Testable Input/output pins (parallel falling edge detection)
Segment signal output pins
INT2
P12
Input
Input
KR0 to KR3
KR4 to KR7
S0 to S23
S24 to S31
COM0 to COM3
P60 to P63
P70 to P73
—
*3
G - A
G - A
G - B
—
Output
*3
BP0 to 7
—
Segment signal output pins
Output
Common signal output pins
*3
V
LC0 to VLC2
—
—
LCD drive power supply pins
—
BIAS
—
—
External split cutting output pin
High impedance
Input
—
LCDCL*2
SYNC*2
Input/output
P30
External extension driver drive clock output pin
E - B
External extension driver synchronization clock output
pin
P31
Input/output
Input
Input
—
E - B
—
Main system clock oscillation crystal/ceramic connection
pins. When an external clock is used, the clock is input
to X1 and the inverted clock to X2.
X1, X2
—
Subsystem clock oscillation crystal connection pins
When an external clock is used, the clock is input to XT1
and the inverted clock toXT2. XT1 can be used as a 1-bit
input (test) pin.
—
Input
—
XT1, XT2
—
Input
System reset input pin (low-level active).
RESET
—
B
—
Mode selection pin for program memory (PROM) write/
verify.
E - B
Input
MD0 to MD3
Input/output
P30 to P33
Program voltage application pin for program memory
(PROM) write/verify . Connected to VDD in normal
operation. Applies +12.5 V in program memory write/
verify.
—
—
VPP
—
—
—
—
—
—
—
—
Positive power supply pin
GND potential pin
VDD
VSS
—
—
7
µPD75P316B
*
1.
: Indicates a Schmitt-triggered input.
2. Pins provided for future system expansion. Currently used only as pins 30 and 31.
3. VLCX shown below can be selected for display outputs.
S0 to S31: VLC1, COM0 to COM2: VLC2 , COM3: VLC0
However, display output levels depend on the display output and VLCX external circuit.
8
µPD75P316B
1.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuits for each of the pin µPD75P316B are shown below in partially simplified form.
TYPE D (For TYPE E-B, F-A)
TYPE A (For TYPE E-B)
V
DD
VDD
data
P-ch
P-ch
OUT
IN
output
disable
N-ch
N-ch
Push-pull output that can be made high-impedance output
(P-ch and N-ch OFF)
CMOS Standard Input Buffer
TYPE B
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
P-ch
data
IN/OUT
IN
Type D
Type A
output
disable
P.U.R.
:
Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
TYPE B-C
TYPE F-A
VDD
P.U.R.
VDD
P.U.R.
enable
P.U.R.
P-ch
P.U.R.
enable
data
P-ch
IN/OUT
Type D
Type B
output
disable
IN
P.U.R. : Pull-Up Resistor
P.U.R.
:
Pull-Up Resistor
9
µPD75P316B
★
TYPE F-B
TYPE G-O
V
DD
VDD
P.U.R.
P-ch
P.U.R.
enable
P-ch
V
LC0
V
DD
output
disable
(P)
P-ch
VLC1
IN/OUT
data
P-ch
output
disable
SEG data/
Bit Port data
N-ch
OUT
N-ch
output
disable
(N)
VLC2
N-ch
P.U.R.
:
Pull-Up Resistor
TYPE G-A
TYPE M-A
IN/OUT
VLC0
P-ch
N-ch
(+10 V
data
VLC1
Withstand
Voltage)
output
disable
P-ch
SEG
data
OUT
N-ch
VLC2
N-ch
Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)
TYPE G-B
TYPE M-C
VDD
V
LC0
P.U.R.
P-ch
IN/OUT
P-ch
P.U.R.
enable
VLC1
N-ch
P-ch
data
OUT
N-ch
COM
data
output
disable
N-ch P-ch
VLC2
N-ch
P.U.R.
:
Pull-Up Resistor
10
µPD75P316B
2. DIFFERENCES BETWEEN PRODUCTS IN SERIES
The µPD75P316B is a version of the µPD75316B with its built-in mask ROM replaced with the one-time PROM
or EPROM. When performing debugging or preproduction of an application system using PROM and then
volume production using a mask ROM product, etc., these differences should be taken into account in the
transition. Table 2-1 shows the differences from the other products in series.
For the details of the CPU functions and the built-in hardware, please refer to the µPD75308 User's Manual
(IEM-5016).
Table 2-1 Differences between Products in Series
Product Name
µPD75P316A
µPD75P316B
µPD75312B/75316B
• Mask ROM
Comparison Item
Program memory (bytes)
• EPROM/one-time PROM • One-time PROM
• 16256
• EPROM
• 16256
• 12160/16256
Data memory (x 4 bits)
1024
Incorporation specifiable
by mask option
Pull-up resistors of ports 4 and 5
None
LCD driving power supplying split
resistor
Incorporation specifiable
by mask option
None
★
★
No.50 to 55
P30/MD0 to P33/MD3
VPP
P30 to P33
IC
Pin connection
No.57
The mask ROM products and PROM products have different consumption
currents, etc. See the Electrical Specifications section in the relevant Data Sheets
for details.
Electrical specifications
Power supply voltage range
2.7 to 6.0 V
2.0 to 5.5 V
• 80-pin plastic QFP
• 80-pin plastic QFP
(■14 mm)
• 80-pin plastic QFP
(14 × 20 mm)
• 80-pin ceramic WQNF
(LCC with window)
(■14 mm)
• 80-pin plastic TQFP
(fine pitch)(■12 mm)
• 80-pin plastic TQFP
(fine pitch)(■12 mm)
• 80-pin ceramic QWFN
(LCC with window)
Package
Other
The mask ROM products and PROM products have different circuit scales and
mask layouts, and therefore differ in terms of noise resistance and noise radiation.
★
★
*
Noise resistance and noise radiation differs between the PROM products and mask ROM products. When
investigating a switch from PROM product to mask PROM product in the transition from preproduction to
volume production, thorough evaluation should be carried out with the mask ROM CS product (not the ES
product).
11
µPD75P316B
3. DATA MEMORY (RAM)
Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area.
The data area consists of memory banks 0 to 3 with each bank consisting of 256 words x 4 bits.
Peripheral hardware has been assigned to the area of memory bank 15.
(1) Data area
The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt
execution stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the
memory content for a long time by battery backup, etc. The data area is operated by memory manipulation
instructions.
The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 x 4 bits each. Bank 0 has been
mapped as a data area but is also available as a general register area (000H to 007H) and a stack area (000H
to 0FFH) (banks 1, 2 and 3 are available only as a data area).
In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory ma-
nipulation instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruc-
tion, an even address should be specified.
(a) General register area
The general register area can be operated either by general register operation instructions or by memory
manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers
which is not used in the program is available as a data area or a stack area.
(b) Stack area
The stack area is set by an instruction. It is available as a subroutine execution or interrupt service
execution save area.
(2) Peripheral hardware area
The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15.
It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware,
however, the operable bit unit differs from one address to another. An address to which peripheral hardware
has not been assigned is inaccessible since no data memory is built in.
12
µPD75P316B
Fig. 3-1 Data Memory Map
Data Memory
Memory Bank
000H
General
Register Area
(8 × 4)
007H
008H
Stack
Area
0
256 × 4
0FFH
100H
Data Area
Static RAM
(1024 × 4)
256 × 4
256 × 4
1
2
3
1FFH
200H
2FFH
300H
256 × 4
3FFH
Not On-Chip
F80H
FFFH
15
128 × 4
Peripheral Hardware Area
13
µPD75P316B
4. PROGRAM MEMORY WRITE AND VERIFY
The ROM built into the µPD75P316B is a 16256 x 8-bit electrically writable one-time PROM. The table below
shows the pins used to program this PROM. There is no address input; instead, a method to update the ad-
dress by the clock input via the X1 pin is adopted.
Pin Name
Function
Voltage applecation pin for program memory write/verify
(normally VDD potential).
VPP
Address update clock inputs for program memory write/
verify. Inverse of X1 pin signal is input to X2 pin.
X1, X2
Operating mode selection pin for program memory write/
verify.
MD0 to MD3
8-bit data input/output pins for progrm memory write/
verify.
P40 to P43 (low-order 4 bits)
P50 to P53 (high-order 4 bits)
Supply voltage application pin.
VDD
Applies 2.0 to 5.5 V in normal operation, and 6 V for
program memory write/verify.
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES
The µPD75P316B assumes the program memory write/verify mode when +6 V and +12.5 V are applied
respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3
pin setting in this mode. All the remaining pins are at the VSS potential by the pull-down resistor.
Operating Mode Setting
Operating Mode
VPP
VDD
MD1 MD2 MD3
MD0
L
H
L
H
H
H
H
L
H
L
Program memory address zero-clear
Write mode
H
H
H
+12.5 V
+6 V
L
Verify mode
X
H
Program inhibit mode
X: L or H
14
µPD75P316B
4.2 PROGRAM MEMORY WRITING PROCEDURE
The program memory writing procedure is shown below. High-speed write is possible.
(1) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level.
(2) Supply 5 V to the VDD and VPP pins.
(3) 10 µs wait.
(4) The program memory address 0 clear mode.
(5) Supply 6 V and 12.5 V respectively to VDD and VPP.
(6) The program inhibit mode.
(7) Write data in the 1-ms write mode.
(8) The program inhibit mode.
(9) The verify mode. If written, proceed to (10); if not written, repeat (7) to (9).
(10) (Number of times written in (7) to (9): X) x 1-ms additional write.
(11) The program inhibit mode.
(12) Update (+1) the program memory address by inputting 4 pulses to the X1 pin.
(13) Repeat (7) to (12) up to the last address.
(14) The program memory address 0 clear mode.
(15) Change the VDD and VPP pins voltage to 5 V.
(16) Power off.
The diagram below shows the procedure of the above (2) to (12).
Repeated X Times
Address
Increment
Additional
Write
Write
Verify
V
V
PP
V
V
PP
DD
V
DD + 1
DD
V
DD
X1
P40-P43
P50-P53
Data Output
Data Input
Data Input
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
15
µPD75P316B
4.3 PROGRAM MEMORY READING PROCEDURE
The µPD75P316B can read the content of the program memory in the following procedure. It reads in the
verify mode.
(1) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level.
(2) Supply 5 V to the VDD and VPP pins.
(3) 10 µs wait.
(4) The program memory address 0 clear mode.
(5) Supply 6 V and 12.5 V respectively to VDD and VPP.
(6) The program inhibit mode.
(7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at
the period of inputting 4 pulses.
(8) The program inhibit mode.
(9) The program memory address 0 clear mode.
(10) Change the VDD and VPP pins voltage to 5 V.
(11) Power off.
The diagram below shows the procedure of the above (2) to (9).
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
P40-P43
P50-P53
Data Output
Data Output
MD0
(P30)
"L"
MD1
(P31)
MD2
(P32)
MD3
(P33)
16
µPD75P316B
4.4 ERASURE PROCEDURE (µPD75P316BKK-T ONLY)
The data programmed in the µPD75P316B can be erased by exposure to ultraviolet radiation through the
window in the top of the package.
Erasure is possible using ultraviolet light with a wavelength of approximately 250 nm. The exposure re-
quired for complete erasure is 15 W.s/cm2 (UV intensity x erasure time).
Erasure takes aproximately 15 to 20 minutes using a commercially available UV lamp (254 nm wavelength,
12 mW/cm2 intensity).
Note 1. Program contents may also be erased by extended exposure to direct sunlight or fluorescent light.
The contents should therefore be protected by masking the window in the top of the package with
light-shielding film.
The light-shielding film provided with NEC's UV EPROM products should be used.
2. Erasure should normally be carried out at a distance of 2.5 cm or less from the UV lamp.
Remarks The erasure time may be increased due to deterioration of the UV lamp or dirt on the package
window.
17
µPD75P316B
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
SYMBOL
TEST CONDITIONS
RATING
UNIT
Supply voltage
VDD
VI1
VI2
VO
–0.3 to + 7.0
V
Except ports 4 & 5
–0.3 to VDD + 0.3
V
Input voltage
Ports 4 & 5
–0.3 to + 11
V
Output voltage
Output current high
–0.3 to VDD + 0.3
V
1 pin
–15
mA
mA
mA
mA
mA
mA
mA
mA
°C
I
OH
All pins
–30
Peak value
R.m.s. value
Peak value
R.m.s. value
Peak value
R.m.s. value
30
1 pin
15
100
Output current low
I
OH*
Total for ports 0, 2, 3, 5
Total for ports 4, 6, 7
60
100
60
Operating temperature
Storage temperature
Topt
–40 to + 85
–65 to + 150
Tstg
°C
*
The r.m.s. value should be calculated as follows [R.m.s. value] = [Peak value] x Duty
Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even
momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions which ensure
that the absolute maximum ratings are not exceeded.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
I/O capacitance
TEST CONDITIONS
SYMBOL
CIN
MIN.
TYP.
MAX.
15
UNIT
pF
f=1 MHz
Unmeasured pins returned to 0 V.
15
pF
COUT
CIO
15
pF
18
µPD75B316B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85°C, VDD = 2.0 to 6.0 V)
MIN.
1.0
TEST CONDITIONS
TYP.
MAX. UNIT
RESONATOR
PARAMETER
RECOMENDED CONSTANT
Oscillation frequency
X1
X2
5.0*3 MHz
(fXX)*1
Ceramic
resonator*3
C2
C1
Oscillation stabilization
After VDD has reached MIN.
of oscillation voltage range.
4
ms
time*2
VDD
Oscillation frequency
X1
X2
1.0
5.0*3 MHz
4.19
(fXX)*1
Crystal*3
C2
C1
VDD=4.5 to 6.0 V
10
30
ms
ms
Oscillation stabilization
time*2
VDD
X1 input frequency
1.0
5.0*3 MHz
X1
X2
(fX)*1
External
clock
X1 input high-/low-level
width (tXH, tXL)
µPD74HCU04
100
500
ns
*
1. The oscillation frequency and X1 input frequency are only indications of the oscillator characteristics. See
the AC characteristics for instruction execution times.
2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches the MIN.
value of the oscillation voltage range, or the STOP mode is released.
3. When the oscillation frequency is 4.19 MHz < fXX <= 5.0MHz, PCC = 0011 should not be selected as the
instruction execution time. If PCC = 0011 is selected, one machine cycle will be less than 0.95 us, and the MIN.
value of 0.95 us in the specification will not be achieved.
Note When the main system clock oscillator is used, the following should be noted concerning wiring in the area
in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VDD. Do not connect
to a ground pattern carrying a high current.
• A signal should not be taken from the oscillator.
19
µPD75P316B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85°C, VDD = 2.0 to 6.0 V)
RESONATOR
MIN.
RECOMENDED CONSTANT
TEST CONDITIONS
TYP.
PARAMETER
MAX. UNIT
Oscillation frequency
(fXT)
XT1
XT2
R
32 32.768
35
kHz
Crystal
C2
C1
resonator
VDD=4.5 to 6.0 V
2
s
s
1.0
Oscillation stabilization
time*
10
VDD
XT1 input frequency
(fXT)
32
5
100 kHz
XT1
XT2
External
clock
Open
XT1 input high-/low-
level width (tXTH, tXTL)
µs
15
*
This is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage
range.
Note When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area
in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VDD. Do not connect
to a ground pattern carrying a high current.
• A signal should not be taken from the oscillator.
The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current,
and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is
therefore required with the wiring method when the subsystem clock is used.
20
µPD75B316B
(1) VDD=2.7 to 6.0 V
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
VIH1
TEST CONDITIONS
MIN.
0.7 VDD
0.8 VDD
0.7 VDD
VDD –0.5
0
TYP.
MAX.
VDD
UNIT
Ports 2 and 3
V
V
V
V
V
V
V
VIH2
Ports 0, 1, 6, 7 and RESET
Ports 4 and 5
VDD
Input voltage
high
VIH3
10
VIH4
X1, X2, XT1
VDD
VIL1
Ports 2, 3, 4, 5
0.3 VDD
0.2 VDD
0.4
Input voltage
low
VIL2
Ports 0, 1, 6, 7 and RESET
X1, X2, XT1
0
VIL3
0
VDD = 4.5 to 6.0 V
VDD –1.0
VDD –0.5
V
V
Ports 0, 2, 3, 6, 7,
and BIAS
IOH = –1 mA
VOH1
VOH2
IOH = -100 µA
Output voltage
high
VDD = 4.5 to 6.0 V
VDD –2.0
VDD –1.0
V
V
BP0 to BP7
(with 2 IOH outputs)
IOH = –100 µA
IOH = –30 µA
Ports 3, 4, 5
VDD = 4.5 to 6.0 V
IOL = 15 mA
0.7
2.0
V
Ports
0, 2, 3, 4, 5, 6, 7
VDD = 4.5 to 6.0 V
IOL = 1.6 mA
0.4
0.5
V
V
V
VOL1
Output voltage
low
IOL = 400 µA
Open–drain
pull-up resistor ≥ 1 kΩ
SB0, 1
0.2 VDD
VDD = 4.5 to 6.0 V
1.0
V
BP0 to BP7
(with 2 IOL outputs)
IOL = 100 µA
VOL2
IL1H1
IOL = 50 µA
Other than below
X1, X2, XT1
1.0
3
V
µA
VIN = VDD
Input leakage
current high
ILIH2
ILIH3
20
20
µA
µA
VIN = 10 V
Ports 4 and 5
ILIL1
Other than below
X1, X2, XT1
–3
µA
Input leakage
current low
VIN = 0 V
ILIL2
–20
3
µA
µA
µA
ILOH1
ILOH2
VOUT = VDD
Other than below
Ports 4 and 5
Output leakage
current high
VOUT = 10 V
20
Output leakage
current low
ILOL
VOUT = 0 V
–3
µA
21
µPD75P316B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
RL
TEST CONDITIONS
MIN.
15
TYP.
40
MAX.
80
UNIT
kΩ
Ports 0, 1, 2, 3, 6, 7
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
Internal pull-up
resistor
(Except P00)
VIN = 0 V
30
200
VDD
kΩ
LCD drive voltage
VLCD
2.0
V
LCD output voltage
deviation*1
(common)
VODC
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
2.7 V ≤ VLCD ≤ VDD
LCD output voltage
deviation
VODS
(segment)
VDD = 5 V ±10%*4
VDD = 3 V ±10%*5
DD
4.0
0.5
12
mA
mA
IDDI
4.19 MHz*3
crystal oscillation
C1 = C2 = 22 pF
1.5
V
V
= 5 V ±10%
1
3
mA
HALT
mode
IDD2
DD
= 3 V ±10%
300
30
900
90
µA
µA
IDD3
IDD4
VDD = 3 V ±10%
Supply current*2
32 kHz*6
crystal oscillation
HALT
mode
DD
V
= 3 V ±10%
7
21
µA
VDD = 5 V ±10%
1
25
15
5
µA
µA
µA
XT1 = 0 V
STOP mode
IDD5
0.5
0.5
VDD =
3 V ±10%
Ta = 25 °C
* 1. The voltage deviation is the difference between the output voltage and the ideal value of the common output
(VLCDn; n = 0, 1, 2).
2. Excluding the current flowing in the internal pull-up resistor.
3. Including the case where the subsystem clock is oscillated.
4. When the processor clock control register (PCC) is set to 0011 for operation in high-speed mode.
5. When PCC is set to 0000 for operation in low-speed mode.
6. When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and
the device is operated on the subsystem clock.
22
µPD75B316B
AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
CPU clock
cycle time*1
(minimum
instruction
execution time
= 1 machine cycle)
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
0.95
3.8
TYP.
122
MAX.
64
UNIT
µs
Operating on main
system clock
64
µs
tCY
Operating on
114
125
µs
subsystem clock
VDD = 4.5 to 6.0 V
0
0
1
MHz
kHz
µs
TI0 input
frequency
fTI
275
VDD = 4.5 to 6.0 V
0.48
1.8
*2
10
10
tTIH,
tTIL
TI0 input high-/low-
level width
µs
INT0
µs
Interrupt input
high-/low-level
width
tINTH,
tINTL
INT1, 2, 4
KR0 to KR7
µs
µs
RESET low-level
width
tRSL
10
µs
* 1. The CPU clock (Φ) cycle time (minimum instruc-
tion execution time) is determined by the oscil-
lation frequency of the connected resonator, the
system clock control register (SCC), and the
processor control register (PCC).
t
CY vs VDD
(Operating on Main System Clock)
70
64
30
The graph on the right shows the characteristic
of the cycle time tCY against the supply current
VDD in the case of main system clock operation.
2. 2tCY or 128/fX depending on the setting of the
interrupt mode register (IM0).
6
5
Guaranteed
Operation Range
4
3
2
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
23
µPD75P316B
SERIAL TRANSFER OPERATIONS
2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
1600
TYP.
MAX.
UNIT
ns
SCK cycle time
tKCY1
3800
ns
VDD = 4.5 to 6.0 V
tKCY1/2-50
tKCY1/2-150
ns
tKL1
tKH1
SCK high-/low-level
width
ns
SI setup time
(to SCK↑)
tSIK1
tKSI1
150
400
ns
ns
SI hold time
(from SCK↑)
*
SO output
delay time
from SCK↓
VDD = 4.5 to 6.0 V
250
ns
ns
RL = 1 kΩ,
CL = 100 pF
tKSO1
1000
2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
tKCY2
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
UNIT
ns
SCK cycle time
3200
400
ns
VDD = 4.5 to 6.0 V
ns
tKL2
tKH2
SCK high-/low-level
width
1600
ns
SI setup time
(to SCK↑)
tSIK2
tKSI2
100
400
ns
ns
SI hold time
(from SCK ↑)
*
SO output
delay time
from SCK↓
VDD = 4.5 to 6.0 V
300
ns
ns
RL = 1 kΩ,
CL = 100 pF
tKSO2
1000
*
RL and CL are the SO output line load resistance and load capacitance.
24
µPD75B316B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
tKCY3
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
1600
TYP.
MAX.
UNIT
ns
SCK cycle time
3800
ns
VDD = 4.5 to 6.0 V
tKCY3/2-50
tKCY3/2-150
ns
tKL3
tKH3
SCK high-/low-level
width
ns
SB0, 1 setup time
(to SCK ↑)
tSIK3
tKSI3
150
ns
ns
SB0, 1 hold time
(from SCK ↑)
tKCY3/2
SB0, 1 output
delay time from
SCK ↓
VDD = 4.5 to 6.0 V
0
250
ns
ns
ns
ns
RL = 1 kΩ,
CL = 100 pF
*
tKSO3
0
1000
SB0, 1 ↓ from SCK ↑
SCK from SB0, 1 ↓
tKSB
tKCY3
tKCY3
tSBK
SB0, 1 low-level
width
SBL
KCY3
t
t
ns
ns
SB0, 1 high-level
width
tSBH
tKCY3
SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
UNIT
ns
SCK cycle time
tKCY4
3200
400
ns
ns
VDD = 4.5 to 6.0 V
tKL4
tKH4
SCK high-/low-level
width
1600
100
ns
ns
SB0, 1 setup time
(to SCK ↑)
tSIK4
tKSI4
SB0, 1 hold time
(from SCK ↑)
tKCY4/2
ns
SB0, 1 output
delay time from
SCK ↓
VDD = 4.5 to 6.0 V
0
0
300
ns
ns
RL = 1 kΩ,
CL = 100 pF
*
tKSO4
1000
SB0, 1 ↓ from SCK ↑
SCK ↓ from SB0, 1 ↓
tKSB
tSBK
tKCY4
tKCY4
ns
ns
SB0, 1 low-level
width
tSBL
tSBH
tKCY4
tKCY4
ns
ns
SB0, 1 high-level
width
*
RL and CL are the SB0, 1 output line load resistance and load capacitance.
25
µPD75P316B
(2) VDD=2.7 to 6.0 V
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
VIH1
TEST CONDITIONS
Ports 2 and 3
MIN.
0.8 VDD
0.8 VDD
0.8VDD
VDD –0.3
0
TYP.
MAX.
VDD
UNIT
V
V
V
V
V
V
V
VIH2
Ports 0, 1, 6, 7 and RESET
Ports 4 and 5
VDD
Input voltage
high
VIH3
10
VIH4
X1, X2, XT1
VDD
VIL1
Ports 2, 3, 4, 5
0.2 VDD
0.2 VDD
0.25
Input voltage
low
VIL2
Ports 0, 1, 6, 7 and RESET
X1, X2, XT1
0
VIL3
0
Ports 0, 2, 3, 6, 7
and BIAS
VOH1
IOH = –100 µA
VDD –0.5
VDD –0.4
V
V
Output voltage
high
BP0 to BP7 (with
2 IOH outputs)
VOH2
IOH = –10 µA
IOL = 400 µA
Ports 0, 2, 3, 4, 5
6, 7
0.5
V
VOL1
Output voltage
low
Open–drain,
pull-up resistor ≥ 1 kΩ
SB0, 1
0.2 VDD
0.4
V
V
BP0 to BP7
(with 2 IOL outputs)
VOL2
IOL = 10 µA
ILIH1
ILIH2
ILIH3
Other than below
X1, X2, XT1
3
µA
µA
µA
VIN = VDD
Input leakage
current high
20
20
VIN = 10 V
Ports 4 and 5
ILIL1
ILIL2
Other than below
X1, X2, XT1
–3
–20
3
µA
µA
µA
µA
Input leakage
current low
VIN = 0 V
ILOH1
ILOH2
VOUT = VDD
Other than below
Ports 4 and 5
Output leakage
current high
VOUT = 10 V
20
Output leadage
current low
ILOL
VOUT = 0 V
–3
µA
Ports 0, 1, 2, 3, 6, 7
(Except P00)
VIN = 0 V
Internal pull-up
resistor
RL
VDD = 2.5 V ±10%
50
600
kΩ
LCD drive voltage
VLCD
2.0
VDD
V
26
µPD75B316B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
0
TYP.
MAX.
UNIT
V
LCD output voltage
deviation *1
(common)
VODC
IO = ±5 µA
IO = ±1 µA
±0.2
VLCDO = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
2.0 V ≤ VLCD ≤ VDD
LCD output
voltage deviation
(segment)
VODS
0
±0.2
V
VDD = 3 V ±10%*4
0.5
0.4
300
200
40
1.5
1.2
900
600
90
75
21
12
15
5
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
IDDI
4.19 MHz*3
VDD = 2.5 V ±10%*4
HALT VDD = 3 V ±10%
mode VDD = 2.5 V ±10%
VDD = 3 V ±10%
crystal oscillation
C1 = C2 = 22 pF
low-speed mode
IDD2
IDD3
IDD4
Supply current*2
VDD = 2.5 V ±10%
25
32 kHz*5
crystal oscillation
HALT VDD = 3 V ±10%
mode VDD = 2.5 V ±10%
7
4
0.5
0.5
0.4
0.4
VDD = 3 V ±10%
Ta = 25°C
XT1 = 0 V
STOP mode
IDD5
15
5
VDD = 2.5 V
±10%
Ta = 25°C
* 1. The voltage deviation is the difference between the output voltage and the ideal value of the common
output (VLCDn; n = 0, 1, 2).
2. Excluding the current flowing in the internal pull-up resistor.
3. Including the case where the subsystem clock is oscillated.
4. When PCC is set to 0000 for operation in low-speed mode.
5. When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and
the device is operated on the subsystem clock.
27
µPD75P316B
AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS
VDD = 2.7 to 6.0 V
MIN.
3.8
5
TYP.
MAX.
64
UNIT
µs
CPU clock
cycle time
(minimum instruc-
tion execution time
= 1 machine
Operating on main
system clock
VDD = 2.0 to 6.0 V
64
µs
tCY
Ta = –40 to + 60 °C
VDD = 2.2 to 6.0 V
3.4
64
µs
µs
cycle)*1
Operating on
114
122
125
subsystem clock
TI0 input
frequency
fTI
0
275
kHz
TI0 input high-/low-
level width
tTIH,
tTIL
1.8
µs
INT0
*2
10
10
µs
µs
µs
Interrupt input
high-/low-level
width
tINTH,
tINTL
INT1, 2, 4
KR0 to KR7
RESET low-level
width
RSL
t
10
µs
* 1. The CPU clock (Φ ) cycle time (minimum instruc-
tion execution time) is determined by the oscil-
lation frequency of the connected resonator,
the system clock control register (SCC), and the
processor clock control register (PCC).
t
CY vs VDD
(Operating on Main System Clock)
70
64
30
6
5
The graph on the right shows the characteristic
of the cycle time tCY against the supply current
VDD in the case of main system clock operation.
2. 2tCY or 128/fX depending on the setting of the
interrupt mode register (IMO).
Guaranteed
4
3
Operation Range
2
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
28
µPD75B316B
SERIAL TRANSFER OPERATIONS
2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
1600
TYP.
MAX.
UNIT
ns
SCK cycle time
tKCY1
3800
ns
VDD = 4.5 to 6.0 V
tKCY1/2-50
tKCY1/2-150
ns
tKL1
tKH1
SCK high-/low-
level width
ns
SI setup time
(to SCK ↑)
tSIK1
250
400
ns
ns
SI hold time
(from SCK ↑)
tKSI1
SO output
delay time
from SCK ↓
VDD = 4.5 to 6.0 V
250
ns
ns
RL = 1 kΩ,
CL = 100 pF*
tKSO1
1000
2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
UNIT
ns
SCK cycle time
tKCY2
3200
400
ns
VDD = 4.5 to 6.0 V
ns
tKL2
tKH2
SCK high-/low-
level width
1600
ns
SI setup time
(to SCK↑)
tSIK2
tKSI2
100
400
ns
ns
SI hold time
(from SCK↑)
SO output
delay time
from SCK↓
VDD = 4.5 to 6.0 V
300
ns
ns
RL = 1 kΩ,
CL = 100 pF*
tKSO2
1000
*
RL and CL are the SO output line load resistance and load capacitance.
29
µPD75P316B
SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
1600
TYP.
MAX.
UNIT
ns
SCK cycle time
tKCY3
3800
ns
VDD = 4.5 to 6.0 V
tKCY3/2-50
tKCY3/2-150
ns
tKL3
tKH3
SCK high-/low-
level width
ns
SB0, 1 setup
time (to SCK↑)
tSIK3
tKSI3
250
ns
ns
SB0, 1 hold
time (from SCK↑)
tKCY3/2
SB0, 1 output
delay time
from SCK↓
VDD = 4.5 to 6.0 V
0
250
ns
ns
ns
ns
RL = 1 kΩ,
CL = 100 pF*
tKSO3
0
1000
SB0, 1 ↓ from SCK↑
SCK from SB0, 1 ↓
tKSB
tSBK
tKCY3
tKCY3
SB0, 1 low-level
width
tSBL
tKCY3
tKCY3
ns
ns
SB0, 1 high-level
width
tSBH
SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)
PARAMETER
SYMBOL
tKCY4
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
UNIT
ns
SCK cycle time
3200
400
ns
VDD = 4.5 to 6.0 V
ns
tKL4
tKH4
SCK high-/low-
level width
1600
ns
SB0, 1 setup
time (to SCK ↑)
tSIK4
tKSI4
100
ns
ns
SB0, 1 hold
time (from SCK ↑)
tKCY4/2
SB0, 1
output delay
time from SCK ↓
VDD = 4.5 to 6.0 V
0
300
ns
ns
ns
ns
RL = 1 kΩ,
CL = 100 pF*
tKSO4
0
1000
SB0, 1 ↓ from SCK ↑
SCK↓ from SB0, 1 ↓
tKSB
tSBK
tKCY4
tKCY4
SB0, 1 low-level
width
tSBL
tSBH
tKCY4
tKCY4
ns
ns
SB0, 1 high-level
width
*
RL and CL are the SBO, 1 output line load resistance and load capacitance.
30
µPD75B316B
AC Timing Test Points (Except X1 and XT1 inputs)
0.8 VDD
0.8 VDD
0.2 VDD
Test Points
0.2 VDD
Clock Timings
1/fX
t
XL
tXH
VDD -0.5 V
0.4 V
X1 Input
1/fXT
t
XTL
t
XTH
VDD -0.5 V
0.4 V
XT1 Input
TI0 Timing
1/fTI
t
TIL
tTIH
TI0
31
µPD75P316B
Serial Transfer Timing
3-wired serial I/O mode:
t
KCY1
t
KL1
t
KH1
SCK
t
SIK1
t
KSI1
Input Data
SI
t
KSO1
SO
Output Data
2-wired serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
tKSI2
SB0,1
t
KSO2
32
µPD75B316B
Serial Transfer Timing
Bus release signal transfer:
t
KCY3,4
t
KL3,4
t
KH3,4
SCK
t
SIK3,4
t
KSB
t
SBL
t
SBH
t
SBK
t
KSI3,4
SB0,1
t
KSO3,4
Command signal transfer:
tKCY3,4
t
KL3,4
tKH3,4
SCK
t
SIK3,4
tKSB
tSBK
t
KSI3,4
SB0,1
tKSO3,4
Interrupt Input Timing
tINTL
t
INTH
INT0,1,2,4
KR0-7
RESET Input Timing
t
RSL
RESET
33
µPD75P316B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 °C)
PARAMETER
SYMBOL
VDDDR
TEST CONDITIONS
MIN.
2.0
TYP.
0.3
MAX.
6.0
UNIT
V
Data retention supply voltage
Data retention supply current*1
Release signal setting time
IDDDR
VDDDR = 2.0 V
15
µA
µs
tSREL
0
Release by RESET
217/fx
ms
ms
Oscillation stabilization
wait time*2
tWAIT
Release by interrupt request
*3
* 1. Excluding current flowing in the internal pull-up resistor.
2. The oscillation stabilization time is the time during which the CPU operation is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the basic interval timer mode register (BTM) setting ( see table below).
WAIT TIME
(Figure in ( ) is for fx = 4.19 MHz)
BTM3
BTM2
BTM1
BTM0
—
—
—
—
0
0
1
1
0
1
0
1
0
1
1
1
220/fx (Approx. 250 ms)
217/fx (Approx. 31.3 ms)
215/fx (Approx. 7.82 ms)
213/fx (Approx. 1.95 ms)
34
µPD75B316B
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
V
DD
V
DDDR
t
SREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
V
DD
VDDDR
t
SREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
t
WAIT
35
µPD75P316B
DC PROGRAMMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
PARAMETER
SYMBOL
VIH1
TEST CONDITIONS
Except X1, X2
MIN.
0.7 VDD
VDD –0.5
0
TYP.
MAX.
VDD
UNIT
V
V
V
V
Input voltage
high
VIH2
X1, X2
VDD
VIL1
Except X1, X2
X1, X2
0.3 VDD
0.4
Input voltage
low
VIL2
0
Input leakage
current
IL1
VIN = VIL or VIH
IOH = –1 mA
10
µA
Output voltage
high
VOH
VDD –1.0
V
Outputvoltage
low
VOH
IOL = 1.6 mA
0.4
30
30
V
VDD supply
current
DD
I
mA
mA
VDD supply
current
PP
IL
IH
I
MD0 = V , MDI = V
Note 1. Ensure that VPP does not exeed +13.5 V including overshoot.
2. VDD must be applied before VPP, and cut after VPP.
36
µPD75B316B
DC PROGRAMMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
PARAMETER
Address setup time*2 (to MD0↓)
MD1 setup time (to MD0↓)
SYMBOL
tAS
*1
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
µs
tAS
2
2
tM1S
tDS
tOES
tDS
µs
Data setup time (to MD0↓)
2
µs
Address hold time*2 (from MD0↑)
Data hold time (from MD0↑)
Data output float delay time from MD0↑
VPP setup time (to MD3↑)
tAH
tAH
2
µs
tDH
tDH
2
µs
tDF
tDF
0
130
ns
µs
tVPS
tVDS
tPW
tVPS
tVCS
tPW
tOPW
tCES
tDV
2
VDD setup time (to MD3↑)
2
µs
Initial program pulse width
Additional program pulse width
MD0 setup time (to MD1↑)
0.95
0.95
2
1.0
1.05
21.0
ms
ms
µs
tOPW
tMOS
tDV
Data output delay time from MD0↓
MD1 hold time (from MD0↑)
MD1 recovery time (from MD0↓)
Program counter reset time
X1 input high-/low-level width
X1 input frequency
MD0=MD1=VIL
1
µs
tM1H
tM1R
tPCR
tXH, tXL
fX
tOEH
tOR
2
2
µs
tM1H+tM1R ≥ 50 µs
µs
10
µs
0.125
µs
4.19
MHz
µs
Initial mode setting time
tI
2
2
2
2
2
0
2
2
MD3 setup time (to MD1↑)
tM3S
tM3H
tM3SR
tDAD
tHAD
tM3HR
tDFR
µs
MD3 hold time (from MD1↓)
MD3 setup time (to MD0↓)
µs
Program memory read
Program memory read
Program memory read
Program memory read
Program memory read
µs
Data output delay time from address*2
Data output hold time from address*2
MD3 hold time (from MD0↑)
Data output float delay time from MD3↓
tACC
tOH
µs
130
µs
µs
µs
* 1. Symbol of corresponding µPD27C256A
2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.
37
µPD75P316B
Program Memory Write Timing
t
VPS
V
PP
V
PP
VDD
t
VDS
V
V
DD + 1
DD
VDD
t
XH
X1
t
XL
P40 - P43
P50 - P53
Data Input
D
ataOutput
Data
Input
Data Input
t
DS
tDH
t
1
t
DS
t
DH
t
DV
t
DF
t
AH
t
AS
MD0
MD1
MD2
MD3
t
PW
t
M1R
t
M0S
t
OPW
t
PCR
tM1S
t
M1H
t
M3H
t
M3S
Program Memory Read Timing
tVPS
VPP
VPP
VDD
tVDS
VDD + 1
VDD
VDD
tXH
X1
t
tXL
tDHAADD
P40 - P43
P50 - P53
Data Output
Data Output
t
DFR
tDV
t1
t
M3HR
MD0
MD1
tPCR
MD2
MD3
tM3SR
38
µPD75P316B
6. PACKAGE INFORMATION
80 PIN PLASTIC QFP ( 14)
A
B
60
61
41
40
detail of lead end
21
20
80
1
G
M
I
H
J
K
N
L
S80GC-65-3B9-3
INCHES
NOTE
ITEM
A
MILLIMETERS
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
±
±
17.2 0.4
0.677 0.016
+0.009
±
B
14.0 0.2
0.551
–0.008
+0.009
±
C
14.0 0.2
0.551
–0.008
±
±
D
F
0.677 0.016
17.2 0.4
0.8
0.8
0.031
G
H
I
0.031
+0.004
±
0.30 0.10
0.012
–0.005
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
±
±
K
1.6 0.2
0.063 0.008
+0.009
±
0.031
L
0.8 0.2
–0.008
+0.10
+0.004
0.15
M
N
P
0.006
–0.05
–0.003
0.10
2.7
0.004
0.106
±
Q
S
0.1 0.1
±
0.004 0.004
3.0 MAX.
0.119 MAX.
39
µPD75P316B
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
A
B
60
41
61
40
detail of lead end
80
21
1
20
G
M
I
J
H
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
A
B
C
D
14.0±0.2
12.0±0.2
12.0±0.2
14.0±0.2
0.551
0.472
0.472
0.551
–0.008
+0.009
–0.008
+0.009
–0.008
+0.009
–0.008
F
1.25
1.25
0.049
0.049
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.055
M
0.145
0.006±0.002
–0.045
N
P
Q
R
S
0.10
1.05
0.004
0.041
0.05±0.05
5°±5°
0.002±0.002
5°±5°
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-4
40
µPD75P316B
80 PIN CERAMIC WQFN
A
B
Q
K
T
80
1
M
J
H
I
U
R
Z
X80KW-65A-1
NOTE
ITEM
A
MILLIMETERS
INCHES
Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
±
±
14.0 0.2
0.551 0.008
B
13.6
13.6
0.535
0.535
C
±
±
D
F
0.551 0.008
14.0 0.2
1.84
0.072
G
H
I
3.6 MAX.
0.142 MAX.
+0.004
–0.005
±
0.45 0.10
0.018
0.06
0.003
J
0.65 (T.P.)
0.024 (T.P.)
+0.007
–0.006
±
1.0 0.15
0.039
K
C 0.3
0.825
0.825
R 2.0
9.0
C 0.012
0.032
Q
R
S
0.032
T
R 0.079
0.354
U
U1
W
Z
2.1
0.083
+0.006
–0.007
±
0.030
0.75 0.15
0.10
0.004
41
µPD75P316B
7. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions for the surface mounting type, refer to the information
document "Surface Mount Technology Manual (IEI 1207)".
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 7-1 Recommended Soldering Conditions
µPD75P316BGC-3B9: 80-Pin Plastic QFP (■14 mm)
Soldering Method
Infrared reflow
Recommended Soldering Conditions
Package peak temperature: 230°C;
Recommended Condition Symbol
IR35-00-1
Duration: 30 sec. max. (at 210°C or above);
Number of times: once;
Pin part temperature: 300°C max.;
Pin part heating
Duration: 3 sec. max. (per device side)
µPD75P316BGK-ΒΕ9: 80-Pin Plastic QFP (■12 mm)
Soldering Method
Recommended Soldering Conditions
Recommended Condition Symbol
IR35-00-1
Package peak temperature: 235°C;
Duration: 30 sec. max. (at 210°C or above);
Infrared reflow
Number of times: once;
Timelimit: 7 days*(thereafter 10 hours prebaking required
at 125°C)
Pin part temperature: 300°C max.;
Pin part heating
Duration: 3 sec. max. (per device side)
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.
Note Use of more than one soldering method should be avoided (except in the case of pin part heating).
42
µPD75P316B
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD75P316B.
IE-75000-R*1
75X series in-circuit emulator
IE-75001-R
IE-7500-R-EM*2
Emulation board for IE-75000-R and IE-75001-R
EP-75308BGC-R
Emulation probe for µPD75P316BGC.
Provided with EV-9200GC-80, 80-pin conversion socket.
EV-9200GC-80
EP-75308BGK-R
µPD75P316BGK emulation probe.
Provided with EV-9200GK-80, 80-pin conversion socket.
EV-9500GK-80
PROM programmer
PG-1500
µPD75P316BGC programmer adapter. Connected with PG-1500.
µPD75P316BGK programmer adapter. Connected with PG-1500.
PA-75P316BGC
PA-75P316BGK
IE control program
Host Machine
PG-1500 controller
PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A*3)
IBM PC/AT™ (PC DOS™ Ver.3.1)
RA75X relocatable assembler
*
1. Maintenance product
2. Not incorporated in the IE-75001-R.
3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software.
★
43
µPD75P316B
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
User's Manual
Document Number
IEM-5016
Instruction Application Table
IEM-994
IEM-5035
IEM-5041
IF-151
Application Note
75X Series Selection Guide
Development Tools Documents
Document Name
Document Number
IE-75000-R/IE-75001-R User's Manual
IE-75000-R-EM User's Manual
EP-75308BGC-R User's Manual
EP-75308BGK-R User's Manual
PG-1500 User's Manual
EEU-846
EEU-673
EEU-825
EEU-838
EEU-651
EEU-731
EEU-730
EEU-704
Operation
Language
RA75X Assembler Package User's Manual
PG-1500 Controller User's Manual
Other Documents
Document Name
Document Number
Package Manual
IEI-635
IEI-1207
IEI-1209
IEM-5068
MEM-539
MEI-603
MEI-604
Surface Mount Technology Manual
Quality Grande on NEC Semiconductor Device
NEC Semiconductor Device Reliability & Quality Control
Electrostatic Discharge(ESD) Test
Semiconductor Devices Quality Guarantee Guide
Microcomputer Related Products Guide Other Manufacturers Volume
*
The contents of the above related documents are subject to change without notice. The latest documents
should be used for design, etc.
44
µPD75P316B
45
µPD75P316B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
相关型号：
UPD75P3216GT
4-BIT, OTPROM, 6MHz, MICROCONTROLLER, PDSO48, 0.375 INCH, 0.65 MM PITCH, PLASTIC, SSOP-48
RENESAS
UPD75P3216GT-A
Microcontroller, 4-Bit, OTPROM, 6MHz, MOS, PDSO48, 0.375 INCH, 0.65 MM PITCH, LEAD FREE, PLASTIC, SSOP-48
NEC
©2020 ICPDF网 联系我们和版权申明