2SJ598-Z [NEC]
SWITCHING P-CHANNEL POWER MOS FET; 切换P沟道功率MOS FET型号: | 2SJ598-Z |
厂家: | NEC |
描述: | SWITCHING P-CHANNEL POWER MOS FET |
文件: | 总8页 (文件大小:154K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ598
SWITCHING
P-CHANNEL POWER MOS FET
ORDERING INFORMATION
DESCRIPTION
The 2SJ598 is P-channel MOS Field Effect Transistor designed
PART NUMBER
PACKAGE
for solenoid, motor and lamp driver.
2SJ598
TO-251 (MP-3)
TO-252 (MP-3Z)
2SJ598-Z
FEATURES
• Low on-state resistance:
RDS(on)1 = 130 mΩ MAX. (VGS = –10 V, ID = –6 A)
RDS(on)2 = 190 mΩ MAX. (VGS = –4.0 V, ID = –6 A)
• Low Ciss: Ciss = 720 pF TYP.
• Built-in gate protection diode
• TO-251/TO-252 package
(TO-251)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
VDSS
VGSS
ID(DC)
ID(pulse)
PT
PT
Tch
Tstg
IAS
–60
m20
m12
m30
23
V
V
A
A
W
W
°C
°C
A
1.0
150
(TO-252)
Storage Temperature
–55 to +150
–12
Single Avalanche Current Note2
Single Avalanche Energy Note2
EAS
14.4
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = –30 V, RG = 25 Ω, VGS = –20 → 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D14656EJ4V0DS00 (4th edition)
Date Published August 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2000, 2001
2SJ598
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
TEST CONDITIONS
VDS = –60 V, VGS = 0 V
GS = m16 V, VDS = 0 V
MIN. TYP. MAX.
UNIT
µA
µA
V
IDSS
–10
V
m10
IGSS
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
VDS = –10 V, ID = –1 mA
VDS = –10 V, ID = –6 A
VGS = –10 V, ID = –6 A
VGS = –4.0 V, ID = –6 A
VDS = –10 V
–1.5
5
–2.0
11
–2.5
Forward Transfer Admittance
Drain to Source On-state Resistance
S
102
131
720
150
50
130
190
mΩ
mΩ
pF
pF
pF
ns
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V
f = 1 MHz
td(on)
tr
ID = –6 A
7
VGS = –10 V
4
ns
Turn-off Delay Time
Fall Time
td(off)
tf
VDD = –30 V
35
ns
RG = 0 Ω
10
ns
Total Gate Charge
QG
ID = –12 A
15
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
QGD
VF(S-D)
trr
VDD= –48 V
3
VGS = –10 V
4
IF = 12 A, VGS = 0 V
IF = 12 A, VGS = 0 V
di/dt = 100 A/µs
0.98
50
ns
Qrr
100
nC
TEST CIRCUIT 2 SWITCHING TIME
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
D.U.T.
L
RG
= 25 Ω
V
GS(−)
R
L
90%
90%
V
GS
V
GS
10%
VDD
50 Ω
PG.
GS = −20 → 0 V
Wave Form
0
RG
V
PG.
VDD
VDS(−)
90%
−
BVDSS
IAS
V
DS
V
0
GS(−)
VDS
10% 10%
VDS
0
Wave Form
I
D
td(on)
tr
td(off)
t
f
VDD
τ
ton
toff
τ = 1
µ
s
Starting Tch
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG
= −2 mA
RL
PG.
VDD
50 Ω
2
Data Sheet D14656EJ4V0DS
2SJ598
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
30
25
20
15
10
5
100
80
60
40
20
0
0
0
20
40 60
80 100 120 140 160
20 40
60
80 100 120 140 160
0
T
C
- Case Temperature - ˚C
T
C
- Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
–100
–10
PW = 10
I
D(pulse)
100
µ
s
µ
s
ID(DC)
1 ms
Power Dissipation
10 ms
Limited
Limited
RDS(on)
DC
–1
TC
= 25˚C
Single Pulse
–0.1
–0.1
–1
–10
–100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
R
R
th(ch-A) = 125˚C/W
100
10
th(ch-C) = 5.43˚C/W
1
0.1
0.01
Single Pulse
100 1000
µ
10
1 m
10 m
100 m
1
10
100
µ
PW - Pulse Width - s
3
Data Sheet D14656EJ4V0DS
2SJ598
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
–50
–40
–30
–20
–10
0
–100
–10
V
GS = –10 V
TA
= −55˚C
25˚C
–1
–4.0 V
75˚C
150˚C
–0.1
–0.01
V
DS = –10 V
Pulsed
–4
Pulsed
–8
–10
0
–2
–4
–6
–5
–1
–2
–3
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
100
10
200
Pulsed
150
100
50
T
A
= 150˚C
75˚C
I = –6 A
D
1
25˚C
−50˚C
0.1
VDS = –10 V
Pulsed
0.01
0
–0.01
–0.1
0
–5
–10
–15
–20
–1
–10
–100
I
D - Drain Current - A
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
–4.0
–3.0
300
200
100
0
V
DS = –10 V
Pulsed
I
D
= –1 mA
V
GS = –4.0 V
–4.5 V
–10 V
–2.0
–1.0
0
–0.1
–1
–10
–100
–50
0
50
100
150
ID - Drain Current - A
Tch - Channel Temperature - ˚C
4
Data Sheet D14656EJ4V0DS
2SJ598
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
–100
300
Pulsed
Pulsed
250
200
150
100
50
–10
–1
VGS = –10 V
VGS = –4.0 V
0 V
–10 V
–0.1
ID = –6 A
150
0
–0.01
0
–1.5
–1.0
- Source to Drain Voltage - V
–0.5
100
0
50
−50
V
SD
Tch - Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
10000
1000
1000
V
DD = –30V
V
GS = 0 V
R
G
= 0 Ω
f = 1 MHz
V
GS = –10 V
100
10
1
C
iss
t
d(off)
t
f
100
10
t
d(on)
C
oss
rss
t
r
C
–0.1
–1
–10
–100
–0.1
–1
–10
–100
I
D
- Drain Current - A
V
DS - Drain to Source Voltage - V
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
1000
100
–60
–50
–40
–30
–20
–10
0
–12
–10
–8
–6
–4
–2
0
µ
di/dt = 100 A/ s
GS = 0 V
I = –12 A
D
V
V
GS
V
DD = –48 V
–30 V
–12 V
10
1
V
DS
0.1
1
10
100
2
4
6
8
10 12
14 16
0
Q
G
- Gate Charge - nC
I
F
- Drain Current - A
5
Data Sheet D14656EJ4V0DS
2SJ598
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
–100
–10
160
140
120
100
80
V
R
V
DD = –30 V
= 25 Ω
GS = –20 → 0 V
G
I
AS ≤ –12 A
I
AS = –12A
EAS
=
14.4 mJ
60
–1
40
V
DD = –30V
= 25 Ω
GS = –20→0 V
20
R
G
V
–0.1
0
10
µ
100
µ
1m
10m
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
L - Inductive Load - H
6
Data Sheet D14656EJ4V0DS
2SJ598
PACKAGE DRAWINGS (Unit: mm)
1) TO-251 (MP-3)
2) TO-252 (MP-3Z)
2.3 0.2
0.5 0.1
6.5 0.2
5.0 0.2
4
6.5 0.2
2.3 0.2
0.5 0.1
5.0 0.2
4
1
2
3
1
2
3
1.1 0.2
0.9
0.8
1.1 0.2
MAX. MAX.
2.3 2.3
0.5 +−00..12
0.5 +−00..21
0.8
1. Gate
2.3 2.3
2. Drain
3. Source
4. Fin (Drain)
1. Gate
2. Drain
3. Source
4. Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
7
Data Sheet D14656EJ4V0DS
2SJ598
•
The information in this document is current as of August, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
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•
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M8E 02. 11-1
相关型号:
2SJ599(0)-Z-E1-AZ
Pch Single Power Mosfet -60V -20A 75Mohm Mp-3Z/To-252, MP-3Z, /Embossed Tape
RENESAS
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NEC
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