MP6401DQT-33BD3 [MPS]

300mA LDO Linear Regulator with Integrated Reset Circuit; 300毫安LDO线性稳压器,集成了复位电路
MP6401DQT-33BD3
型号: MP6401DQT-33BD3
厂家: MONOLITHIC POWER SYSTEMS    MONOLITHIC POWER SYSTEMS
描述:

300mA LDO Linear Regulator with Integrated Reset Circuit
300毫安LDO线性稳压器,集成了复位电路

稳压器 复位电路
文件: 总16页 (文件大小:318K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MP6401  
300mA LDO Linear Regulator with  
Integrated Reset Circuit  
The Future of Analog IC Technology  
DESCRIPTION  
FEATURES  
The MP6401 combines a low-dropout linear  
regulator with an integrated reset circuit. It  
operates from a 2.5V to 5.5V input voltage and  
regulates the output voltage with 2% accuracy  
at 1.8V, 2.5V, 3.3V or adjustable value. It  
delivers up to 300mA of load current. By  
combining an LDO linear regulator with a reset  
circuit, these products can reduce cost and save  
space in compact portable devices such as cell  
phones, smart phones, PDAs, PMPs, and  
portable GPS devices.  
The MP6401 provides a push-pull, active-low  
that asserts when the regulator output voltage  
drops below the microprocessor supply  
threshold (-7.5% or -12.5% of nominal output  
voltage). Four reset delay time, 3.125ms, 25ms,  
200ms and 1580ms can be selected. The  
MP6401 is available in 3mmx3mm TQFN8,  
2mmx2mm TQFN6 and TSOT packages and is  
specified for operation from -40°C to 85°C.  
Low Quiescent Current of 80μA for Battery  
Powered Equipment  
Low 114mV Dropout at 300mA Output  
±2Accurate Output Voltage  
Fixed Output Voltage Options of 1.8V, 2.5V  
or 3.3V  
Adjustable Output Voltage from 1.229V to  
5V Using an External Resistor Divider  
15μVRMS Ultra Low Noise Output  
PSRR: 57dB at 1kHz  
Input Reverse Current, Thermal and  
Short-Circuit Protection  
Microprocessor Reset with Four Delay time  
Options  
Push-Pull  
RESET  
APPLICATIONS  
Smart Phone and Cell Phone  
Portable GPS Devices  
Wireless Devices  
PDA and PMP  
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green  
status, please visit MPS website under Quality Assurance. “MPS” and “The  
Future of Analog IC Technology” are Registered Trademarks of Monolithic  
Power Systems, Inc.  
TYPICAL APPLICATION  
2.5V to 5.5V  
IN  
V
I/O  
OUT  
MP6401  
ADJ  
C
IN  
R1  
uP  
EN  
RESET  
GND  
RESET  
GND  
C
OUT  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
1
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
ORDERING INFORMATION  
Free Air Temperature  
Part Number*  
Package  
Top Marking  
(TA)  
MP6401DQT-18AD3  
MP6401DQT-18BD3  
MP6401DQT-25AD3  
MP6401DQT-25BD3  
MP6401DQT-33BD3  
MP6401DGT-18AD3  
MP6401DGT-18BD3  
MP6401DGT-25AD3  
MP6401DGT-25BD3  
MP6401DGT-33BD3  
MP6401DJ-18AD3  
MP6401DJ-18BD3  
MP6401DJ-25AD3  
MP6401DJ-25BD3  
MP6401DJ-33BD3  
7T  
8T  
5T  
6T  
4T  
7T  
8T  
5T  
6T  
4T  
7T  
8T  
5T  
6T  
4T  
TQFN8 (3mmx3mm)  
–40°C to +85°C  
TQFN6 (2mmx2mm)  
TSOT23-6  
* For other versions, contact factory for availability.  
Note:  
MP6401DQT  
_ _ _ D _ -LFZ  
DG  
DJ  
}
Reset Delay Time (Table 3)  
Reset Threshold Accuracy (Table 2)  
Output Voltage (Table 1)  
Package  
Temperature  
Table 1—Output Voltage Suffix Guide  
Suffix  
18  
25  
Output Voltage  
1.8  
2.5  
3.3  
33  
Table 2—Reset Threshold Accuracy  
Suffix  
Vout Reset Threshold (%)  
A
B
-7.5%  
-12.5%  
Table 3—Reset Delay Time Guide  
Suffix  
Typical Reset Delay Time (ms)  
D1  
D2  
D3  
D4  
3.125  
25  
200  
1580  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
2
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
PACKAGE REFERENCE  
TOP VIEW  
TOP VIEW  
TOP VIEW  
8
7
6
5
IN  
IN  
1
2
3
4
OUT  
EN  
GND  
IN  
1
2
3
6
5
4
RESET  
ADJ  
IN  
GND  
EN  
1
2
3
6
5
4
OUT  
OUT  
ADJ  
GND  
EN  
ADJ  
RESET  
OUT  
RESET  
TSOT23-6  
TQFN8 (3mm x 3mm)  
TQFN6 (2mm x 2mm)  
ABSOLUTE MAXIMUM RATINGS (1)  
Thermal Resistance (4)  
θJA  
θJC  
TQFN8 (3mm x 3mm) ...........48 ...... 11...°C/W  
TQFN6 (2mm x 2mm) ...........80 ...... 16...°C/W  
TSOT .....................................220 .... 110..°C/W  
IN, EN, OUT.................................–0.3V to + 6 V  
ADJ..................................................0.3V to 6V  
RESET.............................................0.3V to 6V  
(2)  
Continuous Power Dissipation. (TA = +25°C)  
Notes:  
TQFN8 (3mm x 3mm) .............................. 2.6W  
TQFN6 (2mm x 2mm) ............................ 1.56W  
TSOT ....................................................... 0.57W  
Junction Temperature...............................150°C  
Lead Temperature ....................................260°C  
Storage Temperature.............. –65°C to +150°C  
Recommended Operating Conditions (3)  
Supply Voltage VIN ..........................2.5V to 5.5V  
Operating Junct. Temp (TJ)..... –40°C to +125°C  
1) Exceeding these ratings may damage the device.  
2) The maximum allowable power dissipation is a function of the  
maximum  
junction  
temperature  
TJ  
(MAX),  
the  
junction-to-ambient thermal resistance θJA, and the ambient  
temperature TA. The maximum allowable continuous power  
dissipation at any ambient temperature is calculated by PD  
(MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable  
power dissipation will cause excessive die temperature, and  
the regulator will go into thermal shutdown. Internal thermal  
shutdown circuitry protects the device from permanent  
damage. Thermal shutdown engages at TJ=150oC(TYP) and  
disengages at TJ=130oC(TYP)  
3) The device is not guaranteed to function outside of its  
operating conditions.  
4) Measured on JESD51-7 4-layer board.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
3
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
ELECTRICAL CHARACTERISTICS  
VIN = (VOUT + 0.5V) or +2.5V, whichever is greater, COUT = 3.3µF. Typical Value at TA = +25°C unless  
otherwise noted.  
Parameter  
Symbol Condition  
Min  
2.5  
1.85  
Typ  
Max  
5.5  
2.2  
Unit  
V
V
Input Supply Range  
Input Undervoltage Lockout  
Hysteresis of UVLO  
VIN  
VUVLO  
VHYS  
VIN falling  
2.05  
190  
mV  
Supply  
Current)  
Current (Ground  
IQ  
IOUT = 0  
80  
155  
1
μA  
μA  
Shutdown Supply Current  
Regulation Circuit  
Output Current  
Output Voltage Accuracy  
(Fixed Output Voltage)  
Adjustable Output Voltage  
Range  
ISHDN  
TA=+25°C  
0.1  
300  
-2  
mA  
%
1mA IOUT 300mA  
+2  
VADJ  
5
V
ADJ Reference Voltage  
ADJ Threshold  
ADJ Input Leakage Current  
VADJ  
1.205  
1.229  
250  
±20  
1.253  
V
mV  
nA  
IADJ  
VADJ = 0, +1.2V  
±100  
220  
Dropout Voltage (Fixed  
Output Voltage) (5)  
VDO  
VOUT = +3.3V, IOUT = 300mA  
114  
mV  
Short Current Limit  
In Regulation Current Limit  
VIN 2.5V  
VIN 2.5V  
375  
500  
mA  
mA  
Input Reverse Leakage  
VIN = 4V, VOUT = 5V, EN  
deasserted, TA=+25°C  
Current  
(OUT  
to  
IN  
0.01  
1
μA  
Leakage Current)  
EN Input Low Voltage  
EN Input High Voltage  
EN Input Current  
Thermal-Shutdown  
Temperature  
VIL  
VIH  
0.3VIN  
+1  
V
V
μA  
0.7Vin  
-1  
EN= VIN or GND, TA=+25°C  
0.1  
TSHDN  
150  
°C  
°C  
Thermal-Shutdown  
Hysteresis  
TSHDN  
20  
V
I
OUT=1.5V, 2.5V VIN 5.5V,  
OUT = 10mA  
Line Regulation  
Load Regulation  
0.02  
%/V  
VOUT = 1.5V, VIN = 2.5V,  
0.1  
15  
%
1mA IOUT 150mA  
10Hz to 100kHz, CIN = 0.1µF,  
Output Voltage Noise  
µVRMS  
IOUT = 100mA,VOUT = 1.5V  
Reset Circuit  
MP6401_ _ - _ _ AD_  
MP6401_ _ - _ _ BD_  
90  
85  
92.5  
87.5  
95  
90  
%
VOUT  
VOUT Reset Threshold  
VOUT to Reset Delay  
VTHOUT  
30  
3.125  
25  
μs  
D1  
D2  
2.2  
17.5  
4.0  
32.5  
Reset Delay Time  
Td  
ms  
D3  
D4  
140  
200  
260  
1106  
1580  
2054  
MP6401 Rev. 1.0  
www.MonolithicPower.com  
4
9/7/2012  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
ELECTRICAL CHARACTERISTICS (continued)  
VIN = (VOUT + 0.5V) or +2.5V, whichever is greater, COUT = 3.3µF. Typical Value at TA = +25°C unless  
otherwise noted.  
Parameter  
Symbol Condition  
VOUT 1.0V, ISINK = 50µA,  
asserted  
Min  
Typ  
Max  
Unit  
0.3  
RESET  
VOUT 1.5V, ISINK = 3.2mA,  
asserted  
VOL  
RESET Output Voltage  
Push-Pull  
V
0.4  
RESET  
VOUT 2.0V, ISOURCE = 500µA,  
deasserted  
VOH  
0.8VOUT  
RESET  
Notes:  
5) Dropout Voltage is defined as the input to output differential when the output voltage drops 100mV below its nominal value.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
5
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
PIN FUNCTIONS  
TQFN8 TQFN6 TSOT  
Name Description  
IN Supply input pin.  
GND Ground.  
Pin #  
Pin# Pin#  
1
2
3
4
1
3
2
3
2
1
EN  
Enable (Active High). Connect EN to IN generally. Don’t float EN pin.  
Push-pull . It asserts when the OUT voltage drops below its  
RESET  
5
6
4
6
RESET  
threshold. When OUT voltage recover,  
time (four options).  
deasserts after a fix delay  
RESET  
Mode selector input. When ADJ is connected to the tap of an external resistor  
divider from the OUT to GND, the OUT voltage is adjustable. When ADJ is  
connected to GND, a preset output voltage is selected.  
5
6
5
4
ADJ  
7
8
OUT Regulator output pin.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
6
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
TYPICAL PERFORMANCE CHARACTERISTICS  
VIN=5V, VOUT=3.3V, COUT=3.3µF, TA= -40°C to +85°C, Typical values are at TA=+25°C, unless  
otherwise noted.  
Supply Current vs.  
Input Votage  
Supply Current vs.  
Input Votage  
Supply Current vs.  
Input Votage  
ADJ=GND, I  
=300mA  
V =1.5V, I  
=300mA  
OUT  
ADJ=GND, I  
=0  
OUT  
O
OUT  
100  
85  
70  
55  
40  
460  
430  
400  
370  
340  
460  
430  
400  
370  
340  
3.8  
4.2  
4.6  
5
5.4  
3.8  
4.2  
4.6  
5
5.4  
2.5  
3.5  
4.5  
5.5  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
Supply Current vs.  
Input Votage  
Dropout Voltage vs.  
Load Current  
PSRR vs. Frequency  
I
=300mA  
OUT  
V =1.5V, I  
=0  
OUT  
O
100  
85  
70  
55  
40  
160  
140  
120  
100  
80  
70  
60  
50  
40  
30  
20  
10  
0
60  
40  
20  
0
2.5  
3.5  
4.5  
5.5  
0
50 100 150 200 250 300  
LOAD CURRENT (mA)  
2
3
4
5
6
10  
10  
10  
10  
10  
10  
INPUT VOLTAGE (V)  
FREQUENCY (Hz)  
Transient Duration  
vs. RESET Threshold  
Overdrive  
Output Voltage Accuray  
vs. Temperature  
Region of Stable Cout ESR  
vs. Load Current  
3
2.5  
2
0.5  
0.3  
120  
90  
60  
30  
0
RESET ASSERTS ABOVE  
THIS LINE  
Unstable Region  
0.1  
1.5  
1
-0.1  
-0.3  
-0.5  
Stable Region  
0.5  
0
1
10  
100  
0
50 100 150 200 250 300  
LOAD CURRENT (mA)  
-40 -20  
0
20  
40  
60 80  
TEMPERATURE (OC)  
RESET THRESHOLD OVERDRIVE (mV)  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
7
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
VIN=5V, VOUT=3.3V, COUT=3.3μF, TA= -40°C to +85°C, Typical values are at TA=+25°C, unless  
otherwise noted.  
V
OUT  
2V/div.  
V
RESET  
2V/div.  
V
IN  
5V/div.  
Reset Response To V Rising  
IN  
ADJ=GND,I  
= 0  
OUT  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
8
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
BLOCK DIAGRAM  
IN  
EN  
EN  
--  
+
Vref1  
Driver  
EA  
Reverse  
Current  
Protection  
Current Limit  
ADJ  
OUT  
--  
+
RESET  
Vref2  
RESET  
Mode  
Selector  
Comparator  
--  
+
Logic  
Thermal  
Protection  
Vref3  
Figure 1—MP6401 Block Diagram  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
9
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
TIMING DIAGRAM  
VIN  
5V  
0
t
Figure 2—RESET Timing Diagram  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
10  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
OPERATION  
The MP6401 integrates a low noise, low dropout,  
low quiescent current linear regulator and a  
microprocessor reset circuit. It operates from a  
2.5V to 5.5V input voltage and regulates the fixed  
output voltage with 2% accuracy at 1.8V, 2.5V,  
3.3V or adjustable value. The MP6401 can supply  
to 300mA of load current. The internal reset  
circuit is used to monitor the regulator output  
EN Shutdown  
The MP6401 can be switched ON or OFF by a  
logic input at the EN pin. A high voltage at this pin  
will turn the device on. When the EN pin is low,  
the regulator output is off and the supply current  
is reduced. Generally, the EN pin should be tied  
to IN to keep the regulator output always on. Do  
not float the EN pin.  
voltage. The  
output voltage drops below the standard  
microprocessor supply threshold.  
asserts when the regulator  
RESET  
Reverse Leakage Protection  
An internal circuit monitors VIN and VOUT to control  
the reverse leakage current from OUT to IN.  
While VIN decreases lower than VOUT and EN still  
hold logic high, the monitor circuit turns off the  
pass element and its parasitic diode. Typically the  
reverse leakage current through pass element  
Linear Regulator  
The MP6401 can output a fixed voltage (1.8V,  
2.5V, 3.3V options) or adjustable voltage which  
ranges from 1.25V to 5V with 2.0% accuracy by  
operating from a +2.5V to +5.5V input. The  
MP6401 can supply up to 300mA of load current.  
When ADJ is connected to GND, a fixed output  
voltage is selected. Connecting ADJ pin to the tap  
of external resistor divider from the OUT to GND,  
adjustable output voltage is selected. The typical  
decreases to 0.1uA.  
deasserts until VIN  
RESET  
returns greater than VOUT and VOUT is higher than  
its preset threshold.  
MP6401 also can work with backup battery at  
OUT after input power supply is removed as  
shown in Fig 4. When input power supply is  
ADJ connection is shown in Fig 3.  
removed,  
asserts. The backup battery  
RESET  
2.5V to 5.5V  
will power the device through two external diodes  
and typically the current from OUT to ground is  
40uA. So, the power supply removing does not  
erase RAM content if the voltage of backup  
battery is greater than memory’s standby  
specification. The backup battery can be replaced  
by a super-cap, while the diode connected with  
battery is changed to a current-limiting resistor.  
IN  
OUT  
MP6401  
R1  
R2  
ADJ  
EN  
GND  
Figure 3—Output Voltage Adjusted with  
Resistor Divider  
Removable  
IN  
MP6401  
OUT  
Reset Function  
3.3uF  
The reset circuit monitors the OUT voltage.  
Backup  
Battery  
uP  
MEMORY  
asserts while OUT voltage falls below its  
RESET  
EN  
threshold. Two OUT voltage thresholds (-7.5%  
and -12.5%) are available. The power-up,  
power-down, and brownout conditions will make  
Figure 4— Maintain Memory with Backup  
Battery  
Current Limit  
asserted. So MP6401 monitor circuit  
RESET  
could right control the microprocessor.  
RESET  
The MP6401 includes a current limit structure  
which monitors and controls pass element gate  
voltage limiting the guaranteed maximum output  
current to 500mA.  
asserts when the input and output voltage below  
their thresholds. asserts when EN is a  
RESET  
low logic. When the assert trigger condition is  
removed, will deassert after a fixed delay  
RESET  
time. Four options of reset delay-time (see Table  
3) can be selected.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
11  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
Thermal Shutdown  
Thermal protection turns off the pass element  
when the junction temperature exceeds +150ºC,  
allowing to cool the IC. When the IC’s junction  
temperature drops by 20ºC, the pass element will  
be turned on again. Thermal protection limits total  
power dissipation on the MP6401. For reliable  
operation, junction temperature should be limited  
to 125 ºC maximum.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
12  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
APPLICATION INFORMATION  
Adjustable Regulator Output  
Output Capacitor Selection  
The OUT voltage of MP6401 has two modes  
available (fixed and adjustable output voltage).  
When ADJ pin is connected to GND, the regulator  
works in fixed voltage mode. The regulator output  
voltage will equal to preset voltage (1.8V, 2.5V or  
3.3V options). In fixed voltage mode, the  
impedance between ADJ and ground should  
always be less than 50k. Generally, ADJ is  
connected directly to ground.  
The MP6401 is designed specifically to work with  
very low ESR ceramic output capacitor 3.3uF  
(min). For performance consideration, a large  
ceramic capacitor such as 10uF is better. X7R or  
X5R capacitor dielectric is recommended.  
OUT Voltage Transient Immunity  
The MP6401 can be immune to OUT pin short  
negative transient. Typically, the immune duration  
is 60us with 10mV overdriving. A shorter negative  
When the ADJ pin is connected to the tap of an  
external resistor divider, the regulator works in  
adjustable voltage mode as shown in Fig 3. The  
output voltage is selected by resistor divider, thus  
transient can not make the  
output assert.  
RESET  
R1 + R2  
VOUT = 1.229×  
R2  
In adjustable voltage mode, R2 equal to 13kis  
recommended as a good tradeoff among stability,  
accuracy and high-frequency PSRR. R2 should  
be not greater than 100k.  
Power Dissipation  
The power dissipation for any package depends  
on the thermal resistance of the case and circuit  
board, the temperature difference between the  
junction and ambient air, and the rate of airflow.  
The power dissipation across the device can be  
represented by the equation:  
P = (VIN - VOUT) ×IOUT  
The allowable power dissipation can be  
calculated using the following equation:  
PD (MAX) = (TJ (MAX)-TA)/θJA  
Where (TJ(MAX)-TA) is the temperature difference  
between the junction and the ambient  
environment, θJA is the thermal resistance from  
the junction to the ambient environment.  
Connecting the GND pin of MP6401 to ground  
using a large pad or ground plane helps to  
channel heat away.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
13  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
PACKAGE INFORMATION  
TQFN8 (3mm x 3mm)  
2.90  
3.10  
0.30  
0.50  
1.45  
1.75  
PIN 1 ID  
SEE DETAIL A  
PIN 1 ID  
MARKING  
0.20  
0.30  
8
1
4
2.25  
2.55  
2.90  
3.10  
0.65  
BSC  
PIN 1 ID  
INDEX AREA  
5
TOP VIEW  
BOTTOM VIEW  
PIN 1 ID OPTION A  
0.30x45º TYP.  
PIN 1 ID OPTION B  
R0.20 TYP.  
0.70  
0.80  
0.20 REF  
0.00  
0.05  
SIDE VIEW  
DETAIL A  
2.90  
1.70  
0.70  
0.25  
0.65  
2.50  
RECOMMENDED LAND PATTERN  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
14  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
TQFN6 (2mm x 2mm)  
1.90  
2.10  
0.30  
0.40  
0.65  
0.85  
PIN 1 ID  
SEE DETAIL A  
PIN 1 ID  
MARKING  
0.20  
0.30  
1
3
6
4
1.25  
1.45  
1.90  
2.10  
PIN 1 ID  
INDEX AREA  
0.65  
BSC  
TOP VIEW  
BOTTOM VIEW  
PIN 1 ID OPTION A  
0.30x45º TYP.  
PIN 1 ID OPTION B  
R0.20 TYP.  
0.70  
0.80  
0.20 REF  
0.00  
0.05  
SIDE VIEW  
DETAIL A  
1.90  
0.70  
NOTE:  
0.70  
0.25  
1) ALL DIMENSIONS ARE IN MILLIMETERS.  
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.  
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.  
4) JEDEC REFERENCE IS MO-229, VARIATION WCCC.  
5) DRAWING IS NOT TO SCALE.  
1.40  
0.65  
RECOMMENDED LAND PATTERN  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
15  
MP6401 – 300mA LDO LINEAR REGULATOR WITH INTEGRATED RESET IC  
TSOT23-6  
0.95  
BSC  
0.60  
TYP  
2.80  
3.00  
6
4
1.20  
TYP  
See Note 7  
EXAMPLE  
TOP MARK  
1.50  
1.70  
2.60  
TYP  
2.60  
3.00  
AAAA  
PIN 1  
1
3
TOP VIEW  
RECOMMENDED LAND PATTERN  
0.84  
0.90  
1.00 MAX  
SEATING PLANE  
0.09  
0.20  
0.30  
0.50  
0.00  
0.10  
0.95 BSC  
SEE DETAIL "A"  
FRONT VIEW  
SIDE VIEW  
NOTE:  
1) ALL DIMENSIONS ARE IN MILLIMETERS.  
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,  
PROTRUSION OR GATE BURR.  
GAUGE PLANE  
0.25 BSC  
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH  
OR PROTRUSION.  
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)  
SHALL BE 0.10 MILLIMETERS MAX.  
5) DRAWING CONFORMS TO JEDEC MO-193, VARIATION AB.  
6) DRAWING IS NOT TO SCALE.  
0.30  
0.50  
0o-8o  
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM  
LEFT TO RIGHT, (SEE EXAMPLE TOP MARK)  
DETAIL  
A
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third  
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not  
assume any legal responsibility for any said applications.  
MP6401 Rev. 1.0  
9/7/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
16  

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