MP6412GQGU-Z [MPS]
Peripheral Driver,;
| 型号： | MP6412GQGU-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Peripheral Driver, 开关 |
| 文件： | 总19页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP6412
DESCRIPTION
FEATURES
The MP6412 is a load-switch controller used to
turn the main-power P-channel MOSFET on
and off. The MP6412 has a 2.2V to 12V
operating input voltage range. The MP6412 is a
space-saving solution for smartphones, tablets,
and other portable device applications.
VIN Range from 2.2V to 12V
P-MOSFET Gate Driver
Auto 150Ω Output Discharge
<2µA Quiescent Current
<1µA Shipping Mode Current
Factory-Fixed Reset Delay
ESD HBM 2kV
Available in a Space-Saving UTQFN-10
(1.4mmx1.8mm) Package
The MP6412 is equipped with reset and power
sequence
functions
with
a
factory-
programmable delay timer. The reset and
power sequence are controlled by the
RST0/RST1 and OFF signals. The MP6412
also has a system discharge path, shipping
mode and charger insert detection feature.
APPLICATIONS
Mobile Phones
Portable/Handheld Devices
Wearable Devices
The MP6412 is available in a UTQFN-10
(1.4mmx1.8mm) package.
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
TYPICAL APPLICATION
MP6412 Rev. 1.0
1/8/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
1
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP6412GQGU
UTQFN-10 (1.4mmx1.8mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP6412GQGU–Z).
TOP MARKING
FV: Product code of MP6412GQGU
LL: Lot number
PACKAGE REFERENCE
TOP VIEW
UTQFN-10 (1.4mmx1.8mm)
MP6412 Rev. 1.0
1/8/2019
www.MonolithicPower.com
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PIN FUNCTIONS
Pin #
Name
Description
Path 1 discharge pin. DCHG1 begins to discharge when the MP6412 enters
RESET mode and TAIN is low.
1
DCHG1
Charger insert detection pin. TAIN pulls down to GND internally through a resistor.
When a charger is inserted, TAIN is pulled high by an external charger.
2
TAIN
3
4
5
VIN
Input power supply.
RST0
RST1
Reset input 0. RST0 is active low. Do not float RST0.
Reset input 1. RST1 is active low. Do not float RST1.
Function to turn off external P-FET to enter shipping mode. OFF pulls down to
GND internally through a resistor.
6
7
8
OFF
GND
SRO
Ground.
System reset output signal. SRO is the push-pull output. SRO has an external P-
FET gate driver.
System reset output negative signal. nSRO is an open-drain output. When SRO is
low, the open-drain MOSFET is off. When SRO is high, the open-drain MOSFET is
on. nSRO is floated in shipping mode.
9
nSRO
Path 0 discharge pin. DCHG0 begins to discharge when the MP6412 enters
RESET mode and TAIN is low.
10
DCHG0
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ........................ -0.3V to 14V
Thermal Resistance (4)
UTQFN-10 (1.4mmx1.8mm).... 140 .. 30 ...°C/W
θJA θJC
V
V
V
RST0/RST1 ........................................... -0.3V to 6V
OFF ................................................... -0.3V to 6V
TAIN, VDCHG0/1, VSRO, VnSRO............... -0.3V to 14V
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
Junction temperature................................ 150°C
Lead temperature...................................... 260°C
(2)
Continuous power dissipation (TA = +25°C)
.....................................................................0.9W
Storage temperature.................-65°C to +150°C
(MAX)-TA)/θJA
. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
Recommended Operating Conditions (3)
Supply voltage (VIN) ......................... 2.2V to 12V
VRST0/RST1 ............................................ 0V to 5.5V
V
V
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB. The value of θJA given
in this table is only valid for comparison with other packages
and cannot be used for design purposes. These values are
calculated in accordance with JESD51-7, and simulated on a
specified JEDEC board. They do not represent the
performance obtained in an actual application.
OFF .................................................... 0V to 5.5V
TAIN, VDCHG0, VDCHG1 ............................ 0V to 12V
Operating junction temp. (TJ)....-40°C to +125°C
MP6412 Rev. 1.0
1/8/2019
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ELECTRICAL CHARACTERISTICS
VIN = 3.6V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C. The limit over temperature is
guaranteed by characterization, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Input and Supply Voltage Range
Input voltage
VIN
2.2
12
V
Supply Current
VIN = 3.6V, load switch off,
shipping mode
Shipping mode current
IOFF
ION1
0.75
1.5
2
µA
µA
VIN = 3.6V, load switch on, no
load, no action assert
VIN = 3.6V, load switch on, no
load, action assert to turn
OSC on
On state current
ION2
10
µA
Gate Driver
SRO rising time
SRO falling time
TRise
TFall
VIN = 4V, Qg = 20nC
VIN = 4V, Qg = 20nC
Between VIN good and SRO
starting to fall
1
1
2
2
3
3
ms
ms
SRO rising delay (5)
TSRO
1
2
3
ms
SRO logic high level
SRO logic low level
VIN-0.3
V
V
0.3
Force 1mA current
VDCH0/1 = 4V
70
150
5
120
ꢀ
ꢀ
ms
VDCHG0/1 discharge resistance
Discharge delay (5)
TDD
4
6
Under-Voltage Protection (UVP)
VIN under-voltage lockout
threshold
UVLO hysteresis (6)
VIN_UVLO
VUVLOHYS
1.43
500
V
mV
RST0/RST1/OFF Logic (Input)
RST0/1 high level
RST0/1 low level
OFF high level
VH
VL
VHOFF
VLOFF
1
1
V
V
V
0.4
0.4
OFF low level
V
OFF pull-down resistor
RST0/RST1 leakage current
1
Mꢀ
nA
ms
µs
VIN = VRST0 = VRST1 = 3.6V
RST0, RST1, TAIN
OFF
150
TDG1
TDG2
10
250
Debounce time (5)
nSRO Logic (Open-Drain Output)
High level
V
IN = 3.3V, pull up VIN
VIN*0.8
VIN
50
V
V
through external 100kꢀ
Sink 1mA
VIN = 3.3V, pull up VIN
through external 100kꢀ
Low level
0.4
nSRO leakage current/logic high
nA
TAIN Logic (Input)
TAIN rising
TAIN hysteresis
TAIN confirm delay (5)
TAIN internal pull-down resistor
2.8
40
3.15
100
50
3.5
60
V
mV
ms
Mꢀ
T7
2
MP6412 Rev. 1.0
1/8/2019
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C. The limit over temperature is
guaranteed by characterization, unless otherwise noted.
Parameters
RESET Time (5)
Symbol Condition
Min
Typ
Max
Units
Power RESET entry time (5)
Power RESET off time (5)
Turn-off response time (5)
Turn-off confirm cycle (6)
Turn-off confirm time (5)
Turn-off delay time (5)
Turn-on response time (5)
SRO pull-up current
T1
T2
T3
8
0.32
1
10
0.4
1.5
5
100
15
2
12
0.48
2
s
s
ms
T4
T5
T6
80
12
1.6
120
18
2.4
ms
s
s
VIN = 4V
1.3
µA
NOTES:
5) Guaranteed by correlation.
6) Guaranteed by engineering sample test, not tested in production.
MP6412 Rev. 1.0
1/8/2019
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5
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6V, TA = 25°C, unless otherwise noted.
On-State Current vs. Temperature
VIN = 2.2V
On-State Current vs. Temperature
VIN = 3.6V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (℃)
TEMPERATURE (℃)
On-State Current vs. Temperature
VIN = 12V
UVLO Rising Voltage vs. Temperature
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (℃)
TEMPERATURE (℃)
TAIN Rising Voltage vs. Temperature
On-State Current vs. VIN
3.5
1.4
1.2
1
3
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
-50
0
50
100
150
0
5
10
15
VIN (V)
TEMPERATURE (℃)
MP6412 Rev. 1.0
1/8/2019
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3.6V, TA = 25°C, unless otherwise noted.
Reset Function
Reset Function (RST1 First)
CH1: VOUT
2V/div.
CH1: VOUT
2V/div.
CH2: RST0
2V/div.
CH2: RST0
2V/div.
CH3: RST1
2V/div.
CH3: RST1
2V/div.
CH4: SRO
2V/div.
CH4: SRO
2V/div.
2s/div.
2s/div.
Reset Function (RST0 First)
Shipping Mode Enter
CH1: VOUT
2V/div.
CH1: VOUT
2V/div.
CH2: OFF
2V/div.
CH3: RST0
5V/div.
CH2: RST0
2V/div.
CH3: RST1
2V/div.
CH4: TAIN
2V/div.
CH4: SRO
2V/div.
2s/div.
5s/div.
Shipping Mode Exit with TAIN
Shipping Mode Exit with RST0
CH1: VOUT
2V/div.
CH1: VOUT
2V/div.
CH2: OFF
2V/div.
CH2: OFF
2V/div.
CH3: RST0
5V/div.
CH3: RST0
2V/div.
CH4: TAIN
2V/div.
CH4: TAIN
2V/div.
5s/div.
5s/div.
MP6412 Rev. 1.0
1/8/2019
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3.6V, TA = 25°C, unless otherwise noted.
Start-Up
Shutdown
CH1: VIN
2V/div.
CH1: VIN
2V/div.
CH2: RST0
2V/div.
CH2: RST0
2V/div.
CH4: SRO
1V/div.
CH4: SRO
1V/div.
CH3: RST1
CH3: RST1
2V/div.
2V/div.
100ms/div.
100ms/div.
MP6412 Rev. 1.0
1/8/2019
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BLOCK DIAGRAM
Figure 1: Functional Block Diagram
MP6412 Rev. 1.0
1/8/2019
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OPERATION
The MP6412 is a load-switch controller to turn
the main power P-channel MOSFET on and off.
The MP6412 has a 2.2V to 12V operating input
voltage range. The MP6412 provides a space-
saving solution for smartphones, tablets, and
other portable device applications.
The MP6412 is equipped with reset and power
sequence
functions
with
a
factory-
programmable delay timer. The reset and
power sequence are controlled by the
RST0/RST1 and OFF signals. For mobile
applications, the MP6412 has two discharge
paths and a charger insert detection feature.
Reset Function (RESET)
Figure 2: RESET Procedure
The MP6412 can reset the system by turning
off the external power MOSFET (load switch) if
needed. This action clears the current status
and restarts to the initial status by cutting off the
power supply of the down-stream system. Enter
the RESET function by pulling both RST0 and
RST1 down to logic low for 10s (Note that T2’ =
T2 + TDD x 2).
Figure 2 and Figure 3 show the waveforms
during a T2’ RESET action.
To avoid an erroneous RST0/1 trigger, a
debounce time (TDG1) can be implemented. If
the logic glitch duration is less than TDG1, the
logic glitch is ignored (see Figure 4).
In normal operation, if the MP6412 detects that
both RST0 and RST1 are low for 10s, the
MP6412 turns off the load switch for T2’ (400 +
10ms) and restarts it. During the 400ms off time,
DCHG0 and DCHG1 turn on their respective
discharge path to pull down the VOUT and
system voltage to clear out the current status.
The RESET function can be activated once
RST0 and RST1 are both active. The next
RESET function is active after the RST0 or
RST1 logic changes again (See Figure 5 and
Figure 6).
Figure 3: SRO and Discharge Procedure
Figure 4: Debounce Procedure
MP6412 Rev. 1.0
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Figure 5: Multiple RST0 Reset
Figure 6: Multiple RST1 Reset
During T1 (after RST0/1 both drop low) and T2’
In normal status, a specific OFF pin signal (on
time more than T3, off time more than T3, repeat
five cycles in 100ms) makes the MP6412 turn
off the load switch and enter shipping mode.
Afterward, nSRO is floated (see Figure 7). The
discharge function is not active in this mode.
(if a RESET action occurs), the RESET action
has the highest priority. This action masks the
high TAIN logic or shipping mode trigger signal.
During T1 and its follow RESET period, all
signals are ignored. Refer to the Enter/Exit
Shipping Mode sections on page 11 and page
13.
If the enter shipping mode signal is confirmed,
all signals are ignored during T5.
Enter Shipping Mode
To avoid an erroneous OFF trigger, a debounce
time (TDG2) can be implemented. If the logic
glitch duration is less than TDG2, the logic
glitch will be ignored (see Figure 8).
The MP6412 can fully turn off the load switch to
achieve a very small shutdown current. In this
mode, the MP6412 cuts off the battery from the
system. Therefore, the battery energy can be
stored for a long time due to the low
consumption current of the MP6412 in shipping
mode.
The OFF signal has lower priority than RST0/1
signal. OFF is terminated if RST0/1 low occurs
(see Figure 9).
MP6412 Rev. 1.0
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Figure 7: Entering Shipping Mode
Figure 8: Cannot Enter Shipping Mode
Figure 9: OFF Priority Procedure
MP6412 Rev. 1.0
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The OFF signal has higher priority than the
TAIN signal. After the OFF signal is confirmed,
the high TAIN signal can exit the MP6412 from
shipping mode (see Figure 10).
Figure 10: OFF Priority Procedure
Exiting Shipping Mode
The MP6412 turns on the load switch when
exiting shipping mode.
make the MP6412 exit shipping mode, but the
MP6412 must confirm the action of TAIN first.
In shipping mode, when the RST0 signal is
pulled down for 2s and VIN is higher than its
under-voltage lockout (UVLO) threshold, the
MP6412 exits shipping mode and turns on the
load switch.
Figure 12: TAIN Procedure
When the MP6412 is in shipping mode, a RST0
or TAIN input is required to exit shipping mode.
The RST0 input requires a logic change to
enable the confirmation sequence. If RST0 is
dead low when the OFF confirm time is
triggered, the MP6412 does not exit shipping
mode (see Figure 13). If TAIN is dead high
when the OFF confirm time is triggered, the
shipping mode logic cannot be masked (see
Figure 14).
Figure 11: Shipping Mode Exit Procedure
In addition to RST0, a high TAIN signal can
also make the MP6412 exit shipping mode.
TAIN is connected to the power jack through a
100kꢀ resistor, typically. When a charger is
inserted, TAIN monitors a high logic, which can
also make the MP6412 exit shipping mode.
Figure 12 shows the MP6412 in shipping mode
initially. TAIN and RST0 can both be used to
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Figure 13: RST0/1 Not Exiting Shipping
Figure 14: TAIN Cycle Exiting Shipping
TAIN Feature
Where V(TAIN) is the TAIN voltage, V(Charger)
is the external charger voltage, RExt is the
external resistor, and RInt is the internal 2Mꢀ
resistor.
TAIN is connected to an external charger
through a 100kꢀ resistor. TAIN has an internal
2Mꢀ pull-down resistor to ground. The external
and internal resistors form a resistor-divider
circuit. The TAIN voltage can be calculated with
Equation (1):
When the TAIN voltage is higher than 3.3V, it is
treated as an active high logic. If the MP6412 is
in shipping mode, this high logic makes the
MP6412 exit it.
(1)
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Figure 15 shows the TAIN internal ESD
current. The power-on procedure is shown in
Figure 16.
structure, which is equal to a Zener diode.
When VCHG is high (maximum 30V), the ESD
breaks down and clamps the TAIN voltage to
14V. The internal ESD safe current is 1mA to
prevent damage to the ESD Zener diode. For
example, when VCHG is 30V, there is a 16V
voltage between VCHG and TAIN pin, and the
current through the resistor and ESD diode is
160µA.
The power-on procedure is a RESET procedure
and ignores the RST0 and RST1 RESET
signals. To enable a RESET function, the RST0
logic must be changed.
Figure 15: TAIN ESD Structure
Power-On
Figure 16: Power-On Priority
When VIN rises from a very low value to the
MP6412 UVLO, a power-on procedure begins.
The MP6412 turns on the external P-channel
MOSFET (P-FET) softly to prevent inrush
Figure 17: RESET after Power-On
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Conflicts Strategy
Discharge
The MP6412 has two discharge paths
(DCHG0/1) to release system energy during a
RESET action. The DCHG0/1 path is enabled
during T2. These discharge paths are through a
passive resistor. If an external charger is
plugged in, the passive resistor is too large to
pull DCH0/1 low, and the discharge current
generates a high temperature on the IC. A TAIN
high logic disables DCH0/1 immediately under
this situation (see Figure 18 and Table 2).
The MP6412 has different response actions
when RST0/RST1/OFF/TAIN has input voltage.
To prevent input conflicts, refer to Table 1.
Table 1: Signal Priority
Priority
Action
RESET
OFF
1
2
3
TAIN
RESET has the highest priority. The MP6412
only answers the highest priority requirement if
several actions occur at the same time.
If some actions are active at the same time and
one of these actions is confirmed first, the other
actions will be ignored. For example, if the OFF
action is confirmed first, the MP6412 enters
shipping mode after 15s. In this period,
RST0/RST1/TAIN cannot terminate it.
nSRO Function
The nSRO output is an open-drain output. Its
output indicates the main power MOSFET
status. When the main power MOSFET is on, it
output a high logic. Otherwise, it outputs a low
logic. nSRO does not have a soft on/off effect
like SRO. The nSRO signal floats if the MP6412
enters shipping mode.
Figure 18: TAIN Disable Discharge
Table 2: State Change Table
Event 0
VIN
STATE0
Event0
STATE1
Duration
between
state1
STATE2
SRO
For (in
seconds)
RST0
RST1
TAIN
OFF
SRO
nSRO
DCHGx
SRO
nSRO
DCHGx
nSRO
DCHGx
and 2
POR
X
L
L
L
H
H
X
H
L
L
L
X
X
X
H
L
X
X
X
X
X
X
X
0
L
L
L
L
L
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
TSRO
H
L
X
X
TFall
L
L
Open
Open
Open
Open
Open
VIN
VIN
VIN
VIN
VIN
Open
Open
Open
T1
T1
T2’
T2’
RESET
L
Open
Open
Open
Open
L
Open
Open
Open
Open
5
T5
T5
0
0
H
pulse
VIN
X
H
X
5
L
Open
Open
Open
Open
H
Open
Open
pulse
Enter
Sleep
VIN
VIN
VIN
X
X
X
X
X
X
X
X
X
H
L
L
L
L
Open
Open
Open
Open
Open
Open
L
L
L
Open
Open
Open
Open
Open
Open
L
L
L
Open
Open
Open
Open
Open
Open
<5
pulse
VIN
VIN
VIN
H
X
L
X
X
X
L
H
X
X
X
X
H
H
H
Open
Open
Open
Open
Open
Open
H
H
H
Open
Open
Open
Open
Open
Open
H
L
L
Open
Open
Open
Open
Open
Open
Exit
Sleep
T7=50m
T6=2
TFALL
MP6412 Rev. 1.0
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APPLICATION INFORMATION
Selecting the Input Capacitor
Input capacitors are important for protecting the
MP6412 from input voltage spikes when a VIN
hot-plug occurs. 0603 ceramic capacitors with
X5R
or
X7R
dielectrics
are
highly
recommended because of their low ESR and
small temperature coefficients. For most
applications, a 1μF 0603 input capacitor is
sufficient.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For the best results, refer to Figure
19.
Top Layer
Bottom Layer
Figure 19: Recommended Layout
MP6412 Rev. 1.0
1/8/2019
www.MonolithicPower.com
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© 2019 MPS. All Rights Reserved.
17
TYPICAL APPLICATION CIRCUIT
Figure 20: Typical Application Circuit
MP6412 Rev. 1.0
1/8/2019
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© 2019 MPS. All Rights Reserved.
18
PACKAGE INFORMATION
UTQFN-10 (1.4mmx1.8mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP6412 Rev. 1.0
1/8/2019
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
19
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