MP2935ADQK-LF [MPS]
Switching Controller, Current-mode, QFN-40;
| 型号： | MP2935ADQK-LF |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Controller, Current-mode, QFN-40 开关 输出元件 |
| 文件： | 总42页 (文件大小：1038K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2935
4-Phase PWM
Controller for VR12.5 Applications
The Future of Analog IC Technology
FEATURES
DESCRIPTION
VR12.5 compliant
Multi-Phase Operation at up to 2MHz per
Phase
MP2935 is
a
high-efficiency, 4-phase,
synchronous, buck-switching PWM controller
with an SVID interface for high-performance
Intel processors. The multi-phase PWM output
signals can be configured for up to 4-phase
operation with interleaved switching.
Tri-State PWM Outputs for Driving MPS
Intelli-PhaseTM Devices
Power-Saving Modes Maximize Efficiency
During Light Load and Deeper-Sleep
Operation
MP2935 adopts three-logic-level PWM outputs
for enhanced noise immunity and flexible fault
management. Depending on the power states
set by SVID command, the multi-phase channel
can switch between multiphase and single-
phase operation. In addition, MP2935 supports
programmable load-line resistance. As a result,
the output voltage is always optimally
positioned for a load transient.
Active Current Balancing between Output
Phases
Independent Current Limit and Load Line
Setting Inputs for Additional Design
Flexibility
8-bit Digitally Programmable 0V to 3.04V
Output through Serial VID Interface
Overload and Short-Circuit Protection with
Latch-Off Delay
The chip also provides accurate and reliable
short-circuit protection with adjustable current
limit threshold and a delayed VR_RDY output
that is masked during on-the-fly output voltage
changes to eliminate false triggering. MP2935
performance is specified over the junction
temperature range of -10°C to 125°C. The chip
is available in 40-lead QFN package.
Output Current Monitor
Fault Latch Output
Regulator Temperature Monitor
Available in a 6mmx6mm 40-lead QFN
package
APPLICATIONS
Power supplies for next-generation Intel®
processors
All MPS parts are lead-free, halogen free, and adhere to the RoHS
directive. For MPS green status, please visit MPS website under Quality
Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered
Trademarks of Monolithic Power Systems, Inc.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
TYPICAL APPLICATION CIRCUIT
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
2
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
ORDERING INFORMATION
Part Number*
MP2935DQK
MP2935ADQK
Package
Top Marking
MP2935
Junction Temperature (TJ)
-40°C to +125°C
6x6mm QFN40
6x6mm QFN40
MP2935A
-40°C to +125°C
* For Tape & Reel, add suffix –Z (e.g. MP2935DQK–Z).
For RoHS compliant packaging, add suffix –LF (e.g. MP2935DQK–LF–Z)
PACKAGE REFERENCE
TOP VIEW
40
39 38 37 36 35 34 33 32 31
30
1
2
VCLAMP
AAMB
OCPSET
SLOPE
ICCMAX
VCM
OTPD
OTPG
29
28
27
SDIO
3
ALERT#
SCLK
4
5
26
25
GND
VRRDY
VRHOT#
6
24
23
7
CS1
ADDR
TEMP
IMON
8
CS2
22
21
9
CS3
10
CS4
11
12 13 14 15 16 17 18 19 20
Recommended Operating Conditions (3)
VCC...........................................................................4.5V to 5.5V
Operating Junction Temp........ –40°C to +125°C
ABSOLUTE MAXIMUM RATINGS (1)
VCC ..............................................0.3V to +6.5V
VDD.....................................................................–0.3V to +4.0V
GNDSEN ....................................–0.3V to +0.3V
SLOPE ........................................–0.3V to +26V
All Other Pins....................–0.3V to (VCC+0.3V)
Continuous Power Dissipation (TA = +25°C) (2)
................................................................... 3.9W
Junction Temperature...............................150°C
Lead Temperature ...................................260°C
Storage Temperature.............. –65°C to +150°C
Thermal Resistance (4)
6x6 QFN40............................32.......8
θJA
θJC
°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)
=
(TJ(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
3
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 5 V, GNDSEN = GND, EN = VCC, VID = 0.50 V to 3.04 V, Current going into pin is positive.
TA = -10°C to +100°C, unless otherwise noted.
Parameter
Symbol Conditions
Min Typ Max Units
VOLTAGE ERROR AMPLIFIER
Error Amplifier Output
VCOMP
0.75
-0.5
4.6
V
Voltage Range(5)
tA = 25°C. No load, closed-loop, measured
+0.5
%
at VOSEN pin to GNDSEN pin. Active
mode range. VID=1.50V to 3.04V
No load, closed-loop, measured at VOSEN
pin to GNDSEN pin. Active mode range.
VID=1.50V to 3.04V
-1
-8
+1
+8
%
tA = 25°C. No load, closed-loop, measured
mV
mV
mV
mV
at VOSEN pin to GNDSEN pin. Active
mode range. VID=1.00V to 1.50V
DC output Accuracy
VOUT
No load, closed-loop, measured at VOSEN
pin to GNDSEN pin. Active mode range. -15
VID=1.00V to 1.50V
+15
+10
+15
tA = 25°C. No load, closed-loop, measured
-10
at VOSEN pin to GNDSEN pin. Active
mode range. VID=0.500V to 1.000V
No load, closed-loop, measured at VOSEN
pin to GNDSEN pin. Active mode range. -15
VID=0.500V to 1.000V
ΔVFB
IFB
Line Regulation
VCC = 4.75 V to 5.25 V
0.3
%
μA
Input Bias Current
Output Source Current
Output Sink Current
Open Loop Gain(5)
Unity Gain Bandwidth(5)
Slew Rate(5)
−1
+1
ICOMP
ICOMP
FB forced to (VVID − 3%), no droop
FB forced to (VVID + 3%), no droop
-3
+3
80
20
25
mA
mA
dB
GBW(ERR)
COMP = FB
MHz
V/μs
CCOMP = 10 pF
REMOTE SENSE AMPLIFIER
Bandwidth(5)
GBW(RSA)
IGNDSEN
IVOSEN
20
10
15
MHz
μA
GNDSEN Current
VOSEN Current
GNDSEN=0.3V
VOSEN=1V
400
50
μA
OSCILLATOR
VFSET
fSW
RFSET = 64.9kΩ to GND
FSET Voltage
0.9
1.0
1.1
V
tA = 25°C, RFSET = 64.9kΩ, 4-phase
configuration
Frequency Setting
540 600 660
kHz
In normal mode
0
800
+1
μA
μA
SLOPE Input Current
Range (5)
ISLP
In shutdown, or in UVLO, SLOPE = 12 V
−1
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
4
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
ELECTRICAL CHARACTERISTICS (continued)
VCC = 5 V, GNDSEN = GND, EN = VCC, VID = 0.50 V to 3.04 V, Current going into pin is positive.
TA = -10°C to +100°C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max Units
CURRENT-SENSE AND OVERCURRENT PROTRECTION
R
OCPSET=80.6kΩ, sink current
Current Limit Level
Droop Current
IVCM_OC
IDRP
1.27
mA
from VCM pin
IVCM= -400µA
IVCM= +400µA
-24
24
-25
25
-26
26
μA
μA
CURRENT BALANCE AMPLIFIER
Common Mode Range(5)
Input Current
VCS_CM
1.0
3.5
1
V
ICS
CSx=4V
μA
ns
Masked Off-Time(5)
Measured from PWM turn-off
350
tOFFMSKD
SYSTEM INTERFACE CONTROL INPUTS
EN
EN Low Threshold Voltage
EN High Threshold Voltage
VIL(EN)
VIH(EN)
0.4
V
V
0.8
EN High Threshold Hysteresis
Voltage
VIH(EN)
IIH(EN)
100
2
mV
µA
Enable High Leakage
EN=1.1V
2
5
VCC≥UVLO, Vboot is not 0V,
EN high to Vout ramping (see
Figure 13)
Enable Delay
T3
ms
THERMAL THROTTLING CONTROL
VTEMP ADC
Register 17h=64h (100°C)
IVRHOT# = 20mA, TA=25oC
0.9
8
V
Ω
VRHOT# Low Output
Impedance
10
1
VRHOT# High Leakage Current
-1
µA
IMON OUTPUT
IMON Current
IMON
IVCM= +400µA
24
25
1.3
1
26
μA
V
IMON Clamp Voltage
IMON ADC
VIMONMAX
IMON = Float, IVCM = 400μA
Register 15h=C8h
Register 15h=64h
V
IMON ADC
0.5
V
VRRDY COMPARATOR
VDIFF
(UV)
Relative to nominal DAC
voltage
Under-Voltage Threshold
−300
mV
mV
Relative to nominal DAC
voltage
400
VDIFF
(OV)
Over Voltage Threshold
Absolute voltage
3.30
60
V
Output Low Voltage
Output High Leakage
VVRRDY (L) IVRRDY(SINK) = 4mA
250
1
mV
μA
IVRRDY
VVRRDY = 3.3V
Relative to GNDSEN, VDIFF
falling
−300
−100
mV
mV
Reverse Voltage Detection
Threshold(5)
VOSEN (RV)
Relative to GNDSEN, VDIFF
rising
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
5
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
ELECTRICAL CHARACTERISTICS (continued)
VCC = 5 V, GNDSEN = GND, EN = VCC, VID = 0.50 V to 3.04 V, Current going into pin is positive.
TA = -10°C to +100°C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max Units
CCM OUTPUT
Output Low Voltage
Output High Voltage
PWM OUTPUTS
VOL
VOH
ISINK = 400µA
10
5
200
200
mV
V
ISOURCE = 400µA
4.8
VOL
(PWM)
Output Low Voltage
IPWM(SINK) = 400µA
10
5
mV
VOH
(PWM)
Output High Voltage(5)
PWM Tri-State Leakage
IPWM(SOURCE) = 400µA
PWM = 2.5V
4.8
-1
V
1
µA
SUPPLY
VCC UVLO Threshold
Voltage
VCCUVLO
VCC is rising
4.1
4.45
V
UVLO Hysteresis
200
mV
EN=high. Both SVID bus and
internal ID bus are idle. No load
condition. 4-phase configuration.
PWMs not switching.
8
16
mA
Supply Current
IVCC
EN = 0V
50
250
μA
VDD REGULATOR
VDD Regulator Output
Voltage
VDD
3.2
V
SVID Interface (SCLK, SDIO, ALERT#)(5)
Leakage current
IL
CPIN
RON
Pull-up voltage: 0V to 1.1V
-10
10
5
13
8.3
μA
pF
Ω
ns
ns
ns
Pin Capacitance(5)
Buffer ON Resistance(5)
VR Clock to Data Delay(5)
Setup Time(5)
4
4
8
7
14
Hold Time(5)
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
6
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
ELECTRICAL CHARACTERISTICS (continued)
VCC = 5 V, GNDSEN = GND, EN = VCC, VID = 0.50 V to 3.04 V, Current going into pin is positive.
TA = -10°C to +100°C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
ADC
Voltage Range
ADC Resolution
ADC Sampling Rate(5)
DNL(5)
Reads FF.
1.28
5
V
mV
Hz
LSB
µs
3000
1
Conversion Time(5)
30
DAC Slew rate (MP2935)
Soft-Start Slew Rate
SetVID_Slow Slew Rate
SetVID_Fast Slew Rate
DAC Slew rate (MP2935A)
Soft-Start Slew Rate
SetVID_Slow Slew Rate
SetVID_Fast Slew Rate
DAC
2.5
2.5
10
mV/µs
mV/µs
mV/µs
5
5
20
mV/µs
mV/µs
mV/µs
DAC resolution
LSB
DNL
INL
8
Bits
mV
LSB
LSB
mV
10
±1
±1
Tolerance
-1
1
1/2/3/4 Phase Detection
PWM Sink Current
PWM Detection Threshold
Voltage
100
2.5
50
µA
V
2
3.2
Phase Detect Timer(5)
µs
Notes:
5) Guaranteed by design or characterization data, not tested in production.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
7
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
PIN DEFINITION
Pin #
Name
OTPD
OTPG
SDIO
I/O
Description
1
2
3
4
5
6
I
I
Factory OTP programming only. Connect to VCC for normal operation.
Factory OTP programming only. Connect to GND for normal operation.
Data Signal between CPU and Serial VID Controller.
Alert Signal from VID Controller to CPU.
I/O
O
I
ALERT#
SCLK
Source Synchronous Clock from CPU.
VRRDY
O
VR Ready Output. Open drain output signal.
Voltage Regulator Thermal Throttling Logic Output. Actively pulls low if
temperature at the monitoring point connected to TEMP exceeds the
programmed VRHOT# temperature threshold.
7
VRHOT#
O
8
9
ADDR
TEMP
I
SVID Address setting pin. Refer to Table 6 for address assignment.
Analog Temperature Signal Input.
I/O
Analog Total Load Current Signal. Sources a current proportional to the
sensed total load current. Connect a resistor from IMON to GND to
program the gain.
10
11
12
IMON
AAM
O
I
Advanced Asynchronous Mode (AAM) Timing Control Input. A resistor
between this pin to ground sets the AAM mode turn-on threshold voltage.
Multiphase Frequency-Setting Input. A resistor connected between FSET
and GND sets the oscillator frequency. The phase switching frequency will
be divided by number of the operating phase.
FSET
I
13
14
15
16
17
18
VBOOT
FAULT#
PWM4
PWM3
PWM2
PWM1
I/O
O
VBOOT Voltage Set. Refer to Table 3 for VBOOT voltage assignment.
VR Fault#. Asserts low to notify the platform of a VR fault condition.
O
Tri-State Logic-Level PWM Outputs. Connecting the PWM2 and/or PWM3
and/or PWM4 outputs to VCC turns off that phase, allowing MP2935 to
change the number of operating phases. The operating phase number is
decided when the part is enable. The number of operating phase cannot be
changed on-the-fly.
O
O
O
Forced CCM Operation Enable. CCM stays high in Power States 00 and
01. Actively pulls low when in Power States 02 and 03 to enable DCM
operation of the power stage. Connect it to the SYNC pin of Intelli-
PhasesTM.
19
CCM
O
Max. Temp. Set. Connect a resistor from TMAX to GND to set the
maximum temperature.
20
TMAX
I
21
22
23
24
25
26
CS4
CS3
I
I
Current Balance Inputs. Measures the current level in each phase. Float
CS pins of unused phases.
CS2
I
CS1
I
VCM
O
I
Buffered 2.5V reference.
ICCMAX
ICCMAX setting. Set the pin voltage to program the desired ICCMAX level.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
8
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
PIN DEFINITION (continued)
Pin #
Name
I/O
Description
PWM Slope Current Input. Connect a 100KΩ resistor from VIN (system’s
12V input voltage) to this pin to set the internal slope for PWM comparator.
27
SLOPE
I
28
29
30
31
32
OCPSET
AAMB
VCLAMP
COMP
FB
I
Total Current Limit Setting.
I
I
Combine with AAM pin, this pin sets the AAM mode threshold voltage.
Connect a resistor to ground to set the per phase current limit.
Error Amplifier Output.
I/O
I
Inverting Input of Error Amplifier.
Droop Current Output. Sources current that is proportional to the sensed
output current.
33
34
35
IDROOP
VDIFF
O
O
I
Differential Amplifier Output.
Remote Core Voltage Sense Input. Connect to VCCSENSE at
microprocessor die.
VOSEN
36
37
38
39
GNDSEN
IREF
I
I
I
I
Remote Voltage Sensing Return. Connect to ground at microprocessor die.
Internal Bias Current Set. Connect an 80.6kΩ resistor from IREF to GND.
Chip Enable.
EN
VCC
5V supply voltage for the controller. Need a 1μF capacitor for decoupling.
3.3V LDO output for internal digital circuit only. Need a 1μF capacitor for
decoupling. Do not connect to any other load.
40
VDD
GND
O
PAD
I/O
Ground.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
9
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VCC = 5V, VOUT = 1.85V, IOUT = 0A, 600kHz, unless otherwise noted.
V
/AC
OUT
V
EN
5V/div.
20mV/div.
V
R_RDY
1V/div.
V
OUT
1V/div.
V
COMP
V
R_RDY
100mV/div.
500mV/div.
V
OUT
V
EN
1V/div.
V
2V/div.
PWM1
5V/div.
V
PWM1
V
V
SW
ALERT#
5V/div.
500mV/div.
10V/div.
V
/AC
OUT
20mV/div.
V
PWM1
2V/div.
V
V
PWM2
COMP
100mV/div.
2V/div.
V
DIFF
500mV/div.
V
PWM1
V
V
PWM3
5V/div.
FAULT#
2V/div.
1V/div.
V
V
PWM1
SW1
V
PWM4
5V/div.
10V/div.
2V/div.
V
FAULT#
1V/div.
V
FAULT#
2V/div.
V
OSEN
V
R_RDY
500mV/div.
1V/div.
V
R_RDY
1V/div.
V
V
DIFF
OSEN
500mV/div.
500mV/div.
V
DIFF
V
FAULT#
1V/div.
1V/div.
V
V
V
PWM1
PWM4
PWM1
5V/div.
2V/div.
5V/div.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
10
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
SET/ EN
VDD
OSCILLATOR
PWM1
3.3V LDO
+
-
RESET
PWM2
PWM3
PWM4
Clock
Divider
RVP
BANDGAP
UVLO
SHUTDOWN
BIAS
EN
1-/2-/3-/4-
PHASE
DRIVER
LOGIC
+
-
CURRENT
BALANCE
RESET
RESET
VOSEN
-300mV
-
+
+
-
GND
3.4V
OVP2
-
+
-
+
VRHOT#
RESET
VID+400mV
VDIFF
VR_HOT#
CONTROL
OVP1
UVP
1-Ph
FAULT
RV
-
+
OV
UV
FAULT
CS1
CS2
FAULT
-
+
TEMP
VID-300mV
OC DCY
CS3
CS4
-
FB
E/A
DECAY
+
OCPSET
VID
VCLAMP
AAMB
CURRENT
SENSE
COMP
-
+
GNDSEN
VOSEN
IMON
IDROOP
IREF
VDIFF
CCM
1-Ph
MODE
CONTROL
+
-
VCM
2.5V
4
4
4-bits
ADC
ADDR
FAULT
DECAY
VR_READY
MONITOR &
DELAY, 2ms
SCLK
8
8
VID
DAC
VRRDY
DVID
VRRDY0
SDIO
Serial Data
Link,
Registers,
And OTP
Control
ALERT#
IMON
+
-
VID +10mV
TEMP
VDIFF
(TBD)
(TBD)
(TBD)
VRSET
8-Channel
MUX
8-bits ADC
OTPD
OTPG
VR SETTLED
COMPARATOR
VFB
+
-
(TBD)
(TBD)
VRSET
FAULT#
VID-10mV
24kHz
Clock
DVID
VRRDY0
DECAY
FAULT
TMAX
8
4MHz
ID Clock
256 8-bits Registers
ICCMAX
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
11
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
OPERATION
MP2935 is
a
4-phase VR12.5-compliant
PWM turns off. The phase shift is applied
between operating phases to minimize the input
and output current ripple.
controller for Intel microprocessors. It is a
multiphase controller for up to 4-phase operation
and is capable for multi-mode PWM/advanced
asynchronous mode (AAM) operation to
maximize the efficiency over the load range. It
includes blocks for a precision DAC, remote
voltage-sense amplifiers, an error amplifier, a
ramp generator with input voltage feed-forward, a
PWM comparator, AAM control, load-line set, a
VR-ready (VRRDY) monitor, a temperature
monitor and serial VID (SVID) registers. It also
includes dynamic-phase current balancing and
phase shedding. Protection features include
under-voltage lockout (UVLO), over-current
protection (OCP), over-voltage protection (OVP),
under-voltage protection (UVP) and reverse
voltage protection (RVP).
In general, the controller needs to wait for the
next clock during a load step transient to turn on
the PWM to support the load current. The waiting
time causes the extra output voltage to drop. To
maximize the current support to reduce the
output voltage drop during the transient load,
MP2935 employs FAST-PWMTM mode to
respond immediately. During the load-step
transient, the output voltage drop causes VCOMP
to rise. When VCOMP rise fast enough to trigger
the FAST-PWM threshold, the controller
overrides the phase clock and turns on all PWMs
without phase shifts. The PWM OFF of each
phase is the same as for normal operation when
the combined ramp hits VCOMP voltage. This
FAST-PWM mode maximizes the regulator’s di/dt
slew rate to support the output load transient step
and minimize the VOUT drop.
PWM Operation
MP2935 uses constant-switching–frequency
current mode control and trailing-edge PWM
operation with injected valley current signals. The
PWM ramp of each phase combines with the
sensed valley current to determine phase-current
balance. Figure 1 shows the operation principles.
The phase clock turns the PWM on. When the
combined ramp voltage hits VCOMP voltage the
When the power state is not PS0, the chip
operates in single phase with AAM mode to
maximize the efficiency in light load condition. A
detailed description of AAM mode operation is
described in “AAM Control Operation and Diode
Emulation.”
Figure 1: Block Diagram of PWM Operation
MP2935 Rev. 1.02
8/25/2015
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12
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
PWM Operation and Power States
•
PS2 is used in Sleep Mode and it represents
a lower current state than PS1; it typically has
a load < 5A. MP2935 runs in single phase
(PWM1 only) AAM with diode emulation
enabled.
PS3 (Mode[1,0]= “11”) is ultra-low current
mode, lower than PS2; it typically has a load
< 1A. MP2935 runs in single phase (PWM1
only) AAM with diode emulation enabled.
The user can select the total number of operating
phases for MP2935, as described in “Switching
Frequency and the Number of Operating
Phases.” Based on the power states, the actual
operating phase dynamically switches between
full phases or single phase to optimize the power
conversion efficiency at heavy and light CPU
loads.
•
In PS0, MP2935 runs in full-phase PWM mode.
While in light-load mode, PS1 to PS3, only Phase
1 is in operation to maximize power conversion
efficiency. During the dynamic VID transition
issued by SVID commands of either SetVID_Fast
or SetVID_Slow, the power state changes to PS0
by default and runs in full-phase PWM mode.
Table 1: Phase Number and Operation Modes
Power
Operating
CCM PWM/AAM
State
Phases
0
1
2
3
Full phases
1
1
0
0
PWM
AAM
AAM
AAM
1
1
1
AAM Control Operation and Diode Emulation
In addition to changing the number of phases,
the operation mode can change dynamically. In
PS0 mode, MP2935 runs in multiphase PWM
mode with switching frequency controlled by the
master clock. In other power states, MP2935
switches to AAM mode where the switching
frequency is no longer controlled by the master
clock, but by the ripple voltage on the COMP pin.
Thus, the switch frequency varies with the load
current, resulting in maximum power conversion
efficiency in low power states.
With the exception of PS0, all other power states
enable AAM mode and run in single phase
operation. Figure 2 shows typical AAM mode
operation where switching frequency is no longer
controlled by the master clock, but by the ripple
voltage on the COMP pin.
PWM1 is set high when VCOMP reaches the AAM
threshold voltage which is set by two resistors,
from AAM pin to GND and from AAMB pin to
GND.
In PS2 and PS3, diode emulation mode is
enabled to maximize the efficiency at light load
condition.
AAM Threshold Voltage
15400 VOUT
IMON RAAMB VCOMMON
RAAM
The VR will switch back to AAM mode if the over
current alarm is clear before latch-off.
16RCS
RAAMB
Table 1 summarizes the dynamically changes to
phase number and operation modes based on
the power state register set through SVID
commands.
N
15400 VOUT
VAAM_Fraction
RAAM
The power states are listed in order of power
savings:
VAAM_Fraction
•
•
PS0 represents full power or Active mode
PS1 is used in Active Mode or Idle Mode and
represents a low current state, similar to PSI#
definition in VR11.1 or IMVP6.5; it typically
has a load < 20A. MP2935 runs in single
phase (PWM1 only) AAM/continuous current
modulation (CCM) mode.
VOUT
SW 3.424106
0.5IL _PKPK RCS 10106
F
VCOMMON is about 1V. VAAM_Fraction is part of the
AAM threshold voltage. N is the number of
MP2935 Rev. 1.02
8/25/2015
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© 2015 MPS. All Rights Reserved.
13
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
emulation mode the low side MOSFET turns OFF
once the inductor current reverses to keep the
inductor current at 0A until the next PWM ON
pulse.
active phase during PS0. IL_PK-PK is the peak to
peak inductor current.
VOUT (V VOUT
)
IN
IL_PK-PK
V LF
IN
SW
In both PS0 and PS1, the CCM pin is high so the
controller operates in CCM mode, which allows
for negative inductor current.
Whenever PWM is high, VRAMP ramps up from 1V
with a slew rate programmed by the current
flowing into the SLOPE pin. When VRAMP reaches
In PS2 and PS3, the CCM pin is low to enable
diode emulation mode on the Intelli-PhaseTM,
allowing Diode Emulation mode operation.
VCOMP, PWM resets to low.
The CCM pin is tied to the SYNC pin of the
Intelli-PhaseTM. When the CCM pin is low, it
enables diode emulation mode. In diode
AAM Threshold
-
+
Voltage
PWM1
S
R
Q
VCOMP
-
+
RAMP
AAM
Threshold
Voltage
VCOMP
VRAMP
1V
PWM1
Figure 2: Block Diagram of AAM Operation and Typical Waveforms
MP2935 Rev. 1.02
8/25/2015
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© 2015 MPS. All Rights Reserved.
14
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Switching Frequency and the Number of
Current Sensing and IMON
Operating Phases
MP2935’s works seamlessly with the Intelli-
PhaseTM family to accurately sense output
current to monitor the total output current to
support Adaptive Voltage Positioning (AVP) and
current limit detection. Simply direct the total
sensed phase current from all of the Intelli-
Phases’sTM CS pins to VCM pin. When utilizing
the Intelli-Phase’sTM accurate current sense
output, it eliminates sensing error due to inductor
DCR variation and removes design effort on DCR
thermal compensation. This simple configuration
In normal operation in the PS0 power state, an
external resistor connected from the FSET pin to
ground determines the clock frequency. To
determine the switching frequency per phase,
divide the clock by N, the number of phases, in
use. If phase 4 is disabled by pulling up PWM4 to
VCC, then divide the master clock by 3 for the
frequency of the remaining phases. If both
PWM3 and PWM4 are pulled up to VCC, then
divide the master clock by 2 for the frequency of
the remaining phases. If PWM2, PWM3 and
PWM4 are pulled up to VCC, then the switching
frequency of phase 1 equals the master clock
frequency. If all phases are in use, then divide
the master clock by 4.
is
shown
in
Figure
3.
1.106
RFSET 340000 F N
SW
In single-phase AAM mode, the switching
frequency is almost constant, until it enters DCM
mode then the frequency decrease proportionally
with load current.
Figure 3: Intelli-PhaseTM Current Sensing Circuit
MP2935 Rev. 1.02
8/25/2015
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15
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
The IMON current is a current proportional to
from VDD voltage. VDD is a 3.3V output voltage
from the controller. Using a smaller resistance
for RBOTTOM will reduce variation. Let’s say we
choose RBOTTOM to be 499Ω and the desired
maximum current is 100A (ICCMAX=100A), then
RTOP is calculated to be 2851Ω. To get the best
possible accuracy, use two resistors to match the
calculated resistance.
IVCM
IMON
VCM pin current,
. A resistor, RIMON,
16
from IMON pin to GND sets the gain from
average sensed inductor current to IMON voltage.
A 1nF capacitor added in parallel with RIMON
filters the voltage ripple reflected from the
inductor ripple current.
Phase Current Sensing
2048000
RIMON
MP2935 has individual inputs to monitor the
current in each phase. The phase current
information is combined with an internal ramp to
create a current-balancing feedback system that
is optimized for initial current accuracy and
dynamic thermal balance. The current balance
information is independent of the total inductor
current information used for voltage positioning.
The magnitude of the internal ramp can be
programmed to optimize the transient response
of the system. MP2935 also monitors the supply
voltage to achieve feed-forward control whenever
the supply voltage changes. A resistor connected
from the power input voltage rail to
ICCMAX
If the desire ICCMAX is 100A, then select
20.5KΩ for RIMON
.
The voltage on the IMON pin is clamped to
prevent it from going above 1.3V. An 8-bit ADC
converts the IMON voltage to the IOUT register. An
IMON voltage of 1.28V indicates the current has
reached the value represented in the ICC_MAX
register.
SLOPE pin determines the slope of the internal
PWM ramp.
1
V
1
IN
Slope
(V/s)
8
RSLOPE 7000 CSLOPE
CSLOPE 4pF
Figure 4 shows the block diagram of the phase
current sense and the ramp generator, and the
idealized waveforms.
(VDD 0.005xICCMAX)RBOTTOM
0.005xICCMAX 2x105 xRBOTTOM
RTOP
Set the ICCMAX register with a resistor divider
MP2935 Rev. 1.02
8/25/2015
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16
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VIN
VIN
ICSx
RSLOPE
IntelliPhase
Vin
L
SW
CS
SLOPE
GND
CSx
+
+
PWM
CSLOPE
PWM
R
PWM
VCM
PWM Comp.
Ramp
COMP
MP2935 Internal Circuit
CLK
PWM
Inductor
Current
0A
VCOMP
VRAMP
0V
Figure 4: Block Diagram of Phase Current Sense and Ramp Generator
MP2935 Rev. 1.02
8/25/2015
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17
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
External resistors, R, from the CSx pin to the
two pins to the Kelvin sense leads of the
processor in parallel and away from rapidly-rising
voltage nodes (switching nodes) and other noisy
traces. To achieve optimal performance, place
common mode and differential mode RC filters to
analog ground on VOSEN and GNDSEN. Keep
the filter resistors on the order of 10Ω so that
they do not interact with the 50kΩ input
resistance of the differential amplifier.
VCM reference pin can convert the ICS current to
a related voltage. To increase the current in any
given phase, reduce the R for that phase. Upon
reaching the current limit, MP2935 switches to
full phase PWM mode regardless of power state
status to avoid inrush current stress to the phase
1 power stage.
Voltage Regulation
The voltage-mode control loop consists of a high-
gain–bandwidth error amplifier. The 8-bit VID
DAC sets the non-inverting input voltage. The
VID codes are listed in Table 2. The output of the
error amplifier goes to the COMP pin, which sets
the termination voltage for the internal PWM
ramps. The inverting input, FB, connects to the
output of the remote sense amplifier through a
resistor, RFB, to sense and control the output
voltage at the remote sense point. RFB generates
the droop voltage as a function of the load
current—commonly known as active voltage
Output voltage remote sensing is available.
Remote sensing allows the voltage regulator to
compensate for various resistive drops in the
power path and ensure that the voltage seen at
the CPU die is the correct level independent of
the load current. The VOSEN and GNDSEN pins
connect to the Kelvin sense leads at the die of
the processor through the processor socket as
the signals VCC_SENSE and VSS_SENSE,
respectively. This allows the voltage regulator to
tightly control the processor voltage at the die,
independent of layout inconsistencies and drops.
This Kelvin sense technique provides extremely
tight load line regulation. Treat these traces as
noise-sensitive. For optimal load-line regulation
performance, lay out the traces connecting these
positioning —by injecting the droop current, IDRP
,
into the FB pin. The main loop compensation is
incorporated into the feedback network
connected between the FB and COMP pins.
MP2935 Rev. 1.02
8/25/2015
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18
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Table 2: SVID Code Table
VOUT
DEC
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
OFF
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
0.710
0.720
0.730
0.740
0.750
0.760
0.770
0.780
0.790
0.800
0.810
0.820
0.830
0.840
0.850
0.860
0.870
0.880
0.890
0.900
0.910
0.920
0.930
0.940
0.950
0.960
0.970
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MP2935 Rev. 1.02
8/25/2015
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19
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VOUT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX
DEC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
0.980
0.990
1.000
1.010
1.020
1.030
1.040
1.050
1.060
1.070
1.080
1.090
1.100
1.110
1.120
1.130
1.140
1.150
1.160
1.170
1.180
1.190
1.200
1.210
1.220
1.230
1.240
1.250
1.260
1.270
1.280
1.290
1.300
1.310
1.320
1.330
1.340
1.350
1.360
1.370
1.380
1.390
1.400
1.410
1.420
1.430
1.440
1.450
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
20
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VOUT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX
DEC
97
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
1.460
1.470
1.480
1.490
1.500
1.510
1.520
1.530
1.540
1.550
1.560
1.570
1.580
1.590
1.600
1.610
1.620
1.630
1.640
1.650
1.660
1.670
1.680
1.690
1.700
1.710
1.720
1.730
1.740
1.750
1.760
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1.840
1.850
1.860
1.870
1.880
1.890
1.900
1.910
1.920
1.930
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
21
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VOUT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX
DEC
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
91
92
93
94
95
96
97
98
99
1.940
1.950
1.960
1.970
1.980
1.990
2.000
2.010
2.020
2.030
2.040
2.050
2.060
2.070
2.080
2.090
2.100
2.110
2.120
2.130
2.140
2.150
2.160
2.170
2.180
2.190
2.200
2.210
2.220
2.230
2.240
2.250
2.260
2.270
2.280
2.290
2.300
2.310
2.320
2.330
2.340
2.350
2.360
2.370
2.380
2.390
2.400
2.410
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
22
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VOUT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX
DEC
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
2.420
2.430
2.440
2.450
2.460
2.470
2.480
2.490
2.500
2.510
2.520
2.530
2.540
2.550
2.560
2.570
2.580
2.590
2.600
2.610
2.620
2.630
2.640
2.650
2.660
2.670
2.680
2.690
2.700
2.710
2.720
2.730
2.740
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
2.860
2.870
2.880
2.890
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
23
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VOUT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX
DEC
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
2.900
2.910
2.920
2.930
2.940
2.950
2.960
2.970
2.980
2.990
3.000
3.010
3.020
3.030
3.040
Load-line Regulation
The droop, known as Adaptive Voltage
Positioning (AVP), on MP2935 can be generated
by injecting the IDRP current to the feedback
resistor.
total output current. Selecting the proper RFB1
value can achieve the desired load-line. In the
case of zero droop, floats the IDROOP pin.
Figure 5 shows the block diagram of droop
generation.
1
The current output on the IDROOP pin is
the IVCM current, which is proportional to the
of
RFB1 16105 Droop
16
For 1mΩ droop, RFB1=1.6KΩ.
VCM
1:16
Figure 5: Block Diagram of Droop Generator
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
24
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
SetVID_Fast/Slow
Output Voltage Offset Programming
If the VR is in a low-power state and receives a
new SetVID_Fast/Slow command, then the VR
exits the low-power state to normal mode (PS0),
operating in full-phase PWM mode to move the
voltage by the preset slew rate. The VR remains
in PS0, until it receives a new power state
command.
After receiving the SVID command for setting the
offset (33h), the SVID controller compares the
VID plus the proposed offset with the maximum
VID of FFh (3.04V), and rejects the SVID
command if this value exceeds FFh. If the VID
plus proposed offset is less than FFh, the SVID
updates the register 33h and the DAC ramps
up/down to the new value of VID+Offset with
slow slew rate defined in register 25h. During
ramp up/down to the new DAC value, the SVID
rejects all SVID commands, which is the same
behavior as SetVID_Fast/Slow.
SetVID_Decay
In the case of a SetVID_Decay command, the
VR automatically goes to PS2 or remain at PS3.
SetVID_Decay command steps up the VID DAC
to the target VID at 10mV/step, with each step
triggered by VR_SETTLE assert. In the event of
a SetPS command during the VOUT decay,
MP2935 will enter into the requested power state
after VOUT reaches the requested VID value.
Whenever the VR exits decay mode whenever it
receives a SetVID_Fast/Slow, enters PS0 power
state, and ramps up/down to the new VID from its
current VID.
Dynamic VID
The SVID bus sends out new target voltage and
slew rate commands to the PWM IC. The VR
responds by slewing to the new voltage in a
controlled manner without falsely tripping VRRDY,
over-voltage, or over-current protection circuits.
To meet all market segment requirements, there
are three different slew rates: fast, slow, and
decay. During fast and slow VID transitions, the
SVID controller ramps up/down the VID code
step-by-step. There is a 4MHz ID clock for VID
change, with defined VID step of 10mV, the
maximum slew rate is up to 20mV/μs.
Figure 6 shows the detailed diagram of the
operation modes with the VID Transition taken
into consideration.
Figure 7(a) to 7(d) show the detailed signals of
Decay mode operation for different cases.
During VID decay, the VR output voltage
converges to the new VID target, but does not
control the slew rate; the output voltage decays
at a rate proportional to the load current.
The VID change triggers a VR_RDY masking
timer to prevent a VR_RDY failure. Each VID
change resets and restarts the internal VR_RDY
masking timer. During the VID transition except
VID decay, MP2935 forces a full-phase PWM
operation and reset the power state to PS0 by
default.
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
25
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VID(Fast/Slow)
Transient
Power State
change
VID
Decay
Power State change
Power State change
SetPS_
(11h)
SetVID_
Slow
SetPS_
(01h)
SetPS_
(01h)
SetVID_
Decay
SetPS_A(01H)
PKT
SetVID_D
ecayA
S etP S_A(01H)
PKT
SetVID_Sl
owA
SetPS_A(11H)
PKT
SVID Bus
DVID
Note 5: During Decay mode, the VID is
changed step by step following the VR_SET
signal.
VID
Vout
Note4: If VR is slewing down with a
SetVID_Decay command and the next
command is a SetPS, then VR could enter that
power state with the decay rate.
VR_SETTLE
MODE0
MODE1
0
0
1
1
1
0
0
1
0
1
0
0
PWM1
PWM2
PWM3
CCM
PS0
PS1
PS0
PS1
PS2
PS3
4Phase
PWM
CCM
1Phase
AAM
CCM
4Phase
PWM
CCM
1Phase
AAM
CCM
1Phase
AAM
DCM
1Phase
AAM
DCM
Note3: With SetVID_Decay
command, the VR
automatically enters into PS2
mode.
Note1: If VR is in a low power state and receive a
SetVID_Fast/Slow (up or down), then the VR exits
the low power state to normal mode and Set the PS
register to 00h
Note2: the VR remain in PS0 until the CPU
commands it to re-enter to a low power state. If
VR is still slewing from previous SetVID_Fast/
Slow command, the VR should reject the SetPS
command.
Figure 6: Detailed Diagram of the Operation Modes
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
26
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Figure 7(a)
Figure 7(b)
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
27
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Figure 7(c)
SetVID_Decay
(1.0V)
SetPS_0
Vcore
1.2V
1.8V
VID
dV<15mV
1.4V
1.4V
0.8V
1.0V
Slow slew-rate
MODE1
DECAY
DECAY changes 1 CLK later than DVID
250ns
(min)
DVID/
!Final_VID
VR_SETTLE
Decay_Settle
ALERT#
Case 4. CPU commands VID 1.8V decay to 1.0V.
Before VOUT reaches 1.0V target, Set the Power Stage to PS0, SetPS(0) command.
Figure 7(d)
Figure 7: Detail Signal during Decay Mode Operation
MP2935 Rev. 1.02
8/25/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
28
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VR_Settle Monitoring
Enable and Disable
To enable MP2935, the VCC supply voltage must
exceed the UVLO upper threshold and the EN
pin must exceed its logic-high threshold. After
start-up, VDD (3.3V) supplies the SVID controller
and interface. Whenever the VCC voltage is less
than the UVLO threshold or the EN pin is logic
low, MP2935 shuts down, and the controller sets
all PWM outputs to a high-impedance (Hi-Z) state.
VR_SETTLE signal indicates whether the
dynamic VID (DVID) transition has completed.
VR_SETTLE is de-asserted when the VR
controller receives a new VID code different from
the previous one; VR_SETTLE is asserted again
when the output voltage is within 10 mV or one
VID step of the target voltage.
Soft-start and Start-up into Pre-biased Output
The falling edge of DVID indicates that the VID
ramping will complete soon. When the SVID
controller receives a new VID target from the
SVID master, it asserts the DVID signal; then the
SVID controller ramps up/down the VID code
step-wise to the target VID. The SVID controller
de-asserts DVID when the current VID code is
within 10mV or one VID step of targeted voltage.
Then the sensed output voltage is compared to
the DAC output to determine VRSETTLE signal
when the DVID is asserted. Once DVID is
asserted, it lasts for at least 250ns.
After enabling MP2935, the VR can start-up. The
DAC ramps up to the VBOOT voltage with the slew
rate set in SR_Slow register. During soft-start,
the PWM is in Hi-Z state until the DAC reaches
FB voltage preventing the pre-biased output from
discharging. Upon completion of soft-start,
VR_RDY asserts if there are no faults during a
typical 2ms delay.
Set VBOOT voltage by using two resistors to
form a resistor divider from VDD to set the
VBOOT pin voltage. VDD pin is the internal 3.3V
LDO output. Table 3 shows the resistor pairs for
different VBOOT voltages.
The only condition that asserts and de-asserts
VR_SETTLE is the VID transition. VRSETTLE
remains unchanged even if the output voltage
exits the ±10mV window when operating under a
stable VID code.
Table 3: VBOOT Setting Resistance
VBOOT
RVBOOT_GND
RVDD_VBOOT
Voltage
When the VID change is within 1 step, the SVID
controller de-asserts the DVID signal for a
minimum of 500ns and VRSETTLE resets.
VR_SETTLE sets if the output is within ±10mV
after DVID is asserted. The SVID responds with
ALERT# after the ACK signal from the CPU if
VR_SETTLE is asserted.
1.85V
1.8V
1.75V
1.7V
1.65V
1.6V
1.5V
1.35V
1.25V
1.2V
1.1V
1V
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
768Ω
47.5kΩ
19.6kΩ
12.1kΩ
8.45kΩ
6.34kΩ
5.11kΩ
4.22kΩ
3.48kΩ
3.01kΩ
2.55kΩ
2.21kΩ
2kΩ
Fault Monitoring and Protections
The fault monitoring and protections provided by
MP2935 are listed below.
1) VR_RDY signals
2) Under-voltage monitor and protection
3) Over-voltage monitor and protection
4) Reverse-voltage monitor and protection
5) Over-current monitor and protection
6) Thermal monitors and over-temperature
indicator (VR_HOT#, active low)
0.9V
0V
1.78kΩ
1.58kΩ
1.43kΩ
1.27kΩ
0.6V
0.8V
7) FAULT# (active low) signal
MP2935 Rev. 1.02
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29
MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VRReady_0V flat is under register 34h
configures multiple slaves (VRs) on the same
bus on the server platforms. It is also used in
notebook and desktop systems to program
VRRDY operation when the VID command is set
to 0V or off condition.
VR_Rdy Signal
VRRDY pin is an active-high (open drain)
output that indicates that the start-up sequence
has completed and that the output voltage has
moved to the VBOOT value or the SVID
programmed VID value. This signal is part of the
start-up sequence for other voltage regulators,
the clock, microprocessor reset, etc. VRRDY
comparator monitors the operation of VR through
the fault latch logic. The signal remains asserted
during normal operation and de-asserts
whenever a fault (OCP, OVP, etc.) or shutdown
conditions occurred. This signal does not
represent DC output accuracy through its VID
value and does not track VID during dynamic VID
events. VRRDY indicates that the VR is
operating properly, not falsely trigger during
dynamic VID transitions.
If “VR_RDY_0V” =0 (default, normal mode), then
VR_RDY de-asserts if the VR is given a SetVID
(0.0V) command, i.e., the VR is off.
If “VR_RDY_0V”=1, then VRRDY does not de-
assert when a SetVID (0.0V) command is issued.
This means that the 0V output is a valid voltage
setting and the VR is ready to accept the next
command. Under this definition, VR_RDY only
de-asserts at power-down or under fault
conditions.
See Figure 8 for more details.
Figure 8: VR_RDY_0V Operation Waveforms
MP2935 Rev. 1.02
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Under-voltage Detection
The first level OV detector (VID+400mV) is
Under-voltage protection is independent of the
over-current limit. A fault triggers if the output
voltage is less than the VID value by 300mV or
more for at least 1ms. Then the VR shuts off and
latches and VR_RDY goes low. Note that most
practical voltage regulators will trigger over-
current before dropping below the -300mV under-
voltage limit. Refer to Figure 9.
blanked until the first falling edge of the DVID
signal after the part is enabled. This prevents the
false latch with start-up with pre-biased output
voltage.
OVP1 monitor is also disabled during the VID
decay transition. It re-activates after finishing
VR_SETTLE re-assertion transition.
During fast or slow VID transitions, the OVP1 is
blanked for 100μs. Figure 10 summarizes the
blanking conditions for the OVP1 monitor.
The OVP2 monitor is active at all times when the
controller is enabled regardless of fault
conditions. This ensures that the load is
protected against high-side MOSFET leakage
while the MOSFETs turn off.
In the event of an OVP condition, the PWMs are
latched low with CCM=1 to turn off the high-side
MOSFETs and turn on low-side MOSFETs to
crowbar the output, while VRRDY de-asserts.
The OVP latch can only reset when toggled
enable, toggles the VCC, or when reverse-
voltage protection (RVP) occurs.
Figure 9: Under-Voltage Protection
Over-voltage Protection
Figure 10 shows the OVP fault latch for the two
levels.
OVP circuit monitors the output for an over-
voltage condition.
There are two levels of over-voltage protection:
OVP1 is the first level of over-voltage protection,
and is defined as VID+400mV; OVP 2 is set at
3.40V. Once the output voltage exceeds either of
these two OVP levels, an over-voltage (OV) fault
will trigger immediately.
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Figure 10: OVP Protection Blanking Conditions
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Figure 11: OVP and RVP Fault Protection
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Whenever VCM current exceeds the OC
Reverse-voltage Detection
threshold, an internal current limit amplifier
controls the internal COMP voltage cycle-by-
cycle to turn off the PWM to maintain peak
current below the OC limit level.
Very large reverse inductor currents cause
negative output voltages that harm the CPU and
other output components. MP2935 provides RVP
without additional system cost. The VOSEN pin
monitors the output voltage: Any time the
VOSEN pin voltage falls below -300 mV, MP2935
triggers RVP by latching all PWM outputs to a
high-Z state. The reverse inductor current can
quickly reset to 0A by dissipating the energy in
the inductor through the input DC voltage source
through the forward-biased body diode of the
high-side MOSFETs.
If an OC event occurs for 1ms, an OC fault
triggers and MP2935 shuts down with all PWM
latched to high-Z output, as shown in Figure 12.
The latch-off can only reset by either toggling
VCC or toggling the EN pin. Program the OC
level with the following equation:
1.024107
ROCPSET
IOC
Occasionally, OVP results in negative output
voltage because turning on all low-side
MOSFETs leads to very large reverse inductor
current. The VR controller’s RVP monitoring
function remains active even after OVP latch-off
to prevent damage to the load by negative
voltage.
MP2935 also has a per-phase current limit to
limit each phase’s duty cycle, so that each phase
will not exceed a current level set by the user.
This per-phase current limit can be programmed
by setting a resistor from VCLAMP pin to ground.
VCOMP _PEAK
The RVP latch can only be reset by toggling
enable, power cycling the VCC or when OVP
occurs. See Figure 11.
RVCLAMP
IVCLAMP
VCOMP_PEAK RCS (IPer _Phase _Limit IL _PKPK )10106
Over-current Protection
VOUT
MP2935 uses VCM current, IVCM, to detect an
over-current condition. VCM current is continually
compared to an internal reference current. IVCM is
provided by Intelli-Phase’sTM CS pin, see
“Current Sensing and IMON” section for details.
1
6
FSW 3.4241010
1mS
Ilim
Iout
In N-phase configuration—where all phases are
switching—the current limit occurs when the
VCM current exceeds the OC threshold. The
threshold is programmable via a resistor from
OCPSET pin to ground. For most designs, select
OC threshold about 130% of the rated current.
Vout
CCM
PWM
In power states PSn (where n = 1 through 3)
running in single phase mode, the OC threshold
is divided by N, i.e. 1/N. N is the number of
operating phases for Power state 0 (PS0). See
Table 4.
VR_RDY
Table 4: OCP Level during PS1/2/3
Figure 12: OCP Fault Protection
Over Current Trip Level
N=4
IOC
N=3
IOC
N=2
IOC
PS0
PS1/2/3
IOC/4
IOC/3
IOC/2
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Table 5: Summary of Fault Protection
Fault
Duration
Prior to
Protection
Fault
Protection Action
Comment
An internal current limit amplifier controls the
internal COMP voltage, turning off the PWM
and monitors for OC events cycle-by-cycle to
keep the current below the OC limit level. All
PWMs are latched to high-Z output if OC
occurs continuously for 1ms.
General Over-Current
Over-Voltage of 3.4V
1ms
Always on
Always on
Immediate
Immediate
PWMs are latched low and CCM is high.
Disabled during VID
transition and
during soft start.
Over-Voltage of VID+
400mV
PWMs are latched low and CCM is high.
All PWMs are latched to high-Z output when
UV occurs for at least 1ms.
Under-Voltage
1ms
Always on
Always on
Always on
Reverse Voltage
Over-Temperature
Immediate
Immediate
All PWMs are latched to high-Z output.
VR_HOT# goes low.
MP2935 Rev. 1.02
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Start up Sequence
Monitoring (VR_HOT#) and Temperature Zone
MP2935 provides a temperature sense pin TEMP
and VR_HOT# signal to indicate an over-
temperature event. VR_HOT# can be routed to
various system thermal management controllers.
VRHOT# pin is an open-drain output, active low
and can be used to drive the CPU’s force thermal
throttle input.
MP2935 must strictly follow the start-up
sequence shown in Figure 13.
Figure 13 shows the diagrams of the start-up
sequence described below:
(1) VCC ramps up to 5V.
(2) VR controllers receive hardware enable,
i.e. EN is high. It takes 35µs (T1) from EN
high to VDD ramped to 3.3V.
The ADC converts the VTEMP voltage to update
the temperature zone register and compare this
value with VRHOT# trip threshold programmed in
the SVID register 22h.
(3) SVID bus exits Reset State when the
VDD is higher than its UVLO threshold.
The part is ready to accept SVID
command 1.6ms (T2) after VDD reached
3.3V.
For the ADC conversion, VTEMP=0.9V equates to
64h stored in the register 17h.
MP2935
utilize
Intelli-Phase’sTM
on-die
(4) Soft-start begins (DAC output starts to
ramp up) 1.6ms (T2) after VDD reached
3.3V. VR ramps to the VBOOT voltage with
slow slew rate. Once VR reached the
VBOOT voltage, it asserts VR_SETTLE,
ALERT# and VR_RDY.(6)
temperature sensing output to monitor the hottest
phase’s junction temperature. Simply connects
every Intelli-Phase’sTM VTEMP pin to MP2935’s
TEMP. Connect a 1KΩ resistor from TEMP pin
to ground to sink the voltage when temperature is
going down.
(5) Start up sequence finished.
Notes:
6) CPU determines when the ALERT# signal is cleared. It may
clear ALERT# after the rail is up.
VR_HOT# trip point is programmable by TMAX
pin. The hysteresis of VR_HOT# is around 3% of
the maximum temperature stored in the register
22h. The tolerance on VR_HOT# should be ± 4%
or approximately ±4°C at 100°C setting.
RTMAX 250 TMAX
If the desire TMAX is 100oC, then select 25KΩ
for RTMAX
.
MP2935 Rev. 1.02
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
VCC
(5V)
EN
T1
VDD
(3.3V)
Pay
ACK
load
GETReg
Status
SetVID_Slow ACK
SVID
Bus
VID
T2
VOUT
T3
VR_SETTLE
ALERT#
Alert# is only
cleared after CPU
sends the read
status command
VR_RDY
Figure 13: Start-Up Sequence
MP2935 Rev. 1.02
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
SVID Operation and Registers
The SVID operation and registers follow the
VR12/IMVP7 SVID protocol, rev. 1.5, issued by
Intel.
are a nominal 55Ω impedance bus. The
reference voltage for SDIO and SCLK is the
processor’s I/O voltage (typically VTT=1.0-1.1V).
The bus operates up to a maximum frequency of
26.25MHz. The alert line, ALERT#, is an active-
low signal driven asynchronously from the slave
device, prompting the master to read the status
register. All signals are routed between the
master and the slave or multiple slaves on a
common bus—the master CPU and the VR
slaves are the only devices allowed on the bus.
SVID is a three-wire (clock, data and alert)
synchronous serial interface that transfers power
management information between a master (the
CPU) and slaves (MP2935). The clock is source-
synchronous from the CPU. The master drives
the SCLK signal with a low-voltage open drain
driver, and may shut down the SCLK signal to
save power in the absence of data to transfer.
SDIO is a low-voltage, open-drain data signal
that the master and slaves use to send
information to each other. The pull-ups for SDIO
Figure 14 shows the block diagram of the SVID
controller.
Figure 14: Block Diagram of SVID Controller
The VID slew rate control block digitally ramps
up/down the 8-bit VIDs to the final VID codes set
by master at a given slew rate. For example, if
the VID chip gets a SetVID_Fast command from
the CPU with a new set of VIDs as the master
payload contents, an internal register latches the
new VIDs immediately. Meanwhile, an 8-bit
counter starts to count up/down from the
previous VIDs to the new codes. The internal
clock determines the counting speed: The
MP2935 has a 4MHz internal ID clock and
supports a slew rate of up to 20mV/μs.
When MP2935 receives 8-bit VID codes, it
automatically converts the VIDs into an internal
reference voltage. The FINAL_VID signal, DVID,
indicates that the SVID controller will finish VID
ramping soon. DVID signal de-asserts once the
VID controller gets a new VID command from
CPU, then the SVID controller ramps up/down
the VID code to the target VID step-by-step.
DVID signal asserts again when the current
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Table 6: SVID Address vs ADDR Resistor
VID code is within 10mV or 1 VID step from the
target voltage. DVID is the enable signal of
VRSETTLE comparator. The sensed output
voltage is compared to the DAC output to
determine VRSETTLE signal when the DVID is
asserted.
RADDR (kꢀ)
Address (HEX)
0
0x0
11.8
19.6
28
0x1
0x2
0x3
35.7
44.2
51.1
59
68.1
80.6
88.7
95.3
105
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
SVID Address
To support multiple MP2935 used on the same
SVID bus, use the ADDR pin to program the
SVID address for each MP2935. There is a 10μA
current on the ADDR pin; connect a resistor from
ADDR pin to ground to set the ADDR voltage.
The internal ADC converts the pin voltage to set
the SVID address. Table 6 shows the SVID
address for different resistor values from ADDR
pin to ground.
0xC
0xD
133
Address 0xE and 0xF are reserved as an “All
Call” address used for the CPU to communicate
with all slave devices on the bus.
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
Table 7: Supported SVID Commands
SVID COMMANDS
Master
Payload
Contents
Salve
Command
Payload Descriptions
Contents
Set the new VID target. VR transitions to new a VID
SetVID-Fast
Individual
Address and All
Call Address
target at a controlled (up or down) slew rate programmed
by the VR. When VR receives a VID moving-up
command, it exits all low-power states to the normal state
to ensure the fastest slew rate to the new VR.
01h
VID code
VID code
VID code
N/A
N/A
Set the VID target. VR transitions to new a VID target at a
controlled slew rate (up or down) programmed by the VR.
SetVID-Slow is 4x slower than SetVID-Fast. When VR
receives a VID moving-up command it exits all low power
states to the normal state to ensure a slow slew rate to
the new VR.
SetVID-Slow
Individual
02h
Address and All
Call Address
SetVID-Decay
Individual
ADDRESs and
All
Sets the VID target, VR transitions to new the VID target,
but does not control the slew rate; the output voltage
decays at a rate proportional to the load current.
SetVID_Decay is only used when VID is falling. VR sets
VR_settled bit, but Alert line is not
03h
04h
N/A
N/A
Call Address
Byte
indicating
power
status of
CPU
SetPS
Individual
Address and All
Call Address
Sends information to VR controller so it can configure VR
to improve efficiency, especially at light load
SetRegADR
Individual
Address Only.
NAK All Call
Address
Address of
the index in
the data
table
Sets the address pointer in the data register table.
Typically the next command, SetRegDAT, gets loaded
into this address. However for multiple writes to the same
address, use only one SetRegADR.
05h
06h
07h
N/A
N/A
SetRegDAT
Individual
Address Only.
NAK All Call
Address
New data
register
contents
Writes the contents to the data register that was
previously identified by the address pointer with
SetRegADR.
GetReg
Individual
Address Only.
NAK All Call
Address
Slave returns the contents of the specified register as the
payload. See Table 8 for list of registers The majority of
the VR monitoring data is accessed through the GetReg
command.
Define
which
register
Specified
register
contents
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
SVID DATA AND CONFIGURATION REGISTERS
Table 8 shows the supported registers.
Table 8: SVID Registers
Index
Register Name
Vendor ID
Product ID
Product Revision
Date code
Access
Default Value (OTP)
00h
01h
02h
03h
04h
R
R
R
R
R
25h
Registers 00h-06h are programmed
by the VR vender at time of
manufacture and are read only. This
information is used to identify the
vender's part in the field or during
platform manufacture.
hard coded
Lot code
hard coded
02h (for VR12.5), hard
code
05h
protocol ID
R
06h
10h
11h
12h
capability
Status_1
Status_2
R
R
R
R
D7h
00h
00h
Temperature Zone
Output Current
00h
Registers 10h-18h are read-write
telemetry data registers that the PWM
controller updates. The Master can
read these registers, but not write.
actual IOUT measured
after start-up
15h
R
(IOUT
)
16h
17h
Output Voltage
VR Temperature
Output Power
R
R
18h
R
(POUT
)
19h
1Ah
1Bh
1Ch
21h
22h
Input Current
Input Voltage
Input Power
R
R
R
R
R
R
Status_2_last read
ICC_MAX
00h
96h (150C)
Temp_MAX
Registers 21h-29h are OTP or pin-
programmed with platform VR design
points. If pin-programmed, the VR
must load the data registers when its
power is applied to the VR control IC.
0Ah (10mv/μs)
14h (20mV/μs)
24h
SR_Fast
SR_Slow
R
05h(5mV/μs) for
fast@20mV/μs
02h (2.5mV/μs) for
fast@10mV/μs
7Eh (1.75V)
25h
R
26h
30h
31h
32h
33h
34h
35h
VBOOT
VOUT_MAX
VID setting
PWR State
Offset
R
RW
RW
RW
RW
RW
RW
FFh (3.04V)
00h
Registers 30h-35h are scratch;pad
registers, programmed by the Master
with SetVID_X, SetPS or SetRegDAT
commands. These registers revert to
default values when power is
removed.
00h
00h
00h
Multi VR Config
SetRegADR
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MP2935 — 4-PHASE PWM CONTROLLER FOR VR12.5 APPLICATIONS
PACKAGE INFORMATION
6x6mm QFN40
5.90
6.10
4.50
4.80
PIN 1 ID
SEE DETAIL A
40
31
PIN 1 ID
MARKING
30
1
0.50
BSC
5.90
6.10
4.50
4.80
PIN 1 ID
INDEX AREA
0.18
0.30
10
21
11
20
0.35
0.45
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.25 TYP.
0.80
1.00
0.20 REF
0.00
0.05
DETAIL A
SIDE VIEW
5.90
4.70
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
0.70
0.25
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-220, VARIATION VJJD-5.
5) DRAWING IS NOT TO SCALE.
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP2935 Rev. 1.02
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42
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MPS
MP29373DF-LF-Z
Switching Regulator, Current-mode, 1400kHz Switching Freq-Max, PDIP20, ROHS COMPLIANT, MO-153ACT, TSSOP-20
MPS
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