MP28128DQ-LF-Z [MPS]
Switching Regulator, Current-mode, 4.5A, 1800kHz Switching Freq-Max, 3 X 3 MM, ROHS COMPLIANT, MO-229VEED-5, QFN-10;
| 型号： | MP28128DQ-LF-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator, Current-mode, 4.5A, 1800kHz Switching Freq-Max, 3 X 3 MM, ROHS COMPLIANT, MO-229VEED-5, QFN-10 开关 输出元件 |
| 文件： | 总11页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP28128
2.5A, 1.5MHz Synchronous
Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP28128 is a 1.5MHz fixed frequency
PWM synchronous step-down regulator with
internal compensation. MP28128 operates from
a 2.7V to 6V input and generates an adjustable
output voltage from 0.8V to 0.9xVIN at up to
2.5A load current.
•
•
•
•
•
•
•
•
•
•
•
•
2.5A Output Current
Input Operation Range: 2.7V to 6V
1.5% Output Accuracy
Internal Power MOSFET Switches
All Ceramic Capacitor Design
1.5MHz Fixed Switching Frequency
Internal Soft-Start
Frequency Synchronization Input
Power Good Output
The MP28128 integrates an 80mΩ high-side
switch and a 60mΩ synchronous rectifier for
high efficiency without an external Schottky
diode. With peak current mode control and
internal compensation, the MP28128 based
solution delivers a very compact footprint with a
minimum component count. Fault condition
Cycle-by-Cycle Current Limiting
Thermal Shutdown
3mm x 3mm 10-lead QFN Package
protection
includes
hiccup
short-circuit
APPLICATIONS
protection, cycle-by-cycle current limiting and
thermal shutdown. Other features include
frequency synchronization input, internal soft-
start and power good output.
•
•
•
•
µP/ASIC/DSP/FPGA Core and I/O Supplies
Printers and LCD TVs
Network and Telecom Equipment
Point of Load Regulators
The MP28128 is available in a small 3mm x
3mm 10-lead QFN package.
“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs.
Output Current
95
V
IN
C3
100nF
90
IN
POK
BS
V
POK
SW
OUT
5V to 1.8V
5V to 3.3V
1.8V / 2.5A
85
80
75
70
MP28128
5V to 2.5V
EN/SYNC
GND
FB
OFF ON
0
0.5
1
1.5
2
2.5
OUTPUT CURRENT (A)
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
1
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
IN to GND................................... –0.3V to +6.5V
SW to GND.......................... –0.3V to VIN + 0.3V
SW to GND............ -2.5V to VIN+2.5V for <50nS
FB, EN/SYNC, POK to GND.......... –0.3V to +6.5V
BS to SW.................................... –0.3V to +6.5V
Junction Temperature...............................150°C
Lead Temperature....................................260°C
Storage Temperature ..............–65°C to +150°C
Recommended Operating Conditions (2)
Supply Voltage VIN............................. 2.7V to 6V
Output Voltage VOUT .................0.8V to 0.9 x VIN
Operating Temperature .............–40°C to +85°C
TOP VIEW
FB
GND
SW
IN
1
2
3
4
5
10 EN/SYNC
9
8
7
6
GND
SW
IN
BS
POK
EXPOSED PAD
ON BACKSIDE
Connect to GND
Thermal Resistance (3)
θJA
θJC
QFN10 (3mm x 3mm).............50...... 12... °C/W
Part Number*
Package
Temperature
QFN10
(3mm x 3mm)
Notes:
MP28128DQ
–40°C to +85°C
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
For Tape & Reel, add suffix –Z (eg. MP28128DQ–Z)
For RoHS Compliant Packaging, add suffix –LF
(eg. MP28128DQ–LF–Z)
*
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS (4)
VIN = VEN = 3.6V, TA = +25°C, unless otherwise noted.
Parameters
Condition
Min
Typ
750
1
Max
Units
μA
VEN = VIN
Supply Current
VFB = 0.85V
Shutdown Current
VEN = 0V, VIN = 6V
μA
IN Undervoltage Lockout
Threshold
Rising Edge
2.59
2.69
V
IN Undervoltage Lockout
Hysteresis
210
mV
TA = +25°C
0.788
0.780
0.800
0.800
±50
0.812
0.820
V
V
Regulated FB Voltage
–40°C ≤ TA ≤ +85°C
VFB = 0.85V
FB Input Current
nA
V
EN High Threshold
EN Low Threshold
Internal Soft-Start Time
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
1.6
0.4
10
V
120
80
µs
mꢀ
mꢀ
High-Side Switch On-Resistance ISW = 300mA
Low-Side Switch On-Resistance ISW = –300mA
60
VEN = 0V; VIN = 6V
SW Leakage Current
–10
μA
VSW = 0V or 6V
BS Under Voltage Lockout
Threshold
1.8
V
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
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© 2016 MPS. All Rights Reserved.
2
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (4) (continued)
VIN = VEN = 3.6V, TA = +25°C, unless otherwise noted.
Parameters
Condition
Sourcing
Sinking
Min
Typ
4.5
3.5
1.5
2
Max
Units
A
High-Side Switch Current Limit
Low-Side Switch Current Limit
Oscillator Frequency
4.0
A
1.2
1.8
MHz
MHz
MHz
ns
Maximum Synch Frequency
Minimum Synch Frequency
Minimum On Time
1
50
90
10
-10
Maximum Duty Cycle
%
POK Upper Trip Threshold
POK Lower Trip Threshold
POK Output Voltage Low
POK Deglitch Timer
FB respect to the nominal value
FB respect to the nominal value
ISINK = 5mA
%
%
0.4
V
30
μs
Thermal Shutdown Threshold
Hysteresis = 20°C
150
°C
Note:
4) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.
PIN FUNCTIONS
Pin #
Name
Description
Open Drain Power Good Output. “HIGH” output indicates VOUT is within ±10% window.
“LOW” output indicates VOUT is out of ±10% window. POK is pulled down in shutdown.
6
POK
Input Supply. A decoupling capacitor to ground is required close to these pins to reduce
switching spikes.
4, 7
3, 8
IN
Switch Node Connection to the Inductor. These pins connect to the internal high and low-
side power MOSFET switches. All SW pins must be connected together externally.
SW
GND,
Exposed
Pad
Ground. Connect these pins with larger copper areas to the negative terminals of the input
and output capacitors. Exposed pad and GND must be connected together.
2, 9
5
Bootstrap. A capacitor between this pin and SW provides a floating supply for the high-side
gate driver.
BS
Feedback. This is the input to the error amplifier. An external resistive divider connects this
pin between the output and GND. The voltage on the FB pin compares to the internal 0.8V
reference to set the regulation voltage.
1
FB
Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V shuts down
10
EN/SYNC the part. Forcing this pin above 1.6V turns on the part. Applying a 1MHz to 2MHz clock
signal to this pin synchronizes the internal oscillator frequency to the external source.
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
3
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT = 1.8V, TA = +25ºC, unless otherwise noted.
Steady State Operation
Half Load
Steady State Operation
Full Load
Steady State Operation
No Load
VOUT
10mV/div.
VOUT
10mV/div.
VOUT
10mV/div.
Inductor
1A/div.
Inductor
1A/div.
Inductor
1A/div.
VSW
5V/div.
VSW
5V/div.
VSW
5V/div.
400ns/div
400ns/div
400ns/div
Load Transient
Start-up through enable
No Load
1.25A-2.5A Step Resistive Load
VOUT
100mV/div.
VOUT
1V/div.
VPOK
2V/div.
Inductor
1A/div.
VEN
2V/div.
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
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© 2016 MPS. All Rights Reserved.
4
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT = 1.8V, TA = +25ºC, unless otherwise noted.
Shut Down through Enable
No Load
Shut Down through Enable
Full Load
Start Up through Enable
Full Load
VOUT
2V/div.
VOUT
1V/div.
VOUT
1V/div.
VEN
5V/div.
VPOK
2V/div.
VEN
2V/div
.
VPOK
5V/div.
VEN
2V/div.
VPOK
2V/div.
v
400ms/div
1ms/div
Short Circut Protection
Short Circuit Recovery
VIN
VIN
=5V,VOUT=1.8V
=5V,VOUT=1.8V
VOUT
1V/div.
VSW
VOUT
1V/div
.
VSW
5V/div.
5V/div.
Inductor
1A/div.
Inductor
2A/div.
1ms/div
400 s/div
MP28128 Rev. 0.92
1/6/2016
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© 2016 MPS. All Rights Reserved.
5
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
POK
0.88V
0.72V
IN
IN
+
--
EN
+
--
BS
EN/SYNC
LOGIC
EN
EN/SYNC
- -
+
EXCLK
OSC
PWM
CURRENT
COMPARATOR
LOGIC
CLK
SW
SW
SLOPE
0.5pF
1.2 MEG
17pF
SLOPE
COMPENSATION
AND PEAK
CURRENT LIMIT
COMP
--
+
+
FB
0.8V
GND
GND
SOFT
-START
Figure 1—Functional Block Diagram
MP28128 Rev. 0.92
1/6/2016
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© 2016 MPS. All Rights Reserved.
6
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
the non-inverting error amplifier input. The soft-
FUNCTIONAL DESCRIPTION
start time is internally set at 120µs. If the output
of the MP28128 is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches. until the
voltage on the internal soft-start capacitor
exceeds the sensed output voltage at the FB pin.
PWM Control
The MP28128 is a constant frequency peak-
current-mode control PWM switching regulator.
Refer to the functional block diagram. The high
side N-Channel DMOS power switch turns on at
the beginning of each clock cycle. The current in
the inductor increases until the PWM current
comparator trips to turn off the high side DMOS
switch. The peak inductor current at which the
current comparator shuts off the high side power
switch is controlled by the COMP voltage at the
output of feedback error amplifier. The
transconductance from the COMP voltage to the
output current is set at 11.25A/V.
Over current Protection
The MP28128 offers cycle-to-cycle current
limiting for both high-side and low-side switches.
The high-side current limit is relatively constant
regardless of duty cycles. When the output is
shorted to ground, causing the output voltage to
drop below 70% of its nominal output, the IC is
shut down momentarily and begins discharging
the soft start capacitor. It will restart with a full
soft-start when the soft- start capacitor is fully
discharged. This hiccup process is repeated until
the fault is removed.
This current-mode control greatly simplifies the
feedback compensation design by approximating
the switching converter as a single-pole system.
Only Type II compensation network is needed,
which is integrated into the MP28128. The loop
bandwidth is adjusted by changing the upper
resistor value of the resistor divider at the FB pin.
The internal compensation in the MP28128
simplifies the compensation design, minimizes
external component counts, and keeps the
flexibility of external compensation for optimal
stability and transient response.
Power Good Output (POK PIN)
The MP28128 includes an open-drain Power
Good output that indicates whether the regulator
output is within ±10% of its nominal output.
When the output voltage moves outside this
range, the POK output is pulled to ground. There
is a 30µs deglitch time when the POK output
change its state.
Enable and Frequency Synchronization
(EN/SYNC PIN)
Bootstrap (BST PIN)
The gate driver for the high-side N-channel
DMOS power switch is supplied by a bootstrap
capacitor connected between the BS and SW
pins. When the low-side switch is on, the
capacitor is charged through an internal boost
diode. When the high-side switch is off and the
low-side switch turns on, the voltage on the
bootstrap capacitor is boosted above the input
voltage and the internal boost-strap diode
prevents the capacitor from discharging.
This is a dual function input pin. Forcing this pin
below 0.4V for larger than 4us shuts down the
part; forcing this pin above 1.6V for larger than
4µs turns on the part. Applying a 1MHz to 2MHz
clock signal to this pin also synchronizes the
internal oscillator frequency to the external clock.
When the external clock is used, the part turns
on after detecting the first few clocks regardless
of duty cycles. If any ON or OFF period of the
clock is longer than 4µs, the signal will be
intercepted as an enable input and disables the
synchronization.
Soft-Start and Output Pre-Bias Startup
When the soft-start period starts, an internal
current source begins charging an internal soft-
start capacitor. During soft-start, the voltage on
the soft-start capacitor is connected to the non-
inverting input of the error amplifier. The soft-start
period lasts until the voltage on the soft-start
capacitor exceeds the reference voltage of 0.8V.
At this point the reference voltage takes over at
MP28128 Rev. 0.92
1/6/2016
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© 2016 MPS. All Rights Reserved.
7
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
V
OUTx(VIN - VOUT)
APPLICATION INFORMATION
L =
V
INxΔI xfOSC
L
Output Voltage Setting
where ∆IL is Inductor Ripple Current. Choose
inductor ripple current approximately 30% of the
maximum load current.
The external resistor divider sets the output
voltage (see Page 1). The feedback resistor R1
also sets the feedback loop bandwidth with the
internal compensation (refer to description
function). The relation between R1 and feedback
loop bandwidth (fC), output capacitance (CO) is as
following:
The maximum inductor peak current is:
ΔI
L
I
L(MAX) =ILOAD +
2
Under light load conditions, larger inductance is
recommended for improved efficiency.
1.24×106
R1(KΩ) =
fC(KHz)× CO(uF)
Input Capacitor Selection
The feedback loop bandwidth (fC) is no higher
than 1/10 of switching frequency of MP28128. In
the case of ceramic capacitor as CO, it’s usually
set to be in the range of 50 kHz and 150 kHz for
optimal transient performance and good phase
margin. If electrolytic capacitor is used, the loop
bandwidth is no higher than 1/4 of the ESR zero
frequency (fESR). fESR is given by:
The input capacitor reduces the surge current
drawn from the input and the switching noise
from the device. The input capacitor impedance
at the switching frequency shall be less than
input source impedance to prevent high
frequency switching current passing to the input
source. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of
their low ESR and small temperature coefficients.
For most applications, a 47µF capacitor is
sufficient.
1
fESR
=
2π×RESR× CO
For example, choose fC=70 kHz with ceramic
capacitor, CO=47uF, R1 is estimated to be 400kꢀ.
R2 is then given by:
Output Capacitor Selection
The output capacitor keeps output voltage ripple
small and ensures a stable regulation loop stable.
The output capacitor impedance shall be low at
the switching frequency. Ceramic capacitors with
X5R or X7R dielectrics are recommended. If
electrolytic capacitor is used, pay attention to
output ripple voltage, extra heating, and the
selection of feedback resistor R1 (refer to “Output
Voltage Setting” section) due to large ESR of
electrolytic capacitor. The output ripple ∆VOUT is
approximately:
R1
R2 =
VOUT -1
0.8V
Table 1—Resistor Selection vs. Output
Voltage Setting
VOUT
(V)
R1
R2
L
(μH)
COUT
(ceramic)
(kΩ) (kΩ)
1.2
1.5
1.8
2.5
3.3
400
400
400
400
400
806 0.47μH-1μH
453 0.47μH-1μH
316 0.47μH-1μH
187 0.47μH-1μH
127 0.47μH-1μH
47μF
47μF
47μF
47μF
47μF
V
OUTx(VIN - VOUT
)
1
ΔVOUT
≤
x(ESR+
)
V
INxfOSCxL
8xfOSCxC
3
Inductor Selection
A 0.47µH to 1µH inductor with DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For best efficiency, the inductor DC resistance
shall be <10mꢀ. For most designs, the
inductance value can be derived from the
following equation:
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
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© 2016 MPS. All Rights Reserved.
8
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
1) For MP28128, a PCB layout with more than
(or) four layers is recommended.
External Schottky Diode
For this part, an external schottky diode is
recommended to be placed close to "SW" and
"GND" pins, especially when the output current is
larger than 2A.
2) The high current paths (GND, IN and SW)
should be placed very close to the device with
short, direct and wide traces.
3) For MP28128, two input ceramic capacitors (2
x (10μF~22μF)) are strongly recommended to be
placed on both sides of the MP28128 package
and keep them as close as possible to the “IN”
and “GND” pins. If this placement is not possible,
a ceramic cap (10μF~47μF) must be placed
across PIN7-“IN”and PIN9-“GND” since the
internal Vcc supply is powered from PIN7, and
good decoupling is needed to avoid any
interference issues.
With the external schottky diode, the voltage
spike and negative kick on "SW" pin can be
minimized; moreover, the conversion efficiency
can also be improved a little.
For the external schottky diode selection, it's
noteworthy that the maximum reverse voltage
rating of the external diode should be larger than
the maximum input voltage. As for the current
rating of this diode, 0.5A rating should be
sufficient.
4) The external feedback resistors shall be
placed next to the FB pin. Keep the FB trace as
short as possible. Don’t place test points on FB
trace if possible.
PCB Layout Guide
PCB layout is very important to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance. If change
is necessary, please follow these guidelines as
follows. Here, the typical application circuit is
taken as an example to illustrate the key layout
rules should be followed.
5) Keep the switching node SW short and away
from the feedback network.
MP28128 Rev. 0.92
1/6/2016
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© 2016 MPS. All Rights Reserved.
9
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
Top Layer
Inner Layer-1
Inner Layer-2
Bottom Layer
Figure 2―Recommended PCB Layout of MP28128
Figure 3—Typical Application Circuit of MP28128
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
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© 2016 MPS. All Rights Reserved.
10
MP28128 – 2.5A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
3mm x 3mm QFN10
2.90
3.10
0.30
0.50
1.45
1.75
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
0.18
10
1
5
0.30
2.25
2.55
2.90
3.10
PIN 1 ID
INDEX AREA
0.50
BSC
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
1.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
0.70
0.25
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
2.50
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28128 Rev. 0.92
1/6/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
11
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