MP2624AGL_技术文档

MP2624A

4.5A, I²C-Controlled, Single-Cell USB/Adaptor Charger

with Narrow VDC Power-Path Management

USB OTG and SYS Reset Function

DESCRIPTION

FEATURES

The MP2624A is a 4.5A, highly integrated,

switching-mode, battery charger IC for single-

cell Li-ion or Li-polymer batteries. The

MP2624A supports NVDC architecture with

power path management and is suitable for

various portable applications. Its low impedance

power path optimizes efficiency, reduces

battery charging time, and extends battery life.

The I²C serial interface with charging and

system settings allows the device to be

controlled flexibly.



High-Efficiency 4.5A 1.7MHz Buck Charger

and 1.7MHz 1.3A Boost Mode to Support

OTG

o 94% Efficiency at 2A Charge Current

o Fast Charge Time By Battery Path

Impedance Compensation

o 94% Efficiency at 5V, 1.2A OTG

o Selectable OTG Current Outputs

3.9V to 7.0V Operating Input Voltage Range

Highest Battery Discharge Efficiency with

10mΩ Battery Discharge MOSFET up to 9A

Narrow System Bus Voltage Power Path

Management



The MP2624A supports a wide range of input

sources, including standard USB host ports and

wall adapters. The MP2624A detects the input

source type according to the USB Battery

Charging Spec 1.2 (BC1.2) and then informs

the host to set the proper input current limit. In

addition, the MP2624A supports USB On-The-

Go operation by supplying 5.0V with current up

to1.3A_.



o Instant On Works with No Battery or

Deeply Discharged Battery

o Ideal Diode Operation in Battery

Supplement Mode



Constant-Off-Time Control to Reduce

Charging Time under Lower Input Voltages

High Accuracy of Charging Parameter

I²C Port for Flexible System Parameter

Setting and Status Reporting



The power-path management regulates the

system voltage slightly above the set maximum

voltage between the battery voltage and the I²C

programmable lowest voltage level. With this

feature, the system is able to operate even

when the battery is depleted completely or

removed. When the input source current or

voltage limit is reached, power path

management reduces the charge current

automatically to meet the priority of the system

power requirement. If the system current

continues increasing, even when the charge

current is reduced to zero, the supplement

mode allows the battery to power the system

together with the input power supply

simultaneously.



Full DISC Control to Support System

Refresh

I²C Control and DISC Control to Support

Shipping Mode

High Integration

o Fully Integrated Power Switches

o Built-In Robust Charging Protection

o Built-In Battery Disconnection Function

High Accuracy

o ±0.5% Charge Voltage Regulation

o ±5% Charge Current Regulation

o ±5% Input Current Regulation

o ±2% Output Regulation in Boost Mode

Safety



The MP2624A is available in a QFN-22

(3mmx4mm) package.

o Battery Temperature Sensing for

Charge Mode

o Battery Charging Safety Timer

o Thermal Regulation and Thermal

Shutdown

o Battery System Over-Voltage Protection

o MOSFET Over-Current Protection

Charging Operation Indicator



MP2624A Rev. 1.02

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1

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG



Thermal Limiting Regulation on Chip



Tiny

QFN-22

(3mmx4mm)

Package

Mobile Internet Devices

APPLICATIONS



All MPS parts are lead-free, halogen-free, and adhere to the RoHS

directive. For MPS green status, please visit the MPS website under

Quality Assurance. “MPS” and “The Future of Analog IC Technology” are

registered trademarks of Monolithic Power Systems, Inc.

Tablet PCs

Smart Phones

TYPICAL APPLICATION

470nF

PMID

IN

BST

2.2µH

Load

VBUS

SW

4.7µF

1µF

4.7µF

22µF

PGND

USB/

Adapter

Port

SYS

BATT

VNTC

DM

DP

GND

VREF

22µF

10µF

Battery

100k 100k 100k

MP2624A

INT

NTC

OTG

CE

Host

AGND

SCL

SDA

1k

STAT

ILIM

100k

VSYS

VREF

DISC

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ORDERING INFORMATION

Part Number*

Package

Top Marking

MP2624AGL

QFN-22 (3mmx4mm)

See Below

* For Tape & Reel, add suffix –Z (e.g. MP2624AGL–Z)

TOP MARKING

MP: MPS prefix

Y: Year code

W: Week code

2624A: Product code of MP2624AGL

LLL: Lot number

PACKAGE REFERENCE

TOP VIEW

____

__

DM

22

INT

21

NTC

19

STAT

CE

20

18

17

16

15

14

13

12

1

2

3

4

5

6

DP

IN

DISC

BATT

SYS

SW

PMID

SW

PGND

VNTC

BST

OTG

7

8

9

10

11

SCL

SDA VREF ILIM AGND

QFN-22 (3mmx4mm)

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

PIN FUNCTIONS

Package

Pin #

Name

Type Description

Positive pin of the USB data line pair. DP and DM achieve USB host/charging

port detection automatically.

1

2

DP

I

Power input of the IC from the adapter or USB. Place a 1μF ceramic capacitor

from IN to PGND as close to the IC as possible.

IN

Power

Internal power. Connect PMID to the drain of the reverse-blocking MOSFET and

3

PMID

SW

Power the drain of the high-side MOSFET. Bypass with a 4.7μF capacitor from PMID to

PGND as close to the IC as possible.

4, 14

5

Power Switching node.

PGND Power Power ground.

Voltage source for NTC. VNTC is the pull-up voltage bias of the NTC comparator

resistive divider for both the feedback and the reference.

6

VNTC

O

7

8

SCL

SDA

I/O

I²C interface clock. Connect SCL to the logic rail through a 10kΩ resistor.

I²C interface data. Connect SDA to the logic rail through a 10kΩ resistor.

PWM low-side driver output. Connect a 10μF ceramic capacitor from VREF to

AGND as close to the IC as possible.

9

VREF

ILIM

P

I

Programmable input current limit. A resistor is connected from ILIM to ground to

set the minimum input current limit. The actual input current limit is the lowest setting

by ILIM and I²C.

10

11

AGND

I/O

Analog ground.

OTG mode enable control or input current limiting selection. On-The-Go is

enabled through the I²C. During OTG operation, OTG low suspends boost operation

while OTG high enable the operation again. If the input is detected as the USB host,

OTG is used as the input current limiting selection pin. When OTG is high, I_{IN_LMT}is

500mA. When OTG is low, I_{IN_LMT}is 100mA.

12

OTG

I

Bootstrap. Connect a 470nF bootstrap capacitor between BST and SW to form a

floating supply across the power switch driver to drive the power switch gate above

the supply voltage.

13

15

BST

SYS

P

System output. Connect a 2x22μF ceramic capacitor from SYS to PGND as close

to the IC as possible.

Battery positive terminal. Connect a 2x22μF ceramic capacitor from BATT to

PGND as close as possible to the IC.

16

17

BATT

DISC

P

I

Battery disconnection control.

Active low charge enable. Battery charging is enabled when the corresponding

-------

18

19

I

CE

register is set to active and CE is low.

Temperature sense input. Connect NTC to a negative temperature coefficient

thermistor. Program the hot and cold temperature windows with a resistor divider

from VNTC to NTC to AGND. The charge is suspended when VNTC is out of range.

NTC

--------------

20

21

O

Indicator for charging operation.

STAT

Open-drain interrupt output. INT sends the charging status, and the fault

interrupts the host.

INT

DM

Negative pin of the USB date line pair. DM and DP achieve USB host/charging

port detection automatically.

22

I

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Thermal Resistance ⁽⁵⁾θ_JA

QFN-22 (3mmx4mm)..............48....... 11... °C/W

θ_JC

----------------

IN, PMID, STAT to GND.............. -0.3V to +20V

SW to GND............-0.3V (-2V for 20ns) to +20V

BST to GND…………........................SW to +6V

BATT, SYS to GND………………. . -0.3V to +6V

All other pins to GND..................... -0.3V to +6V

STAT, INT sink current .............................10mA

NOTES:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is a function of the

maximum junction temperature T_J(MAX), the junction-to-

ambient thermal resistance θ_JA, and the ambient temperature

T_A. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by P_D(MAX) = (T_J

(MAX)-T_A)/θ_JA. Exceeding the maximum allowable power

dissipation produces an excessive die temperature, causing

the regulator to go into thermal shutdown. Internal thermal

shutdown circuitry protects the device from permanent

damage.

(2)

Continuous power dissipation (T_A= +25°C)

..................................................................2.6W

Junction temperature…............................150°C

Lead temperature (solder) .......................260°C

Storage temperature….. ..........-65°C to +150°C

3) The device is not guaranteed to function outside of its

operating conditions.

4) The inherent switching noise voltage should not exceed the

absolute maximum rating on either BST or SW. A tight layout

minimizes switching loss.

Recommended Operating Conditions ⁽³⁾

V_INto GND…………………….......3.9V to 7.0V

(4)

5) Measured on JESD51-7, 4-layer PCB.

I_IN......................................................... Up to 3A

I_SYS.................................................... Up to 4.5A

I_CHG................................................... Up to 4.5A

V_BATT............................................. Up to 4.425V

I_DCHG.................................(Continuous) up to 6A

I_DCHG..........................................(Pulse) up to 9A

Operating junction temp. (T_J) ...-40°C to +125°C

MP2624A Rev. 1.02

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ELECTRICAL CHARACTERISTICS

V_IN= 5V, T_A= 25°C, unless otherwise noted.

Parameter

Symbol Condition

Min

Typ

Max

Units

Step-Down Converter

Input voltage range

V_IN

3.9

7.0

65

70

V

V_IN= 5V, both DC/DC and

battery FET are disabled

Input shutdown current

μA

V_IN= 7.0V, both DC/DC and

battery FET are disabled

V_IN> V_{IN_UVLO}, V_IN> V_BATT

,

charge disabled, switching,

SYS float

3

5

mA

Input quiescent current

V_IN> V_{IN_UVLO}, V_IN> V_BATT

,

charge enabled, switching

BATT and SYS float

5

Input under-voltage lockout

V_{IN_UVLO}hysteresis

V_{IN_UVLO}V_INrising

3.45

200

3.6

V

V_INfalling

mV

V_INrising

V_INfalling

200

65

250

90

300

115

mV

V_INvs V_BATTheadroom

Internal reverse-blocking

MOSFET on resistance

R_{IN to PMID}Measure from IN to PMID

25

35

mΩ

High-side NMOS on resistance

Low-side NMOS on resistance

R_{H_DS}

R_{L_DS}

Measure from PMID to SW

Measure from SW to PGND

25

28

35

mΩ

High-side NMOS peak current

limit

7.5

A

Low-side NMOS peak current

limit

7

A

Switching frequency

V_BATT= 4.2V, I_CHG= 2A

1.4

1.7

2.0

MHz

SYS Output

I_SYS= 0, V_BATT= 3.4V, POR

V_{SYS_MIN}default, REG01 Bit[2:0] =

110

Minimum system regulation

voltage [I²C]

3.6

V

50mV or 100mV

(REG01Bit[0]) higher than

System regulation voltage

V_{SYS_MAX}

3.53

4.525

V_{BATT_FULL}depends on the

I²C setting

Ideal diode forward voltage in

supplement mode

V_{F_IDD}

50mA discharge current

24

40

mV

SYS/BAT comparator

V_SYSfalling

V_BATTrising to the battery

FET being turned on

completely

Battery good comparator

(threshold compared with

60

mV

V_{SYS_MIN}

)

V_BATTfalling

-40

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 5V, T_A= 25°C, unless otherwise noted.

Parameter

Symbol Condition

Min

Typ

Max

Units

Battery Charger

Depends on the I²C setting

V_{BATT_FULL}default (REG04 Bit04[7:2] =

110000): 4.2V

Battery charge full voltage

[I²C]

3.48

4.425

V

Charge voltage regulation

accuracy

V_{BATT_FULL}= 4.2V

Depends on the I²C setting

I_CHG= 2A

-0.5

0.512

-5

0.5

4.544

5

%

A

Constant current charge

current [I²C]

Charge current regulation

accuracy

%

V

Battery pre-charge threshold

[I²C]

REG04 Bit[4] = 1,

V_{BATT_PRE}

2.8

3.0

3.1

V_BATTrising

Battery pre-charge hysteresis

Battery short threshold

V_BATTfalling

220

2.1

mV

V

V_{BATT_SHORT}V_BATTrising

2.0

64

2.2

Battery short threshold

hysteresis

V_BATTfalling

230

128

mV

mA

Trickle-charge current

Pre-charge current [I²C]

I_TC

V_BATT= 1.8V

1024

I_PRE

Depends on the I²C setting

Pre-charge current accuracy

Termination current [I²C]

V_BATT= 2.6V, I_PRE= 256mA

Depends on the l²C setting

-25

25

%

I_BF

128

1024

mA

V_{BATT_FULL}= 4.2V,

I_BF= 512mA

Termination current accuracy

-30

30

%

Recharge threshold below

V_{BATT_FULL}

V_RECH

REG04 Bit[0] = 1

100

20

mV

ms

mΩ

Recharge threshold delay

BATT to SYS FET on

resistance

R_BATFETV_BATT= 3.8V

V_IN= 0V, V_BATT= 3.8V,

10

15

Battery discharge peak

current limit

I_{DSG_LMT}

11⁽⁶⁾

A

s

OTG disabled, I_SYSrising

DISC pulled low, time period

to turn off the battery

discharge function

7.5

9.5

Battery discharge function

controlled by DISC

t_DISC

Off time before auto-on

0.5

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 5V, T_A= 25°C, unless otherwise noted.

Parameter

Symbol Condition

Min

Typ

Max

Units

Input Voltage and Input Current-Based Power Path

Input voltage regulation

V_{IN_REG}

3.9

-4

5.1

4

V

threshold [I²C]

Input voltage regulation

accuracy

REG00 Bit[6:3] = 1011,

V_{IN_REG}= 4.76V

%

USB100

70

100

150

500

USB150

120

Input current limit

I_{IN_LMT}

mA

USB500

400

750

USB900

900

I_{IN_LMT}= 1.8A,

REG00 Bit[2:0] = 101

Input current limit accuracy

1450

1800

Protection

Rising, compared to

V_{BATT_FULL}

Battery over-voltage protection V_{BATT_OVP}

200

68

mV

°C

Battery over-voltage protection

hysteresis

Compared to V_{BATT_FULL}

Thermal shutdown rising

T_{J_SHDN}T_Jrising

184

threshold⁽⁶⁾

Thermal shutdown hysteresis

20

71.5

1.4

°C

%

(6)

NTC low temp rising threshold

V_COLDAs a percentage of V_VNTC

As a percentage of V_VNTC

70.9

68.6

72.1

69.8

NTC low temp rising threshold

hysteresis

NTC cool temp rising

threshold

V_COOLAs a percentage of V_VNTC

As a percentage of V_VNTC

69.2

1.3

%

NTC cool temp rising

threshold hysteresis

NTC warm temp falling

threshold

V_WARMAs a percentage of V_VNTC

As a percentage of V_VNTC

55.9

47.9

56.5

1.4

57.1

49.1

NTC warm temp falling

threshold hysteresis

NTC hot temp falling threshold

V_HOT

As a percentage of V_VNTC

48.5

1.3

NTC hot temp falling threshold

hysteresis

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 5V, T_A= 25°C, unless otherwise noted.

Parameter

VREF LDO

Symbol Condition

Min

Typ

Max

Units

V_IN= 10V, I_VREF= 40mA

4.82

5

VREF LDO output voltage

V

V_IN= 5V, I_VREF= 20mA

V_VREF= 4V

4.8

VREF LDO current limit

OTG Boost Mode

50

mA

Battery operating range

V_{BATT_OTG}

2.5

4.5

20

V

V_IN

<

V_{IN_UVLO}

,

μA

V_{BATT_OTG}= 4.2V,

battery FET is off

Battery discharge current

I_{BATT_OTG}

V_IN

<

V_{IN_UVLO}

35

2

μA

V_{BATT_OTG}= 4.2V,

battery FET is on

OTG output voltage

V_{IN_OTG}I_OTG= 0A

5.15

V

%

As percentage of V_{IN_OTG}

I_OTG= 0A

,

OTG output voltage accuracy

Battery operation UVLO

-2

V_{BATT_UVLO}V_BATTfalling

2.5

V

Battery operation UVLO

hysteresis

260

mV

V_BATT

=

3.7V, OTG is

OTG output voltage

protection threshold

V_{OTG_OVP}enabled, force a voltage at

IN until switching is off

5.75

175

V

OTG output voltage

protection threshold

hysteresis

mV

Falling

V_{OTG_SHORT}

V_BATT+ 0.1

4.65

OTG overload short-circuit

threshold⁽⁶⁾

V

A

Rising

REG02 Bit[1:0]

V_BATT= 3.7V

=

00,

01,

0.5

1.3

0.6

0.7

1.7

OTG output current limit [I²C]

I_OLIM

REG02 Bit[1:0]

V_BATT= 3.7V

1.5

NOTE:

6) Guaranteed by design.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 5V, T_A= 25°C, unless otherwise noted.

Parameter

Symbol Condition

Min

Typ

Max

Units

DP/DM USB Detection

DP voltage source

V_{DP_SRC}

I_{DP_SRC}

0.5

7

0.6

0.7

13

V

Data connect detect current

source

μA

DM sink current

I_{DM_SINK}

I_{DP_LKG}

50

-1

100

150

1

μA

V

Leakage current input

DP/DM

I_{DM_LKG}

-1

1

Data detect voltage

Logic low

V_{DAT_REF}

V_{LGC_LOW}

0.25

0.4

0.8

V

Session valid to connect

time for powered-up

peripheral

45

mins

Logic I/O Characteristics

Low-logic voltage threshold

V_L

0.4

V

High-logic voltage threshold

I²C Interface (SDA, SCL)

Input high threshold level

V_H

1.3

V_{PULL UP}= 1.8V,

SDA and SCL

V

V_{PULL_UP}= 1.8V,

SDA and SCL

Input low threshold level

Output low threshold level

I²C clock frequency

0.4

400

V

I_SINK= 5mA

F_SCL

kHz

Digital Clock and Watchdog Timer

Digital clock 1

F_DIG1

VREF LDO enabled

REG05 Bit[5:4] = 11

1400

1700

39

2000

kHz

Digital clock 2

F_DIG2

Watchdog timer

t_WDT

160

s

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= 5.0V, V_BATT= full range, I²C controlled, I_CHG= 4.5A, I_{IN_LMT}= 3.0A, V_{IN_REG}= 4.36V, L = 2.2μH,

T_A= 25°C, unless otherwise noted.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN= 5.0V, V_BATT= full range, I²C controlled, I_CHG= 4.5A, I_{IN_LMT}= 3.0A, V_{IN_REG}= 4.36V, L = 2.2μH,

T_A= 25°C, unless otherwise noted.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

BLOCK DIAGRAM

IN

PMID

25mΩ

DP

VREF

BST

USB

Port

DM

LDO

Power

Control

OTG

25mΩ

System

Output

SW

PWM

Driver

SDA

SCL

28mΩ

10mΩ

PGND

SYS

CE

I²C + Logic

Control +

Volatile

ILIM

Memory

INT

Linear

Charge&

Ideal Diode

Control

DISC

BATT

Li-ion

Battery

Pack

STAT

VSYS

NTC

MP2624A

NTC

Protection

VNTC

AGNG

Figure 1: Functional Block Diagram

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Narrow VDC Power Structure

OPERATION

The MP2624A employs a narrow VDC (NVDC)

power structure with the battery FET decoupling

the system from the battery, thus allowing

separate control between the system and the

battery. The system is always given priority to

start-up even with a deeply-discharged or

missing battery. When the input power is

available (even with a depleted battery), the

system voltage is always above the preset

minimum system voltage (V_{SYS_MIN}) set by the I²C

register REG01 Bit[3:1].

Introduction

The MP2624A is a highly integrated, I²C-

controlled, switching-mode battery charger IC

with NVDC power path management for single-

cell lithium-ion or lithium-polymer battery

applications. The MP2624A integrates a reverse-

blocking FET, a high-side switching FET, a low-

side switching FET, and a battery FET between

SYS and BATT. Its low impedance and high

efficiency allows higher current (4.5A) capacity

for a given package size.

As depicted in Figure 2, the NVDC power

structure is composed of a front-end, step-down,

DC/DC converter and a battery FET between

SYS and BATT.

Power Supply

The internal bias circuit of the MP2624A is

powered from the higher voltage of V_INand V_BATT

.

When V_INor V_BATTrises above the respective

UVLO threshold, the sleep comparator, battery

depletion comparator, and the battery FET driver

are active. The I²C interface is ready for

communication and all registers are reset to the

default value. The host can access all registers.

The DC/DC converter is a 1.7MHz, step-down,

switching regulator that adopts constant-off-time

(COT) control to provide power to the system,

which drives the system load directly and

charges the battery through the battery FET.

System voltage control has three scenarios:

Input Power Status Indication

The MP2624A qualifies the voltage and current

of the input source before start-up. The input

source has to meet the following requirements:

1. A minimum system voltage (V_{SYS_MIN}) can be

set via the register REG01 Bit[3:1]. When the

battery voltage is lower than V_{SYS_MIN}+ 60mV,

the system voltage is regulated at

Max(V_{SYS_MIN}, V_BATT) + ∆V, and the battery

FET works linearly to charge the battery with

a trickle-charge, pre-charge, or fast-charge

current through the battery FET, depending

on the battery voltage. ∆V can be set to

50mV or 100mV via the I²C register REG01

Bit[0].



V_IN> V_BATT+ 250mV

V_{IN_UVLO}< V_IN

OTG is not enabled by the host

Once the input power source meets the

conditions above, the system status register

REG08 Bit[2] asserts that the input power is good,

and DP/DM detection starts if enabled. Then the

step-down converter is ready to operate.

2. When the battery voltage exceeds V_{SYS_MIN}

60mV, the system voltage tracks the battery

voltage with voltage differential of

+

The conditions above are monitored continuously,

and the charge cycle is suspended if a condition

is outside one of the limits (see Figure 2).

a

(I_CHG•R_BATFET), where R_BATFETis the ON

resistance of the battery FET.

Charger IC

DC/DC Rails

3. When the charging is suspended or

completed, the system voltage is regulated

at ∆V higher than Max(V_{SYS_MIN}, V_BATT). ∆V

can be set to 50mV or 100mV via the I²C

register REG01 Bit[0].

or

DC/DC

Backlighting

3G Module

Battery

FET

Figure 2: NVDC Power Path Management

Structure

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14

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

V_SYSregulation is shown in Figure 3.

Phase 2: Pre-Charge

When the battery voltage exceeds V_{BATT_SHORT}

,

the MP2624A starts to pre-charge the depleted

battery safely until the battery voltage reaches

the "pre-charge to fast-charge threshold"

(V_{BATT_PRE}). If V_{BATT_PRE}is not reached before the

pre-charge timer expires ,the charge cycle ends,

and a corresponding timeout fault signal is

asserted. The pre-charge current can be

programmed via the I²C register REG03 Bit[7:4].

Phase 3: Constant-Current Charge

When the battery voltage exceeds V_{BATT_PRE}set

via the REG04 Bit[1], the MP2624A enters a

constant-current charge (fast charge) phase. The

fast-charge current can be programmed as high

as 4.5A via the REG02 Bit[7:2].

Phase 4: Constant-Voltage Charge

When the battery voltage rises to the pre-

programmable charge-full voltage (V_{BATT_FULL}) set

via REG04 Bit[7:2], the charge current begins to

taper off.

The charge cycle is considered complete when

the charge current reaches the battery-full

termination threshold (I_BF) set via the REG03

Bit[3:0], assuming the termination function is

enabled by REG05 Bit[7] = 1. If I_BFis not reached

before the safety charge timer expires (see the

"Safety Timer" section), the charge cycle ends,

and the corresponding timeout fault signal is

asserted.

Figure 3: V_SYSVariation with V_BATT

Figure 4 shows the battery charge profile.

Battery Charge Profile

The MP2624A provides four main charging

phases: trickle charge, pre-charge, constant-

current charge, and constant-voltage charge.

Phase 1: Trickle Charge

When the input power is qualified as a good

power supply, the MP2624A checks the battery

voltage to decide if trickle charge is required. If

the battery voltage is lower than V_{BATT_SHORT}

(2.1V), a charging current of 128mA is applied on

the battery, which helps reset the protection

circuit in the battery pack.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Figure 4: Battery Charge Profile

--------

During the entire charging process, the actual

CE Control

charge current may be less than the register

setting due to other loop regulations, like

dynamic power management (DPM) regulation

(input current limit or input voltage regulation loop)

or thermal regulation. Thermal regulation reduces

the charge current, so the IC junction

temperature does not exceed the preset limit.

The multiple thermal regulation thresholds (from

60°C to 120°C) help system design meet thermal

requirements for different applications. The

junction temperature regulation threshold can be

set via REG06 Bit[1:0].

--------

CE is a logic input pin for enabling or disabling

battery charging functions while the DC/DC

converter continues operating. The battery

charging is enabled when the REG01 Bit[5:4] is

--------

set to 01 and CE is pulled to low logic.

Indication

Apart from multiple status bits designed in the I²C

registers, the MP2624A also has a hardware

----------------

status output pin (STAT). The status of STAT in

different states is shown in Table 1.

A new charge cycle starts when the following

conditions are valid:

Table 1: Operation Indications

----------------

Charging State

STAT



The input power is re-plugged.

Charging

Low

Battery charging is enabled by the I²C, and

Charging complete,

sleep mode, charge

disable

--------

High

CE is forced to a low logic.

No thermistor fault.



Charging suspended

Blinking at 1Hz

No safety timer fault.

Battery Over-Voltage Protection (OVP)

The MP2624A is designed with built-in battery

over-voltage protection. When the battery voltage

exceeds V_{BATT_FULL}+ 160mV, the MP2624A

suspends the charging immediately and asserts

a fault. When battery OVP occurs, only the

charging is disabled, and the DC/DC converter

continues operating.

No battery over voltage.

The BATT FET is not forced to turn off.

Automatic Recharge

When the battery is charged full or the charging

is terminated, the battery may be discharged

because of the system consumption or self-

discharge. When the battery voltage is

discharged below the recharge threshold, the

MP2624A starts

automatically.

a

new charging cycle

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

a) Charging Start-Up with Battery Absent

Battery Floating Detection

The MP2624A is capable of detecting whether a

battery is connected or not. The following

conditions initiate battery float detection:

Battery Always Present

V_SYS

4.2V

3.6V

V_BATT

2.1V



Charging is enabled.

Auto-recharge is triggered.

Battery OVP recovery.

1.5s

1s

b) Charging Start-Up with Battery Present

Before a charging cycle is initiated, the MP2624A

implements battery floating detection (see Figure

5). Under this condition, the detection block sinks

a 3mA current for 1.5 seconds to check if V_BATTis

lower than 2.1V. If V_BATTis higher than 2.1V, the

battery present is detected. Otherwise, the

MP2624A continues to source a 3mA current and

starts a 1 second timer to check when V_BATT

exceeds 3.6V. If V_BATTis still lower than 3.6V

when the 1 second timer expires, the battery

present is asserted. The system regulation

voltage is set to Max(V_{SYS_MIN}, V_BATT) + ∆V, and

the charging begins to soft start. Before the 1

second timer expires and once V_BATTrises up to

3.6V, the 3mA sink current source is disabled,

and the battery absent is detected. In this case,

the charging is disabled, and the system

regulation voltage is set to V_{BATT_FULL}+ ∆V.

Remove Battery

V_SYS

4.2V

3.6V

V_BATT

2.1V

V_BATT

1.5s

1s

c) Remove Battery during Charging

Figure 5: Battery Float Detection Examples

System Over-Voltage Protection (OVP)

The MP2624A always monitors the voltage at

SYS. When system over-voltage is detected

(V_SYS> V_{BATT_FULL}+ ∆V + 100mV), the DC/DC

converter is turned off, and the system is

powered by the battery via the battery FET. ∆V

can be set to 50mV or 100mV via the I²C register

REG01 Bit[0].

Battery floating detection flow is shown in Figure

6.

During heavy system load transient, System OVP

often happens when load transient from heavy to

light. The timer is suspend when system OVP, so

the timer may transfer between normal and

suspend frequently, the timer counter will receive

a fault timer clock signal, then fault timer out may

happen under this condition.

Battery Always Absent

V_SYS

4.2V

3.6V

2.1V

V_BATT

1.5s

1s

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17

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

1. EnChg

2. Auto-recharge

3. Battery OVP Recover

Battery

Dectection

Battery Present

As Default

Sink 3mA for 1.5s

V_BATT< 2.1V?

Yes

Battery Present

Source 3mA for 1s

No

Source 3mA, Start

1s Timer

Yes

No

1s Timer

Expired?

V_BATT> 3.6V?

Yes

No

Yes

Set the V_SYSto

Max (V_{SYS_MIN}, V_BATT) +

50mV or 100mV

1s Timer

Expired?

Disable 3mA Source

Current

Battery Present

No

Battery Absent

Charge Start

Set the V_SYSto

V_{BATT_FULL}+ 50mV or 100mV

Disable Charge

Figure 6: Battery Float Detection Flow

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18

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Input Voltage Based and Input Current Based

Power Management

input voltage from dropping when DPM occurs. If

the input source is still overloaded, even when

the charge current has decreased to zero, the

system voltage starts to fall off. Once the system

voltage falls below the battery voltage, the

MP2624A enters battery supplement mode.

The battery powers the system together with the

DC/DC converter simultaneously.

To meet the maximum current limit for the USB

specification and avoid overloading the adapter,

the MP2624A uses both input current and input

voltage power management by continuously

monitoring the input current and input voltage.

The total input current limit is programmable to

prevent the input source from being overloaded.

When the input current hits the limit, the charge

current tapers off to keep the input current from

increasing further.

An ideal diode mode is designed in the MP2624A

to optimize the control transition between the

battery FET and DC/DC converter. The battery

FET enters ideal diode mode under the following

conditions:

If the preset input current limit is higher than the

rating of the adapter, the back-up input voltage

based power management works to prevent the

input source from being overloaded. When the

input voltage falls below the input voltage

regulation threshold due to the heavy load, the

charge current is reduced to keep the input

voltage from dropping further.



Charging start-up when V_BATT> V_{SYS_MIN}+ ∆V.

When V_BATT< V_{SYS_MIN}+ ∆V, if the system

voltage drops below the battery voltage, the

battery FET enters ideal diode mode.

During ideal diode mode, the battery FET

operates as an ideal diode. When the system

voltage is 40mV below the battery voltage, the

battery FET turns on and regulates the gate

driver of the battery FET. The voltage drop (V_DS)

of the battery FET remains around 20mV. As the

discharge current increases, the battery FET

obtains a stronger gate drive and a smaller on-

state resistance (R_DS) until the battery FET is fully

on.

During CV mode, while battery voltage has been

charged to the value only 100mV lower than the

battery full threshold, if the power path

management happens and charge current drops

be lower than I_BF, the charge full will be fault

detected.

The operation of the power path management is

applied in the following two cases:

NTC (Negative Temperature Coefficient)

Thermistor

As mentioned in the "NVDC Power Structure"

section,

“Thermistor” is the generic name given to a

thermally sensitive resistor. Generally, a negative

temperature coefficient thermistor is called a

thermistor. Depending on the manufacturing

method and the structure, there are many

thermistor shapes and characteristics for various

applications. The thermistor resistance values,

unless otherwise specified, are classified at a

standard temperature of 25°C. The resistance of

a temperature is solely a function of its absolute

temperature.

a) When V_BATT< V_{SYS_MIN}+ 60mV, the system

voltage is regulated at Max(V_{SYS_MIN}, V_BATT) +

∆V. If the input current or voltage regulation

threshold is reached, the system voltage loop

loses control of the DC/DC converter, which

causes system voltage drops. Once the

system voltage drops by (2%•V_{SYS_MIN}), the

charge current decreases to keep the system

voltage from dropping further.

b) When V_BATT> V_{SYS_MIN}+ 60mV (since the

battery is connected to the system directly

due to the free transition between each

control loop), the charge current decreases

automatically when the input current limit or

the voltage regulation threshold is reached.

The mathematical expression, which relates to

the resistance and the absolute temperature of a

thermistor is shown in Equation (1):

1









R₁ R₂e^

(1)







T1 T2

Battery Supplement Mode

Where R1 is the resistance at the absolute

temperature T1, R2 is the resistance at the

During battery supplement mode, the charge

current is reduced to keep the input current or

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19

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

absolute temperature T2, and β is a constant

which depends on the material of the thermistor.

threshold (45°C < T_NTC< 60°C), and the hot

battery threshold (T_NTC> 60°C).

In charge mode, the MP2624A continuously

monitors the battery’s temperature by measuring

the voltage at NTC. This voltage is determined by

the resistive divider, whose ratio is produced by

the different resistances of the NTC thermistor

under different ambient temperatures of the

battery.

For a given NTC thermistor, these temperatures

correspond to V_COLD, V_COOL, V_WARM, and V_HOT

.

When V_NTC< V_HOTor V_NTC> V_COLD, the charging

is suspended, and the timer is suspended, too.

When V_HOT< V_NTC< V_WARM, the charge-full

voltage (V_{BATT_FULL}) is reduced by 150mV,

compared to the programmable battery-full

voltage. When V_COOL< V_NTC< V_COLD, the charging

current is reduced to half of the programmable

charge current. Figure 7 shows the JEITA control.

Maximum Charge Current 1C

0.5C

Separate Pull-Up Pin VNTC for NTC

Protection

As shown in Figure 8, a separate pull-up VNTC is

designed as the internal pull-up terminal of the

resistive divider for the NTC comparator. Both the

reference divider and the feedback divider are

connected together to VNTC. The VNTC is

connected to VREF via an internal switch (in

charge mode only).

Maximum Charge Voltage : 4.25V

(4.2V Typical)

4.15V Maximum

4.10V Maximum

Cold

Cool

Normal

Warm

T4

Hot

T5

T1

(0DegC)

T2

(10DegC)

T3

(45DegC) (50DegC) (60DegC)

VREF

Charge/

Discharge?

Figure 7: NTC Window

VNTC

MP2624A internally sets a pre-determined upper

and lower bound of the range. If the voltage at

NTC goes out of this range, which means the

temperature is outside the safe operating limit,

the charging is ceased unless the operating

temperature returns to a safe range.

R_T1

NTC

Protection

Cold

Hot

Cool

NTC

R_NTC

R_T2

Warm

To satisfy the JEITA requirement, the MP2624A

monitors four temperature thresholds: the cold

battery threshold (T_NTC< 0°C), the cool battery

threshold (0°C < T_NTC< 10°C), the warm battery

Figure 8: NTC Protection Circuit

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

POR or Host

Command

Check V_BUS

No

V_BUS>3.8V?

Yes

DCD

Start 500ms Timer

Enable I_{DP_SRC}(10µA)

Connect R_{DM_PULL_DOWN}(20kΩ)

DP< V_{DAT_REF}(0.325V) for

No

40ms?

Yes

No

500ms Timer Expires?

Release DP, DM

Yes

Primary

Detection

DM/DP Floating

Release DP/DM,

set I_{IN_LMT}at 100mA

Enable V_{DP_SRC}(0.6V)

Enable I_{DM_SINK}(50µA)

DM< V_{DAT_REF}(0.325V) after

56ms?

No

Yes

SDP

DCP/CDP

Release DP/DM,

set I_{IN_LMT}at

100mA (OTG=Low)

500mA(OTG=High)

Release DP/DM,

set I_{IN_LMT}at

1800mA

Figure 9: USB Detection Flow Chart

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

DM/DP USB Detection

Primary detection is used to distinguish between

the USB host (or SDP) and different types of

charging ports.

The USB ports in personal computers are

convenient places for portable devices to draw

current for charging batteries. If the portable

device is attached to a USB host or hub, then the

USB specification requires the portable device to

draw a limited current (100mA/500mA in USB2.0,

and 150mA/ 900mA in USB3.0). When the

device is attached to a charging port, it can draw

more than 1.5A.

During primary detection, the PD turns on the

V_{DP_SRC}on DP and the I_{DM_SINK}on DM. If the

portable device is attached to a USB host, DM is

low.

Figure 9 shows the USB detection flow chart.

To be compatible with the USB specification and

BC1.2, set the input current limit according to the

values listed in Table 2.

The MP2624A features input source detection

compatible

with

the

Battery

Charging

Specification Revision 1.2 (BC1.2) to program

the input current limit during default mode.

DP/DM detection can be forced in host mode by

writing 1 to REG07 Bit[7].

Table 2: Input Current Limit vs USB Type

DP/DM

Detection

REG08

Bit[7:6]

OTG

I_{IN_LMT}

Floating

SDP

X

100mA

500mA

1.8A

00

10

01

LOW

HIGH

X

When the input source is first applied, the input

current limit begins with 100mA by default. If the

input source passes the input source qualification,

the MP2624A starts DP/DM detection. The

DP/DM detection circuit is shown in Figure 10.

DCP

The USB detection runs as soon as VIN is

detected and is independent of the charge

enable status. After the DP/DM detection is

complete, the MP2624A sets the input current

limit according to Table 2 and asserts the USB

port type in REG08 Bit[7-6]. The host is able to

revise the input current limit as well according to

the USB port type asserted in REG08 Bit[7:6].

The DP/DM detection has two steps:

1. Data contact detection (DCD)

2. Primary detection

DCD detection uses a current source to detect

when the data pins have made contact during an

attach event. The protocol for data contact

detection is as follows:

DP

V_{DP_SRC}

V_{LGC_HI}



The power device (PD) detects V_INis

asserted.

I_{DP_SRC}

CHG_DET

V_{DAT_REF}



The PD turns on DP I_{DP_SRC}and the DM

pull-down resistor for 40ms.

I_{DM_SINK}



The PD waits for the DP line to be low.

The PD turns off I_{DP_SRC}and the DM pull-

down resistor when the DP line is

detected as low or the 40ms timer

expires.

DM

R_{DM_DWN}

DCD allows the PD to start primary detection as

soon as the data pins have made contact. Once

the data contact is detected, the MP2624A jumps

to primary detection immediately. If the data

contact is not detected, the MP2624A jumps to

primary detection automatically after 300ms from

the beginning of the DCD.

Figure 10: DP/DM Detection Circuit

When the detection algorithm is complete, the

DP and DM signal lines enter a high-Z (HZ) state

with an approximate 4pF capacitive load.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Input Current Limit Setting via ILIM

The safety timer is reset at the beginning of a

new charging cycle. It can also be reset by

For safe operation, the MP2624A has an

additional hardware pin (ILIM) to adjust the

maximum input current limit. It can be set by a

resistor connected from ILIM to GND. The actual

input current limit is the lower value between the

ILIM setting and the register setting value via I²C.

--------

toggling CE or writing 00 and 01 to the REG01

Bit[5:4] sequentially. The following actions restart

the safety timer:



A new charge cycle begins.

--------

Interrupt to Host (INT)

Toggling CE from low to high to low (charge

enable).

The MP2624A has an alert mechanism, which

can output an interrupt signal via INT to notify the

system of the operation by outputting a 256μs

low-state INT pulse. All of the events below can

trigger the INT output:



Writing REG01 Bit[5:4] from 00 to 01 (charge

enable).

Writing REG05 Bit[3] from 0 to 1 (safety timer

enable).



Good input source detected.

USB detection completed.

UVLO

Writing REG01 Bit[7] from 0 to 1 (software

reset).

The timer can be refreshed after timer out when

one of the following thing happens:

Charge completed.

Any fault in REG09 (watchdog timer fault,

OTG fault, thermal fault, safety timer fault,

battery OVP fault, or NTC fault).



The input power reset.

--------

Toggling CE from low to high to low (charge

When a fault occurs, the charge device sends out

an INT signal and latches the fault state in

REG09 until the host reads the fault register.

Before the host reads REG09, the charger device

will not send a new INT signal upon new fault

except for NTC faults. The NTC fault is not

latched and always reports the current thermistor

conditions.

enable).



Writing REG01 Bit[5:4] from 00 to 01 (charge

enable).

MP2624A adjusts automatically or suspends the

timer when a fault occurs.

The timer is suspended during the conditions

below:

In order to read the current fault status, the host

must read REG09 two times consecutively.

During the first reading, the host reads the fault

register status from the last INT. During the

second reading, the host reads the current fault

register status.



The battery is discharging.

System OVP occurs.

NTC hot or cold fault occurs..

If the input current limit, input voltage regulation,

or thermal regulation threshold is reached, the

rest of the timer is doubled by enable the 2X

timer in PPM function (REG07H Bit[6]=1). Once

the PPM operation is removed, the rest of the

timer returns to the original setting. This setting

may cause an application issue, if the IC

operates in and out of PPM frequently, the single

timer period will be divided, which causes false

timer out termination. The solution is to disable

the 2X timer function by set REG07H Bit[6] to 0.

Safety Timer

The MP2624A provides both a pre-charge and a

complete charge safety timer to prevent the

extended charging cycle due to abnormal battery

conditions. The total safety timer for both trickle

charge and pre-charge is 1 hour when the battery

voltage is lower than V_{BATT_PRE}. The complete

charge safety timer starts when the battery

enters a constant-current charge. The constant-

current charge safety timer can be programmed

by I²C. The safety timer feature can be disabled

via I²C. The safety timer does not operate in USB

OTG mode.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

VREF LDO Output

When the junction temperature reaches 150°C,

the PWM step-down converter enters shutdown

mode.

The VREF LDO supplies the internal bias circuits,

as well as the high-side and low-side FET gate

----------------

Host Mode and Default Mode

driver. The pull-up rail of STAT can be connected

to VREF as well. The VREF LDO is enabled once

OTG is enabled. In non-OTG mode, the internal

VREF LDO is enabled when the following

conditions are valid:

The MP2624A is a host-controlled device. After

the power-on reset, the MP2624A starts in the

watchdog timer expiration state or default mode.

All registers are in the default settings.



V_IN> 3.3V

Any write to the MP2624A makes it transition into

host mode. All device parameters are

programmable by the host. To keep the device in

host mode, the host must reset the watchdog

timer regularly by writing 1 to REG01 Bit[6]

before the watchdog timer expires. Once the

watchdog timer expires, the MP2624A resumes

default mode. Figure 12 shows the host mode

and default mode change flow chart.

No thermal shutdown

Both the internal LDO output and V_BATTare

passed to VREF via a PMOS. The internal LDO

output is delivered to VREF only when V_INis

greater than V_BATT+ 250mV.

The VREF power supply circuit is shown in

Figure 11.

Battery Discharge Function

S1

If only the battery is connected and the input

source is absent (but the OTG function is

disabled), the battery FET is turned on

completely when V_BATTis above the V_{BATT_UVLO}

threshold. The 10mΩ battery FET minimizes the

conduction loss during discharge, and VREF

LDO stays off. The quiescent current of the

MP2624A is as low as 20μA. The low ON

resistance and low quiescent current help extend

the running time of the battery.

IN

VREF

LDO

Control

BATT

S2

Figure 11: VREF Power Supply Circuit

There is an over-current limit designed in the

MP2624A to prevent system over current when

the battery is discharging. Once the discharged

current exceeds this limit (I_{DSG_LMT}in the EC table)

for 20μs blanking time, the discharge FET is

turned off. After a one second of recovery time,

the discharge FET is turned on again.

Thermal Regulation and Thermal Shutdown

The MP2624A continuously monitors the internal

junction temperature to maximize power delivery

and prevent overheating the chip. When the

internal junction temperature reaches the preset

threshold, the MP2624A starts to reduce the

charge current to prevent higher power

dissipation.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Figure 12: Host Mode and Default Mode

Battery Disconnect Function

In applications where the battery is not

removable, the MP2624A has a dedicated DISC

pin to cut off the path from the battery to the

system when the host has lost control. Once the

logic at DISC is set to low for more than t_DISC

seconds, the battery is disconnected from the

system by turning off the battery FET. After a 0.5

second off period, the battery FET is softly turned

on again to reset the power to the system (see

Figure 13).

In applications where the battery is not

removable, it is essential to disconnect the

battery from the system for shipping mode or to

allow the system power reset. The MP2624A

provides both shipping mode and system reset

mode for different applications.

The MP2624A can enter and exit shipping mode

through the I²C control to the REG07H Bit[5].

Writing 1 to REG07 Bit[5] turns off the battery

FET immediately when in battery discharge mode.

Writing 0 to REG07 Bit[5] turns the battery FET

on again.

0.5s

t_DISC

DISC

V_BATT

V_SYS

Figure 13: DISC Control Function

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25

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Boost Start-Up

Power the PMID Pin to 5V

Regulate the current at IIN _ LMT + 300 mA

Yes

No

V _BUS> 4. 6V ?

6ms timer expires?

Yes

8ms timer expires?

No

Yes

Turn off block switch

Start 8 ms timer

Turn on the block switch

Figure 14: OTG Boost Start-Up Flow

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

OTG Boost Function

and a corresponding fault register is set high to

indicate the fault.

The MP2624A is able to supply a regulated 5V

output at IN for powering the peripherals

compliant with the USB On-The-Go specification.

To ensure that the battery is not drained, the

MP2624A will not enter OTG mode if the battery

is below the battery UVLO threshold. In order to

enable OTG mode, the input voltage at IN must

be below 1.0V.

Any fault that occurs during boost operation sets

the fault register REG09 Bit[6] to 1.

In OTG mode, the MP2624A employs a fixed,

1.7MHz, PWM, step-up switching regulator. It

switches from PWM operation to pulse-skipping

operation at light load.

OTG Output CC Mode

Boost operation can be enabled when REG01

Bit[5:4] = 10/11 and OTG is high. The OTG

output current can be selected as 500mA

and1.3A, o via I²C (REG02 Bit[1:0]). During boost

mode, the status register REG08 Bit[7:6] is set to

11.

When in the OTG mode, the load at the V_INhas a

current limit, which could be set up to 2A via the

I²C REG02 Bit[1:0]. MP2624A could operate in

CC mode when the current limit is reached, and

V_INdoes not drop to the overload or short-circuit

threshold (<V_BATT+ 100mV) as shown in Figure

15. Therefore, MP2624A not only has the CC

mode during the charging process, but also has

CC mode operation in OTG mode for various

applications.

Boost operation is enabled only when the

following conditions are met:

 V_BATT> V_{BATT_UVLO}(rising 2.7V).

 OTG is high and REG01 Bit[5:4] = 10/11.

 Boost mode is enabled after a 200ms delay.

 V_IN< 1V.

V_IN

V_{OTG_REG}

Once OTG is enabled, if the voltage at V_INdoes

not rise above the USB UVLO (4.6V) level within

6ms, the IC turns off the block switch for 8ms and

regulates the switch linearly again for 6ms. The

condition repeats until the OTG voltage is higher

than 4.6V.

V_BATT+100mV

SCP

I_OTG

I_OLIM

When both charging and OTG are enabled, OTG

operation takes priority.

Figure 15: OTG Output U-I Curve

Impedance Compensation to Accelerate

Charging

Figure 14 shows the OTG boost start-up time

sequence. Once OTG is enabled, the MP2624A

boosts PMID to 5.0V first. Then the block FET is

Throughout the charging cycle, the constant-

voltage charging stage occupies large ratios. To

accelerate the charging cycle, it is better to have

the charging remain in the constant-current

charge stage for as long as possible.

regulated linearly with the current limit of I_OLIM

+

300mA. When V_IN_{_OTG}is charged higher than 4.6V

within 6ms, the block FET is turned on fully.

Otherwise, PMID tries to charge IN again after an

8ms off period. The condition repeats until V_{IN_OTG}

is higher than 4.6V.

MP2624A allows the user to compensate the

intrinsic resistance of the battery by adjusting the

charge full voltage threshold, according to the

charge current and internal resistance. In

addition, a maximum-allowed regulated voltage is

set for the sake of the safety condition. See

Equation (2):

The MP2624A provides output short-circuit

protection and output over-voltage protection. In

OTG mode, if V_INfalls to only 100mV higher than

V_BATT, the operation enters the 6ms linear control,

turns off for 8ms, and enters hiccup mode.

V_{BATT _REG} V_{BATT _FULL}Min I_{CHG_ ACT}R_{BAT _CMP},V_CLAMP





(2)

The MP2624A monitors the voltage at V_IN

OTG boost mode continuously. Once the V_IN

exceeds V_{OTG_OVP}, the MP2624A stops switching,

in

_OTG

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Where V_{BATT_REG}is the battery regulation voltage,

The IC operates as a slave device with the

address 4BH receiving control inputs from the

master device, like a microcontroller or a digital

signal processor.

The I²C interface supports both standard mode

(up to 100k bits) and fast mode (up to 400k bits).

V_{BATT_FULL}is the charge-full voltage set via the I²C

REG04 Bit[7:2], I_{CHG_ACT}is the real-time charge

current during the operation, R_{BAT_CMP}is the

compensated resistor to simulate the resistor of

the connection wire of the battery( it is selected

through the REG06 Bit[7:5]), and V_CLAMPis the

battery compensation voltage clamp (above

V_{BATT_FULL}) selected via REG06 Bit[4:2].

Both SDA and SCL are bidirectional lines,

connecting to the positive supply voltage via a

current source or pull-up resistor. When the bus

is free, both lines are HIGH. SDA and SCL are

open drain.

Sleep Mode

When the input power source is missing and

OTG is disabled, the MP2624A transitions into

sleep mode. During sleep mode, the battery

powers the internal circuit, and the internal VREF

LDO is turned off. The system is connected to

the battery through the battery FET, and IN is

bridged off from SYS by the reverse blocking

FET. In order to extend battery life during

shipping and storage, the MP2624A can turn off

the battery FET to minimize leakage.

The Data on the SDA line must be stable during

the HIGH period of the clock. The HIGH or LOW

state of the data line can change only when the

clock signal on the SCL line is LOW. One clock

pulse is generated for each data bit transferred

(see Figure 16).

Series Interface

The MP2624A uses I²C compatible interface for

flexible parameter settings and instantaneous

device status reporting. Only two bus lines are

required: a serial data line (SDA) and a serial

clock line (SCL).

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

SDA

SCL

Change of

data allowed

Data line stable;

data valid

Figure 16: Bit Transfer on the I²C Bus

All transactions begin with a START (S) and can

be terminated by a STOP (P). A HIGH-to-LOW

transition on the SDA line while the SCL line is

high defines a start condition. A LOW-to-HIGH

transition on the SDA line when the SCL line is

high defines a STOP condition.

START and STOP conditions are always

generated by the master. The bus is considered

busy after the START condition; it is considered

free after the STOP condition (see Figure 17).

SDA

SCL

START (S)

STOP (P)

Figure 17: Start and Stop Conditions

Every byte on the SDA line must be 8 bits long.

The number of bytes transmitted per transfer is

unrestricted. Each byte has to be followed by an

Acknowledge bit. Data is transferred with the

Most Significant Bit (MSB) first. If a slave cannot

receive or transmit another complete byte of data

until it has performed some other function, it can

hold the SCL line LOW to force the master into a

wait state (clock stretching). Data transfer then

continues when the slave is ready for another

byte of data and releases the SCL line (see

Figure 18).

Acknowledgement

signal from receiver

Acknowledgement

signal from slave

SDA

SCL

MSB

1

START or

repeated

START

STOP or

repeated

START

7

9

1

2

8

9

2

8

ACK

Figure 18: Data Transfer on the I²C Bus

The acknowledge takes place after every byte.

The acknowledge bit allows the receiver to signal

the transmitter that the byte was received

successfully and another byte may be sent. All

clock pulses, including the acknowledge 9^thclock

pulse, are generated by the master.

The transmitter releases the SDA line during the

acknowledge clock pulse, so the receiver can pull

the SDA line LOW and it remains HIGH during

the 9^thclock pulse. This is the “Not Acknowledge”

signal. The master can then generate either a

STOP to abort the transfer or a repeated START

to start a new transfer.

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

After the START, a slave address is sent. This

A zero indicates a transmission (WRITE), and a

one indicates a request for data (READ). The

complete data transfer is shown in Figure 19

though Figure 23.

address is 7 bits long followed by an 8^thbit a data

direction bit (bit R/W).

SDA

SCL

1-7

9

8

START

1-7

8

9

1-7

DATA

8

9

STOP

ADDRESS

ACK

R/W

ACK

DATA

Figure 19: Complete Data Transfer

1

7

1

8

1

8

1

S

Slave Address

0

ACK

Reg Address

ACK

Data Address

ACK

P

Figure 20: Single Write

1

7

1

8

1

7

1

8

1

Data

S

Slave Address

0

ACK

Reg Address

ACK

S

Slave Address

ACK

NCK

P

Figure 21: Single Read

1

7

1

8

1

S

Slave Address

0

ACK

Reg Address

ACK

8

1

8

1

8

1

Data to Addr+1

Slave Address

ACK

P

Figure 22: Multi-Write

1

7

1

8

1

7

1

S

Slave Address

0

ACK

Reg Address

ACK

S

Slave Address

1

ACK

8

1

8

1

8

1

Data @

Address

Data @ Addr+1

Data @ Addr+n

ACK

NCK

P

Figure 23: Multi-Read

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30

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

If the register address is not defined, the charger

IC sends back NACK and returns to an idle state.

Case2: When a fault occurs, an INT is sent to

host to the show that the fault occurred if host did

not read REG09 in time. When the fault

disappears and another fault occurs, the IC will

not send INT to the host, since the host did not

react to the previous interrupt, but REG09 will be

written as the current fault status. For example, if

there is a battery OVP fault, but it recovers

immediately, then a timer-out fault occurs, and

the IC does not send the INT again. But if the

host reads REG09, it reads the register’s current

state timer-out fault.

The charger device supports multi-read and

multi-write on REG00 through REG08.

The fault register REG09 records the fault status

in time and sends an interrupt signal (INT) to the

host to read the fault status:

Case1: if the fault disappears before the host

reads it, the host could read a normal status only.

For example, if the system OVP fault occurs but

recovers later, the fault register REG09 reports

the fault when the fault occurs and clears the

fault when the fault disappears. So, if the host

reads REG09 after the fault disappears, it reads

a normal status. Additionally, the fault register

REG09 supports multi-read.

Case3: The NTC fault is an exception to this

condition. Once the NTC fault occurs, an

interrupt is sent to the host by setting the REG09

status.

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31

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

I²C REGISTER MAP

IC Address: 4BH

Input Source Control Register/Address: 00H (Default: 0011 0000)

Bit

Symbol

Description

Read/Write

Default

0: Disable

1: Enable

Bit 7

EN_{_}HZ⁽⁸⁾

Read/Write

Default: Disable (0)

Input Voltage Regulation

Bit 6

Bit 5

Bit 4

Bit 3

V_{IN_REG}[3]

V_{IN_REG}[2]

V_{IN_REG}[1]

V_{IN_REG}[0]

640mV

320mV

160mV

80mV

Offset: 3.88V

Range:3.88V - 5.08V

Default: 4.36V (0110)

Read/Write

Input Current Limit

000: 100mA

001: 150mA

010: 500mA

011: 900mA

100: 1200mA

101: 1800mA

110: 2000mA

111: 3000mA

Bit 2

Bit 1

Bit 0

I_{IN_LMT}[2]

Default: SDP: 100mA

(000) or 500mA (010)

I

_{IN_LMT}[1]

Read/Write

Default: DCP/CDP:

1.8A (101)

_{IN_LMT}[0]

Power-On Configuration Register/Address: 01H (Default: 0001 1011)

Bit

Symbol

Description

Read/Write

Default

0: Keep current setting

1: Reset

Keep current register

setting (0)

Bit 7

Register reset

Read/Write

I²C watchdog

timer reset

0: Normal

1: Reset

Bit 6

Read/Write

Normal (0)

Charger Configuration

00: Charge disable

01: Charge battery

10/11: OTG

Bit 5

Mode [1]

Read/Write

Charge battery (01)

Bit 4

Mode [0]

Minimum System Voltage

Bit 3

Bit 2

Bit 1

V_{SYS_MIN}[2]

V_{SYS_MIN}[1]

V_{SYS_MIN}[0]

0.4V

0.2V

0.1V

Offset: 3V

Range: 3V - 3.7V

Default: 3.6V (110)

Read/Write

System Regulation Voltage Higher than Full Battery Voltage

0: 50mV

1: 100mV

Bit 0

V_{SYS_MAX}[0]

Default: 100mV (1)

NOTE:

7) This is used to turn off the DC/DC only. At this time, the system is powered by the battery.

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32

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Charge Current Control Register/Address: 02H (Default: 0010 0001)

Bit

Symbol

I_CHG[5]

I_CHG[4]

I_CHG[3]

I_CHG[2]

I_CHG[1]

I_CHG[0]

Description

2048mA

1024mA

512mA

Read/Write

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Offset: 512mA

Range: 512mA -

4544mA

Read/Write

256mA

Default: 1024mA

(001000)

128mA

64mA

USB OTG Current Limit

Bit 1

Bit 0

I_OLIM[1]

I_OLIM[0]

00: 500mA

01: 1.3A

Read/Write

1.3A (01)

Pre-Charge/Termination Current/Address: 03H (Default: 0011 0011)

Bit

Symbol

Description

Read/Write

Default

Pre-Charge Current

Bit 7

Bit 6

Bit 5

Bit 4

I_PRE[3]

I_PRE[2]

I_PRE[1]

I_PRE[0]

512mA

256mA

128mA

64mA

Offset: 64mA

Range: 64mA -

1024mA

Default: 256mA

(0011)

Read/Write

Termination Current

Bit 3

Bit 2

Bit 1

Bit 0

I_BF[3]

I_BF[2]

I_BF[1]

I_BF[0]

512mA

256mA

128mA

64mA

Offset: 64mA

Range: 64mA -

1024mA

Default: 256mA

(0011)

Read/Write

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Charge Voltage Control Register/Address: 04H (Default: 1100 0011)

Bit

Symbol

Description

Read/Write

Default

Charge Full Voltage

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

V_{BATT_FULL}[5]

480mV

240mV

120mV

60mV

V_{BATT_FULL}[4]

V_{BATT_FULL}[3]

V_{BATT_FULL}[2]

V_{BATT_FULL}[1]

V_{BATT_FULL}[0]

Offset: 3.48V

Range: 3.48V -

4.425V

Default: 4.2V

(110000)

Read/Write

30mV

15mV

Pre-Charge Threshold

Bit 1 V_{BATT_PRE}

0: 2.8V

1: 3.0V

Read/Write

3.0V (1)

Battery Recharge Threshold (below V_{BATT_FULL}

)

0: 200mV

1: 100mV

Bit 0

V_RECH

100mV (1)

Charge Termination/Timer Control Register/Address: 05H (Default: 1001 1000)

Bit

Symbol

Description

Read/Write

Default

Termination Setting

0: Disable

1: Enable

Bit 7

EN_BF

Read/Write

Enable (1)

Termination Indicator Threshold

0: Match I_BF

Bit 6

BF_STAT

1: Indicate before the actual

termination on START

Read/Write

Match I_BF(0)

I²C Watchdog Timer Limit

Bit 5

Bit 4

WATCHDOG [1]

WATCHDOG [0]

00: Disable timer

01: 40s

10: 80s

Read/Write

40s (01)

11: 160s

Safety Timer Setting

Bit 3 EN_TIMER

0: Disable

1: Enable

Enable timer (1)

Constant-Current Charge Timer (2x during PPM)

00: 5hrs

01: 8hrs

Bit 2

CHG_TMR [1]

Read/Write

5hrs (00)

(0)

10: 12hrs

11: 20hrs

Bit 1

Bit 0

CHG_TMR [2]

Reserved

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Compensation/Thermal Regulation Control Register/Address: 06H (Default: 0000 0011)

Bit

Symbol

Description

40mΩ

Read/ Write

Default

Bit 7

Bit 6

Bit 5

R_{BAT_CMP}[2]

R_{BAT_CMP}[1]

R_{BAT_CMP}[0]

Range: 0 - 70mΩ

Default: 0mΩ (000)

20mΩ

Read/Write

10mΩ

Battery Compensation Voltage Clamp (above V_{BATT_FULL}

)

Bit 4

Bit 3

Bit 2

V_CLAMP[2]

V_CLAMP[1]

V_CLAMP[0]

64mV

32mV

16mV

Range: 0 - 112mV

Default: 0mV (000)

Read/Write

Thermal Regulation Threshold

00: 60°C

01: 80°C

10: 100°C

11: 120°C

Bit 1

Bit 0

T_REG[1]

T_REG[0]

Default: 120°C (11)

Miscellaneous Operation Control Register/Address: 07H (Default: 0101 1011)

Bit

Symbol

Description

Read/Write

Default

0: Not in DP/DM detection

1: Force DP/DM detection

Not in DP/DM

detection (0)

Bit 7

USB_DET_EN

Read/Write

0: Disable 2x extended safety timer

1: Enable 2x extended safety timer

Bit 6

TMR2X_EN

Read/Write

Enable (1)

0: Enable

1: Turn off

Bit 5

Bit 4

Bit 3

BATFET_DIS

Reserved

Read/Write

Enable (0)

(0)

0: Disable

1: Enable

EN_NTC

Enable (1)

0: Enable

1: Disable

Bit 2

Bit 1

BATUVLO_DIS

INT_MASK [1]

Read/Write

(0)

0: No INT in CHG_FAULT

1: INT in CHG_FAULT

INT in CHG_FAULT

(1)

0: No INT in BAT_FAULT

1: INT in BAT_FAULT

INT in BAT_FAULT

(1)

Bit 0

INT_MAST [0]

Read/Write

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

System Status Register/Address: 08H (Default: 0000 0001)

Bit

Symbol

Description

Read/Write

Default

00: Unknown

01: Adaptor port

10: USB host

11: OTG

Unknown (00)

Bit 7

V_{BUS_STAT}[1]

(including no input or

DPDM detection

incomplete)

Read only

Bit 6

V_{BUS_STAT}[0]

00: Not charging

01: Trickle charge

10: Constant-current charge

11: Charge done

Bit 5

Bit 4

CHG_STAT [1]

CHG_STAT [0]

Read only

Not charging (00)

No PPM (0)

(no power path

management occurs)

0: No PPM

1: VINPPM or IINPPM

Bit 3

PPM_STAT

0: No power good

1: Power good

Bit 2

Bit 1

Bit 0

PG_STAT

Read only

No power good (0)

Normal (0)

0: Normal

1: Thermal regulation

THERM_STAT

VSYS_STAT

0: In VSYSMIN regulation

1: Not in VSYSMIN regulation

Not in VSYSMIN

regulation (1)

Fault Register/Address: 09H (Default: 0000 0000)

Bit

Symbol

Description

Read/Write

Default

0: Normal

1: Watchdog timer expiration

Bit 7

WATCHDOG_FAULT

Read only

Normal (0)

0: Normal

Bit 6

Bit 5

OTG_FAULT

1: VBUS overloaded, VBUS

OVP, or battery under-voltage

Read only

Normal (0)

CHG_FAULT [1]

00: Normal

01: Input fault (OVP or bad

source)

00: Thermal shutdown

11: Safety timer expiration

Read only

Normal (00)

Normal (0)

Bit 4

Bit 3

CHG_FAULT [0]

BAT_FAULT

0: Normal

1: Battery OVP

000: Normal

Bit 2

Bit 1

Bit 0

NTC_FAULT [2]

NTC_FAULT [1]

NTC_FAULT [0]

001: NTC cold

010: NTC cool

011: NTC warm

100: NTC hot

Read only

Normal (000)

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Vender/Part/Reversion Status Register/Address: 0AH (Default: 0000 0100)

Bit

Symbol

Description

Read/Write

Read only

Default

(0)

Bit 7

Bit 6

Reserved

(0)

Part Number

Bit 5

Bit 4

Bit 3

PN [2]

PN [1]

PN [0]

MP2624A (000)

Read only

(000)

(1)

0: Standard

1: JEITA

Bit 2

NTC_TYPE

Revision

Bit 1

Rev [1]

Rev [0]

Read only

(00)

Bit 0

MP2624A Rev. 1.02

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37

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

CONTROL FLOW CHART

Different Operations in Host Mode

I²C Ready for

Commnunication

No

OTG Enabled by Host?

Yes

V_IN>V_BATT

?

Yes

OTG Active?

No

USB Detection

Done?

Yes

OTG Boost

Operation

Charger Ready for

Operation

Sleep Mode

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

CONTROL FLOW CHART (continued)

Charging Process

Charger Ready for

Operation

v_SYS= Max (V_{SYS_MIN}, v_BATT) + ∆V

DC/DC Soft Start

∆V=50mV or 100mV

depending on I²C Setting

No

Done?

Yes

Charger Enabled by

Host?

No

Yes

Charger Enabled by

CE?

No

Yes

Battery Detection

Charge Disabled

v_SYS= Max (V_{SYS_MIN}, v_BATT) + ∆V

No

v_SYS= V_{BATT_FULL}+ ∆V

Battery Present or Not?

Yes

Charging Start

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

CONTROL FLOW CHART (continued)

Charging Process

Charging Start

Charge Mode?

V_BATT<V_{BATT_SC}

V_BATT= V_{BATT_FULL}

V_{BATT_GD}< V_BATT< V_{BATT_FULL}

V_{BATT_TC}< V_BATT< V_{BATT_GD}

V_BATT< V_{BATT_TC}

CV Charge

Battery FET On

v_SYS=V_{BATT_FULL+}I_CHG*R_BATFET

CC Charge

Battery FET On

v_SYS=v_BATT+ I_CHG*R_BATFET

TC Charge

v_SYS=V_{SYS_MIN}+ ∆V

Wake Up

v_SYS=V_{SYS_MIN}+ ∆V

CC Charge

v_SYS=V_{SYS_MIN}+ ∆V

No

V_BATT>V_{BATT_GD}

V_BATT>V_{BATT_TC}

?

V_BATT>V_{BATT_SC}?

I_CHG<I_BF

Yes

?

V_BATT=V_{BATT_FULL?}

Yes

∆V=50mV or 100mV

Charger “Off”,

Indicate battery full

v_SYS= v_BATT+ ∆V

depending on I²C Setting

Yes

No

v_BATT< V_RECH

?

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40

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

Although the maximum charge current can be set

APPLICATION INFORMATION

to a high 4.5A, the real charge current cannot

reach this value as the input current limit. For

most applications, allow for a large enough

margin to avoid reaching the peak current limit of

the high-side switch (7A, typically). The

maximum inductor current ripple is set to 1.0A

with 5V_IN(30% of the max load- about 3.5A

considering the input current limit); the inductor is

0.75μH. Select 1.0μH in the application with the

saturation current over 4.5A

Setting the Input Current Limit

The input current limit setting is set according to

the input power source. For an adapter input, the

input current limit can be set through I²C by the

GUI. To set a value that is not provided by the

I²C, the input current limit can be set through

ILIM. Connect a resistor from ILIM to AGND to

program the input current limit. The relationship

can be calculated using Equation (3):

Choose a larger inductance such as 2.2μH is

good for the EMI consideration with smaller

current ripple, while the size may be larger.

48.48

(3)

I_{IN_LMT}



（A）

R

_ILIM（k）

The MP2624A selects the smaller one of the I²C

and resistor settings for its input current limit

setting. For resistor setting, use 1% accuracy

resistor.

Selecting the Input Capacitor

The input current to the step-down converter is

discontinuous and therefore requires a capacitor

to supply AC current to the step-down converter

while maintaining the DC input voltage. Use low

ESR capacitors for the best performance.

Ceramic capacitors are preferred, but tantalum or

low ESR electrolytic capacitors are also sufficient.

Choose X5R or X7R dielectrics when using

ceramic capacitors.

For a USB input, the input current limit is set

according to Table 2.

Selecting the Inductor

Inductor selection is a trade-off between cost,

size, and efficiency. A lower inductance value

corresponds with a smaller size, but it results in a

Since the input capacitor (C_IN) absorbs the input

switching current, it requires an adequate ripple

current rating. The RMS current in the input

capacitor can be estimated with Equation (6):

higher ripple current,

a

higher magnetic

hysteretic loss, and a higher output capacitance.

Choosing a higher inductance value provides a

lower ripple current and smaller output filter

capacitors, but it may result in higher inductor DC

resistance (DCR) loss and larger size.







V_OUT

_^1

(6)

I_C I_LOAD











IN

V

IN

From a practical standpoint, the inductor ripple

current should not exceed 30% of the maximum

load current under worst-case conditions. When

operating with a typical 5V input voltage, the

maximum inductor current ripple occurs at the

corner point between the trickle charge and the

CC charge (VBATT = 3V). Estimate the required

inductance with Equation (4) and Equation (5):

Where V_OUTis V_SYS

.

The worst-case condition occurs at V_IN= 2V_OUT

shown in Equation (7):

,

I_CIN= I_LOAD/2

(7)

For simplification, choose an input capacitor with

an RMS current rating greater than half of the

maximum load current.

V  V_BATT

I_{L _MAX}V  f_S(MHz)

V_BATT

IN

(µH)

(4)

(5)

L 

For the MP2624A, the RMS current in the input

capacitor comes from PMID to GND, so a small,

high-quality, ceramic capacitor (e.g.: 4.7μF),

should be placed as close to the IC as possible

from VPMID to PGND. The remaining capacitor

should be placed from VIN to GND.

IN

%ripple

(A)

)

I_PEAK I_LOAD(MAX)(1

2

Where VIN is the typical input voltage, VBATT is the

battery voltage, f_Sis the switching frequency, and

When using ceramic capacitors, ensure they

have enough capacitance to provide a sufficient



I_{L_MAX}is the maximum inductor ripple current,

which is usually 30% of the CC charge current.

MP2624A Rev. 1.02

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41

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

charge to prevent excessive voltage ripple at the

Resistor Selection for the NTC Sensor

input.

Figure 8 shows an internal resistor divider

reference circuit that limits both the high and low

Selecting the Output Capacitor

temperature thresholds at V_{TH_High}and V_{TH_Low}

,

The output capacitor (C_SYS) from the typical

application circuit is in parallel with the SYS load.

C_SYSabsorbs the high-frequency switching ripple

current and smooths the output voltage. Its

impedance must be much less than the system

load to ensure it properly absorbs the ripple

current.

respectively. For a given NTC thermistor, select

an appropriate R_T1and R_T2to set the NTC

window using Equation (10) and Equation (11):

R_T2//R_{NTC_Cold}

V_COLD

V_NTC

(10)



R_T1R_T2//R_{NTC_Cold}

R_T2//R_{NTC_Hot}

V_HOT

Ceramic capacitors are recommended because

they have a lower ESR and a smaller size. This

allows the ESR of the output capacitor to be

ignored. Thus, the output voltage ripple is given

with Equation (8):

(11)



R_T1R_T2//R_{NTC_Hot}VCC

R_{NTC_Hot}is the value of the NTC resistor at a high

temperature (within the required temperature

operating range), and R_{NTC_Cold}is the value of the

NTC resistor at a low temperature.

V_SYS

1

ΔV_SYS

V

IN

(8)

Δr 



%

The two resistors (R_T1and R_T2)allow the high and

low temperature limits to be programmed

independently. With this feature, the MP2624A

can fit most types of NTC resistors and different

temperature operating range requirements.

2

V_SYS

8C_SYS f_SL

To guarantee ±0.5% system voltage accuracy,

the maximum output voltage ripple must not

exceed 0.5% (e.g.: 0.1%). The maximum output

voltage ripple occurs at the minimum system

voltage and the maximum input voltage.

The R_T1and R_T2values depend on the type of

NTC resistor selected. For example, for a 103AT

thermistor, the thermistor has the following

electrical characteristics: at 0°C, R_{NTC_Cold}

27.28kΩ, and at 60°C, R_{NTC_Hot}= 3.02kΩ.

For V_IN= 7V, V_{SYS_MIN}= 3.6V, L = 2.2µH, f_S=

1.6MHz, and r = 0.1%. The output capacitor can

be calculated as 11µF using Equation (9):

=

The following equation calculations are derived

assuming that the NTC window is between 0°C

and 50°C. According to Equation (10) and

V_{SYS_MIN}

1

V

IN

(9)

C_SYS



2

8 f_SL Δr

V_HOT

V_COLD

V_NTC

Equation (11), use

and

from the EC

Then choose a 22µF ceramic capacitor.

V_NTC

table to calculate R_T1= 2.27kΩ and R_T2= 6.86kΩ.

MP2624A Rev. 1.02

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

PCB Layout Guidelines

8. Connect the PCB ground plane directly to the

return of all components. It is recommended

to place it inside the PGND pads for the IC, if

possible.

Efficient PCB layout is critical for meeting

specified noise rejection requirements and

improving efficiency. For best results, follow the

guidelines below.

Typically, a star ground design approach is

used to keep the circuit block currents

isolated (high-power/low-power small signals),

which reduces noise coupling and ground-

bounce issues. A single ground plane for this

design produces good results. With this small

layout and a single ground plane, there is no

ground-bounce issue. Segregating the

components minimizes coupling between the

signals and stability requirements.

1. Route the power stage adjacent to the

grounds.

2. Minimize the high-side switching node (SW,

inductor) trace lengths in the high-current

paths and the current sense resistor trace.

3. Keep the switching node short and away from

all small control signals, especially the

feedback network.

9. Pull the connection wire from the MCU (I²C)

far away from the SW mode and copper

regions.

4. Place the input capacitor as close to PMID

and PGND as possible.

5. Place the output inductor close to the IC.

10. Keep SCL and SDA close in parallel.

6. Connect the output capacitor between the

inductor and PGND of the IC.

7. Connect the pins for the power pads (IN, SW,

SYS, BATT, and PGND) to as much copper

on the board as possible for high-current

applications.

This improves thermal performance because

the board conducts heat away from the IC.

MP2624A Rev. 1.02

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43

MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

TYPICAL APPLICATION CIRCUITS

R5

PMID

IN

INT

2k

R6

VREF

VBUS

USB/

Adaptor

Port

STAT

4.7uF

C3

1k

4.7uF 1uF

C1 C2

PGND

DM

BATT

SYS

SW

C7

22uF

Battery

Load

1.0uH

DP

MP2624A

C4

1uF

VNTC

RT1

10k

L1

C8

GND

SW

22uF

NTC

R_NTC

10k

470nF

C6

RT2

15k

BST

100k

R2

VREF

AGND

DISC

MPS I2C

Connector

100k

R3

R4

OTG

/EN

SCL

SDA

C5

10uF

R1

30.9k

Figure 24: Typical Application Circuit of MP2624A with 5VIN

Table 3. The BOM of the Key Components

Description

Qty

Ref

Value

Package

Manufacture

Ceramic Capacitor;10V;

X5R or X7R

1

C1

C2

4.7μF

1206

Any

Ceramic Capacitor;10V;

X5R or X7R

1

1μF

4.7μF

1μF

0603

0805

0603

Any

Ceramic Capacitor;10V;

X5R or X7R

C3

C4

C5

Ceramic Capacitor;6.3V;

X5R or X7R

Ceramic Capacitor;6.3V;

X5R or X7R

10μF

Ceramic Capacitor;16V;

X5R or X7R

Ceramic Capacitor;10V;

X5R or X7R

1

2

C6

470nF

0603

1206

Any

C7,C8

22μF

1

RT1

RT2

10k

15k

Film Resistor;1%

Film Resistor;1%;

0603

Any

Inductor;1.0μH;Low

DCR;I_SAT>5A

1

L1

1.0μH

SMD

Any

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MP2624A – 4.5A, SW CHARGER W/ I²C CONTROL, NVDC POWER PATH, USB OTG

PACKAGE INFORMATION

QFN-22 (3mmx4mm)

PIN1 ID

MARKING

PIN 1 ID

0.20X0.10

PIN 1 ID

INDEX AREA

TOP VIEW

BOTTOM VIEW

SIDE VIEW

0.10x45?

0.20x0.10

NOTE:

1) ALL DIMENSIONS ARE IN

MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES

NOT INCLUDE MOLD FLASH.

3) LEAD COPLANARITY SHALL BE

0.10 MILLIMETERS MAX.

4) JEDEC REFERENCE IS MO-220.

5) DRAWING IS NOT TO SCALE.

RECOMMENDED LAND PATTERN

NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.

Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS

products into any application. MPS will not assume any legal responsibility for any said applications.

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45


型号：	MP2624AGL
厂家：	MONOLITHIC POWER SYSTEMS
描述：	4.5A, I2C-Controlled, Single-Cell USB/Adaptor Charger with Narrow VDC Power-Path Management USB OTG and SYS Reset Function
文件：	总45页 (文件大小：2006K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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