MP2107DQ [MPS]
4A, 6V Synchronous Step-Down Switching Regulator; 4A ， 6V同步降压型开关稳压器
| 型号： | MP2107DQ |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | 4A, 6V Synchronous Step-Down Switching Regulator |
| 文件： | 总14页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2107/MP2107A
4A, 6V Synchronous
Step-Down Switching Regulator
The Future of Analog IC Technology
DESCRIPTION
FEATURES
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4A Output Current
The MP2107 is an internally compensated
1.5MHz fixed-frequency PWM synchronous
step-down regulator. MP2107 operates from a
2.7V to 6V input and generates an output
voltage as low as 0.8V.
Input Operation Range: 2.7V to 6V
60mΩ Internal Power MOSFET Switches
All Ceramic Capacitor Design
Up to 95% Efficiency
1.5MHz Fixed Switching Frequency
Adjustable Output from 0.8V to 0.9xVIN
Internal Soft-Start
Frequency Synchronization Input
Power Good Output
Cycle-by-Cycle Current Limiting
Hiccup Short Circuit Protection
Thermal Shutdown
The MP2107 integrates a 80mΩ high-side
switch and a 60mΩ synchronous rectifier for
high efficiency without an external Schottky
diode. With peak current mode control and
internal compensation, the MP2107 based
solution delivers a very compact footprint with a
minimum component count.
The MP2107 is available in a small 3mm x 3mm
10-pin QFN package and the MP2107A is
available in an 8-pin SOIC package with an
exposed pad.
3mm x 3mm 10-pin QFN (MP2107) and
8-pin SOIC (MP2107A) Packages
APPLICATIONS
•
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µP/ASIC/DSP/FPGA Core and I/O Supplies
Printers and LCD TVs
Network and Telecom Equipment
Point of Load Regulators
“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs
Output Current
95
V
5V
IN
C3
100nF
90
IN
POK
BS
SW
5V to 1.8V
V
POK
(MP2107)
OUT
5V to 3.3V
85
1.8V / 4A
5V to 2.5V
80
EN/SYNC
GND
FB
OFF ON
75
70
0
1
2
3
4
OUTPUT CURRENT (A)
MP2107/MP2107A Rev. 1.1
10/13/2010
www.MonolithicPower.com
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© 2010 MPS. All Rights Reserved.
1
MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
ORDERING INFORMATION
Part Number
MP2107DQ*
MP2107ADN**
Package
Top Marking
Free Air Temperature (TA)
-40°C to +85°C
QFN10 (3mm x 3mm)
P2
SOIC8E
MP2107ADN
-40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP2107DQ–Z).
For RoHS Compliant packaging, add suffix –LF (e.g. MP2107DQ–LF–Z)
** For Tape & Reel, add suffix –Z (e.g. MP2107ADN–Z).
For RoHS Compliant packaging, add suffix –LF (e.g. MP2107ADN–LF–Z)
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
FB
GND
SW
IN
1
2
3
4
5
10 EN/SYNC
FB
GND
IN
1
2
3
4
8
7
6
5
EN/SYNC
SW
9
8
7
6
GND
SW
IN
SW
BS
VCC
BS
POK
EXPOSED PAD
ON BACKSIDE
CONNECT TO GND
EXPOSED PAD
ON BACKSIDE
CONNECT TO GND
Thermal Resistance (4)
QFN10 (3mm x 3mm).............50...... 12... °C/W
SOIC8E ..................................50...... 10... °C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
IN to GND ....................................-0.3V to +6.5V
SW to GND ...........................-0.3V to VIN + 0.3V
................................-2.5V to VIN+2.5V for <50ns
FB, EN/SYNC, POK to GND...........-0.3V to +6.5V
BS to SW .....................................-0.3V to +6.5V
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)
Continuous Power Dissipation (TA = +25°C)
QFN10 (3mm x 3mm) ................................ 2.5W
SOIC8E...................................................... 2.5W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Recommended Operating Conditions (3)
Supply Voltage VIN .............................2.7V to 6V
Output Voltage VOUT..................0.8V to 0.9 x VIN
Operating Junct. Temp (TJ)...... -40°C to +125°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP2107/MP2107A Rev. 1.1
10/13/2010
www.MonolithicPower.com
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
ELECTRICAL CHARACTERISTICS (5)
VIN = VEN = 3.6V, VCC = 5V (MP2107A Only), TA = +25°C, unless otherwise noted.
Parameters
Condition
Min
Typ
750
1
Max
Units
µA
VEN = VIN
Supply Current
Shutdown Current
VFB = 0.85V
VEN = 0V, VIN = 6V
µA
IN
Undervoltage
Lockout
Lockout
Rising Edge
2.59
2.69
V
Threshold
IN
Hysteresis
Undervoltage
210
mV
Regulated FB Voltage
FB Input Current
TA = +25°C
VFB = 0.85V
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
0.776
1.6
0.800
±50
0.824
0.4
V
nA
V
EN High Threshold
EN Low Threshold
Internal Soft-Start Time
Maximum Synch Frequency
Minimum Synch Frequency
Minimum On Time
V
120
2
1
50
90
10
-10
µs
MHz
MHz
ns
%
%
%
V
µs
°C
Maximum Duty Cycle
POK Upper Trip Threshold
POK Lower Trip Threshold
POK Output Voltage Low
POK Deglitch Timer
FB respect to the nominal value
FB respect to the nominal value
ISINK = 5mA
0.4
30
150
Thermal Shutdown Threshold
Hysteresis = 20°C
Note:
5) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.
MP2107/MP2107A Rev. 1.1
10/13/2010
www.MonolithicPower.com
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© 2010 MPS. All Rights Reserved.
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
PIN FUNCTIONS
SOIC QFN
Name
POK
IN
Description
Pin#
Pin#
Open Drain Power Good Output. “HIGH” output indicates VOUT is within ±10%
window. “LOW” output indicates VOUT is out of ±10% window. POK is pulled down
in shutdown.
–
6
Input Supply. A decoupling capacitor to ground is required close to these pins to
reduce switching spikes.
3
4, 7
3, 8
Switch Node Connection to the Inductor. These pins connect to the internal high
and low-side power MOSFET switches. All SW pins must be connected together
externally.
6, 7
SW
Ground. Connect these pins with larger copper areas to the negative terminals of
the input and output capacitors.
2
4
2, 9
5
GND
BS
Bootstrap. A capacitor between this pin and SW provides a floating supply for the
high-side gate driver.
Feedback. This is the input to the error amplifier. An external resistive divider
connects this pin between the output and GND. The voltage on the FB pin
compares to the internal 0.8V reference to set the regulation voltage.
1
1
FB
Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V
shuts down the part. Forcing this pin above 1.6V turns on the part. Applying a
1MHz to 2MHz clock signal to this pin synchronizes the internal oscillator frequency
to the external clock.
8
5
10
–
EN/SYNC
VCC
Logic circuitry bias supply. Connect directly to VIN or 3.3V to 5V supply. Bypass
with a low ESR 1µF ceramic capacitor as close to the pin as possible
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VCC = 5V (MP2107A Only), VO = 1.8V, L1 = 1.0µH, C2 = 47µF, TA = +25°C, unless otherwise noted.
Steady State Operation
Steady State Operation
Half Load
No Load
V
OUT
10mV/div.
V
OUT
10mV/div.
I
INDUCTOR
1A/div.
I
INDUCTOR
2A/div.
V
V
SW
SW
5V/div.
5V/div.
400ns/div.
400ns/div.
Steady State Operation
Load Transient
1A-4A Step Resistive Load
Full Load
V
OUT
10mV/div.
V
OUT
200mV/div.
I
INDUCTOR
2A/div.
V
SW
5V/div.
I
INDUCTOR
1A/div.
400ns/div.
Start-up through Enable
Start-up through Enable
No Load
Full Load
V
OUT
V
OUT
1V/div.
1V/div.
V
POK
2V/div.
V
POK
2V/div.
V
EN
V
EN
2V/div.
2V/div.
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VCC = 5V (MP2107A Only), VO = 1.8V, L1 = 1.0µH, C2 = 47µF, TA = +25°C, unless otherwise noted.
Shut-down through Enable
Shut-down through Enable
Full Load
No Load
V
OUT
2V/div.
V
OUT
1V/div.
V
EN
5V/div.
V
EN
2V/div.
V
V
POK
POK
2V/div.
2V/div.
1ms/div.
400ms/div.
Short Circuit Protection
Short Circuit Recovery
=5V, V
=1.8V
V
V
=5V, V =1.8V
OUT
IN
IN
OUT
V
OUT
V
OUT
1V/div.
1V/div.
V
sw
V
sw
5V/div.
5V/div.
I
INDUCTOR
2A/div.
I
INDUCTOR
2A/div.
1ms/div.
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
FUNCTIONAL BLOCK DIAGRAM
POK
0.88V
0.72V
IN
IN
+
--
EN
+
--
BS
EN/SYNC
LOGIC
EN
EN/SYNC
- -
+
EXCLK
OSC
PWM
CURRENT
COMPARATOR
LOGIC
CLK
SW
SW
SLOPE
0.5pF
1.2 MEG
17pF
SLOPE
COMPENSATION
AND PEAK
CURRENT LIMIT
COMP
--
+
+
FB
0.8V
GND
GND
SOFT
-START
Figure 1—Function Block Diagram (MP2107)
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
FUNCTIONAL DESCRIPTION
At this point the reference voltage takes over at
the non-inverting error amplifier input. The soft-
start time is internally set at 120µs. If the output
of the MP2107 is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches until the
voltage on the internal soft-start capacitor
exceeds the sensed output voltage at the FB pin.
PWM Control
The MP2107 is a constant frequency peak-
current-mode control PWM switching regulator.
Refer to the functional block diagram. The high
side N-Channel DMOS power switch turns on at
the beginning of each clock cycle. The current in
the inductor increases until the PWM current
comparator trips to turn off the high side DMOS
switch. The peak inductor current at which the
current comparator shuts off the high side power
switch is controlled by the COMP voltage at the
output of feedback error amplifier. The
transconductance from the COMP voltage to the
output current is set at 11.25A/V.
Over Current Protection
The MP2107 offers cycle-to-cycle current limiting
for both high-side and low-side switches. The
high-side current limit is relatively constant
regardless of duty cycles. When the output is
shorted to ground, causing the output voltage to
drop below 70% of its nominal output, the IC is
shut down momentarily and begins discharging
the soft start capacitor. It will restart with a full
soft-start when the soft-start capacitor is fully
discharged. This hiccup process is repeated until
the fault is removed.
This current-mode control greatly simplifies the
feedback compensation design by approximating
the switching converter as a single-pole system.
Only Type II compensation network is needed,
which is integrated into the MP2107. The loop
bandwidth is adjusted by changing the upper
resistor value of the resistor divider at the FB pin.
The internal compensation in the MP2107
simplifies the compensation design, minimizes
external component counts, and keeps the
flexibility of external compensation for optimal
stability and transient response.
Power Good Output (POK PIN)
The MP2107 includes an open-drain Power
Good output that indicates whether the regulator
output is within ±10% of its nominal output. When
the output voltage moves outside this range, the
POK output is pulled to ground. There is a 30µs
deglitch time when the POK output change its
state.
Enable and Frequency Synchronization
(EN/SYNC PIN)
This is a dual function input pin. Forcing this pin
below 0.4V for longer than 4µs shuts down the
part; forcing this pin above 1.6V for longer than
4µs turns on the part. Applying a 1MHz to 2MHz
clock signal to this pin also synchronizes the
internal oscillator frequency to the external clock.
When the external clock is used, the part turns
on after detecting the first few clocks regardless
of duty cycles. If any ON or OFF period of the
clock is longer than 4µs, the signal will be
intercepted as an enable input and disables the
synchronization.
Bootstrap (BST PIN)
The gate driver for the high-side N-channel
DMOS power switch is supplied by a bootstrap
capacitor connected between the BS and SW
pins. When the low-side switch is on, the
capacitor is charged through an internal boost
diode. When the high-side switch is on and the
low-side switch turns off, the voltage on the
bootstrap capacitor is boosted above the input
voltage and the internal bootstrap diode prevents
the capacitor from discharging.
Soft-Start and Output Pre-Bias Startup
When the soft-start period starts, an internal
current source begins charging an internal soft-
start capacitor. During soft-start, the voltage on
the soft-start capacitor is connected to the non-
inverting input of the error amplifier. The soft-start
period lasts until the voltage on the soft-start
capacitor exceeds the reference voltage of 0.8V.
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
APPLICATION INFORMATION
where ꢁIL is Inductor Ripple Current. Choose
inductor ripple current approximately 30% of the
maximum load current, 4A.
Output Voltage Setting
The external resistor divider sets the output
voltage (see Page 1, Schematic Diagram). The
feedback resistor R1 also sets the feedback loop
bandwidth with the internal compensation (refer
to description function). The relation between R1
and feedback loop bandwidth (fC), output
capacitance (CO) is as follows:
The maximum inductor peak current is:
∆I
L
I
L(MAX) =ILOAD +
2
Under light load conditions, larger inductance is
recommended for improved efficiency.
1.24×106
fc(kHz)×CO (µF)
R1(kΩ) =
Input Capacitor Selection
The input capacitor reduces the surge current
drawn from the input and the switching noise
from the device. The input capacitor impedance
at the switching frequency shall be less than
input source impedance to prevent high
frequency switching current passing to the input
source. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of
their low ESR and small temperature coefficients.
For most applications, a 47µF capacitor is
sufficient.
The feedback loop bandwidth (fC) is no higher
than 1/10th of switching frequency of MP2107. In
the case of ceramic capacitor as CO, it is usually
set in the range of 50kHz and 150kHz for optimal
transient performance and good phasemargin. If
an electrolytic capacitor is used, the loop
bandwidth is no higher than 1/4 of the ESR zero
frequency (fESR). fESR is given by:
1
fESR
=
2π×RESR× CO
For example, choose fC=70kHz with a ceramic
capacitor, CO=47µF, R1 is estimated to be
400KΩ. R2 is then given by:
Output Capacitor Selection
The output capacitor keeps output voltage ripple
small and ensures a stable regulation loop. The
output capacitor impedance shall be low at the
switching frequency. Ceramic capacitors with
X5R or X7R dielectrics are recommended. If an
electrolytic capacitor is used, pay attention to
output ripple voltage, extra heating, and the
selection of feedback resistor R1 (refer to “Output
Voltage Setting” section) due to the large ESR of
electrolytic capacitor. The output ripple ꢁVOUT is
approximately:
R1
OUT
R2 =
V
-1
0.8V
Table 1—Resistor Selection vs.
Output Voltage Setting
Cout
(Ceramic)
Vout
R1
R2
L
1.2V
1.5V
1.8V
2.5V
3.3V
400kꢀ 806kꢀ 0.47µH-1µH
400kꢀ 453kꢀ 0.47µH-1µH
400kꢀ 316kꢀ 0.47µH-1µH
400kꢀ 187kꢀ 0.47µH-1µH
400kꢀ 127kꢀ 0.47µH-1µH
47µF
47µF
47µF
47µF
47µF
V
OUTx(VIN - VOUT
)
1
∆VOUT
≤
x(ESR+
)
V
INxfOSCxL
8xfOSCxC
3
External Schottky Diode
Inductor Selection
For this part, an external schottky diode is
recommended to be placed close to "SW" and
"GND" pins, especially when the output current is
larger than 2A.
A 0.47µH to 1µH inductor with DC current rating at
least 25% higher than the maximum load current is
recommended for most applications. For best
efficiency, the inductor DC resistance shall be
<10mꢀ. See Table 2 for recommended inductors
and manufacturers. For most designs, the
inductance value can be derived from the following
equation:
With the external schottky diode, the voltage
spike and negative kick on "SW" pin can be
minimized; moreover, the conversion efficiency
can also be improved a little.
V
OUTx(VIN - VOUT)
L =
V
INx∆I xfOSC
L
MP2107/MP2107A Rev. 1.1
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
For the external schottky diode selection, it's
placed on both sides of the MP2107 package
and keep them as close as possible to the “IN”
and “GND” pins. If this placement is not possible,
a ceramic cap (10µF~47µF) must be placed
across PIN7-“IN”and PIN9-“GND” since the
internal Vcc supply is powered from PIN7, and
good decoupling is needed to avoid any
interference issues.
noteworthy that the maximum reverse voltage
rating of the external diode should be larger
thanthe maximum input voltage. As for the
current rating of this diode, 0.5A rating should be
sufficient
PC Board Layout
PCB layout is very important to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance. If change
is necessary, please follow these guidelines as
follows. Here, the typical application circuit is
taken as an example to illustrate the key layout
rules should be followed.
For MP2107A, a input ceramic capacitor should
be placed as close as possible to “IN” and “GND”
pins.
4) The external feedback resistors shall be
placed next to the FB pin. Keep the FB trace as
short as possible. Don’t place test points on FB
trace if possible.
1) For MP2107, a PCB layout with more than (or)
four layers is recommended.
5) Keep the switching node SW short and away
from the feedback network.
2) The high current paths (GND, IN and SW)
should be placed very close to the device with
short, direct and wide traces.
6) For MP2107A, a RC low pass filter is
recommended for VCC supply. The Vcc
decoupling capacitor must be placed as close as
possible to “VCC” pin and “GND” pin.
3) For MP2107, two input ceramic capacitors (2 x
(10µF~22µF)) are strongly recommended to be
Table 2—Suggested Surface Mount Inductors
Part
Number
Inductance
Max DCR
(mΩ)
Current Rating
(A)
Dimensions
L x W x H (mm3)
Manufacturer
(µH)
Wurth Electronics
744310055
744310095
0.55
0.95
4.5
7.4
14
11
7×6.9×3
7×6.9×3
TOKO
B1015AS-1R0N
1
11
6.9
8.4×8.3×4
Recommended Layout Pattern
Top Layer
Inner Layer 1
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
Inner Layer 2
Bottom Layer
Figure 2—Recommended PCB Layout of MP2107
Bottom Layer
Figure 3—Recommended PCB Layout of MP2107A
Top Layer
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
TYPICAL APPLICATION CIRCUIT
Vin
C4
100nF
C1
10
C2
10
2.7V to 5V
4,7
5
L1
IN
BS
1
6
3,8
1
SW
POK
Vout
1.8V/4A
R4
D1
B0530
MP2107
R1
400k
100k
10
EN/SYNC
GND
2,9
FB
R3
100k
C3
47
R2
316k
Figure 4—Typical application circuit of MP2107
Vin
C4
2.7V to 5V
C1
22
100nF
3
4
R3
10
L1
1
IN
BS
5
8
6,7
1
SW
Vcc
Vout
1.8V/4A
C3
1
D1
B0530
MP2107A
R1
400k
EN/SYNC
FB
GND
R4
100k
C2
47
R2
316k
2
Figure 5—Typical application circuit of MP2107A
MP2107/MP2107A Rev. 1.1
10/13/2010
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MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
PACKAGE INFORMATION
QFN10 (3mm x 3mm)
2.90
3.10
0.30
0.50
1.45
1.75
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
0.18
10
1
5
0.30
2.25
2.55
2.90
3.10
PIN 1 ID
INDEX AREA
0.50
BSC
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
1.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
0.70
0.25
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
2.50
0.50
RECOMMENDED LAND PATTERN
MP2107/MP2107A Rev. 1.1
10/13/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
13
MP2107/MP2107A – 4A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
0.189(4.80)
0.197(5.00)
0.124(3.15)
0.136(3.45)
8
5
0.150(3.80)
0.157(4.00)
0.228(5.80)
0.244(6.20)
0.089(2.26)
0.101(2.56)
PIN 1 ID
1
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.051(1.30)
0.067(1.70)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.0075(0.19)
0.0098(0.25)
0.013(0.33)
0.020(0.51)
SIDE VIEW
0.050(1.27)
BSC
FRONT VIEW
0.010(0.25)
0.020(0.50)
x 45o
GAUGE PLANE
0.010(0.25) BSC
0.050(1.27)
0.024(0.61)
0.063(1.60)
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
0.103(2.62)
0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
0.138(3.51)
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2107/MP2107A Rev. 1.1
10/13/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
14
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