HR1000A [MPS]
Resonant Half-Bridge Controller; 谐振半桥控制器
| 型号： | HR1000A |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Resonant Half-Bridge Controller |
| 文件： | 总23页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HR1000A
Resonant Half-Bridge Controller
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The HR1000A is a controller designed specifically
for the resonant half-bridge topology. It provides
•
•
•
50% Duty Cycle, Variable Frequency
Control For Resonant Half-Bridge Converter
600V High-Side Gate Driver with Integrated
Bootstrap Diode and High dV/dt Immunity
1.5A/2A Source/Sink Capability for Both
High-Side and Low-Side Gate Drivers
High-Accuracy Oscillator
two
drive-signal
channels
that
output
complementary signals at a 50% duty cycle. An
internal fixed dead-time of 350ns between the
two complementary gate signals guarantees
zero-voltage switching during the transient and
enables high-frequency operation.
•
•
•
Operates at up to 600kHz
Two-Level
Over-Current
Protection:
The integrated bootstrap diode simplifies the
external driving circuit for the high-side switch. It
can withstand up to 600V with immunity against
high dV/dt noise.
Frequency-Shift and Latched Shutdown with
Programmable Duration Time
Remote ON/OFF Control and Brown-Out
Protection through the BO Pin
Latched-Disable Input for Easy Protections
Implementation
Interfaces with PFC Controller
Programmable Burst-Mode Operation at
Light-Load
•
•
Modulating the switching frequency regulates the
topology output voltage.
A
programmable
oscillator can set both the maximum and
minimum switching frequencies.
•
•
The IC starts up at the programmed maximum
switching frequency and gradually slows until the
control loop takes over to prevent excessive
inrush current
•
•
Non-Linear Soft-Start for Monotonic Output
Voltage Rise
SO-16 package
The IC can be forced to enter a controlled burst-
mode operation at light-load to minimize the
power consumption and tighten output regulation.
APPLICATIONS
•
•
•
•
•
•
LCD and PDP TVs
Desktop PCs and Servers
Telecom SMPS
AC-DC Adapter, Open-Frame SMPS
Video Game Consoles
Electronic Lighting Ballast
Protections features—including latched shutdown,
auto-recovery, brown-out protection, and over-
temperature
protection—improve
converter
design safety without engendering additional
circuit complexity.
The IC provide 1.5A/2A source/sink capability for
both high-side and low-side gate drivers.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
The HR1000A is available in a SO-16 package.
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
TYPICAL APPLICATION BLOCK DIAGRAM
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
2
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
ORDERING INFORMATION
Part Number*
Package
Top Marking
HR1000AGS
SOIC16
HR1000A
* For Tape & Reel, add suffix –Z (e.g. HR1000AGS–Z).
PACKAGE REFERENCE
TOP VIEW
SS
TIMER
CT
1
2
3
4
5
6
7
8
16 BST
15 HG
14 SW
13 N.C.
12 VCC
11 LG
Fset
Burst
CS
BO
10 GND
LATCH
9
PFC
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VBST
VSW
dVSW/dt
VCC
VPFC
IPFC
Pin
16
14
14
12
9
Parameter
Value
-1 to 618
-3 to VBST-18
50
Self-limited
-0.3 to VCC
Self-limited
2
Unit
V
V
V/ns
V
V
A
mA
V
Floating supply voltage
Floating ground voltage
Floating ground max. slew rate
IC supply voltage (ICC<25mA)
Maximum voltage (pin open)
Maximum sink current (pin low)
Maximum source current
Maximum voltage
9
4
IFset
LG
11
1 to 8
-0.3 to 16
-0.3 to 6
Analog inputs and outputs
V
(2)
PIC
1.56
W
Continuous power dissipation (TA = +25°C)
Junction Temperature
Lead Temperature (Solder)
Storage Temperature
TJ
TLead
TStorage
150
260
-55 to +150
°C
°C
°C
Notes:
Recommended Operating Conditions (3)
Supply Voltage VCC ......................13V to 15.5V
Analog inputs and outputs .............-0.3V to 6.5V
Operating Junction Temp (TJ). -40°C to + 125°C
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any
ambient
temperature
is
calculated
by
Thermal Resistance (4)
θJA
θJC
D(MAX)=(TJ(MAX)- TA)/ θJA. Exceeding the maximum
allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal shutdown.
Internal thermal shutdown circuitry protects the device from
permanent damage.
SOIC16...................................80 ...... 35... °C/W
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
3
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
ELECTRICAL CHARACTERISTICS
TJ=25°C, VCC=13V, CHG=CLG=1nF; CT=470pF, RFset=12kΩ, unless otherwise specified.
Parameter
Symbol
Min
Typ
Max
Unit
IC supply voltage (VCC)
VCC operating range
VCC high threshold, IC switch-on
8.9
10.3
15.5
11.7
V
V
VCCH
VCCL
Vhys
11
8.2
2.5
VCC low threshold, IC switch-off
7.5
8.9
V
V
Hysteresis
VCC clamp current during fault condition (VCC=16V,
Latch=2V)
IClamp
6
mA
VCC clamp voltage during fault condition (VCC>16V or
VLATCH>1.85V or VCS>1.5V or VTIMER>3.5V or VBO<1.25V
or VBO>5.5V or OTP)
VClamp
15.3
V
IC supply current (VCC)
Start-up current (Before the device turns on,
VCC=VCCH-0.2V)
Istart-up
250
300
µA
Quiescent current (Device on, VBurst=1V)
Iq
Iop
1.5
3
2
5
mA
mA
Operating current (Device on, VBurst=VFset
Residual consumption (VCC>16V or VCC<8V
LATCH>1.85V or VCS>1.5V or VTIMER>3.5V or VBO<1.25V
)
V
Ir
350
400
µA
or VBO>5.5V or OTP)
High-side floating-gate-driver supply (BST, SW)
BST pin leakage current (VBST=600V)
SW pin leakage current (VSW=582V)
ILKBST
ILKSW
ICS
tLEB
VCSx
VCSlatch
10
10
1
µA
µA
µA
ns
V
Input bias current (VCS=0 to VCSlatch
Leading-edge blanking
Frequency shift threshold
Latch-off threshold
)
250
0.8
1.5
0.75
1.41
0.85
1.59
V
Line voltage sensing (BO)
Threshold voltage
Clamp level
Current Hysteresis (VCC>5V, VBO=0.3V)
Latch function (LATCH)
Input bias current (VLATCH=0 to Vth)
LATCH threshold
Oscillator
Output duty cycle
Oscillation frequency
Dead-time
CT peak value
CT valley value
Voltage reference at Fset pin
PFC function (PFC)
Low saturation level (IPFC=1mA, VLATCH=2V)
Soft start function (SS)
Discharge resistance (VCS>VCSx
Standby function (Burst)
Disable threshold
Vth
Vclamp
IHyst
1.2
5.1
9
1.25
5.5
12
1.3
5.8
15
V
V
µA
ILATCH
Vth
1
1.95
µA
V
1.75
48
1.85
50
D
fosc
tD
VCFp
VCFv
VREF
52
600
400
%
kHz
ns
V
V
V
300
350
3.8
0.9
2
1.92
1.18
2.08
0.2
VL
R
V
)
120
Ω
Vth
Vhys
1.23
100
1.28
V
mV
Hysteresis
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
4
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
TJ=25°C, VCC=13V, CHG=CLG=1nF; CT=470pF, RFset=12kΩ, unless otherwise specified.
Parameter
Symbol
Min
Typ
Max
Unit
Delayed shutdown (TIMER)
Charge current (VTIMER=1V, VCS=0.85V)
Threshold for forced operation at maximum
frequency
ICHARGE
Vth1
80
130
2
180
µA
V
1.88
2.08
Shut down threshold
Restart threshold
Vth2
Vth3
3.3
0.25
3.5
0.3
3.7
0.35
V
V
Low-side gate driver (LG, referenced to GND)
Peak source current
Peak sink current
Sourcing resistor
Sinking resistor
Isourcepk
Isinkpk
Rsource
Rsink
tf
1.5
2
A
A
Ω
4
2
20
20
Ω
Fall time
Rise time
ns
ns
V
tr
UVLO saturation (VCC=0 to VCCH, Isink=2mA)
High side gate driver (HG, referenced to SW)
Peak source current
Peak sink current
Sourcing resistor
Sinking resistor
Fall time
Rise time
1.1
Isourcepk
Isinkpk
Rsource
Rsink
tf
1.5
2
A
A
Ω
Ω
ns
ns
4
2
20
20
tr
Thermal Shutdown
Thermal shutdown threshold
Thermal shutdown recovery threshold
150
120
°C
°C
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
5
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are generated using the evaluation board built with design example on
page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted.
15.8
15.7
15.6
15.5
15.4
15.3
15.2
15.1
15.0
14.9
100
10
1
10.0
1.0
Operating @50kHz
Quiescent
Falling
Residual
Start-up
Rising
0.1
0.1
0.01
0
5
10
15
20
-50
0
50
100
150
-50
0
50
100
150
Current Sense Threshold
vs. T
J
12
11
10
9
6
5
4
2.0
1.5
1.0
0.5
VCC Rising
Clamp
8
3
2
1
0
VCC Falling
7
Enable
6
5
4
-50
0
50
100
150
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE ( C)
1.1
2.0
1.9
20
17
1.05
14
11
1.8
1.7
1.6
1
0.95
0.9
8
5
-50
0
50
100
150
-50
0
50
100
150
-50
0
50
100
150
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
6
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with design example on
page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted.
Oscillator Frequency vs.
Frequency-Set Resistance
1000
100
10
1.2
1.1
1
4.0
220pF
3.5
3.0
Peak value
Valley value
330pF
2.5
2.0
1.5
1.0
0.5
0
470pF
680pF
1nF
2.2nF
0.9
0.8
1
-50
0
50
100
150
1
10
100
-50
0
50
100
150
Current Mirror Ratio vs. T
Reference Voltage vs. T
Standby Threshold vs. T
J
J
J
1.45
1.40
1.04
1.03
2.3
2.2
Restart
Disable
1.35
1.30
1.25
1.20
1.15
1.02
1.01
1.00
0.99
0.98
2.1
2.0
1.9
1.8
1.7
-50
0
50
100
150
-50
0
50
100
150
-50
0
50
100
150
Delay Shutdown Charge
Current vs. T
OCP Delay Threshold vs. T
J
J
180
160
140
120
100
80
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Shut down
Force to Max Fsw
Restart
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE ( C)
TEMPERATURE ( C)
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
7
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with design example on
page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted.
Efficiency
Steady State
Steady State
V
= 19V, I
OUT
= 4.7A
V
= 19V, I
OUT OUT
= 0A
OUT
95
90
85
80
75
70
V
V
SW
SW
100V/div.
100V/div.
V
LG
V
10V/div.
LG
10V/div.
I
I
R
R
1A/div.
1A/div.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IOUT (A)
Steady State
Steady State
Start-up
V
= 19V, I
= 4.7A
V
= 19V, I
OUT
= 0A
V = 19V, I
OUT OUT
= 0A
OUT
OUT
OUT
V
LG
V
V
OUT_RIPPLE
/AC
OUT_RIPPLE
5V/div.
/AC
100mV/div.
100mV/div.
V
OUT
10V/div.
I
R
2A/div.
Start-up
Shutdown
Shutdown
V
= 19V, I
OUT
= 4.7A
V
= 19V, I
OUT
= 0A
V = 19V, I
OUT OUT
= 4.7A
OUT
OUT
V
V
V
LG
LG
LG
5V/div.
5V/div.
5V/div.
V
V
V
OUT
OUT
OUT
10V/div.
10V/div.
10V/div.
I
I
I
R
R
R
2A/div.
2A/div.
2A/div.
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
8
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with design example on
page 20. VAC=230V, Vout=19V, Iout=4.7A, TA=25°C, unless otherwise noted.
SCP Entry
SCP Entry
SCP then Power-on
V
= 19V, I
OUT
= 0A
V
= 19V, I
OUT
= 4.7A
V
= 19V
OUT
OUT
OUT
V
OUT
V
10V/div.
V
OUT
OUT
10V/div.
10V/div.
V
V
V
LG
LG
LG
10V/div.
10V/div.
10V/div.
I
I
I
R
R
R
2A/div.
2A/div.
2A/div.
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
9
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
PIN FUNCTIONS
Pin #
Name Description
Soft-start. Connect an external capacitor with this pin to GND and a resistor to Fset pin to
set the maximum oscillator frequency and the time constant for the frequency shift during
start-up. An internal switch discharges the capacitor when the chip turns off (VCC < UVLO,
VCC > 16V, BO < 1.25V or > 5.5V, LATCH > 1.85V, CS >1.5V, TIMER > 2V, thermal
shutdown) to guarantee soft-start when the current sense pin voltage exceeds 0.8V, and as
long as it stays above 0.75V.
1
SS
Period between over-current and shutdown. Connect a capacitor and a resistor from this
pin to GND to set both the maximum duration from an over-current condition before the IC
stops switching, and the delay before the IC resumes switching. Each time the CS pin
voltage exceeds 0.8V, an internal 130µA source charges the capacitor; an external resistor
slowly discharges this capacitor. If the pin voltage reaches 2V, the soft-start capacitor
discharges completely, pushing the switching frequency to its maximum value; the 130µA
source remains on. When the voltage exceeds 3.5V the IC stops switching and the internal
current source turns off so that the pin voltage decays. The IC enters soft-started when the
voltage drops below 0.3V. This allows the converter to work intermittently with very low
average input power under short-circuit conditions.
2
TIMER
Time-Set. An internal current source programmed by the external network connected to pin
4 charges and discharges a capacitor connected to GND. Determines the converter’s
switching frequency.
Switching Frequency Set. Provides a precise 2V reference. A resistor connected from this
pin to GND defines a current that sets the minimum oscillator frequency. Connect the
phototransistor of an opto-coupler to this pin through a resistor to close the feedback loop
that modulates the oscillator frequency to regulate the converter output voltage. The value
of this resistor will set the maximum operating frequency. An R-C series connected from
this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-
start).
3
4
CT
Fset
Burst-Mode Operation Threshold. The pin senses some voltage related to the feedback
control, which is compared to an internal reference (1.25V). If the voltage on the pin is
lower than the reference, the IC enters an idle state and reduces its quiescent current. The
chip resumes switching when the voltage exceeds the reference by 50mV. Soft-start is not
invoked. This function enables burst-mode operation when the load falls below a
programmed level, determined by connecting an appropriate resistor to the opto-coupler to
pin Fset (see block diagram). Tie the pin to Fset if burst-mode is not used.
5
Burst
Primary-Current Sense. Uses a sense resistor or a capacitive divider to sense the primary
current. The voltage signal requires an averaging filter because this input is not intended
for cycle-by-cycle control. As the voltage exceeds a 0.8V threshold (with 50mV hysteresis),
the soft-start capacitor on pin 1 discharges internally: The frequency increases, limiting the
power throughput. Under an output short circuit, this normally results in a nearly-constant
peak-primary current. A timer set on pin 2 limits the duration of this condition. If the current
continues to build up despite the frequency increase, a second comparator referenced at
1.5V latches the device off and brings its consumption up to about pre-start-up levels. The
information is latched, requiring cycling the IC supply voltage to restart: The latch is
removed as the VCC voltage drops below the UVLO threshold. Tie the pin to GND if the
function is not used.
6
CS
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
10
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name Description
Input Voltage Sense. Connect to the high-voltage input bus through the tap of a resistor
divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage
below 1.25V shuts down (without latching) the IC, lowers its consumption and discharges
the soft-start capacitor. The IC operation resumes (with soft-start) when the voltage
exceeds 1.25V. The comparator has current hysteresis: An internal 12µA current source is
ON as long as the applied voltage is below 1.25V, and is OFF if this value is exceeded.
Bypass the pin with a capacitor to GND to reduce noise pick-up. An internal Zener diode
top-limits the pin voltage. Activating the Zener diode causes the IC to shut down (without
latching). Bias the pin between 1.25V and 5.5V if the function is not used.
7
BO
IC Latch. Connects internally to a comparator that—when the pin voltage exceeds 1.85V—
shuts the IC down and brings its consumption to near pre-start-up levels. The latch is
removed as the VCC voltage goes below the UVLO threshold. Tie the pin to GND if the
function is not used.
8
9
LATCH
PFC
Interface to the front-end PFC. This pin—normally high—stops the PFC controller for
protection purposes or during burst-mode operation. It goes low when the IC shuts down
from the following conditions: VCC > 16V, LATCH > 1.85V, CS > 1.5V, BO > 5.5V, thermal
shutdown and BURST < 1.25V. The pin also goes low when the voltage on TIMER
exceeds 2V, and goes back open as the voltage falls below 0.3V. During UVLO, it is open.
Leave the pin unconnected if not used.
Ground. Current return for both the low-side gate-driver current and the IC bias current. Tie
all bias component ground connections to a trace to this pin. Keep separate from any
pulsed current return.
10
11
GND
LG
Low-Side Gate Driver. The driver is capable of a minimum 0.5A source and a minimum 1A
sink-peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively
pulled to GND during UVLO.
Supply Voltage. Supplies both the IC signal and the low-side gate driver. Sometimes a
small bypass capacitor (e.g., 0.1µF) can help provide a clean bias voltage for the IC signal.
12
13
14
VCC
N.C.
SW
High-Voltage Spacer. Not internally connected—isolates the high-voltage pin and eases
compliance with safety regulations (creepage-distance) on the PCB.
High-Side Switch Source. Current return for the high-side gate-drive current. Requires
careful layout to avoid large spikes below ground.
High-Side Floating Gate-Driver. Capable of minimum 0.5A source and minimum 1A sink-
peak current to drive the upper MOSFET of the half-bridge leg. An internal resistor
connected to pin 14 (SW) ensures that the pin does not floating during UVLO.
15
16
HG
High-Side Gate Driver for Floating Voltage Supply. Connect a bootstrap capacitor between
this pin and pin 14 (SW)—fed by an internal bootstrap diode driven in-phase with the low-
side gate-drive.
BST
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
11
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
HR1000A Rev. 1.01
8/30/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
12
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
FUNCTIONAL DESCRIPTION
Oscillator
source-1 (IS-1) to charge the CT capacitor. Here,
the current mirror ratio inside the HR1000A is
1A/A. When a switching cycle starts, IS-1
charges the CT capacitor until the voltage
triggers the peak threshold voltage. Then the
discharge current source (IS-2) with twice the
source current of the Fset pin turns on.
Therefore, the CT capacitor discharges with the
source current of the Fset pin. When the
voltage on the CT capacitor drops to the valley
threshold voltage, the IS-2 turns off and then a
new switching cycle is enabled.
The charge/discharge time of the CT capacitor
determines the oscillator frequency. The
voltage on the CT capacitor fluctuates between
the peak threshold and valley threshold to form
a triangle waveform. Figure 2 shows the
detailed waveform during steady state.
Based on the block diagram shown in Figure 3,
the Fset RC network functions as described:
1. Rfmin from the Fset pin to GND sets the
maximum resistance of external RC network
when the phototransistor is blocked,
therefore setting the Fset minimum source
current, which sets the minimum switching
frequency;
Figure 2: CT Waveform and Gate Signal
The network connecting the Fset pin
charges/discharges the current on the CT
capacitor, as Figure 3 shows. The source
current of the Fset pin controls the current
Figure 3: Oscillator Block Diagram
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HR1000A – RESONANT HALF-BRIDGE CONTROLLER
2. Under normal operation, the phototransistor
modulates the current flow through Rfmax to
modulate the frequency for output voltage
regulation. When the phototransistor is
saturated, the current flow through Rfmax is
at its maximum, setting the frequency at its
maximum
3. A series RC circuit connected between Fset
and GND determines the frequency shift at
start-up. (Please see the soft-start section
for details.)
Burst pin drops below 1.25V, HR1000A will shut
down the HG and LG gate drive outputs,
leaving only the 2V reference voltage on the
Fset pin and the SS pin to retain the previous
state and minimize HR1000A’s power
consumption. When the voltage on the Burst
pin exceeds 1.25V by 50mV, HR1000A
resumes normal operation.
Based on the Burst-mode operating principle,
the Burst pin voltage must connect to the
feedback loop. Figure 4 shows a typical circuit
connect the Burst pin to the feedback signal for
narrow-input–voltage range applications:
Based on the previous principles, the following
equations describe the minimum and maximum
frequency:
1
fmin
=
3⋅CT ⋅Rfmin
1
fmax
=
3⋅CT ⋅(Rfmin || Rfmax
)
Typically, the CT capacitance is between 0.1nF
and 1nF, so the values of Rfmin and Rfmax are:
1
Rfmin
=
3⋅CT ⋅ fmin
Figure 4: Bust-Mode Operation Set-Up
In addition to setting the oscillator, Rfmax also
determines the maximum switching frequency
that HR1000A operates in burst-mode. After
confirming fmax, calculate Rfmax as below:
Rfmin
Rfmax
=
fmax
−1
fmin
For the CT capacitance selection, here is a note
for low temperature and high switching
frequency application: when the temperature is
low, the source current capability of Fset pin
drops a little due to the property of internal
transistor circuit, which means there might be
not big enough current to charge/discharge the
large CT capacitor. So a small CT cap
(<=330pF) is recommended for such application.
Rfmin
3
8
Rfmax
=
⋅
fmax
−1
fmin
Here, fmax corresponds to a load point, PBurst
,
where the peak current flow through the
transformer is too low to cause audible noise.
The above introduction is based on a narrow
input voltage range. As a property of the
resonant circuit, input voltage also determines
the switching frequency. That means the PBurst
has a large variance over the wide input voltage
range. To stabilize PBurst over the input range,
use the circuit in Figure 5 to insert the input
voltage signal into feedback loop.
Burst-Mode Operation
Under light-load or in the absence of a load, the
maximum frequency limits the resonant half-
bridge switching frequency. To control the
output voltage and limit power consumption, the
HR1000A can enable compatible converters to
operate in burst-mode to sharply reduce the
average switching frequency, thus reducing the
average residual magnetizing current and the
associated losses.
Operating in burst-mode requires setting the
Burst pin on the HR1000A; if the voltage on the
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14
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
Figure 5: Bust-mode Operation Set-up for Wide
Input Voltage Range
Figure 6: PFC Disable Block Diagram
The HR1000A provide PFC disabling. Pull the
PFC pin low for one of following conditions:
RB1 and RB2 from Figure 5 correct against the
wide input voltage range. Select both resistors
based on experimental results. Note that the
total resistance of RB1 and RB2 should be much
bigger than RH to minimize the effect on the BO
pin voltage.
•
gate-off
(Burst<1.25V);
during
burst-mode
•
OCP (CS>1.5V); input over-voltage
(BO>5.5V);
During burst-mode operation, when the load is
lower than PBurst, the switching frequency is
clamped at the maximum frequency. Then the
output voltage must rise over the set value,
which would increase the current flowing
•
•
Latch pin HIGH (Latch>1.85V);
TIMER pin voltage exceeding 2V
without dropping to 0.3V; and
•
over-temperature protection triggering.
through the
opto-coupler. Therefore, the
voltage on Rfmax must rise due to the increased
opto-transistor current. The Burst pin voltage
would then drop below 1.25V, triggering the
gate signal OFF state. Until the output voltage
falls below the setting value, the current flow
through opto-coupler then decreases, causing
the Burst pin voltage to rise. When the voltage
exceeds 1.25V+100mV, the IC restarts to
generate the gate signal. The IC will continue to
operate in this mode under no-load or light-load
to decrease average power consumption.
Shutdown the PFC to reduce power
consumption or to protect the system. Figure 7
shows the typical application circuit between
the HR1000A and the PFC controller
(MP44010/1 is a PFC Controller).
PFC-Disable Function
Many applications require a PFC function,
making a pre-regulator widely before a resonant
circuit common. Under some conditions—e.g.
no-load or light load, OCP, OVP—require
disabling the PFC.
Figure 7: Communication Circuit between
HR1000A and PFC Controller
If this function is not used, PFC pin can float.
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HR1000A – RESONANT HALF-BRIDGE CONTROLLER
Soft-Start Operation
Rfmin
Rss
=
fstart
For the resonant half-bridge converter, the
power delivered is inversely proportional to the
switching frequency. To achieve soft-start, start
the switching frequency with a high value until
the value is controlled by the closed loop.
−1
fmin
3⋅10-3
Rss
Css
=
The converter + HR1000A can easily achieve
soft-start using an external RC series circuit as
shown in Figure 8.
Select an initial frequency, fstart, at least 4×fmin.
Select CSS as a trade-off between the desired
soft-start operation and the OCP speed (see
the next section for details).
Current Sensing
Figure 9 shows the current sense block
diagram.
Figure 8: Soft-Start Block
When start-up begins, the SS voltage is 0V, so
the soft-start resistor (RSS) is in parallel to Rfmin:
Rfming and RSS determine the initial frequency as:
Figure 9: Current Sensing Block Diagram
There are two levels over-current protection.
1
fstart
=
The first level occurs when the CS voltage
exceeds 0.8V, the comparator triggers the
control logic to output a high-level control signal
that turns on the transistor connecting SS and
GND. Then the CSS voltage drop results a sharp
increase in oscillator frequency, and therefore
reduces the energy transferred to the output.
When the CS pin voltage drops back to
0.79V,the converter resumes normal operation
with the help of the 10mV hysteresis.
3⋅CT ⋅(Rfmin||Rss )
During start-up, the CSS charges until its voltage
reaches the reference–2V, and the current flow
through RSS drops to zero. This period takes
about 5×(RSS×CSS). During this period, the
switching frequency changes following an
exponential curve: the CSS charge initially
decays relatively quickly but the rate
progressively slows.
Generally, the CS pin voltage continues to rise
during a short circuit. The second level over-
current protection triggers when the CS pin
voltage rises to 1.5V. Then the IC is latched at
very low consumption (residual consumption in
EC table).
After this period ends, the output voltage is not
still close to the setting value, so the feedback
loop will take over start-up.
With soft-start, the input current increases
gradually until the output voltage reaches the
setting point with little overshoot.
For two-level protection, a very large CSS slows
the discharge to the point that the transformer
and the resonant inductor saturate and
damages the secondary diode.
Select the soft-start RC network as per the
equations below:
HR1000A Rev. 1.01
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HR1000A – RESONANT HALF-BRIDGE CONTROLLER
To design the lossless current sensing network,
consider these two conditions:
1. R1 is smaller than several hundred ohms.
The sensing network acts as a capacitive
current divider. Use the equations below:
Cr
C1 ≤
100
0.8⋅ π
ICrpk
Cr
R2 =
⋅(1+
)
C1
2. R1 is ~10kΩ. The sensing network acts to
divide the ripple voltage on Cr. Design for
this condition as per the equations below:
Figure 10: Current Sensing with a Sense
Resistor
Cr
C1 ≤
There are two types of current sensing methods:
one uses a sense resistor in series with the low-
side MOSFET; the other uses a lossless
current-sensing network. The first method is
simple but causes some unnecessary power
consumption.
100
2
2
R1 + XC1
0.8⋅ π
ICrpk
R2 =
⋅
XCr
Calculating the reactance of C1 and Cr at the
frequency where the maximum peak resonant
current occurs. Empirically, the R2 and C2 time
constant is about 10/fmin.
Calculate the sense resistor using the following
equation:
4
RS =
Depending on the circuit, consider the
calculated value as a cut value that requires
adjustments based on experimental results to
meet the design target.
ICrpk
Where ICrpk is the desired peak current through
the primary MOSFET for the resonant capacitor
at low input voltage and full load.
The OCP can limit the energy transferred from
the primary to the secondary during over-load
or short-circuit period. However, excessive
power consumption due to high continuous
currents can damage the secondary-side
windings and the rectifiers. The HR1000A
provides additional protection to reduce the
average power consumption during OCP: When
OCP triggers, the converter enters a hiccup-like
protection mode that operates intermittently.
Since the circuit require an RC filter between
the sensing resistor and CS pin, select an RC
time constant at around 10/fmin.
Set the maximum over-load or short circuit
operating time (tOC) by selecting appropriate
CTimer and RTimer. During the first OCP level
when the CS voltage exceeds 0.8V, an internal
130µA current source turns on to charge CTimer
.
When the voltage on CTimer reaches 2V, the CSS
voltage drops below the OCP comparator
output. This forces the switching frequency to
equal fstart to minimize the transferred energy.
tOC is the time for the voltage on CTimer to rise
Figure 11: Current Sensing with Lossless
Network
HR1000A Rev. 1.01
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HR1000A – RESONANT HALF-BRIDGE CONTROLLER
Latch Operation
from 0V to 2V. However, there is no simple
relationship between tOC and CTimer. Select CTimer
based on experimental results (based on
experiments: CTimer may increase operating time
by 100ms).
After the voltage on CTimer rises to 2V, the
130uA current source continues to charge it
until the voltage reaches the shutdown
threshold (3.5V). This period is approximately:
tOP = 104 ⋅ tTimer
tOC
tOP
tSTOP
tSS
Figure 13: Latch Function Block
VCC
SS
The HR1000A provides a simple latch-off
function through the Latch pin. Applying an
t
2V
external voltage >1.85V causes the IC to enter
a latched shutdown. After IC is latched, its
consumption drops, as shown by the residual
current in the EC table. Resetting the IC
requires dropping the VCC voltage below the
UVLO threshold.
t
t
t
t
t
t
ICr
CS
0.8V
3.5V
2V
TIMER
Vout
0.3V
Input Voltage Sensing
The HR1000A can stop when the input voltage
drops below a specified value, and then
restarted when the input voltage goes back to
normal. This function guarantees that the
resonant half-bridge converter always operates
within the specified input voltage range. The IC
senses voltage on BO through the tap of a
resistor divider connected to the rectified AC
voltage or the PFC output.
PFC
Over load /
Short circuit
Normal
operation
Shutdown
Soft-start
Pmin
Figure 12: Delayed Shutdown and Soft-start Time
Sequence
During this period, the switching frequency
remains at fstart to limit the energy transferred.
When the shutdown threshold triggers, the gate
drive turns off and the 130µA current source
shuts down. Then RTimer slowly discharges CTimer
This procedure lasts until the CTimer voltage
drops below 0.3V, then the IC restarts. This
time period is:
Figure 14 shows the line-sensing internal block
diagram.
.
HV Input bus
Shutdown
3.5
tOFF =RTimer ⋅CTimer ⋅ln
≈ 2.5RTimer ⋅CTimer
5.5V
RH
0.3
BO
7
VinOK
Figure 12 shows the operation’s time sequence.
12μA
1.25V
RL
HR1000A
Figure 14: Input Voltage Sensing Block
HR1000A Rev. 1.01
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HR1000A – RESONANT HALF-BRIDGE CONTROLLER
The internal 12µA current source turns on when
the BO voltage drops below 1.25V, and turns
off when the BO voltage exceeds 1.25V. When
the BO voltage drops below 1.25V, the IC shuts
down the gate drive, and consumes very little
power as per the residual current in the EC
table. Calculate the input-voltage resistor
divider with the desired ON (VinON) and OFF
(VinOFF) input voltage as below:
VinON -VinOFF
RH =
12⋅10−6
1.25
RL = RH ⋅
VinOFF −1.25
Figure 15: High-Side Gate Driver
Low-Side Gate Drive
For additional protection, when the BO voltage
exceeds the internal 5.5V clamp voltage, the IC
will shutdown. When the BO voltage is between
1.25V and 5.5V, the IC will restart.
The LG pin provides the gate driver signal for
the low-side MOSFET. The maximum absolute
rating table shows that the maximum LG pin
voltage is 16V. Under some conditions, a large
voltage spike occurs on the LG pin due to
oscillations from the long gate-driver wire, the
MOSFET parasitic capacitance, and the small
gate-driver resistor. This voltage spike is
dangerous to the LG pin, so add a 15V Zener
diode close to the LG and GND pins.
High-Side Gate Driver
The external BST capacitor provides energy to
the high-side gate driver. An integrated
bootstrap diode charges this capacitor through
VCC. This diode simplifies the external driving
circuit for the high-side switch, allowing the BST
capacitor to charge when the low side MOSFET
is on.
To provide enough gate driver energy and
considering the BST capacitor charge time, use
a 100nF-to-1μF capacitor for the BST capacitor.
Figure 16: Low-Side Gate Driver
HR1000A Rev. 1.01
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HR1000A – RESONANT HALF-BRIDGE CONTROLLER
Design Example
A
90W adatptor is designed with beow
Figure 17 shows the detailed application
schematic. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section.
specifications:
Input AC voltage
Output voltage
Output current
90-265VAC
19V
4.7A
Figure 17: Design Example for 19V/4.7A Output
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20
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
FLOW CHART
START
VCC capacitor is charged
through pull-up resistor
N
VCC>10.5V
Y
Soft Start
Normal Operation
switching frequency
is modulated by IFset
Burst
Latched
Shutdown
OCP
OCP
OTP
Brown-out
UVLO
Mode
Monitor Thermal
Monitor CS
Monitor TIMER
Monitor BO
Monitor VCC
Monitor Burst
Monitor LATCH
N
N
N
N
N
N
N
BO>4.7V or
BO<1.25V
Burst<1.25V
Y
>10ºC
CS>0.8V
Y
TIMER>2V
Y
VCC<8V
Y
LATCH>1.85V
Y
Y
Y
1. Stop the
switching pulse
2. PFC pin pulled
low
1. Stop the
switching pulse
2. Soft start
capacitor fully
discharged
1. Stop the
switching pulse
2. Soft start
capacitor fully
discharged
1. Stop the
switching pulse
2. Soft start
capacitor fully
discharged
1. Latch off the
switching pulse
2. Soft start
capacitor fully
discharged
1. Increase the
switching
frequency
2. Soft start
capacitor
begin to
1. Switching
frequency is
pushed to
maximum value
2. Soft start
capacitor fully
discharge
3. PFC pin pulled
low
3. PFC pin pulled
low
discharge
3. TIMER
3. TIMER
N
capacitor is
charged by an
internal 150uA
current source
Burst>1.3V
Y
capacitor is
charged by an
internal 150uA
current source
4 PFC pin pulled
low
N
N
N
N
<120ºC
VCC>12V
Y
1.25V<BO<6V
Y
VCC<6.4V
Y
1. Resume the
switching pulse
2. PFC pin pulled
high
Y
N
CS>1.5V
Y
N
TIMER>3.5V
Y
1. Latch off the
switching pulse
2. Soft start
capacitor fully
discharged
1. Stop the
switching pulse
2. Soft start
capacitor fully
discharged
3. PFC pin pulled
low
3. TIMER
capacitor
discharged by
external resistor
4. PFC pin pulled
low
N
VCC<6.4V
Y
N
TIMER<0.3V
Y
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21
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
TYPICAL WAVEFORMS
Unplug from
main input
Over temperature
VCC
12V
8V
LG/HG
Soft
Start
PFC
1.85V
LATCH
CS
1.5V
0.8V
TIMER
3.5V
2V
0.3V
BO
Burst
1.25V
Latch
Shutdown
Soft
Start
Brown-
out
Burst
Mode
OCP
OCP
OTP
HR1000A Rev. 1.01
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22
HR1000A – RESONANT HALF-BRIDGE CONTROLLER
PACKAGE INFORMATION
SOIC16
0.386( 9.80)
0.394(10.00)
0.024(0.61)
0.050(1.27)
9
16
0.063
(1.60)
0.150
(3.80)
0.157
(4.00)
0.228
(5.80)
0.244
(6.20)
0.213
(5.40)
PIN 1 ID
8
1
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.0075(0.19)
0.0098(0.25)
0.050(1.27)
BSC
0.013(0.33)
0.020(0.51)
0.004(0.10)
0.010(0.25)
SEE DETAIL "A"
SIDE VIEW
FRONT VIEW
NOTE:
0.010(0.25)
0.020(0.50)
x 45o
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE
0.010(0.25) BSC
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AC.
6) DRAWING IS NOT TO SCALE.
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
HR1000A Rev. 1.01
8/30/2012
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23
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