HR1001C [MPS]
Enhanced LLC Controller with Adaptive Dead-Time Control, Capacitive Mode Protection and Enhanced Surge Protection;
| 型号： | HR1001C |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Enhanced LLC Controller with Adaptive Dead-Time Control, Capacitive Mode Protection and Enhanced Surge Protection |
| 文件： | 总26页 (文件大小：1802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HR1001C
Enhanced LLC Controller with
Adaptive Dead-Time Control,
Capacitive Mode Protection and
Enhanced Surge Protection
DESCRIPTION
FEATURES
The HR1001C is an enhanced LLC controller
that provides adaptive dead-time adjustment
(ADTA) and capacitive mode protection (CMP)
features, as well as functional improvements on
surge performance.
Over-Current Protection (OCP) with
Programmable Delay for Enhanced Surge
Performance
Adaptive Dead-Time Adjustment (ADTA)
Capacitive Mode Protection (CMP)
50% Duty Cycle, Variable Frequency
Control for Resonant Half-Bridge Converter
600V High-Side Gate Driver with Integrated
Bootstrap Diode with a High-Accuracy
Oscillator of High dV/dt Immunity
Operates up to 600kHz
ADTA inserts a dead time between the two
complimentary gate outputs automatically. This
is ensured by keeping the outputs off while
sensing the dV/dt current of the half-bridge
switching node. ADTA features easier design,
lower EMI, and higher efficiency.
Two-Level Over-Current Protection (OCP):
Frequency Shift and Latched Shutdown with
Programmable Duration Time
The HR1001C incorporates anti-capacitive
mode protection, which prevents potentially
destructive capacitive mode switching if the
output is shorted or has a severe overload.
This feature protects the MOSFET during
abnormal conditions, making the converter
robust.
Latched Disable Input for Easy Protection
Remote On/Off Control and Brown-Out
Protection through BO
Programmable Burst Mode Operation at
Light Load
Non-Linear Soft Start for Monotonic Output
Voltage Rise
The HR1001C has a programmable oscillator
that sets both the maximum and minimum
switching frequencies. It starts up at a
programmed maximum switching frequency
and decays until the control loop takes over to
prevent excessive inrush current.
Available in a SOIC-16 Package
APPLICATIONS
LCD and PDP TVs
Desktop PCs and Servers
Telecom SMPS
AC/DC Adapter, Open-Frame SMPS
Video Game Consoles
Electronic Lighting Ballasts
The HR1001C enters a controlled burst mode
at light load to minimize power consumption
and tighten the output regulation.
Full protection features include two-level over-
current protection (OCP) with external latch
shutdown, auto-recovery, brown-in and brown-
out, capacitive mode protection (CMP), and
over-temperature protection (OTP), improving
converter design safety with minimal extra
components.
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology”
are registered trademarks of Monolithic Power Systems, Inc.
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
1
HR1001C – ENHANCED LLC CONTROLLER
Typical Application
Vdc
BO
Cbst
BST
SS
16
15
14
13
12
11
10
9
1
Rss
HG
SW
S1
TIMER
2
Lr
CT
Css
3
4
5
6
7
8
CT
Rfmax
NC
FSET
BURST
CS
D1
D2
Output
CHBVS
S2
HR1001C
VCC
LG
Lm
Rfmin
GND
HBVS
BO
VCC
LATCH
Cr
Rf
Cs
Rs
Cf
TL431
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
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2
HR1001C – ENHANCED LLC CONTROLLER
ORDERING INFORMATION
Part Number*
Package
Top Marking
HR1001CGS
SOIC-16
See Below
* For Tape & Reel, add suffix –Z (e.g. HR1001CGS–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
HR1001C: Part number
LLLLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
SS
BST
HG
TIMER
CT
SW
NC
FSET
HR1001C
VCC
LG
BURST
CS
GND
HBVS
BO
LATCH
SOIC-16
HR1001C Rev.1.0
2/6/2017
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HR1001C – ENHANCED LLC CONTROLLER
THERMAL RESISTANCE (4) ΘJA
ΘJC
ABSOLUTE MAXIMUM RATINGS (1)
BST voltage................................. -0.3V to 618V
SW voltage ..................................... -3V to 600V
Max voltage slew rate of SW...................50V/ns
Supply voltage (VCC) ...................... Self-limited
Sink current of HBVS..............................±65mA
Voltage on HBVS.....................-0.3V to self-limit
Source current of FSET ..............................2mA
Voltage rating LG.......................... -0.3V to VCC
Voltage on CS .................................... -3V to 6V
Other analog inputs and outputs...... -0.3V to 6V
SOIC-16................................ 80.......35 ... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)
3) The device is not guaranteed to function outside of its
operating conditions.
Continuous power dissipation (TA = +25°C)
PIC............................................................1.56W
Junction temperature...............................150°C
Lead temperature ....................................260°C
Storage temperature................-65°C to +150°C
ESD immunity: BST, HG, SW passes HBM
2.5kV, other pins can pass HBM 4kV.
4) Measured on JESD51-7, 4-layer PCB.
RECOMMENDED OPERATING CONDITIONS
(3)
Supply voltage (VCC) ................... 13V to 15.5V
Analog inputs and outputs ............... -0.3V to 6V
Operating junction temp (TJ) ... -40°C to + 125°C
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
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HR1001C – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C ~ 125°C, min and max values
guaranteed by characterization, typical value tested under 25°C, unless otherwise specified.
Parameter
Symbol Condition
Min
Typ
Max Units
IC Supply Voltage (VCC)
VCC operating range
VCC high threshold, IC switch on
VCC low threshold, IC switch off
Hysteresis
8.9
10.3
7.5
15.5
11.7
8.9
V
V
V
V
VCCH
VCCL
11
8.2
2.8
VCC-hys
IC Supply Current (VCC)
Before the device turns on,
VCC = VCCH - 0.2V
Start-up current
Istart-up
Iq
250
1.2
320
1.5
μA
Device on, VBurst < 1.23V,
RFSET = 12kΩ, FMIN = 60kHz
mA
Quiescent current
Device on, VBurst < 1.23V,
RFSET = 3.57kΩ,
Iq-f
1.42
3
1.8
5
mA
mA
FBURST = 200kHz
Operating current
ICC-nor
Device on, VBurst = VFSET
VCC < 8.2V or VLATCH > 1.85V
or VCS > 1.5V or VTIMER > 3.5V
or VBO < 1.81V or VBO > 5.5V
or OTP
Residual consumption
IFault
240
350
420
μA
High-Side Floating Gate Driver Supply (BST and SW)
BST leakage current
SW leakage current
Current Sensing (CS)
Input bias current
ILK-BST
ILK-SW
VBST = 600V, TJ = 25°C
VSW = 582V, TJ = 25°C
14
14
µA
µA
ICS
VCS = 0 to VCS-OCP
2
µA
V
Frequency shift threshold
OCP threshold
VCS-OCR
VCS-OCP
0.71
1.41
0.78
1.5
0.85
1.59
V
Current polarity comparator
reference when HG turns off
VCSPR
VCSNR
50
85
131
-50
mV
mV
Current polarity comparator
reference when LG turns off
-131
-85
Line Voltage Sensing (BO)
Start-up threshold voltage
Turn-off threshold voltage
Clamp level
VBO-On
VBO-Off
2.30
1.81
5.5
2.40
5.9
V
V
V
1.72
5.1
VBO-Clamp
Latch Function (LATCH)
Input bias current (VLATCH = 0 to Vth)
LATCH threshold
ILATCH
1
µA
V
VLATCH
1.72
1.85
1.95
HR1001C Rev.1.0
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2/6/2017
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HR1001C – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C ~ 125°C, min and max values
guaranteed by characterization, typical value tested under 25°C, unless otherwise specified.
Parameter
Oscillator
Symbol Condition
Min
Typ
Max
Units
TJ = 25°C
D
48
47
50
50
52
53
%
%
Output duty cycle
TJ = -40 ~ 125°C
Oscillation frequency
CT peak value
fosc
CT ≤ 150pF, RFSET ≤ 2kΩ
600
kHz
V
VCFp
VCFv
VREF
tDMIN
tDMAX
tD-float
tCMP
3.8
0.9
2
CT valley value
V
Voltage reference at FSET
1.87
180
2.05
290
V
CHBVS = 5pF typically
HBVS floating
235
1
ns
µs
ns
µs
Dead time
250
350
52
450
Timer for CMP
Half-Bridge Voltage Sense (HBVS)
VHBVS-
Clamp
Voltage clamp
7.6
V
Minimum voltage change rate that
can be detected
dvmin/dt CHBVS = 5pF, typically
180
V/µs
ns
Turn-on delay
Td
Slope finish to turn-on delay
100
Soft-Start Function (SS)
Discharge resistance
Threshold for OCP latch
Standby Function (BURST)
Disable threshold
RSS
VCS > VCS-OCR
130
Ω
VSS-OCP VCS > VCS-OCP
1.64
1.17
1.73
1.82
V
VBurst
1.23
30
1.28
100
V
Hysteresis
VBurst-hys
mV
Delayed Shutdown (TIMER)
VTIMER = 1V, VCS = 0.85V,
TJ = 25°C
Charge current
ITIMER
80
130
2
180
µA
V
Threshold for forced operation at
maximum frequency
VTIMER-fmax
1.80
2.10
Shutdown threshold
Restart threshold
VTIMER-SD
VTIMER-R
3.2
3.5
3.7
V
V
0.21
0.28
0.35
Low-Side Gate Driver (LG, Referenced to GND)
Peak source current (5)
Peak sink current (5)
Sourcing resistor
Sinking resistor
Fall time
ILG-source-pk
0.75
0.87
4
A
A
ILG-sink-pk
RLG-source LG_R @ Isrc = 0.01A
Ω
RLG-sink LG_R @ Isnk = 0.01A
2
Ω
tLG-f
30
30
ns
ns
V
Rise time
tLG-r
UVLO saturation
VCC = 0 to VCCH, Isink = 2mA
1
HR1001C Rev.1.0
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2/6/2017
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HR1001C – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C ~ 125°C, min and max values
guaranteed by characterization, typical value tested under 25°C, unless otherwise specified.
Parameter
Symbol Condition
Min
Typ
Max
Units
High-Side Gate Driver (HG, Referenced to SW)
Peak source current (5)
Peak sink current (5)
Sourcing resistor
Sinking resistor
IHG-source-pk
0.74
0.87
4
A
A
IHG-sink-pk
RHG-source HG_R @ Isrc = 0.01A
Ω
RHG-sink
tHG-f
HG_R @ Isnk = 0.01A
2
Ω
Fall time
30
30
ns
ns
Rise time
tHG-r
Thermal Shutdown
Thermal shutdown threshold (5)
150
120
°C
°C
Thermal shutdown recovery
threshold (5)
NOTE:
5) Guaranteed by design.
HR1001C Rev.1.0
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HR1001C – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are generated using the evaluation board built with the design example
on page 22. VAC = 120V, VOUT = 24V, IOUT = 4.16A, TA = 25°C, unless otherwise noted.
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
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HR1001C – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with the design example
on page 22. VAC = 120V, VOUT = 24V, IOUT = 4.16A, TA = 25°C, unless otherwise noted.
HR1001C Rev.1.0
2/6/2017
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HR1001C – ENHANCED LLC CONTROLLER
PIN FUNCTIONS
Pin #
Name Description
Soft start. Connect an external capacitor from SS to GND and a resistor to FSET to set the
maximum oscillator frequency and the time constant for the frequency shift during start-up.
An internal switch discharges the capacitor when the chip turns off (VCC < UVLO, BO <
VBO-Off or > VBO-Clamp, LATCH > VLATCH, CS > VCS-OCP, TIMER > VTIMER-fmax, thermal
shutdown) to guarantee a soft start.
1
SS
Period between over-current and shutdown. Connect a capacitor and a resistor from
TIMER to GND to set both the maximum duration from an over-current condition before the
IC stops switching and the delay before the IC resumes switching. Whenever the voltage
on CS exceeds VCS-OCR, an internal current source (ITIMER) charges the capacitor. An
external resistor discharges this capacitor slowly. If the voltage on TIMER reaches VTIMER-
fmax, the soft-start capacitor discharges completely, raising its switching frequency to its
maximum value. ITIMER remains on. When the voltage exceeds VTIMER-SD, the IC stops
switching, the internal current source turns off, and the voltage decays. The IC enters soft
start when the voltage drops below VTIMER-R. This converter works intermittently with very
low average input power under short-circuit conditions.
2
TIMER
Time set. An internal current source programmed by an external network connected to
FSET charges and discharges a capacitor connected to GND. This determines the
converter’s switching frequency.
Switching frequency set. FEST provides a precise 2V reference. A resistor connected
from FSET to GND defines a current that sets the minimum oscillator frequency. Connect
the phototransistor of an optocoupler to FSET through a resistor to close the feedback loop
that modulates the oscillator frequency, which regulates the converter’s output voltage. The
value of this resistor sets the maximum operating frequency. An R-C series connected from
FSET to GND sets the frequency shift at start-up to prevent excessive inrush energy.
3
4
CT
FSET
Burst mode operation threshold. BURST senses the voltage related to the feedback
control, which is compared to an internal reference (VBurst). When the voltage on BURST is
lower than this reference, the IC enters an idle state and reduces its quiescent current.
When the feedback drives BURST above VBurst + 30mV (VBurst-hys), the chip resumes
switching. There is no soft start. This function enables burst mode operation when the load
falls below a programmed level determined by connecting an appropriate resistor to the
optocoupler to FSET (see the Block Diagram on page 12). Connect BURST to FSET if
burst mode is not used.
5
BURST
Current sense of the half-bridge. CS uses a sense resistor or a capacitive divider to
sense the primary current. CS has the following functions:
Over-current regulation: If the voltage exceeds VCS-OCR, the soft-start capacitor on SS
discharges internally. The frequency increases, limiting the power throughout. During an
output short circuit, this normally results in a nearly constant peak primary current.
TIMER limits the duration of this condition.
Over-current protection (OCP): If the current continues to build despite the frequency
increase, when VCS > VCS-OCP, SS is discharged continuously, and OCP is not triggered
immediately until VSS < VSS-OCP. If the condition for VCS > VCS-OCP remains once VSS
drops below VSS-OCP, OCP is triggered in latch mode. This requires cycling the IC supply
voltage to restart. The latch is removed once the VCC voltage drops below the UVLO
threshold. This prevents OCP from mistriggering in surge tests or other transient tests.
6
CS
Capacitive mode protection (CMP): Once LG turns off, CS is compared to the VCSNR
CMP threshold. If VCS > VCSNR, the HG gate is blocked from turning on until the slope is
detected or the CMP timer is complete. Once HG turns off, CS is compared to the VCSPR
CMP threshold. If VCS < VCSPR, the low-side gate is blocked from turning on until the
slope is detected or the CMP timer is completed. If a capacitive mode status is
detected, SS is not discharged immediately; there is a 1µs delay. After the blanking
delay, SS is discharged if the fault condition in capacitive mode remains. This prevents
the influence of CS noise. Connect CS to GND if the CMP function is not used.
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
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HR1001C – ENHANCED LLC CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name Description
Input voltage sense and brown-in/brown-out protection. If the voltage on BO is over
VBO-On, the IC enables the gate driver. If the voltage on BO is below VBO-Off, the IC is
disabled.
7
BO
IC latch off. When the voltage on LATCH exceeds VLATCH, the IC shuts down and lowers
its bias current almost to its pre-start-up level. LATCH is reset when the voltage on VCC is
discharged below its UVLO threshold. Connect LATCH to GND if the function is not used.
Half-bridge dV/dt sense. To detect the dV/dt of the half-bridge, a high-voltage capacitor is
connected between SW and HBVS. The dV/dt current through HVBS is used to adjust the
dead-time adaptively between the high-side gate and the low-side gate.
Ground. GND is the current return for both the low-side gate driver and the IC bias.
Connect all external ground connections with a trace to GND—one for signals and a
second for pulsed current return.
8
9
LATCH
HBVS
GND
10
Low-side gate driver output. The driver is capable of a 0.8A source/sink peak current to
drive the lower MOSFET of the half-bridge. LG is pulled to GND during UVLO.
Supply voltage. VCC supplies both the IC bias and the low-side gate driver. Use a small
bypass capacitor (e.g.: 0.1µF) to achieve a clean bias voltage for the IC signal.
High-voltage spacer. No internal connection. NC isolates the high-voltage pin (SW) and
eases compliance with safety regulations (creepage-distance) on the PCB.
High-side switch source. SW is the current return for the high-side gate drive current. SW
requires careful layout to avoid large spikes below ground.
11
12
13
14
LG
VCC
NC
SW
High-side floating gate driver output. HG is capable of a 0.8A source/sink peak current
to drive the upper MOSFET of the half-bridge. Connect an internal resistor to SW to ensure
that HG does not float during UVLO.
Bias for floating voltage supply of high-side gate driver. Connect a bootstrap capacitor
between BST and SW. This capacitor is charged by an internal bootstrap diode driven in-
phase with the low-side gate driver.
15
16
HG
BST
HR1001C Rev.1.0
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HR1001C – ENHANCED LLC CONTROLLER
block diagram
VCC
VBUS
VCC
BST
HSG
DRIVER
CBOOT
HG
SW
Internal
circuit
LEVEL
SHIFTER
Lr
DRIVING
LOGIC
VDD
BURST
STANDBY
RESONANT
OTP
LG
TANK CIRCUIT
1.26V/
1.23V
LSG
DRIVER
Dtmin/
Dtada/
DTmax
Cr
GND
ADTA
2V
Ifmin
HBVS
FSET
Right
Slope detected
/52µs Timer out
Current
Polarity
CMP
wrong
1.73V
CS
SS
OCP
Control
Logic
1.5V
VCC
0.78V
LATCH
OCR
Q
S
Disable
1.85V
R
Boost _OK
UVLO
2.3V/1.81V
CT
VCLK
BO
TIMER
Figure 1: Functional Block Diagram
HR1001C Rev.1.0
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HR1001C – ENHANCED LLC CONTROLLER
APPLICATION INFORMATION
Oscillator
An R-C network connected to FSET externally
determines the normal switching frequency and
the soft-start switching frequency.
Figure 2 shows the oscillator block diagram. A
modulated current charges and discharges the
CT capacitor repeatedly between its peak valley
thresholds, which determines the oscillator
frequency.
Rfmin from FSET to GND contributes to the
maximum resistance of the external R-C
network when the phototransistor does not
conduct. This sets the FSET minimum source
current, which defines the minimum switching
frequency.
VREF
Is-1
Fset
Iset
Rss Rfmax
Css
Iset
CT
Under normal operation, the phototransistor
adjusts the current flow through Rfmax to
modulate the frequency for output voltage
regulation. When the phototransistor is
saturated, the current through Rfmax is at its
maximum, which sets the frequency at its
maximum.
Rfmin
VCFv
+
-
R
S
Is-2
2Iset
GND
Q
CT
VCFp
+
-
HR1001C
Figure 2: Oscillator Block Diagram
An R-C in series connected between FSET and
GND shifts the frequency at start-up. Please
see the Soft-Start Operation section on page 14
for details.
FSET sets the CT charging current, Iset (IS-1).
When CT passes its peak threshold (VCFp), the
flip-flop is set, and a discharge current source
twice the charge current is enabled. The
difference between these two currents forces
the charge and discharge of CT to be equal.
When the voltage on the CT capacitor falls
below its valley threshold (VCFv), the flip-flop is
reset and turns off IS-2. This starts a new
switching cycle. Figure 3 shows the detailed
waveform of the oscillator.
Set the minimum and maximum frequencies
with Equation (1) and Equation (2):
1
fmin
(1)
(2)
3CT Rfmin
1
fmax
3CT (Rfmin ||Rfmax
)
Typically, the CT capacitance is between 0.1nF
and 1nF. Calculate the values of Rfmin and Rfmax
with Equation (3) and Equation (4):
CT
TD
LG
t
t
t
t
1
Rfmin
(3)
(4)
3CT fmin
HG
SW
Rfmin
fmax
Rfmax
1
fmin
It is recommended to use a CT capacitor
(≤330pF) for best overall temperature
performance.
Figure 3: CT Waveform and Gate Signal
HR1001C Rev.1.0
2/6/2017
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HR1001C – ENHANCED LLC CONTROLLER
Soft-Start Operation (SS)
Select an initial frequency (fstart) at least four
times fmin. When selecting CSS, there is a trade-
off between the desired soft-start operation and
the over-current protection (OCP) speed. See
the Over-Current Protection section on page 17
for details.
For the resonant half-bridge converter, the
power delivered is inversely proportional to its
switching frequency. To ensure that the
converter starts or restarts with safe currents,
the soft start forces a high initial switching
frequency until the value is controlled by the
closed loop.
Adaptive Dead-Time Adjustment (ADTA)
When operating in inductive mode, the soft
switching of the power MOSFETs results in
high efficiency of the resonant converter. A
fixed dead time may result in hard switching in
light load, especially if the magnetizing
inductance (Lm) is too large. A dead time that is
too long may lead to ZVS loss. The current may
change polarity during the dead time, resulting
in capacitive mode switching. The adaptive
dead-time control adjusts the dead time
automatically by detecting the dV/dt of the half-
bridge switching node (SW).
Soft start is achieved by using an external R-C
series circuit (see Figure 4).
Fset
4
HR1001C
RSS
Rfmin
SS
1
CSS
Figure 4: Soft-Start Block
The HR1001C incorporates an intelligent
adaptive dead-time adjustment (ADTA) logic
circuit, which detects SW’s dV/dt and inserts a
proper dead time automatically. For the external
circuit, connect a capacitor (CHBVS, typically 5pF)
between SW and HBVS to sense dV/dt. Figure
5 shows the simplified block diagram of ADTA.
Figure 6 shows the operation waveform of
ADTA.
When start-up begins, the SS voltage is 0V, so
the soft-start resistor (RSS) is in parallel to Rfmin.
Rfmin and RSS determine the initial frequency,
which can be calculated with Equation (5):
1
fstart
(5)
3CT (Rfmin||RSS )
During start-up, CSS charges until its voltage
reaches the reference (VREF), and the current
through RSS decays to zero. This period takes
about 5x(RSSxCSS). During this period, the
switching frequency change follows an
exponential curve. Initially, the CSS charge
reduces the frequency relatively quickly, but the
rate decreases gradually.
Vbus
BST
HSG Driver
CBOOT
HG
SW
HG
Lr
VDD
LG
LG
LSG Driver
CHBVS
Cr
GND
After the soft-start period, the switching
frequency is dominated by the feedback loop to
regulate the output voltage. With the soft start,
the current of the resonant tank increases
during the start-up gradually.
HG
LG
CLK
id
HBVS
ADTA
Logic
D1
CLKN
Select the soft-start R-C network with Equation
(6) and Equation (7):
Figure 5: Block Diagram of ADTA
Rfmin
RSS
(6)
fstart
1
fmin
310-3
RSS
CSS
(7)
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HR1001C – ENHANCED LLC CONTROLLER
Dead time adaptively
adjusted
Then design CHBVS with Equation (10):
C
700uA
Im
LG
HG
HG
oss
(10)
CHBVS
2
im
ir
Where Coss is the output capacitance when
drain-source voltage on the MOSFET is almost
zero volts (refer to the Coss characteristics curve
in the MOSFET’s datasheet).
V
SW
V
In a typical design, Lm = 870µH, VIN = 450Vdc,
and fmax = 140kHz. CHBVS is calculated at 4.5pF,
indicating that 5pF is suitable for most
MOSFETs.
HBVS
TDmin
Current of C HBVS
Figure 7 illustrates a possible dead time by
ADTA logic. Note that there are three kinds of
dead time: minimum dead time (tDmin), maximum
dead time (tDmax), and adjusted dead time (tDadj),
which is between tDmin and tDmax. ADTA logic
sets tDmin = 235ns. When the SW transition time
is smaller than tDmin, the logic does not let the
gate turn on, which prevents a shoot-through
between the low-side and high-side MOSFETs.
A maximum dead time (tDmax = 1µs) forces the
gate to turn on, preventing duty cycle losses or
soft switching.
id
CLK
Figure 6: Operation Waveform of ADTA
When HG switches off, SW voltage swings from
high to low due to the resonant tank current (ir).
Accordingly, this negative dV/dt pulls current
from HBVS via CHBVS. If the dV/dt current is
higher than the internal comparison current, the
voltage on HBVS (VHBVS) is pulled down and
clamped at zero. When SW stops slewing and
differential current stops, VHBVS starts to ramp
up. LG turns on after a delay (minimum dead
time). Dead time is the duration between the
moment HG turns off and the moment LG turns
on.
ADTA adjusts the dead time automatically and
ensures zero-voltage switching (ZVS), which
enables more flexibility in the MOSFET and Lm
selection. ADTA also prevents hard switching if
the design does not carefully account for light
load or no load. At light load, the switching
frequency goes high, and the magnetizing
current goes low, risking hard switching that
can lead to a thermal or reliability issue.
When LG switches off, the SW voltage swings
from low to high, and a positive dV/dt current is
detected via CHBVS. The dead time between LG
turning off and HG turning on is maintained
automatically by sensing the dV/dt current.
DTmin
DTmin
DTmax
Vosc
To avoid damaging HBVS, CHBVS should be
selected carefully. Keep the dV/dt current below
65mA using Equation (8):
t
VCLK
Vgate
t
dv
(8)
id CHBVS
65mA
LG
HG
LG
HG
dt
t
VSW
If CHBVS is designed too low to sense the dV/dt,
the minimum voltage change rate (dVmin/dt)
must be accounted for to design a proper CHBVS
value.
t
t
VDT
t1 t2 t3
t4 t5 t6
t7
t8
First, calculate the peak magnetizing current (Im)
Figure 7: Dead Time in ADTA
with Equation (9):
V
in
(9)
Im
8Lm fmax
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HR1001C – ENHANCED LLC CONTROLLER
If HBVS is not connected, the internal circuit
cannot detect the differential current from HBVS,
so the dead time remains fixed at 350ns.
Capacitive Mode Protection (CMP)
When the resonant HB converter output is in an
overload or short circuit, it may cause the
converter to run into a capacitive region. In
capacitive mode, the voltage applied to the
resonant tank causes the current of the
resonant tank to lag. Under this condition, the
body diode of one of the MOSFETs is
conducting. The other MOSFET should not be
turned on to prevent device failure. The
functional block diagram of capacitive mode
protection (CMP) is shown in Figure 10.
Figure 8 shows the dead-time waveform when
HG turns off, and Figure 9 shows the dead-time
waveforms when LG turns off. ADTA logic
inserts the dead time automatically according to
the transition shape of SW.
If VHBVS is pulled down too low by the negative
current of CHBVS, the dead time from HG turning
off to LG turning on may be too long. To clamp
HBVS at zero and ensure an optimum dead
time, connect a Schottky diode (D1) (such as
BAT54) on HBVS to GND.
Figure 11 shows the operating current principle
of CMP. CSPOS and CSNEG stand for the
current polarity, which is generated by
comparing the voltage on CS with the internal
VCSNR and VCSPR voltage reference.
VSW
At t0, LG turns off. CSNEG is high, which
means the current is in the correct direction and
is operating in inductive mode.
VLG
VHG
VHBVS
At t1, HG turns off. CSPOS is high, which
means the current is in the correct direction and
is operating in inductive mode.
At t2, LG turns off for the second time. CSNEG
is low, indicating the current is in the wrong
direction (the low-side MOSFET body diode is
conducting), and the converter is operating in
capacitive mode.
Figure 8: Dead Time at High-to-Low Transition
SW does not swing high until the current
returns to the correct polarity. DT stays high
and VOSC is stopped, preventing the other
MOSFET from turning on. This prevents
capacitive switching.
VSW
VLG
VHBVS
VHG
At t3, the current returns to the correct polarity,
and the other MOSFET turns on after the dV/dt
current is detected.
Between t2 to t5, the correct current polarity
cannot be detected, or there is so little current
that SW cannot be pulled up or down.
Eventually, the timer (tCMP) for CMP expires,
and the other MOSFET is forced to switch on
(see Figure 11).
Figure 9: Dead Time at Low-to-High Transition
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HR1001C – ENHANCED LLC CONTROLLER
Vbus
BST
HG
HSG
DRIVER
CBOOT
2V
HG
FSET
SS
Lr
SW
Iset
Discharge:
OCR
VDD
LG
CMP
VH VL
LG
Restart
LSG
DRIVER
VS
Cr
GND
SET
CLR
Q
Q
D
-85mV
CLK
CLK
Capacitive
detected
CS
SET
CLR
Q
Q
D
85mV
130uA
CMP
Latch off
2.0
TIMER
V
ir
S
R
1.5
V
Q
3.5
V
Protection
Timer
QN
OCP
Control
Logic
UVLO
0.3
V
Protection
Timer
OCR
0.8
V
HR1001C
Figure 12: Capacitive Mode Protection Waveform
Figure 10: Block Diagram of CMP and OCP
Figure 12 shows CMP behavior when the
output is shorted. The current polarity goes in
the wrong direction when LG switches off. The
CMP logic detects this capacitive mode
immediately and prevents HG from turning on.
This prevents destructive capacitive switching.
Once the current (ir) returns to the correct
polarity, SW ramps up, the dV/dt current is
detected, and HG turns on at the ZVS condition.
DTmin
DTmin
Timer out
Vosc
DTmax
t
VCLK
t
Vgate
LG
HG
LG
HG
HG
t
Slope Missing
VSW
Vcs
t
t
Over-Current Protection (OCP)
CSNEG
CSPOS
t
t
t
The HR1001C provides two levels of over-
current protection (see Figure 13).
tOC
tOP
tSTOP
tSS
Vss
DT
VCC
VCCH
VCCL
VSS
SS
t
t
VSS-OCP
t
t0
t1
t2
t3 t4
t5
t6
ICr
Figure 11: Operating Principle of CMP
t
VCS-OCP
VCS-OCR
When capacitive mode operation is detected,
the VSS control signal goes high, turning on an
internal transistor to discharge CSS after a 1µs
blanking delay. This causes the frequency to
increase to a very high level quickly to limit the
output power. The VSS control is reset, and soft
start is activated when the first gate driver is
switched off after CMP. The switching
frequency decreases smoothly until the control
loop takes over.
VCS
t
VTIMER-SD
TIMER
VTIMER-fmax
VTIMER-R
t
Vout
t
Normal
operation
OCP(Latch-off mode)
Over load
Shutdown
Soft-start
Soft-start
Pmin
Figure 13: OCP Timing Sequence
The first level of protection occurs when the
voltage on CS (VCS) exceeds VCS-OCR. Once this
occurs, two actions take place. First, the
internal transistor connected between SS and
GND turns on for at least 10µs, which
discharges CSS. This creates a sharp increase
in the oscillator frequency, reducing the energy
transferred to the output. Second, an internal
current source (ITIMER) turns on to charge CTIMER
,
ramping the TIMER voltage.
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HR1001C – ENHANCED LLC CONTROLLER
If VCS drops below VCS-OCR before the voltage on
TIMER (VTIMER) reaches VTIMER-fmax, both the
discharge of CSS and the charge of CTIMER are
stopped. The converter resumes normal
operation.
VSS
tOC is the time for VTIMER to rise from 0V to
VTIMER-fmax. tOC is also a delay time for over-
current regulation. There is no simple
relationship between tOC and CTIMER. Select
CTIMER based on experimental results. Based on
experiments, CTIMER may increase the operating
time by 100ms.
VCS
VLG
If VCS is still larger than VCS-OCR after VTIMER rises
to VTIMER-fmax, CSS is discharged completely.
Simultaneously, ITIMER continues to charge
CTIMER until VTIMER reaches VTIMER-SD and then
turns off all gate drivers.
Figure 14: SCP Waveform
OCP limits the energy transferred from the
primary side to the secondary side during an
overload or short-circuit condition. Excessive
power consumption due to high continuous
currents can damage the secondary-side
windings and rectifiers. TIMER provides
additional protection to reduce the average
power consumption. When OCP is triggered
(except in a VCS > VCS-OCP condition), the
converter enters a hiccup-like protection mode
that operates intermittently.
Calculate the time VTIMER takes to rise from
VTIMER-fmax to VTIMER-SD with Equation (11):
tOP 104 CTIMER
(11)
The IC maintains the condition until VTIMER
decreases to VTIMER-R, and then the IC restarts.
Calculate this time period with Equation (12):
3.5
(12)
2.5RTIMER CTIMER
tOFF=RTIMER CTIMER ln
0.3
Current Sensing
There are two current sensing methods:
lossless current sensing and current sensing
with a sense resistor.
The second level of over-current protection is
triggered when VCS rises to VCS-OCP. Typically,
this condition occurs when VCS continues to rise
during a short circuit. Once VCS reaches VCS-OCP
the HR1001C does not stop switching
immediately, and CSS is discharged by an
internal transistor continuously. If VCS remains
above VCS-OCP until VSS drops below VSS-OCP, the
,
Generally, a lossless current sensing solution is
used in high-power applications (see Figure 15).
IC shuts down in latch-off mode (see Figure 14).
While VSS is dropping, the converter resumes
normal operation if VCS decreases below VCS-
OCR. This is a particular characteristic of the
Lr
R1
HR1001C
and
prevents
instantaneous
CS
Cs
interference on CS to trigger any protection
when the converter suffers a surge or other
transient waves. Once the latch is triggered, it is
not reset until VCC drops below UVLO.
Cr
C1
Rs
Figure 15: Current Sensing with a Lossless
Network
Design a lossless current sensing network with
Equation (13) and Equation (14):
Cr
Cs
(13)
100
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HR1001C – ENHANCED LLC CONTROLLER
Choose Rs with Equation (14):
Input Voltage Sensing (BI/BO)
The HR1001C stops switching when the input
voltage drops below a specified value and
restarts when the input voltage returns to
normal. This function guarantees that the
resonant half-bridge converter always operates
within the specified input voltage range. The IC
senses the voltage on BO (VBO) through the tap
of a resistor divider connected to the rectified
AC voltage or the PFC output.
Cr
0.8
ICrpk
(14)
Rs<
(1
)
CS
Where ICrpk is the peak current of the resonant
tank at a low input voltage and full load.
Calculate ICrpk with Equation (15):
NVO
I
2N
2
)
)2 ( O
(15)
ICrpk (
4Lmfs
Figure 17 shows the line-sensing internal block
diagram.
Where N is the turns ratio of the transformer, lo
is the output current, Vo is the output voltage, fS
is the switching frequency, and Lm is the
magnetizing inductance.
Shutdown
For capacitive mode detection in no load or
tiny-load conditions, Rs should fulfill the
condition in Equation (16):
VBO-Clamp
RH
BO
7
VinOK
85mV
Im
Cr
(16)
RS
(1
)
VBO-On
VBO-Off
/
RL
CS
HR1001C
In some conditions, especially where a large
Lm is used, it can be difficult to fulfill both
Equation (14) and Equation (16). The IC
operates without a CMP function at light load if
it does not have the restriction of Equation (16).
Figure 17: Input Voltage Sensing Block
If VBO is higher than VBO-On, the IC provides the
gate driver outputs. The IC does not stop the
gate driver until VBO drops below VBO-Off
.
The R1 and C1 network is used to attenuate
switching noise on CS. The time constant
should be in the range of 100ns.
For a minimum operation input voltage of the
half-bridge (VIN-min), select a value for RH that is
large enough to reduce power consumption at
no load. Then calculate RL with Equation (18):
An alternate solution uses a sense resistor in
series with the resonant tank (see Figure 16).
This method is simple but causes unnecessary
power loss on the sense resistor.
1.81
(18)
RL RH
V
1.81
IN-min
For additional protection, the IC shuts down
when VBO exceeds the internal clamp voltage
(VBO-Clamp). When VBO is between VBO-On and VBO-
Clamp, the IC operates normally.
Burst Mode Operation
Cr
At light load or in the absence of a load, the
maximum frequency limits the resonant half-
bridge switching frequency. To control the
output voltage and limit power consumption, the
HR1001C enables compatible converters to
operate in burst mode. This reduce the average
switching frequency greatly, thus reducing the
average residual magnetizing current and
associated losses.
R1
CS
C1
Rs
Figure 16: Current Sensing with a Sense
Resistor
Design the sense resistor using Equation (17):
0.8
RS
(17)
ICrpk
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HR1001C – ENHANCED LLC CONTROLLER
Operating in burst mode requires setting
BURST. If the voltage on BURST (VBURST
Vin
)
drops below the internal threshold (VBurst), the
HR1001C shuts down the HG and LG gate
drive outputs, leaving only the 2V reference
voltage on FSET and SS to retain the previous
state and minimize the power consumption.
When VBURST exceeds VBurst over 30mV (VBurst-
hys), the HR1001C resumes normal operation.
FSET
RH
BO
Rfmax
Rss
Css
HR1001C
BURST
Rfmin
RL
RB1
Cburst
RB2
Based on the burst mode operating principle,
BURST must be connected to the feedback
loop. Figure 18 shows a typical circuit
connecting BURST to the feedback signal for
narrow input voltage range applications.
Figure 19: Burst Mode Operation Set-Up for a
Wide Input Voltage Range
RB1 and RB2 in Figure 19 correct against the
wide input voltage range. Select both resistors
based on experimental results. The total
resistance of RB1 and RB2 should be much
larger than RH to minimize the effect on VBO.
During burst mode operation, when the load is
lower than PBurst, the switching frequency is
clamped at the maximum frequency. The output
voltage must rise over the setting value, which
increases the current flowing through the
optocoupler. Therefore, the voltage on Rfmax
rises due to the increased phototransistor
Fset
4
Rfmax
HR1001C
Rfmin
Burst
5
current. Then VBURST drops below VBurst
,
triggering the gate signal off state. Until the
output voltage falls below the setting value, the
current flow through the optocoupler decreases,
causing VBURST to rise. When VBURST exceeds
VBurst over 30mV, the IC restarts to generate the
gate signal. The IC operates in this mode under
no load or light load to decrease average power
consumption.
Figure 18: Burst Mode Operation Set-Up
In addition to setting the oscillator maximum
frequency at start-up, Rfmax and determines the
maximum burst mode frequency. After
confirming fmax, calculate Rfmax with Equation
(19):
Rfmin
3
8
(19)
Rfmax
Latch Operation
fmax
1
fmin
The HR1001C provides a simple latch-off
function through LATCH. Applying an external
voltage over VLATCH causes the IC to enter a
latched shutdown. After the IC is latched, its
consumption drops, as shown by the residual
current in the Electrical Characteristics table on
page 5. Resetting the IC requires dropping the
VCC voltage below the UVLO threshold (see
the latch internal block diagram in Figure 20).
Here, fmax corresponds to a load point (PBurst),
where the peak current flow through the
transformer is too low to cause audible noise.
So far, this section has been based on a narrow
input voltage range. As a property of the
resonant circuit, the input voltage determines
the switching frequency. This means PBurst has
a large variance over the wide input voltage
range. To stabilize PBurst over the input range,
use the circuit in Figure 19 to insert the input
voltage signal into the feedback loop.
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HR1001C – ENHANCED LLC CONTROLLER
Low-Side Gate Driver
LG provides the gate driver signal for the low-
side MOSFET. The maximum absolute rating
table shows the maximum voltage on LG is 16V.
Under some conditions, a large voltage spike
occurs on LG due to oscillations from the long
gate driver wire, the MOSFET parasitic
capacitance, and the small gate driver resistor.
This voltage spike is dangerous to LG, so a 15V
Zener diode close to LG and GND is
recommended (see Figure 22).
HR1001C
8
LATCH
+
-
Disable
S
Q
VLATCH
UVLO
R
Figure 20: Latch Function Block
High-Side Gate Driver
SW
The external BST capacitor provides energy to
the high-side gate driver. An integrated
bootstrap diode charges this capacitor through
VCC. This diode simplifies the external driving
circuit for the high-side switch, allowing the BST
capacitor to charge when the low-side MOSFET
is on (see the high-side gate driver internal
block diagram in Figure 21).
Vs
Cgd
Cds
Rg
Low-Side
Driver
LG
11
10
Cgs
15V
HR1001C
GND
To provide enough gate driver energy
(considering the BST capacitor charge time),
use a 100nF to 470nF capacitor for the BST
capacitor.
Figure 22: Low-Side Gate Driver
VCC
12
BST
16
15
CBST
High-Side
Driver
HG
SW
14
Level
Shifter
HR1001C
Figure 21: High-Side Gate Driver
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HR1001C – ENHANCED LLC CONTROLLER
Design Example
Figure 23 shows the detailed application
schematic. The typical performance and circuit
waveforms are shown in the Typical
Performance Characteristics section. The
HR1001C has passed 4kV surge test for 30s
duration on the EV44010-S + HR1001 - S - 00A
evaluation board built with the design example.
A 100W LED driver is designed with the
specifications below (see Table 1).
Table 1: Design Example
Input AC Voltage
Output Voltage
Output Current
90-305VAC
24V
4.16A
PFC Stage
LLC Stage
Figure 23: Design Example for a 24V/4.16A Output
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HR1001C – ENHANCED LLC CONTROLLER
CONTROL FLOW CHARTS
START
VCC capacitor is charged
by external circuit
N
VCC>11V
& BO>2.3V?
Y
Soft Start
Slope
Y
N
detected?
Fixed
DT=350ns
ADTA
Normal operation, IFset
controls fs
Latched
Shutdown
Burst
Mode
CMP
OCP
OTP
Brown-Out
Monitor BO
UVLO
Monitor CS
Vcs>85mV or
Monitor Thermal
Monitor VCC
Monitor Burst
Monitor LATCH
Vcs<-85mV
Monitor TIMER
Y
CS>0.8V
Y
N
N
N
N
N
Enable CMP
BO>5.5V or
BO<1.81V
Burst<1.23V
Y
>150ºC
VCC<8.2V
Y
LATCH>1.85V
N
TIMER>2V
Y
1. Discharge soft-
start capacitor
Y
Monitor current polarity
at the moment of gate
driver turning off
Y
Y
(10µs), increasing
switching frequency
2. TIMER capacitor is
charged (10µs) by an
internal 130µA
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
Stop the
switching pulse
1. Stop the
switching pulse
2. Soft start
capacitor is fully
discharged
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
1. Latch off the
switching pulse
2. Soft-start
capacitor is fully
discharged
1. Switching
frequency is
pushed to
N
Polarity is
wrong?
current source
maximum
Y
2. Soft-start
capacitor is fully
discharged
N
N
Burst>1.26V
Y
CS>0.8V
CMP timer à 52µs
N
3. TIMER
N
N
N
Y
CS>1.5V
Y
<120ºC
VCC>11V
Y
capacitor is
charged by an
internal 130µA
current source
2.3V<BO<5.5V
Y
VCC<8.2V
Y
1. Discharge SS cap
after 1µs delay.
2. VCLK is held.
3. Both HSG and LSG
are turned off
N
Resume the
switching pulse
Y
1. Stop
discharging
soft-start
Y
capacitor
2. Stop
charging TIMER
capacitor
N
N
SS<1.73V
Y(Latch)
CMP timer
out?
Y
TIMER>3.5V
Y
3. Continue
normal
operation
N
1. Stop the
switching pulse
2. Soft start
capacitor is fully
discharged
N
Y
No slope
detected?
1. Stop the
switching pulse
2. TIMER
3. Stop charging
TIMER capacitor
capacitor is
discharged by
external resistor
Turn on the
other gate
driver
N
VCC<8.2V
Y
N
TIMER<0.3V
Y
Figure 24: Control Flow Chart
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HR1001C – ENHANCED LLC CONTROLLER
TYPICAL APPLICATION CIRCUIT
PFC Pre-Regulator
Resonant Half-Bridge
MP44010/
MP44014
HR1001C
Figure 25: Application Circuit
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2/6/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
24
HR1001C – ENHANCED LLC CONTROLLER
SYSTEM TIMING
Unplug from
main input
Over temperature
VCC
VCCH
VCCL
LG/HG
Soft Start
VSS-OCP
VLATCH
LATCH
CS
VCS-OCP
VCS-OCR
TIMER
VTIMER-SD
VTIMER-fmax
VTIMER-R
BO
VBO-On
VBO-Off
Burst
VBurst
Brown-
Out
Burst
Mode
Brown- Normal
UVLO
OTP
OCP
OCP
Latch
OCP
In
Latch
Soft
Shutdown
Start
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
25
HR1001C – ENHANCED LLC CONTROLLER
PACKAGE INFORMATION
SOIC-16
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
26
相关型号：
HR1001CGS
Enhanced LLC Controller with Adaptive Dead-Time Control, Capacitive Mode Protection and Enhanced Surge Protection
MPS
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