HR1001A [MPS]
Enhanced LLC Controller with Adaptive Dead-Time Control;
| 型号： | HR1001A |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Enhanced LLC Controller with Adaptive Dead-Time Control |
| 文件： | 总25页 (文件大小：1407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HR1001A
Enhanced LLC Controller with
Adaptive Dead-Time Control
The Future of Analog IC Technology
DESCRIPTION
HR1001A is the OCP auto-recovery version of
HR1001B.
FEATURES
•
Two-Level
Over-Current
Protection:
Frequency Shift and Auto-Recovery Mode
with Programmable Duration Time
Adaptive Dead-Time Adjustment
Capacitive Mode Protection
50% Duty Cycle, Variable Frequency
Control for Resonant Half-Bridge Converter
600V High-Side Gate Driver with Integrated
Bootstrap Diode with High dv/dt Immunity
High-Accuracy Oscillator
HR1001A is an enhanced LLC controller, which
provides new features of adaptive dead-time
adjustment (ADTA) and capacitive mode
protection (CMP).
•
•
•
The adaptive dead-time adjustment inserts a
dead time between the two complimentary gate
•
outputs automatically.
This is ensured by
keeping the outputs off while sensing the dv/dt
current of the half-bridge switching node. The
ADTA features easier design, lower EMI, and
higher efficiency.
•
•
•
Operates up to 600kHz
Latched Disable Input for Easy Protection
Remote On/Off Control and Brown-Out
Protection through BO
Programmable Burst Mode Operation at
Light Load
Non-Linear Soft Start for Monotonic Output
Voltage Rise
SOIC-16 Package
HR1001A incorporates anti-capacitive mode
•
•
•
protection,
which
prevents
potentially
destructive capacitive mode switching if the
output is shorted or has a severe overload.
This feature protects the MOSFET during
abnormal conditions, making the converter
robust.
APPLICATIONS
HR1001A has a programmable oscillator that
sets both the maximum and minimum switching
frequencies. It starts up at a programmed
maximum switching frequency and decays until
the control loop takes over to prevent excessive
inrush current.
•
•
•
•
•
•
LCD and PDP TVs
Desktop PCs and Servers
Telecom SMPS
AC/DC Adapter, Open-Frame SMPS
Video Game Consoles
Electronic Lighting Ballast
HR1001A enters a controlled burst mode at
light load to minimize the power consumption
and tighten output regulation.
All MPS parts are lead-free, halogen-free, and adhere to the RoS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
HR1001A provides rich protection features,
including two-level OCP, auto—recovery,
external latch shutdown, brown in/out, CMP,
and OTP, improving converter design safety
with minimal extra components.
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
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© 2016 MPS. All Rights Reserved.
1
HR1001A – ENHANCED LLC CONTROLLER
TYPICAL APPLICATION
Vdc
BO
Cbst
BST
SS
16
15
14
13
12
11
10
9
1
Rss
HG
SW
S1
TIMER
2
Lr
CT
Css
3
4
5
6
7
8
CT
Rfmax
NC
FSET
BURST
CS
D1
D2
Output
CHBVS
S2
HR1001A
VCC
LG
Lm
Rfmin
GND
HBVS
BO
VCC
LATCH
Cr
Rf
Cs
Rs
Cf
TL431
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
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© 2016 MPS. All Rights Reserved.
2
HR1001A – ENHANCED LLC CONTROLLER
ORDERING INFORMATION
Part Number*
Package
Top Marking
HR1001AGS
SOIC-16
See Below
* For Tape & Reel, add suffix –Z (e.g. HR1001AGS–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
HR1001A: Part number
LLLLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
SOIC-16
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
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3
HR1001A – ENHANCED LLC CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
BST voltage......………..................-0.3V to 618V
SW voltage …………...... .................-3V to 600V
Max. voltage slew rate of SW….............. 50V/ns
Supply voltage (VCC)……..................Self limited
Sink current of HBVS….. ....................... ± 65mA
Voltage on HBVS...... …. .....-0.3V to Self limited
Source current of FSET…........................... 2mA
Voltage rating of LG………. ............ -0.3V to VCC
Voltage on CS...... …….. .....................-3V to 6V
Other analog inputs and outputs.......-0.3V to 6V
Continuous power dissipation (TA = +25°C) (2)
PIC ………………………. .......................... 1.56W
Junction temperature…. ...........................150°C
Lead temperature ….….............................260°C
Storage temperature….…........ -65°C to +150°C
ESD immunity:
Recommended Operating Conditions (3)
Supply voltage VCC…................... 13V to 15.5V
Analog inputs and outputs................-0.3V to 6V
Operating junction temp (TJ)....-40°C to + 125°C
Thermal Resistance (4) θJA θJC
SOIC-16
80......35 .……°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on a JESD51-7, 4-layer PCB.
BST, HG, SW passes HBM 2.5kV,
other pins can pass HBM 4kV.
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
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4
HR1001A – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS
VCC=13V, CHG=CLG=1nF, CT=470pF, RFSET=12kΩ, TJ=-40°C ~ 125°C, min & max are guaranteed by
characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol Condition
Min
Typ
Max
Units
IC Supply Voltage (VCC)
VCC operating range
VCC high threshold, IC switch on
VCC low threshold, IC switch off
Hysteresis
8.9
10.3
7.5
15.5
11.7
8.9
V
V
V
V
V
VCCH
11
8.2
VCCL
VCC-hys
2.8
VCC clamp voltage
VCC-Clamp IClamp =1mA
16.5
IC Supply Current (VCC)
Before the device turns on,
VCC=VCCH-0.2V
Start-up current
Istart-up
250
1.2
320
1.5
μA
Device on, VBurst<1.23V,
RFSET =12k,
Iq
mA
(Fmin=60kHz)
Quiescent current
Device on VBurst<1.23V
RFSET=3.57k,
Iq-f
1.42
3
1.8
5
mA
mA
(Fburst=200kHz)
Operating current
ICC-nor
Device on VBurst=VFSET
VCC<8.2V or VLATCH>1.85V
or VCS>1.5V or VTIMER>3.5V
or VBO<1.81V or VBO>5.5V
or OTP.
Residual consumption
IFault
240
350
420
μA
High-Side Floating Gate Driver Supply (BST, SW)
BST leakage current
SW leakage current
Current Sensing (CS)
ILK-BST
ILK-SW
VBST=600V, TJ=25°C
VSW=582V, TJ=25°C
12
12
µA
µA
Input bias current
ICS
VCS=0 to VCSlatch
2
µA
V
Frequency shift threshold
OCP threshold
VCS-OCR
VCS-OCP
0.71
1.41
0.78
1.5
0.85
1.59
V
Current polarity comparator ref.
when HG turns off
VCSPR
VCSNR
50
85
131
-50
mV
mV
Current polarity comparator ref.
when LG turns off
-131
-85
Line Voltage Sensing (BO)
Start-up threshold voltage
Turn-off threshold voltage
VBO-On
VBO-Off
2.30
1.81
2.4
5.9
V
V
1.72
5.1
Clamp level
VBO-Clamp
5.5
V
HR1001A Rev.1.1
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3/14/2016
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HR1001A – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC=13V, CHG=CLG=1nF, CT=470pF, RFSET=12kΩ, TJ=-40°C ~ 125°C, min & max are guaranteed by
characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol Condition
Min
Typ
Max
Units
Latch Function (LATCH)
Input bias current (VLATCH=0 to Vth)
LATCH threshold
ILATCH
1
µA
V
VLATCH
1.72
1.85
1.95
Oscillator
TJ=25°C
D
48
47
50
50
52
53
%
%
Output duty cycle
TJ=-40 ~ 125°C
Oscillation frequency
CT peak value
fosc
CT≤150pF, RFSET≤ 2k
600
kHz
V
VCFp
VCFv
VREF
tDMIN
tDMAX
tD-float
tCMP
3.8
0.9
2
CT valley value
V
Voltage reference at FSET
1.87
180
2.05
290
V
CHBVS=5pF, typically
HBVS floating
235
1
ns
µs
ns
µs
Dead-time
250
350
52
450
Timer for CMP
Half-Bridge Voltage Sense (HBVS)
Voltage clamp
VHBVS-Clamp
7.6
V
Minimum voltage change rate can
be detected
dvmin/dt
CHBVS=5pF, typically
180
V/µs
Slope finish to turn-on
delay
Turn-on delay
Td
100
130
ns
Soft-Start Function (SS)
Discharge resistance
Standby Function (BURST)
Disable threshold
Rd
VCS> VCS-OCR
Ω
VBurst
1.17
1.23
30
1.28
100
V
Hysteresis
VBurst-hys
mV
Delayed Shutdown (TIMER)
V
TIMER=1V, VCS=0.85V,
Charge current
ITIMER
80
130
2
180
µA
V
TJ=25°C
Threshold for forced operation at
maximum frequency
VTIMER-fmax
1.80
2.10
Shutdown threshold
Restart threshold
VTIMER-SD
VTIMER-R
3.2
3.5
3.7
V
V
0.21
0.28
0.35
Low-Side Gate Driver (LG, Referenced to GND)
(5)
Peak source current
Isourcepk
Isinkpk
0.75
0.87
A
A
(5)
Peak sink current
Sourcing resistor
Sinking resistor
Fall time
Rsource
Rsink
tf
LG_R@Isrc=0.1 A
LG_R@Isnk=0.1 A
4
2
Ω
Ω
30
ns
HR1001A Rev.1.1
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6
3/14/2016
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HR1001A – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC=13V, CHG=CLG=1nF, CT=470pF, RFSET=12kΩ, TJ=-40°C ~ 125°C, min & max are guaranteed by
characterization, typical is tested under 25°C, unless otherwise specified.
Parameter
Symbol Condition
Min
Typ
Max
Units
Rise time
tLG-r
30
ns
VCC=0 to VCCH,
Isink=2mA
UVLO saturation
1
V
High-Side Gate Driver (HG, Referenced to SW)
Peak source current (5)
Peak sink current (5)
Sourcing resistor
Sinking resistor
Fall time
IHG-source-pk
0.74
0.87
4
A
A
IHG-sink-pk
RHG-source HG_R@Isrc=0.01 A
Ω
RHG-sink
tHG-f
HG_R@Isnk=0.01 A
2
Ω
30
30
ns
ns
Rise time
tHG-r
Thermal Shutdown
Thermal shutdown threshold(5)
150
120
°C
°C
Thermal shutdown recovery
threshold(5)
NOTE:
5). Guaranteed by design.
HR1001A Rev.1.1
www.MonolithicPower.com
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3/14/2016
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HR1001A – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with the design example
on page 22, VAC=120V, Vout=24V, Iout=4.16A, TA=25°C, unless otherwise noted.
93
92
91
90
89
88
87
86
85
84
V
V
LG
LG
5V/div.
5V/div.
V
V
HG
HG
5V/div.
5V/div.
I
I
R
R
1A/div.
1A/div.
V
V
SW
SW
100V/div.
100V/div.
0
1
2
3
4
5
V
LG
10V/div.
V
V
RIPPLE-PP
200mV/div.
RIPPLE-PP
V
SW
200mV/div.
100V/div.
I
R
I
R
V
1A/div.
OUT
1A/div.
10V/div.
I
R
2A/div.
V
LG
V
LG
10V/div.
10V/div.
V
LG
V
5V/div.
SW
100V/div.
V
HG
5V/div.
V
OUT
V
SW
10V/div.
V
100V/div.
SW
I
100V/div.
R
V
1A/div.
OUT
I
R
10V/div.
2A/div.
I
R
2A/div.
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
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8
HR1001A – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with the design example
on page 22, VAC=120V, Vout=24V, Iout=4.16A, TA=25°C, unless otherwise noted.
V
V
RIPPLE-PP
500mV/div.
RIPPLE-PP
1V/div.
V
LG
10V/div.
V
CS
1V/div.
V
TIMER
1V/div.
I
I
OUT
OUT
2A/div.
2A/div.
V
OUT
10V/div.
V
SW
V
100V/div.
LG
V
10V/div.
HG
5V/div.
HBVS
2V/div.
V
CS
V
V
LG
1V/div.
10V/div.
V
CS
V
LG
1V/div.
5V/div.
V
TIMER
V
TIMER
1V/div.
1V/div.
V
OUT
V
OUT
10V/div.
10V/div.
V
SW
V
100V/div.
LG
V
LG
V
HG
5V/div.
5V/div.
5V/div.
V
HBVS
2V/div.
V
HG
V
V
HG
LG
5V/div.
HBVS
5V/div.
HBVS
5V/div.
V
V
2V/div.
2V/div.
V
SW
V
SW
100V/div.
100V/div.
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
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9
HR1001A – ENHANCED LLC CONTROLLER
PIN FUNCTIONS
Pin # Name Description
Soft-start. Connect an external capacitor from SS to GND and a resistor to FSET to set the
maximum oscillator frequency and the time constant for the frequency shift during start-up. An
internal switch discharges the capacitor when the chip turns off (VCC < UVLO, BO < 1.81V or
> 5.5V, LATCH > 1.85V, CS >1.5V, TIMER > 2V, thermal shutdown) to guarantee soft-start.
1
SS
Period between over-current and shutdown. Connect a capacitor and a resistor from
TIMER to GND to set both the maximum duration from an over-current condition before the IC
stops switching, and the delay before the IC resumes switching. Each time the voltage on CS
exceeds 0.78V, an internal 130µA source charges the capacitor; an external resistor
discharges this capacitor slowly. If the voltage on TIMER reaches 2V, the soft-start capacitor
discharges completely, raising its switching frequency to its maximum value. The 130µA
source remains on. When the voltage exceeds 3.5V, the IC stops switching and the internal
current source turns off, then the voltage decays. The IC enters soft start when the voltage
drops below 0.28V. This converter works intermittently with very low average input power
under short-circuit conditions.
2
TIMER
Time set. An internal current source programmed by an external network connected to FSET
charges and discharges a capacitor connected to GND. This determines the converter’s
switching frequency.
Switching frequency set. FSET provides a precise 2V reference. A resistor connected from
FSET to GND defines a current that sets the minimum oscillator frequency. Connect the
phototransistor of an optocoupler to FSET through a resistor to close the feedback loop that
modulates the oscillator frequency. It regulates the converter’s output voltage. The value of
this resistor sets the maximum operating frequency. An R-C series connected from FSET to
GND sets the frequency shift at start-up to prevent excessive inrush energy.
3
4
CT
FSET
Burst mode operation threshold. BURST senses the voltage related to the feedback
control, which is compared to an internal reference (1.23V). When the voltage on BURST is
lower than this reference, the IC enters an idle state and reduces its quiescent current. When
the feedback drives BURST above 1.26V (30mV hysteresis), the chip resumes switching. A
soft start is not invoked. This function enables burst mode operation when the load falls below
a programmed level, determined by connecting an appropriate resistor to the optocoupler to
FSET (see Functional Block Diagram). Connect BURST to FSET if burst mode is not used.
5
BURST
Current sense of half-bridge. CS uses a sense resistor or a capacitive divider to sense the
primary current. CS has the following functions:
•
Over-current regulation: As the voltage exceeds a 0.78V threshold, the soft-start
capacitor on SS discharges internally. The frequency increases, limiting the power
throughput. Under an output short circuit, this normally results in a nearly constant peak
primary current . TIMER limits the duration of this condition.
•
Over-current protection: If the current continues to build despite the frequency increase,
when Vcs>1.5V, the IC stops switching immediately and TIMER continues to be
charged. Once the voltage on TIMER exceeds 3.5V, the IC turns off the internal charge
current and the voltage on TIMER decays. The IC re-enters soft start when the voltage
falls below 0.28V. This is the auto-recovery operation in an over-current condition.
Capacitive mode protection: The moment LG turns off, CS is compared to the VCSNR
CMP threshold. If Vcs > VCSNR, it blocks the HG gate turning on until the slope is
detected, or the CMP timer is complete. The moment HG turns off, CS is compared to
the VCSPR CMP threshold. If Vcs < VCSPR, it blocks the low-side gate turning on until the
slope is detected, or the CMP timer is complete. If a capacitive mode status is detected,
SS is not discharged immediately; there is a 1µs delay. After the blanking delay, SS is
discharged if the fault condition in capacitive mode remains. It avoids the influence of CS
noise effectively. Connect CS to GND if the function is not used.
6
CS
•
HR1001A Rev.1.1
3/14/2016
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HR1001A – ENHANCED LLC CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name Description
Input voltage sense and brown in/out protection. If the voltage on BO is over 2.3V, the
IC enables the gate driver. If the voltage on BO is below 1.81V, the IC is disabled.
7
BO
IC latch off. When the voltage on LATCH exceeds 1.85V, the IC shuts down and lowers its
8
9
LATCH bias current to its near pre-startup level. LATCH is reset when the voltage on VCC is
discharged below its UVLO threshold. Connect LATCH to GND if the function is not used.
Half-bridge dv/dt sense. In order to detect the dv/dt of the half-bridge, a high-voltage
HBVS capacitor is connected between SW and HBVS. The dv/dt current through HVBS is used to
adjust the dead-time adaptively between the high-side gate and the low-side gate.
Ground. Current return for both the low-side gate-driver and the IC bias. Connect all
10
GND
external ground connections with a trace to GND, one for signals and a second for pulsed
current return.
Low-side gate driver output. The driver is capable of a 0.8A source/sink peak current to
drive the lower MOSFET of the half-bridge. LG is pulled to GND during UVLO.
11
12
13
14
LG
VCC
NC
Supply voltage. VCC supplies both the IC bias and the low-side gate driver. A small
bypass capacitor (e.g., 0.1µF) is helpful to get a clean bias voltage for the IC signal.
High-voltage spacer. No internal connection. It isolates the high-voltage pin and eases
compliance with safety regulations (creepage-distance) on the PCB.
High-side switch source. Current return for the high-side gate drive current. SW requires
careful layout to avoid large spikes below ground.
SW
High-side floating gate driver output. HG is capable of a 0.8A source/sink peak current
to drive the upper MOSFET of the half-bridge. An internal resistor connected to SW
ensures that HG does not float during UVLO.
15
16
HG
Bias for floating voltage supply of high-side gate driver. Connect a bootstrap capacitor
between BST and SW. This capacitor is charged by an internal bootstrap diode driven in-
phase with the low-side gate drive.
BST
HR1001A Rev.1.1
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HR1001A – ENHANCED LLC CONTROLLER
FUNCTIONAL BLOCK DIAGRAM
Figure 1: Functional Block Diagram
HR1001A Rev.1.1
3/14/2016
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HR1001A – ENHANCED LLC CONTROLLER
APPLICATION INFORMATION
Oscillator
The RC network connected externally to FSET
determines the normal switching frequency as
well as the soft start switching frequency.
Figure 2 shows the oscillator block diagram. A
modulated current charges and discharges the
CT capacitor repeatedly between its peak valley
thresholds, which determines the oscillator
frequency.
•
Rfmin from FSET to GND contributes the
maximum resistance of the external RC
network when the phototransistor does not
conduct. This sets the FSET minimum
source current, which defines the minimum
switching frequency.
•
Under normal operation, the phototransistor
adjusts the current flow through Rfmax to
modulate the frequency for output voltage
regulation. When the phototransistor is
saturated, the current through Rfmax is at its
maximum as setting the frequency at its
maximum).
•
An RC in series connected between FSET
and GND shifts the frequency at start-up.
(Please see the “Soft-Start Operation”
section for details.)
Figure 2: Oscillator Block Diagram
FSET sets the CT charging current, Iset (IS-1).
When CT passes its peak threshold (3.8V), the
filp-flop is set and a discharge current source of
twice the charge current is enabled. The
difference between these two currents forces
the charge and discharge of CT to be equal.
When the voltage on the CT capacitor falls
below its valley threshold (0.9 V), the flip-flop is
reset and turns off IS-2. This starts a new
switching cycle. Figure 3 shows the detailed
waveform of the oscillator.
Equation (1) and Equation (2) are used to set
the minimum and maximum frequency:
1
fmin
=
(1)
(2)
3⋅CT ⋅Rfmin
1
fmax
=
3⋅CT ⋅(Rfmin || Rfmax
)
Typically, the CT capacitance is between 0.1nF
and 1nF. Equation (3) and Equation (4)
calculate the values of Rfmin and Rfmax
:
1
Rfmin
=
(3)
(4)
3⋅CT ⋅ fmin
Rfmin
=
Rfmax
fmax
−1
fmin
It is recommended to use a CT capacitor
(<=330pF) for best overall temperature
performance.
Figure 3: CT Waveform and Gate Signal
HR1001A Rev.1.1
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HR1001A – ENHANCED LLC CONTROLLER
3⋅10-3
Rss
Soft-Start Operation (SS)
Css
=
(7)
For the resonant half-bridge converter, the
power delivered is inversely proportional to its
switching frequency. To ensure the converter
starts or restarts with safe currents, the soft-
start forces a high initial switching frequency
until the value is controlled by the closed loop.
Select an initial frequency (fstart) at least 4×fmin.
When selecting CSS, there is a trade-off
between the desired soft-start operation and the
OCP speed (see the “Over-Current Protection”
section for details).
The soft start is achieved using an external RC
series circuit, as shown in Figure 4.
Adaptive Dead-Time Adjustment (ADTA)
When operating in inductive mode, the soft
switching of the power MOSFETs result in high
efficiency of the resonant converter. A fixed
dead time may result in hard switching at light
load, especially when the magnetizing
inductance (Lm) is too large. Too long of a dead
time may lead to loss of ZVS, the current may
change polarity during the dead time, then
results in capacitive mode switching. The
adaptive dead-time control adjusts the dead-
time automatically by detecting the dv/dt of the
half-bridge switching node (SW).
Figure 4: Soft-Start Block
When start-up begins, the SS voltage is 0V, the
soft-start resistor (RSS) is in parallel to Rfmin.
Rfming and RSS determine the initial frequency.
Refer to Equation (5):
HR1001A incorporates an intelligent ADTA
logic circuit, which detects SW’s dv/dt and
inserts the proper dead time automatically. The
external circuit is quite simple; connect a
capacitor (5pF, typically) between SW and
HBVS to sense dv/dt. Figure 5 shows the
simplified block diagram of ADTA. Figure 6
shows the operation waveform of ADTA.
1
fstart
=
(5)
3⋅CT ⋅(Rfmin||Rss )
During start-up, CSS charges until its voltage
reaches the reference (2V) and the current
through RSS decays to zero. This period takes
about 5×(RSS×CSS). During this period, the
switching frequency change follows an
exponential curve: initially, the CSS charge
reduces the frequency relatively quickly, but the
rate decreases gradually.
Vbus
HSG
Driver
Lr
VDD
After soft start period, the switching frequency
is dominated by the feedback loop for
regulating the output voltage.
LSG
Driver
Cr
ADTA
Logic
With soft start, the current of resonant tank
increases gradually during the start-up.
D1
Use Equation (6) and Equation (7) to select the
soft-start RC network:
Figure 5: Block Diagram of ADTA
Rfmin
Rss
=
(6)
fstart
−1
fmin
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HR1001A – ENHANCED LLC CONTROLLER
V
in
Im =
(9)
8⋅Lm ⋅ fmax
Then use Equation (10) to design CHBVS
:
C
700uA
Im
oss
(10)
CHBVS
>
2
Where Coss is the output capacitance when
drain-source voltage on MOSFET is near zero
volts (user can refer to the Coss characteristics
curve in MOSFET’s datasheet).
In a typical design Lm=870uH, Vin=450Vdc,
and fmax=140kHz, CHBVS is calculated at 4.5pF,
indicating that 5pF is suitable for most
MOSFETs.
Figure 7 illustrates a possible dead time by
ADTA logic. Note that there are three kinds of
dead time; minimum dead time (DTmin),
maximum dead time (DTmax), and adjusted
dead time (DTadj), which is between DTmin
and DTmax. ADTA logic sets DTmin=235ns.
When the SW’s transition time is smaller than
DTmin, the logic does not let the gate turn on,
which guards against shoot-through between
the low-side and high-side FETs. A maximum
dead time (DTmax=1µs) forces the gate to turn
on, preventing the losses of duty cycle or soft
switching.
Figure 6: Operation Waveform of ADTA
When HG switches off, SW voltage swings from
high to low due to the resonant tank current (ir).
Accordingly, this negative dv/dt pulls current
from HBVS via CHBVS. If the dv/dt current is
higher than the internal comparison current, the
voltage on HBVS (VHBVS) is pulled down and
clamped at zero. When SW stops slewing and
the differential current stops, VHBVS starts to
ramp up. LG turns on after a delay (the
minimum dead time). Dead time is defined as
the duration between the momemt HG turns off
and the moment LG turns on.
ADTA adjusts the dead time automatically and
ensures ZVS. It enables more flexibility in
MOSFET and Lm selection. Also, it prevents
hard switching if the design does not carefully
account for light load or no load. At light load,
the switching frequency goes high, and the
magnetizing current goes low, risking hard
switching that can lead to a thermal or reliability
issue.
When LG switches off, the SW voltage swings
from low to high, and a positive dv/dt current is
detected via CHBVS. The dead time between the
LG turning off and the HG turning on is
maintained automatically by sensing the dv/dt
current.
To avoid damaging HBVS, it should be taken
care with selecting CHBVS. Use Equation (8) to
keep the dv/dt current below 65mA:
dv
(8)
id = CHBVS
< 65mA
dt
If CHBVS is designed too low to sense the dv/dt,
the minimum voltage change rate (dvmin/dt)
must be accounted for to design the proper
CHBVS
.
First, calculate the peak magnetizing current (Im)
with Equation (9):
Figure 7: Dead Time in ADTA
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HR1001A – ENHANCED LLC CONTROLLER
Capacitive Mode Protection (CMP)
If HBVS is not connected, the internal circuit
never detects the differential current from HBVS,
keeping the dead time fixed at 350ns.
When the resonant HB converter output is in
overload or short circuit, it may cause the
converter to run into a capacitive region. In
capacitive mode, the voltage applied to the
resonant tank causes the current of the
resonant tank to lag. Under this condition, the
body diode of one of the MOSFETs is
conducting; the turning on of the other
MOSFET should be prevented to avoid device
failure.
Figure 8 and Figure 9 show the waveforms of
the dead time when HG turns off and when LG
turns off respectively. ADTA logic inserts the
dead time automatically according to the
transition shape of SW.
If HBVS is pulled down too low by the negative
current of CHBVS, the dead time from the HG
turning off to the LG turning on may be too long.
In order to clamp HBVS at zero and ensure an
optimum dead time, a Schottky diode (D1), like
BAT54, is strongly recommended to connect on
HBVS to GND.
The functional block diagram of CMP is shown
in Figure 10.
Figure 11 shows the operating current principle
of capacitive mode protection. CSPOS and
CSNEG stand for the current polarity, which is
generated by comparing the voltage on CS with
the internal VCSNR and VCSPR voltage reference.
VSW
At t0, LG turns off, CSNEG is high, which
means the current is in the correct direction,
operating in inductive mode.
VLG
VHG
VHBVS
At t1, HG turns off. CSPOS is high, which
means the current is in the correct direction,
operating in inductive mode.
At t2, LG turns off for the second time. CSNEG
is low, indicating the current is in the wrong
direction (the low-side MOSFET body diode is
conducting). This means the converter is
operating in capacitive mode.
Figure 8: Dead Time at High to Low Transition
SW does not swing high until the current
returns to the correct polarity. DT stays high
and VOSC is stopped, preventing the other
MOSFET from turning on.This effectively avoids
capacitive switching.
VSW
VLG
VHBVS
VHG
At t3, the current returns to the correct polarity,
and the other MOSFET turns on after the dv/dt
current is detected.
Between t2 and t5, the correct current polarity
cannot be detected, or there is so little current
that it is unable to pull SW up or down.
Eventually, the timer (52µs) for CMP expires,
and the other MOSFET is forced to switch on
(see Figure 11).
Figure 9: Dead Time at Low to High Transition
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HR1001A – ENHANCED LLC CONTROLLER
VHG
VLG
VSW
ir
Figure 10: Block Diagram of CMP and OCP
Figure 12: Capacitive Mode Protection Waveform
Figure 12 shows CMP behavior when the
output is shorted. The current polarity goes in
the wrong direction when LG switches off..The
CMP logic detects this capacitive mode
immediately and prevents HG from turning on.
This avoids destructive capacitive switching.
Once the current (ir) returns to the right polarity,
SW ramps up, dv/dt current is detected, and
HG turns on at the ZVS condition.
Over-Current Protection (OCP)
HR1001A provides two levels of over-current
protection, as shown in Figure 13.
1. The first level of protection occurs when the
voltage on CS (VCS) exceeds 0.78V. Once this
occurs, and two actions take place:
Figure 11 Operating Principle of CMP
When capacitive mode operation is detected,
the Vss control signal goes high, turning on an
internal transistor to discharge Css (after a 1µs
blanking delay). This causes the frequency to
increase to a very high level quickly to limit the
output power. The Vss control is reset, and the
soft start is activated when the first gate driver
is switched off after CMP. The switching
frequency decreases smoothly until the control
loop takes over.
First, the internal transistor connected between
SS and GND turns on for at least 10µs, which
discharges CSS. This creates a sharp increase
in the oscillator frequency, reducing the energy
transferred to the output.
Second, an internal 130µA current source turns
on to charge CTimer, ramping the TIMER voltage.
If VCS drops below 0.78V before the voltage on
TIMER (VTIMER) reaches 2V, both the discharge
of Css and the charge of CTIMER are stopped. The
converter returns to normal operation.
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HR1001A – ENHANCED LLC CONTROLLER
tOC is the time for VTIMER to rise from 0V to 2V. It
is a delay time for over-current regulation.
There is no simple relationship between tOC and
CTiIMER. Select CTIMER based on experimental
results (based on experiments: CTIMER may
increase the operating time by 100ms.)
If VCS is still larger than 0.78V after VTIMER rises
to 2V, Css is discharged completely. At the
same time, the internal 130µA continues to
charge CTIMER until VTIMER reaches 3.5V, then
turns off all gate drivers.
a
Use Equation (11) to calculate the time it takes
for VTIMER to rise from 2V to 3.5V:
Figure 13: OCP Timing Sequence
Current Sensing
tOP = 104 ⋅CTIMER
(11)
There are two current sensing methods:
lossless current sensing and current sensing
with a sense resistor.
It maintains the condition until VTIMER decreases
to 0.28V. then the IC restarts. Use Equation (12)
to calculate this time period:
Generally, a lossless current sensing solution
is used in high-power applications, as shown in
Figure14.
3.5
(12)
≈ 2.5RTIMER ⋅CTIMER
tOFF=RTIMER ⋅CTIMER ⋅ln
0.28
2. The second level of over-current protection is
triggered when VCS rises to 1.5V. Normally, this
condition happens when VCS continues to rise
during a short circuit. The IC stops switching
immediately and Css is discharged completely.
The internal 130µA current source turns on to
charge CTimer. Once VTIMER is charged up to
3.5V, the charge current turns off. The IC
restarts when VTIMER falls below 0.28 V.
Lr
R1
CS
Cs
Cr
C1
Rs
The time sequence of OCP is shown in Figure
13. OCP limits the energy transferred from the
primary side to the secondary side during an
overload or short-circuit condition. Excessive
power consumption due to high continuous
currents can damage the secondary-side
windings and the rectifiers. TIMER provides
additional protection to reduce the average
power consumption. When OCP is triggered,
the converter enters a hiccup-like protection
mode that operates intermittently.
Figure 14: Current Sensing with a Lossless
Network
Use Equation (13) and Equation (14) to design
a lossless current sensing network:
Cr
Cs ≤
(13)
100
Rs chosen must be according to the equation
below:
Cr
0.8
ICrpk
Rs<
⋅(1+
)
(14)
CS
ICrpk is the peak current of the resonant tank at
low input voltage and full load, which is
expressed in Equation (15):
NVO
I π
2N
2
)
ICrpk = (
)2 + ( O
(15)
4Lmfs
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HR1001A – ENHANCED LLC CONTROLLER
Where, N is the turns ratio of transformer, lo
and Vo are the output current and voltage, fs is
the switching frequency, and Lm is the
magnetizing inductance.
Figure 16 shows the line-sensing internal block
diagram.
For capacitive mode detection in no load or tiny
load condition, Rs should fulfill the condition in
Equation (16) as well:
85mV
Im
Cr
(16)
RS >
(1+
)
CS
In some conditions, especially large Lm used,
it’s difficult to fulfill Equation (14) and (16) both.
It operates without CMP function at light load if
it’s without the restriction of Equation (16).
Figure 16: Input Voltage Sensing Block
If VBO is higher than 2.3V, the IC provides the
gate driver outputs; the IC does not stop the
gate driver until VBO drops below 1.81V.
The R1 and C1 network is used to attenuate
switching noise on CS. The time constant
should be in the range of 100ns.
First, for a minimum operation input voltage of
half-bridge (VIN-min), select a value for RH large
enough to reduce power loss at no load. Then
RL is calculated with Equation (18):
An alternate solution uses a sense resistor in
series with the resonant tank, as shown in the
Figure 15. This method is simple but causes
unnecessary power loss on the sense resistor.
1.81
(18)
RL = RH ⋅
V
−1.81
IN-min
For additional protection, the IC shuts down
when VBO exceeds the internal 5.5V clamp
voltage. When VBO is between 2.3V and 5.5V,
the IC operates normally.
Burst Mode Operation
At light load or in the absence of a load, the
maximum frequency limits the resonant half-
bridge switching frequency. To control the
output voltage and limit power consumption,
HR1001A enables compatible converters to
operate in burst mode. This greatly reduces the
average switching frequency, thus reducing the
average residual magnetizing current and the
associated losses.
Cr
R1
CS
C1
Rs
Figure 15: Current Sensing with a Sense
Resistor
Design the sense resistor using Equation (17):
0.78
RS =
(17)
Operating in burst mode requires setting
ICrpk
BURST. If the voltage on BURST (VBURST
)
drops below 1.23V, HR1001A shuts down the
HG and LG gate drive outputs, only leaving the
2V reference voltage on FSET and SS to retain
the previous state and minimize the power
consumption. When VBURST exceeds 1.23V over
30mV, HR1001A resumes normal operation.
Input Voltage Sensing (BI/BO)
HR1001A stops switching when the input
voltage drops below a specified value. It
restarts when the input voltage returns to
normal. This function guarantees that the
resonant half-bridge converter always operates
within the specified input-voltage range. The IC
senses the voltage on BO (VBO) through the tap
of a resistor divider connected to the rectified
AC voltage or the PFC output.
Based on the burst mode operating principle,
the BURST must be connected to the feedback
loop. Figure 17 shows a typical circuit
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HR1001A – ENHANCED LLC CONTROLLER
connecting BURST to the feedback signal for
narrow-input-voltage range applications.
must rise over the setting value, which increases
the current flowing through the optocoupler.
Therefore, the voltage on Rfmax rises due to the
increased phototransistor current. Then VBURST
drops below 1.23V, triggering the gate signal off
state. Until the output voltage falls below the
setting value, the current flow through the
optocoupler decreases, causing VBURST to rise.
When VBURST exceeds 1.23V over 30mV, the IC
restarts to generate the gate signal. The IC
operates in this mode under no load or light load
to decrease the average power consumption.
Figure 17: Burst Mode Operation Set-Up
In addition to setting the oscillator maximum
frequency at start-up, Rfmax determines the
maximum burst mode frequency. After confirming
Latch Operation
HR1001A provides a simple latch-off function
through LATCH. Applying an external voltage
over 1.85V causes the IC to enter a latched
shutdown. After the IC is latched, its consumption
drops, as shown by the residual current in the EC
table. Resetting the IC requires dropping the
VCC voltage below the UVLO threshold (see the
latch internal block diagram in Figure 19).
f
max, calculate Rfmax with Equation (19):
Rfmin
3
8
Rfmax
=
⋅
(19)
fmax
−1
fmin
Here, fmax corresponds to a load point (PBurst),
where the peak current flow through the
transformer is too low to cause audible noise.
The above introduction is based on a narrow-
input-voltage range. As a property of the
resonant circuit, the input voltage determines the
switching frequency as well. This means PBurst
has a large variance over the wide-input-voltage
range. To stabilize PBurst over the input range,
use the circuit in Figure 18 to insert the input
voltage signal into the feedback loop.
9
LATCH
+
-
Disable
S
R
Q
1.85 V
UVLO
Figure 19: Latch Function Block
High-Side Gate Driver
The external BST capacitor provides energy to
the high-side gate driver. An integrated bootstrap
diode charges this capacitor through VCC. This
diode simplifies the external driving circuit for the
high-side switch, allowing the BST capacitor to
charge when the low-side MOSFET is on (see
the high-side gate driver internal block diagram in
Figure 20).
Figure 18: Burst Mode Operation Set-Up for a
Wide Input Voltage Range
RB1 and RB2 in Figure 18 correct against the
wide-input-voltage range. Select both resistors
based on experimental results. Note that the total
resistance of RB1 and RB2 should be much larger
than RH to minimize the effect on VBO. During
burst mode operation, when the load is lower
than PBurst, the switching frequency is clamped at
the maximum frequency. The output voltage
To provide enough gate driver energy
(considering the BST capacitor charge time), use
a 100nF to 470nF capacitor for the BST capacitor.
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HR1001A – ENHANCED LLC CONTROLLER
Figure 20: High-Side Gate Driver
Low-Side Gate Driver
LG provides the gate driver signal for the low-
side MOSFET. The maximum absolute rating
table shows the maximum voltage on LG is 16V.
Under some conditions, a large voltage spike
occurs on LG due to oscillations from the long
gate-driver wire, the MOSFET parasitic
capacitance, and the small gate-driver resistor.
This voltage spike is dangerous to LG, so a 15V
Zener diode close to LG and GND pins is
recommended (as shown in Figure 21).
Figure 21: Low-Side Gate Driver
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HR1001A – ENHANCED LLC CONTROLLER
Design Example
A 100W LED driver is designed with the
specifications below (see Table 1):
Figure 22 shows the detailed application
schematic. The typical performance and circuit
waveforms have been shown in the “Typical
Performance Characteristics” section.
Table 1: Design Example
Input AC voltage
Output voltage
Output current
90-305VAC
24V
4.16A
PFC Stage
R28
R29
R30
R31
53.6k
3M/1206
3M/1206
3M/1206
C19
47nF/1206
PQ2620
L5
Lr=180uH
T1
Q8
PQ26/20 36:4:4:4 Lm=0.87mH
GND
D10
1N4148
2
1
SGND
VOUT
L6
VOUT
14uH
C32 NC
VOUT 24V/4.1A
R54 NC
C26
0.47uF/25V
1
C27
1
0.22uF/25V/0805
C37
C110
C111
R34
10/0805
C34
16
15
14
13
12
11
10
9
C28
10nF/1000V
C45
SS
BST
HG
VG1
Q5
IPP65R600E
1uF/50V/0805
R36
LED1
4.7uF/50V
820k
R35
100K/0603
1000uF/35V
1000uF/35V
2
3
4
5
6
7
8
Q7
TIMER
CT
GND
100nF/50V/0805
R38
3K
SW
C30
470pF/50V
R55
NC
C41
NC
U2
C46
5pF/1KV
C113
NC
C31
2.2uF/25V/0805
R57
1K
NC
Fset HR1001A
D12
R39
10.7k
1N4148
2 1
2.2nF/4000V
CY3
Burst
VCC
LG
VCC
C35
C33
10nF/50V
U4
EL357N
R40
2K
R41
10K
1
CS
BO
C44
R33
R42
10/0805
R58
1K
Q6
102k
GND
1uF/50V/0805
IPP65R600E
1nF/50V
C36
0.1uF/25V
R44
100K/0603
D17
R45
0/1206
2
1
LATCH
HBVS
C112
R56
30k
BAT54
C39
R50
10K
C40
220pF/1KV/1206
27nF/50V
10nF/50V
C114
R52
100
D13
NC
B160/60V/1A
U3
1
R51
C42
1nF/50V
30/1206
TL431
D16
BZT52C30
BIAS
R59
C52
1uF/50V
11.86k
C49
100uF/35V
C43
R53
0/1206
100uF/35V
D103
BZT52C5V1
VOUT
VOUT
100k
R101
VD2
1
2
3
4
5
6
7
14
PGND
PGND
VG2
EN
R108
NC
13
12
11
10
9
VG1
VDD
RCP
NC
C104
C101
10nF/50V/0603
U6
100nF/50V
20k
R102
LL
C102
1nF/50V
MP6922DS
C103
NC
100K
R103
R109
0
NC
VD2
VS2
VD1
VS1
8
R105
1k
R106
1k
R107
4.99
D101
D102
1N4148
2
1
1N4148
R104
4.99
LLC Stage
Figure 22: Design Example for a 24V/4.16A Output
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HR1001A – ENHANCED LLC CONTROLLER
CONTROL FLOW CHARTS
START
VCC capacitor is charged
by external circuit
N
VCC>11 V
& BO>2.3 V?
Y
Soft Start
Slope
Y
N
detected?
Fixed
DT=350ns
ADTA
Normal operation, IFset
controls fs
Latched
Shutdown
Burst
Mode
CMP
OCP
OTP
Brown-Out
Monitor BO
UVLO
Monitor CS
Vcs>85mV or
Monitor Thermal
Monitor VCC
Monitor Burst
Monitor LATCH
Vcs<-85mV
Monitor TIMER
Y
CS>0.78V
Y
N
N
N
N
N
Enable CMP
BO>5.5 V or
BO<1.81 V
Burst<1.23 V
Y
>150ºC
VCC<8.2 V
Y
LATCH>1.85V
N
TIMER>2V
Y
Y
Monitor current polarity
once the gate driver is
turning off
Y
Y
1. Discharge soft-
start capacitor
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
(10µs), increasing
switching frequency
2. TIMER capacitor is
charged (10µs) by an
internal 130µA
Stop the
switching pulse
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
1. Latch off the
switching pulse
2. Soft-start
capacitor is fully
discharged
N
Switching
frequency is
pushed to
maximum
N
Polarity is
wrong?
current source
Y
N
Burst>1.26 V
Y
CMP timer
52us
1. Soft-start
capacitor is fully
discharged
2. TIMER
capacitor is
charged by an
internal 130µA
current source
N
N
N
<120ºC
N
VCC>11 V
Y
2.3 V<BO<5.5 V
Y
VCC<8.2V
Y
CS>0.78V
1. Discharge S cap
after 1µs delay
2. VCLK is held
3. Both HSG and LSG
are turned off
Resume the
switching pulse
Y
Y
1. Stop
discharging the
soft-start
N
CS>1.5V
Y
capacitor
2. Stop charging
the TIMER
capacitor
3. Continue
normal operation
CMP timer
out?
Y
Y(auto-
recovery)
N
TIMER>3.5V
Y
Stop switching
immediately
N
N
Y
No Slope
detected?
1. Stop the
switching pulse
2. TIMER
capacitor is
discharged by
external resistor
Turn on the
other gate
driver
N
TIMER<0.28 V
Y
Figure 23: Control Flow Chart
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
23
HR1001A – ENHANCED LLC CONTROLLER
TYPICAL APPLICATION CIRCUITS
PFC Pre-Regulator
Resonant Half-Bridge
Figure 24: Application Circuit
SYSTEM TIMING
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
24
HR1001A – ENHANCED LLC CONTROLLER
PACKAGE INFORMATION
SOIC-16
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
25
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