PS21767-V [MITSUBISHI]
Dual-In-Line Package Intelligent Power Module; 双列直插式封装智能功率模块
| 型号： | PS21767-V |
| 厂家： | 
Mitsubishi Group |
| 描述： | Dual-In-Line Package Intelligent Power Module |
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHISEMICONDUCTOR<Dual-In-LinePackageIntelligentPowerModule>
PS21767-V
TRANSFER-MOLDTYPE
INSULATEDTYPE
PS21767-V
INTEGRATED POWER FUNCTIONS
600V/30A low-loss CSTBTTM inverter bridge with N-side
three-phase output DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply).
• Input interface : 3, 5V line (High Active)
• UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
0.2
0.2
(2.2)
A = 1.78
B = 4.32
(2.2)
(11×1.78)
F
5.6
0.3
2.04
(1.7)
(1.7)
B
B
B
B
B
0.2
1.78
A
A
A
A
A
2
D
28 27 26 25 24 23 22 21 201918 16
17
15 13
14
12 10
11
9
7
6
4
3
1
2
8
5
29
Type name, Lot No.
30
C
C
QR
CODE
32
33
34
35
36
37
38
31
0.3
0.3
0.3
0.3
0.3
7.62
6.6
7.62
7.62
7.62
TERMINAL CODE
(1)
0.3
0.3
3.95
3.3
0.3
1
2
3
4
5
6
7
8
9
VUFS 20 VNO
(UPG) 21 UN
VUFB 22 VN
HEAT SINK SIDE
1.55
3.1
3.3
0.2
0.1
46
3.25
VP1
(COM) 24 FO
UP 25 CFO
23 WN
52.5
(0.6)
(1)
(φ3.5)
φ3.3
(2.9)
(1.6)
0.5
1.5
VVFS 26 CIN
(VPG) 27 VNC
VVFB 28 VN1
1
E
2
10 VP1
11 (COM) 30 (VNG)
12 VP 31 NW
29 (WNG)
13 VWFS 32 NV
14 (WPG) 33 NU
15 VWFB 34 W
(0.75)
(φ3.7)
16 VP1
17 (COM) 36 U
18 WP 37 P
19 (UNG) 38 NC
35 V
C-C
DETAIL D
DETAIL E
Note: All outer lead terminals are with lead free solder (Sn-Cu) plating.
Aug. 2007
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Ratings
Unit
V
Applied between P-NU, NV, NW
Applied between P-NU, NV, NW
Supply voltage
Supply voltage (surge)
450
500
VCC
VCC(surge)
VCES
IC
V
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
V
600
30
A
Tc = 25°C
ICP
60
A
Tc = 25°C, less than 1ms
Tc = 25°C, per 1 chip
PC
Tj
90.9
–20~+150
W
°C
Junction temperature
CONTROL (PROTECTION) PART
Symbol
Parameter
VD
Control supply voltage
Condition
Ratings
20
Unit
V
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP, UN, VN, WN-
VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
VDB
Control supply voltage
V
V
20
VIN
Input voltage
–0.5~VD+0.5
–0.5~VD+0.5
Fault output supply voltage
Fault output current
Current sensing input voltage
V
mA
V
VFO
IFO
VSC
1
–0.5~VD+0.5
TOTAL SYSTEM
Symbol
Ratings
400
Unit
V
Condition
Parameter
Self protection supply voltage limit
(short circuit protection capability)
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
VCC(PROT)
Module case operation temperature
(Note 1)
–20~+100
–40~+125
°C
°C
Tc
Tstg
Storage temperature
60Hz, Sinusoidal, AC 1 minute,
All pins to heat-sink plate
Viso
Isolation voltage
2500
Vrms
Note 1 : TC measurement point
Control Terminals
DIP-IPM
18mm
18mm
Groove
IGBT Chip position
FWDi Chip position
Tc point
Heat sink side
Power Terminals
Aug. 2007
2
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Limits
Symbol
Parameter
Condition
Unit
Min.
—
Typ.
—
Max.
1.1
Rth(j-c)Q
Rth(j-c)F
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
°C/W
°C/W
Junction to case thermal
resistance (Note 2)
—
—
2.8
Note 2 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal con-
ductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and the
thermal conductivity is 1.0W/m·k
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Limits
Symbol
VCE(sat)
Parameter
Condition
Unit
V
Min.
—
Typ.
Max.
2.20
2.30
2.00
1.90
—
VD = VDB = 15V
VIN = 5V
IC = 30A, Tj = 25°C
IC = 30A, Tj = 125°C
Tj = 25°C, –IC = 30A, VIN = 0V
1.70
1.80
1.50
1.30
0.30
0.50
1.50
0.35
—
Collector-emitter saturation
voltage
—
—
FWDi forward voltage
VEC
ton
trr
V
µs
µs
µs
µs
µs
0.70
—
VCC = 300V, VD = VDB = 15V
—
↔
5V
tc(on)
toff
tc(off)
IC = 30A, Tj = 125°C, VIN = 0
0.80
2.10
0.55
1
Switching times
—
Inductive load (upper-lower arm)
—
Tj = 25°C
Tj = 125°C
—
Collector-emitter cut-off
current
ICES
mA
VCE = VCES
—
—
10
CONTROL (PROTECTION) PART
Symbol Parameter
Limits
Typ.
—
Condition
Unit
Min.
—
Max.
7.00
0.55
7.00
0.55
—
0.95
0.53
2.0
mA
mA
mA
mA
V
VD = VDB = 15V
VIN = 5V
Total of VP1-VNC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Total of VP1-VNC, VN1-VNC
—
—
Circuit current
ID
—
—
VD = VDB = 15V
VIN = 0V
—
—
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
4.9
—
—
—
VFOH
VFOL
VSC(ref)
IIN
VSC = 0V, FO terminal pull-up to 5V with 10kΩ
Fault output voltage
V
VSC = 1V, IFO = 1mA
Short circuit trip level
Input current
0.43
1.0
10.0
10.5
10.3
10.8
1.0
—
0.48
1.5
—
V
Tj = 25°C, VD = 15V
VIN = 5V
(Note 3)
mA
V
Trip level
12.0
12.5
12.5
13.0
—
UVDBt
UVDBr
UVDt
UVDr
tFO
Reset level
Trip level
—
V
Control supply under-voltage
protection
Tj ≤ 125°C
—
—
V
V
Reset level
1.8
2.3
1.4
0.9
ms
V
CFO = 22nF
(Note 4)
Fault output pulse width
ON threshold voltage
2.6
Vth(on)
Vth(off)
Vth(hys)
Applied between UP, VP, WP, UN, VN, WN-VNC
0.8
0.5
—
V
OFF threshold voltage
ON/OFF threshold hysteresis voltage
—
V
Note 3: Short circuit protection is functioning only at the low-arms. Please select the external shunt resistance such that the SC trip-level is
less than 2.0 times of the current rating.
4: Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions works. The fault output pulse-
width tFO depends on the capacitance of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F].
Aug. 2007
3
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Limits
Condition
Recommended : 0.78 N·m
Unit
Min.
Typ.
—
Max.
Mounting torque
Weight
Mounting screw : M3
0.59
—
0.98
—
N·m
g
µm
21
—
(
)
Heat-sink flatness
Note 5
–50
100
Note 5 : Flatness measurement position
Measurement position
3mm
+ –
Heat sink side
–
+
Heat sink side
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Supply voltage
Recommended value
Condition
Unit
Min.
Typ.
Max.
VCC
Applied between P-NU, NV, NW
0
13.5
13.0
–1
300
15.0
15.0
—
400
16.5
18.5
1
V
V
VD
Control supply voltage
Control supply voltage
∆VD, ∆VDB
Control supply variation
Applied between VP1-VNC, VN1-VNC
VDB
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
V
V/µs
µs
kHz
2
—
tdead
Arm shoot-through blocking time For each input signal, Tc ≤ 100°C
—
—
—
fPWM
PWM input frequency
Tc ≤ 100°C, Tj ≤ 125°C
20
VCC = 300V, VD = VDB = 15V,
P.F = 0.8, sinusoidal PWM
Tc ≤ 100°C, Tj ≤ 125°C (Note 6)
fPWM = 5kHz
fPWM = 15kHz
—
—
21
IO
Output r.m.s. current
Arms
—
16
—
—
—
0.3
PWIN(on)
(Note 7)
Below rated current
200 ≤ VCC ≤ 350V,
13.5 ≤ VD ≤ 16.5V,
—
—
—
—
—
—
1.6
3.3
Minimum input
pulse width
µs
13.0 ≤ VDB ≤ 18.5V,
–20°C ≤ Tc ≤ 100°C,
N-line wiring inductance less
Between rated current and
1.7 times of rated current
PWIN(off)
Between 1.7 times and
(Note 8)
2.0 times of rated current
3.9
than 10nH
—
—
VNC
Tj
VNC voltage variation
Junction temperature
–5.0
–20
5.0
125
V
°C
Between VNC-NU, NV, NW (including surge)
Note 6: The allowable r.m.s. current value depends on the actual application conditions.
7: Input signal with ON pulse width less than PWIN(on) might make no response.
8: IPM might make delayed response (less than about 2µsec) or no response for the input signal with off pulse width less than PWIN(off).
Please refer Fig. 2 about delayed response and Fig. 6 about N-line inductance.
Aug. 2007
4
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 ABOUT DELAYED RESPONSE AGAINST SHORTER INPUT OFF SIGNAL THAN PWIN (off) (P side only)
P side control input
Internal IGBT gate
t2
t1
Output current Ic
...
Real line off pulse width > PWIN(off) : turn on time t1
...
Broken line off pulse width < PWIN(off) : turn on time t2
Fig. 3 THE DIP-IPM INTERNAL CIRCUIT
V
UFB
UFS
DIP-IPM
P
V
HVIC1
V
B
IGBT1
Di1
VP1
V
CC
UP
HO
IN
V
S
B
COM
U
VVFB
VVFS
HVIC2
V
V
CC
VP1
IGBT2
Di2
HO
IN
VP
V
S
B
COM
V
V
WFB
WFS
V
HVIC3
V
VP1
V
CC
IGBT3
IGBT4
Di3
Di4
VP
HO
IN
V
S
COM
W
LVIC
UOUT
NU
VN1
VCC
IGBT5
IGBT6
Di5
Di6
Fo
Fo
V
OUT
NV
U
N
N
N
UN
V
VN
WOUT
W
WN
NW
V
NO
CIN
VNO
VNC
GND
CFO
CFO
CIN
Aug. 2007
5
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input “L” : IGBT OFF.
a7. Input “H”
a8. IGBT OFF state in spite of input “H”.
Lower-arms control
input
a6 a7
Protection circuit state
Internal IGBT gate
SET
a2
RESET
a3
SC
a4
a1
Output current Ic
a8
SC reference voltage
Sense voltage of the
shunt resistor
CR circuit time
constant DELAY
Fault output Fo
a5
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT turns OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
b1
SET
RESET
UVDr
Control supply voltage V
D
b6
UVDt
b2
b3
b4
b7
Output current Ic
Fault output Fo
b5
Aug. 2007
6
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage level reaches UVDBr, the circuits start to operate.
c2. Protection circuit state reset : IGBT ON and carrying current.
c3. Normal operation : IGBT ON and carrying current.
c4. Under-voltage trip (UVDBt).
c5. IGBT OFF inspite of control input condition, but there is no FO signal output.
c6. Under-voltage reset (UVDBr).
c7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
SET
RESET
c6
UVDBr
Control supply voltage VDB
c1
c2
UVDBt
c3
c4
c5
c7
Output current Ic
High-level (no fault output)
Fault output Fo
Fig. 5 RECOMMENDED MCU I/O INTERFACE CIRCUIT
5V line
DIP-IPM
10kΩ
UP,VP,WP,UN,VN,WN
MCU
Fo
NC(Logic)
V
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
Fig. 6 RECOMMENDED WIRING AROUND THE SHUNT RESISTOR
DIP-IPM
Each wiring inductance should be less than 10nH
Equivalent to the inductance of a copper
pattern in dimension of width=3mm,
thickness=100µm, length=17mm
V
NC
NO
NU
NV
V
NW
Shunt resistor
The GND wiring from VNO, VNC should be
as close to the shunt resistors as possible
Aug. 2007
7
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21767-V
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1: Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering
V
UFB
UFS
C2
C1
DIP-IPM
V
P
U
HVIC1
V
P1
V
CC
V
B
C3
C3
C3
U
P
IN
HO
COM
VS
C2
C1
V
V
VFB
VFS
HVIC2
V
P1
V
CC
VB
V
P
IN
HO
V
COM
VS
M
C2
C1
V
V
WFB
WFS
HVIC3
V
P1
V
CC
VB
W
P
IN
HO
W
COM
V
S
LVIC
U
OUT
NU
V
U
N1
V
CC
C3
5V line
V
OUT
NV
N
U
N
V
N
V
N
W
OUT
C
W
N
W
N
NW
CIN
Fo
F
o
Too long wiring here might
cause short-circuit.
CFO
V
NC
NO
GND
V
NO
V
CIN
CFO
C4(CFO
)
If this wiring is too long, the SC
level fluctuation might be larger
and cause SC malfunction.
15V line
Shunt resistors
A
N1
R1
C5
B
+
-
Vref
Vref
Vref
Long GND wiring here might
generate noise to input and cause
IGBT malfunction.
R1
C5
B
B
+
-
R1
C5
+
-
OR Logic
Comparator
External protection circuit
Note 1
:
Input drive is High-active type. There is a 2.5kΩ(Min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each in-
put should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage.
2
3
: Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
: FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ.
FO output pulse width is determined by the external capacitor (CFO) between CFO and VNC terminals (e.g CFO = 22nF → tFO =
1.8ms (typ.))
4
5
: To prevent erroneous protection, the wiring of A, B should be as short as possible.
: The time constant R1C5 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C5.
6
7
: All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency character-
istic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.)
: To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.
: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
: If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended
to connect control GND and power GND at only a point.
8
9
10 : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V).
11 : OR logic output high level should exceed the maximum short circuit trip level (Vsc(ref): max.0.53V).
Aug. 2007
8
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