PS21864 [MITSUBISHI]
AC Motor Controller, 30A, Hybrid, DIP-41;
| 型号： | PS21864 |
| 厂家： | 
Mitsubishi Group |
| 描述： | AC Motor Controller, 30A, Hybrid, DIP-41 电动机控制 |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHISEMICONDUCTOR<Dual-In-LinePackageIntelligentPowerModule>
PS21864/-A
TRANSFER-MOLDTYPE
INSULATEDTYPE
PS21864
INTEGRATED POWER FUNCTIONS
600V/15A low-loss 5th generation IGBT inverter bridge for
3 phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). (Fig.3)
• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
• Input interface : 5V line CMOS/TTL compatible. (High Active)
• UL Approved :Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
TERMINAL CODE
1. UP
14. VN1
27✕2.8(=75.6)
2. VP1
3. VUFB
4. VUFS
5. VP
6. VP1
7. VVFB
8. VVFS
9. WP
10. VP1
11. VPC
12. VWFB 25.
13. VWFS 26.
15. VNC
16. CIN
17. CFO
18. FO
19. UN
20. VN
21. WN
±0.3
2.8
(8.5)
Heat sink side
(2.2)
C
(2.5)
(2.4) (14.4)
(17.6)
(2.4)
34
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15 16 17 18 19 20 21
27
28
30
31
33
35
22.
23.
24.
P
U
V
W
N
36
29
32
±0.2
2-f4.5
37
38
39
Type name , Lot No.
41
40
DUMMY TERMINAL CODE
(0.6)
(2)
27. VPC
28. UPG
29. P
30. VPC
31. VPG
35. UNG
36. VNC
37. VNO
38. WNG
39. VNG
22
23
±0.3
24
±0.3
25
±0.3
26
(1.5)
±
0.3
±0.3
8.5
(0.6)
(2)
10
10
10
20
±0.2
3.8
±0.3
±0.5
67
32.
33. WPG
34.
U
40.
41.
W
P
79
±0.05
±0.05
1.7
±0.2
0.8
1.9
±0.2
V
1
A
B
3.25MAX
1.85MAX
Detail : A
(t=0.7)
Detail : B
(t=0.7)
Detail : C
Heat sink side
✕ -A : Long terminal type (16.0mm)
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
High-side input (PWM)
(5V line) (Note 1,2)
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2
C1
Input signal Input signal Input signal
conditioning conditioning conditioning
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
Level shifter Level shifter Level shifter
(Note 6)
Protection
circuit (UV)
Protection
Protection
circuit (UV)
circuit (UV)
DIP-IPM
Drive circuit Drive circuit Drive circuit
Inrush current
limiter circuit
P
AC line input
H-side IGBT
S
U
V
(Note 4)
M
W
C
Fig. 3
N1
AC line output
Z
N
L-side IGBT
S
VNC
CIN
Z : ZNR (Surge absorber)
Drive circuit
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
Control supply
Under-Voltage
protection
Protection
circuit
Fo logic
Input signal conditioning
Low-side input (PWM)
F
O
CFO
(5V line)
(Note 1, 2)
Fault output (5V line)
(Note 3, 5)
VNC
VD
(15V line)
Note1: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
3: This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.
(see also Fig. 8)
4: The wiring between the power DC link capacitor and the PN1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these PN1 DC power input pins.
5: Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))
6: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
Drive circuit
P
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
Trip Level
H-side IGBTS
L-side IGBTS
U
V
W
External protection circuit
Shunt Resistor
(Note 1)
A
N
N1
VNC
R
C
Drive circuit
CIN
Collector current
waveform
B
Protection circuit
C
(Note 2)
0
2
tw (µs)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Applied between P-N
Ratings
Unit
V
Supply voltage
Supply voltage (surge)
450
500
VCC
VCC(surge)
VCES
±IC
Applied between P-N
V
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
V
600
15
A
Tf = 25°C
±ICP
PC
Tj
30
A
Tf = 25°C, less than 1ms
Tf = 25°C, per 1 chip
43.5
–20~+125
W
°C
Junction temperature
(Note 1)
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C).
CONTROL (PROTECTION) PART
Symbol
VD
Parameter
Control supply voltage
Condition
Ratings
20
Unit
V
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
VDB
Control supply voltage
V
V
20
VIN
Input voltage
–0.5~VD+0.5
–0.5~VD+0.5
Fault output supply voltage
Fault output current
Current sensing input voltage
V
mA
V
VFO
IFO
VSC
1
–0.5~VD+0.5
TOTAL SYSTEM
Symbol
Ratings
400
Unit
V
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
Parameter
Self protection supply voltage limit
(short circuit protection capability)
VCC(PROT)
Module case operation temperature
(Note 2)
–20~+100
–40~+125
°C
°C
Tf
Tstg
Storage temperature
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Viso
Isolation voltage
2500
Vrms
Note 2 : Tf MEASUREMENT POINT
Al Board Specification :
Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm
Groove
Control Terminals
DIP-IPM
AI board
18mm
13.5mm
P
U
V
W
N
Temp. measurement point
(inside the AI board)
IGBT Chip
Power Terminals
Temp. measurement point
(inside the AI board)
FWDi Chip
Silicon-grease should be applied evenly with a thickness of 100~200µm
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Limits
Symbol
Parameter
Condition
Unit
Min.
—
Typ.
—
Max.
2.30
3.20
Rth(j-f)Q
Rth(j-f)F
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
°C/W
°C/W
Junction to case thermal
resistance (Note 3)
—
—
Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Limits
Symbol
VCE(sat)
Parameter
Condition
Unit
V
Min.
—
Typ.
Max.
2.20
2.30
2.00
2.10
—
VD = VDB = 15V
VIN = 5V
IC = 15A, Tj = 25°C
IC = 15A, Tj = 125°C
Tj = 25°C, –IC = 15A, VIN = 0V
1.70
1.80
1.50
1.50
0.30
0.50
1.40
0.50
—
Collector-emitter saturation
voltage
—
—
FWDi forward voltage
VEC
ton
V
µs
0.80
—
µs
µs
µs
µs
VCC = 300V, VD = VDB = 15V
trr
—
↔
5V
tc(on)
toff
IC = 15A, Tj = 125°C, VIN = 0
0.70
2.10
0.80
1
Switching times
—
Inductive load (upper-lower arm)
tc(off)
—
Tj = 25°C
Tj = 125°C
—
Collector-emitter cut-off
current
ICES
mA
VCE = VCES
—
—
10
CONTROL (PROTECTION) PART
Symbol
Parameter
Limits
Typ.
—
Condition
Unit
Min.
—
Max.
5.00
0.40
7.00
0.55
—
mA
mA
mA
mA
V
VD = VDB = 15V
VIN = 5V
Total of VP1-VPC, VN1-VNC
—
—
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Total of VP1-VPC, VN1-VNC
ID
Circuit current
—
—
VD = VDB = 15V
VIN = 0V
—
—
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
4.9
—
—
VFOH
VFOL
VSC(ref)
IIN
VSC = 0V, FO circuit pull-up to 5V with 10kΩ
VSC = 1V, IFO = 1mA
Tj = 25°C, VD = 15V
VIN = 5V
Fault output voltage
—
0.95
0.53
2.0
V
0.43
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8
0.48
1.5
—
V
Short circuit trip level
Input current
(Note 4)
mA
V
Trip level
12.0
12.5
12.5
13.0
—
UVDBt
UVDBr
UVDt
UVDr
tFO
Reset level
—
V
Supply circuit under-voltage
protection
Tj ≤ 125°C
Trip level
—
V
Reset level
CFO = 22nF
—
V
1.8
2.3
1.4
ms
V
(Note 5)
Fault output pulse width
ON threshold voltage
OFF threshold voltage
2.6
Vth(on)
Vth(off)
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
2.1
V
Note 4: Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 25.5 A.
5: Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F].
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Limits
Condition
Recommended 1.18 N·m
Unit
Min.
Typ.
—
Max.
Mounting torque
Weight
Mounting screw : M4
0.98
—
1.47
—
N·m
g
65
—
(
)
µm
Heat-sink flatness
Note 6
–50
100
Note 6: Measurement point of heat-sink flatness
+
–
3mm
Measurement location
Heat-sink side
–
+
Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Symbol Parameter
Supply voltage
Limits
Typ.
300
15.0
15.0
—
Condition
Unit
Min.
Max.
400
16.5
18.5
1
VCC
Applied between P-N
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
0
13.5
13.0
–1
V
V
VD
Control supply voltage
Control supply voltage
Control supply variation
VDB
V
∆VD, ∆VDB
tdead
V/µs
µs
2
Arm shoot-through blocking time For each input signal, Tf ≤ 100°C
—
—
—
fPWM
PWM input frequency
Tf ≤ 100°C, Tj ≤ 125°C
VCC = 300V, VD = 15V, fc = 5kHz
P.F = 0.8, sinusoidal
5
—
kHz
—
—
10
Arms
IO
Allowable r.m.s. current
Tj ≤ 125°C, Tf ≤ 100°C
ON
(Note 7)
(Note 8)
300
—
—
ns
V
—
PWIN
VNC
Minimum input pulse width
VNC variation
–5.0
between VNC-N (including surge)
5.0
Note 7: The allowable r.m.s. current value depends on the actual application conditions.
8: The input pulse width less than PWIN might make no response.
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
V
UFB
UFS
DIP-IPM
V
P
HVIC1
V
B
IGBT1
Di1
VP1
V
CC
UP
HO
IN
V
S
B
COM
U
VVFB
VVFS
HVIC2
V
V
CC
VP1
IGBT2
Di2
HO
IN
VP
V
S
B
COM
V
V
WFB
WFS
V
HVIC3
V
VP1
V
CC
IGBT3
IGBT4
Di3
Di4
W
P
HO
IN
V
S
VPC
COM
W
LVIC
UOUT
VN1
VCC
IGBT5
IGBT6
Di5
Di6
V
OUT
U
N
N
N
U
N
V
VN
W
OUT
W
W
N
VNO
Fo
Fo
CIN
N
VNC
GND
CFO
CFO
CIN
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-arms only)
(With the external shunt resistance and CR connection)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. Hard IGBT gate interrupt.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input “L” : IGBT OFF state.
a7. Input “H” : IGBT ON state, but during the FO active signal period the IGBT doesn’t turn ON.
a8. IGBT OFF state.
Lower-arms control
input
a6 a7
Protection circuit state
Internal IGBT gate
SET
a2
RESET
a3
SC
a4
a1
Output current Ic
a8
SC reference voltage
Sense voltage of the
shunt resistance
CR circuit time
constant DELAY
Error output Fo
a5
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
b1
SET
RESET
UVDr
Control supply voltage V
D
b6
UVDt
b2
b3
b4
b7
Output current Ic
Error output Fo
b5
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input condition, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
c1
SET
RESET
UVDBr
Control supply voltage VDB
c5
UVDBt
c2
c3
c4
c6
Output current Ic
Error output Fo
High-level (no fault output)
Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT
5V line
DIP-IPM
10kΩ
UP,VP,WP,UN,VN,WN
CPU
2.5kΩ (min)
Fo
NC(Logic)
V
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
Fig. 7 RECOMMENDED WIRING OF SHUNT RESISTANCE
Wiring inductance should be less than 10nH.
DIP-IPM
width=3mm, thickness=100µm, length=17mm
in copper pattern (rough standard)
Shunt resistor
VNC
N
Please make the connection point
as close as possible to the terminal
of shunt resistor.
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21864/-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1:Tight tolerance temp-compensated electrolytic type
~
C2,C3: 0.22 2µF R-category ceramic capacitor for noise filtering.
(Note: The capacitance value depends on the PWM control used in the applied system.)
V
UFB
C2
C1
DIP-IPM
V
UFS
P
HVIC1
V
P1
V
CC
VB
C3
UP
IN
HO
U
COM
V
S
C2
C1
V
V
VFB
VFS
HVIC2
V
P1
V
CC
V
B
C3
V
P
IN
HO
V
COM
V
S
M
C2
C1
V
V
WFB
WFS
HVIC3
V
P1
V
CC
V
B
C3
W
P
IN
HO
V
PC
W
COM
VS
LVIC
UOUT
V
N1
V
CC
C3
5V line
V
OUT
UN
UN
V
N
V
N
W
OUT
W
N
Too long wiring here might
cause short-circuit.
W
N
V
NO
Fo
F
o
CIN
N
V
NC
GND
CFO
C
CIN
CFO
C4(CFO
)
B
15V line
R1
Shunt
Resistance
C5
A
N1
Long GND wiring here might generate
noise to input and cause IGBT
malfunction.
If this wiring is too long, the SC level
fluctuation might be larger and cause
SC malfunction.
Note 1: To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm)
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3: FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
10kΩ resistor.
4: FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22 nF → tFO
= 1.8 ms (typ.))
5: The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when
using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
6: To prevent malfunction of protection, the wiring of A, B, C should be as short as possible.
7: Please set the R1C5 time constant in the range 1.5~2µs.
8: Each capacitor should be located as nearby the pins of the DIP-IPM as possible.
9: To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approxi-
mately a 0.1~0.22µF snubber capacitor between the P&N1 pins is recommended.
Jul. 2003
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