MH16S64PHB-6 [MITSUBISHI]
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM; 1,073,741,824位（ 16777216 - WORD 64位）同步动态RAM
| 型号： | MH16S64PHB-6 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM |
| 文件： | 总40页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH16S64PHB is 16777216 - word x 64-bit Synchronous
DRAM module. This consist of eight industry standard 16M
x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities
memory are required.
85pin
1pin
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Max.
Frequency
Access Time from CLK
[component level]
94pin
95pin
10pin
11pin
Type name
5.4ns
(CL = 3)
MH16S64PHB-6
133MHz
Utilizes industry standard 16M X 8 Synchronous DRAMs in TSOP
package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
124pin
125pin
40pin
41pin
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
APPLICATION
84pin
168pin
Main memory or graphic memory in computer systems
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NAME
VSS
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
NC
VSS
NC
85
86
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
NC
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
2
CKE0
NC
87
3
/S2
88
4
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
89
5
90
6
91
7
VDD
NC
VDD
NC
92
8
93
9
NC
NC
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
NC
95
NC
NC
96
VSS
VSS
97
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NC
NC
NC
NC
VSS
VSS
NC
NC
VSS
NC
DQ21
DQ22
DQ23
VSS
VSS
NC
DQ53
DQ54
DQ55
VSS
NC
NC
VDD
/WE
DQMB0
DQMB1
/S0
VDD
/CAS
DQMB4
DQMB5
NC
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
NC
/RAS
VSS
A1
VSS
A0
A2
A3
A4
A5
A6
A7
A8
A9
CK2
NC
CK3
NC
A10
BA1
VDD
VDD
CK0
BA0
SA0
SA1
SA2
VDD
WP
A11
SDA
SCL
VDD
VDD
CK1
NC
NC = No Connection
MIT-DS-0321-0.0
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MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
/S0
DQ0
DQ1
DQ32
DQ33
DQ2
DQ3
DQ4
DQ5
DQ34
DQ35
DQ36
DQ37
D0
D4
DQ6
DQ7
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D5
/S2
DQ16
DQ48
DQ17
DQ18
DQ19
DQ20
DQ21
DQ49
DQ50
DQ51
DQ52
DQ53
D6
D2
DQ54
DQ55
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D7
DQ28
DQ29
DQ30
DQ31
SERIAL PD
SDA
SCL
WP
A0 A1 A2
47K
SA0 SA1 SA2
D0-7
D0-7
VDD
VSS
DQM0
DQM 1
DQM 2
DQM 3
DQM 4
DQM 5
DQM 6
DQM 7
D0
D1
D2
D3
D4
D5
D6
D7
4DRAMs+3.3pF
TERMINATION
4DRAMs+3.3pF
CK0
CK1
CK2
CK3
CKE0
D0-7
A11-0,BA0-1
/RAS
D0-7
D0-7
TERMINATION
/CAS
/WE
D0-7
D0-7
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
Input
CK0,2
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Input
CKE0
Chip Select: When /S is high,any command means
No Operation.
/S0,2
Input
Input
Combination of /RAS,/CAS,/W defines basic
commands.
/RAS,/CAS,/W
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is specifies the four bank to which
a command is applied.BA must be set with ACT ,PRE
,READ ,WRITE commands
Input
A0-11
Input
BA0-1
Data In and Data out are referenced to the rising edge
of CK
DQ0-63
Input/Output
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted
Input
DQM0-7
Vdd,Vss
Power Supply
module.
12/May. /1999
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MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH16S64PHB provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
Chip Select : L=select, H=deselect
/S
Command
/RAS
Command
define basic commands
/CAS
/WE
CKE
A10
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
CKE CKE
COMMAND
MNEMONIC
/RAS /CAS /WE BA0,1 A11 A10 A0-9
/S
n-1
n
Deselect
No Operation
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
X
X
PREA
H
Column Address Entry
& Write
X
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with Auto-
Precharge
X
X
X
WRITEA
READ
H
H
H
X
X
X
L
L
L
H
H
H
L
L
L
L
V
V
V
H
L
V
V
V
Column Address Entry
& Read
H
H
Column Address Entry
& Read with Auto
Precharge
READA
H
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Entry
L
L
H
H
X
H
X
H
Self-Refresh Exit
REFSX
L
Burst Terminate
TBST
MRS
H
H
X
X
L
L
H
L
H
L
L
L
X
L
X
L
X
L
X
Mode Register Set
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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MITSUBISHI
ELECTRIC
6
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State
IDLE
/S
/RAS /CAS /WE
Address
Command
Action
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
DESEL
NOP
NOP
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA,CA,A10
READ/WRITE ILLEGAL*2
H
H
L
BA,RA
ACT
PRE/PREA
REFA
Bank Active,Latch RA
NOP*4
L
BA,A10
L
H
X
Auto-Refresh*5
Op-Code,
L
L
L
L
MRS
Mode Register Set*5
Mode-Add
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
Precharge/Precharge All
ILLEGAL
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
PRE/PREA
REFA
BA,A10
H
X
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
X
BA
TBST
Terminate Burst,Latch CA,
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
PRE/PREA
REFA
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
WRITE
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
X
H
H
X
H
H
X
H
L
X
X
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
L
BA
TBST
Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
L
H
L
H
BA,CA,A10 READ/READA
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
WRITE/
BA,CA,A10
L
H
L
L
WRITEA
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
PRE/PREA
REFA
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
BA,A10
H
X
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
READ with
AUTO
X
BA
TBST
PRECHARGE
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
Bank Active/ILLEGAL*2
ILLEGAL*2
PRE/PREA
REFA
H
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
WRITE with
AUTO
X
BA
TBST
PRECHARGE
L
H
L
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
H
H
H
L
BA,RA
Bank Active/ILLEGAL*2
ILLEGAL*2
BA,A10
PRE/PREA
L
L
L
H
X
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
PRE -
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
X
H
H
H
L
X
H
H
L
X
H
L
X
X
CHARGING
L
BA
TBST
L
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
L
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
L
L
NOP*4(Idle after tRP)
ILLEGAL
L
L
H
Op-Code,
Mode-Add
X
L
L
L
L
MRS
ILLEGAL
ROW
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ACTIVATING
X
BA
TBST
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
WRITE RE-
COVERING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA,CA,A10
BA,RA
BA,A10
READ/WRITE ILLEGAL*2
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
L
H
X
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRC)
NOP(Idle after tRC)
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING
L
BA
TBST
ILLEGAL
L
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL
L
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
H
Op-Code,
Mode-Add
X
L
L
L
L
MRS
ILLEGAL
MODE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
REGISTER
SETTING
X
BA
TBST
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL
ILLEGAL
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
12/May. /1999
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MITSUBISHI
10
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
CKE CKE
Current State
/RAS /CAS /WE Add
Action
/S
n-1
n
SELF -
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
REFRESH*1
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
L
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP(Maintain Self-Refresh)
INVALID
POWER
DOWN
H
L
X
H
L
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
ALL BANKS
IDLE*2
H
H
H
H
H
H
H
L
H
L
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
Enter Power Down
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ANY STATE
other than
H
H
L
listed above
H
L
L
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
12/May. /1999
MIT-DS-0321-0.0
11
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/CAS
0
0
0
0
WM
0
0
LTMODE
BT
BL
/WE
BA0,1 A11-0
V
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1
2
4
8
1
2
4
8
CL
/CAS LATENCY
BURST
R
R
0 0 0
0 0 1
LENGTH
1 0 0
1 0 1
R
R
R
R
2
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
3
1 1 0
1 1 1
R
R
R
MODE
FP
R
R
R
R
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
0
1
BURST
SINGLE BIT
WRITE
MODE
R:Reserved for Future Use
FP: Full Page
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
12
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
Y
Write
Y
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CL= 3
BL= 4
/CAS
Burst
Burst
Latency
Length
Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
13
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Condition
Ratings
Unit
V
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
VI
Input Voltage
with respect to Vss
with respect to Vss
-0.5 ~ 4.6
-0.5 ~ 4.6
V
VO
IO
Output Voltage
Output Current
V
mA
W
50
8
Pd
Power Dissipation
Ta=25C
Topr
Tstg
Operating Temperature
Storage Temperature
0 ~ 70
C
-45 ~ 100
C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted)
Limits
Typ.
Symbol
Vdd
Parameter
Unit
V
Min.
3.0
Max.
3.6
Supply Voltage
3.3
0
Vss
Supply Voltage
0
0
V
V
V
VIH*1
VIL*2
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
NOTES)
1. VIH(max)=5.5V for pulse width less than 10ns.
2. VIL(min)= -1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition
Limits(max.)
Unit
pF
CI(A) Input Capacitance, address pin
CI(C) Input Capacitance, control pin
45.5
45.5
32.3
16.5
1Mhz
pF
1.4V bias
200mV swing
Vcc=3.3V
pF
CI(K)
CI/O
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
pF
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
14
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
(max)
Parameter
operating current
Symbol
Test Condition
Unit Note
Icc1
1040 mA *1
200 mA *1
120 mA *1
16 mA *1
tRC=min.tCLK=min, BL=1, CL=3
single bank operation (discrete)
precharge stanby current in
CKE=H,tCLK=15ns,VIH> Vcc-0.2V, VIL<0.2V
Icc2N
Icc2NS
Icc2P
Non power-down mode
/CS> Vcc-0.2V
precharge stanby current
CLK=L & CKE=H, VIH> Vcc-0.2V, VIL<0.2V (fixed)
CKE=L,tCLK=15ns
in Power-down mode
/CS> Vcc-0.2V
Icc2PS CKE=CLK=L
mA *1
8
CKE=H,tCLK=15ns
Icc3N
320 mA *1
280 mA *1
active stanby current
burst current
CKE=H,CLK=L
Icc3NS
tCLK=min, BL=4, CL=3
all banks active(discerte)
Icc4
mA *1
1600
auto-refresh current
self-refresh current
Icc5
Icc6
tRC=min, tCLK=min
CKE <0.2V
1600 mA *1
16 mA *1
Note)
1.Icc(max) is specified at the output open condition.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
Unit
Min. Max.
2.4
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA
VOL(DC) Low-Level Output Voltage(DC) IOL=2mA
V
V
0.4
IOZ
Ii
Off-stare Output Current
Input Current
Q floating VO=0 ~ Vdd
VIH=0 ~ Vdd+0.3V
-10 10
uA
uA
80
-80
12/May. /1999
MIT-DS-0321-0.0
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
Min.
Unit
Symbol Parameter
tCLK CK cycle time
Max.
CL=3
CL=2
ns
ns
7.5
-
tCH
tCL
tT
tIS
tIH
CK High pulse width
CK Low pulse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row Cycle time
2.5
2.5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
1.5
0.8
tRC
67.5
80
22.5
45
tRFC Row Refresh Cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP
tWR
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
tSRX Self Refresh Exit time
tPDE Power Down Exit time
tREF Refresh Interval time
100K
22.5
15
Row Precharge time
Write Recovery time
15
ns
ns
ns
15
7.5
7.5
ms
64
1.4V
1.4V
Any AC timing is
CK
referenced to the input
signal crossing
through 1.4V.
Signal
12/May. /1999
MIT-DS-0321-0.0
16
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Limits
Note
*1
Symbol
Unit
Parameter
Min. Max.
5.4
CL=3
CL=2
tAC
tOH
Access time from CK
ns
ns
-
Output Hold time from CK
2.7
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
tOLZ
tOHZ
0
ns
ns
2.7
5.4
NOTE)
1.If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
Output Load Condition
CK
1.4V
1.4V
DQ
VOUT
Ext.CL=50pF
Output Timing
Measurement
Reference Point
CK
DQ
1.4V
1.4V
tOHZ
tAC
tOH
12/May. /1999
MIT-DS-0321-0.0
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MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-9
A10
X
X
X
0
Y
X
X
X
0
Y
A11
BA0,1
0
0
0
DQ
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
18
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-9
A10
A11
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
X
X
1
BA0,1
0
1
0
1
0
DQ
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
12/May. /1999
19
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
DQM read latency =2
X
X
X
0
Y
X
X
X
0
Y
A0-9
A10
A11
BA0,1
0
0
0
CL=3
DQ
Q0
Q0 Q0
Q0
Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
20
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-9
A10
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
0
X
X
X
2
Y
X
X
1
A11
BA0,1
0
1
0
1
0
CL=3
CL=3
DQ
Q0
Q0
Q0
Q0
Q1 Q1
Q1
Q1
Q0
ACT#0
READ#0
ACT#1
PRE#0
READ#1
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
12/May. /1999
21
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
CKE
DQM
A0-9
A10
A11
X
X
X
0
X
Y
Y
X
X
X
0
Y
X
X
X
1
Y
X
X
1
BA0,1
0
1
0
1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
D1
DQ
ACT#0
WRITE#0 with
ACT#0
WRITE#0
ACT#1 AutoPrecharge
WRITE#1 with
AutoPrecharge
ACT#1
WRITE#1
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
22
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL+tRP
BL+tRP
CKE
DQM
DQM read latency =2
Y
A0-9
A10
A11
X
X
X
0
X
Y
X
X
X
0
Y
X
X
X
1
Y
X
X
1
BA0,1
DQ
0
1
0
1
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0 Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
ACT#0
READ#0
READ#1 with
Auto-Precharge
ACT#1
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
23
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9
A10
X
X
X
0
X
Y
Y
Y
Y
X
X
1
A11
0
0
1
0
BA0,1
DQ
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
ACT#0
WRITE#0
ACT#1
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
24
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
DQM read latency=2
Y
A0-9
A10
A11
X
X
X
0
X
Y
Y
Y
X
X
1
BA0,1
0
0
1
0
CL=3
CL=3
CL=3
DQ
Q0
Q0 Q0
Q0
Q0 Q0
Q0
Q0 Q1
Q1
Q1 Q1
ACT#0
READ#0
ACT#1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
25
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tCCD
CKE
DQM
A0-9
A10
A11
X
X
X
0
X
Y
Y
Y
Y
Y
X
X
1
BA0,1
0
0
0
1
0
CL=3
DQ
D0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0 Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0
ACT#1
READ#0
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
26
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
DQM read latency=2
A0-9
A10
A11
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
BA0,1
0
0
0
1
0
0
Q0
Q0 Q0
Q0
Q0 Q0
Q1
Q1 Q0
D0
D0
DQ
ACT#0
READ#0 READ#0 READ#0
ACT#1
READ#0
WRITE#0
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
27
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9
A10
X
X
X
0
X
Y
Y
X
X
X
1
Y
X
X
1
A11
0
1
0
1
1
BA0,1
DQ
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted
by Precharge of the other bank.
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
12/May. /1999
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ELECTRIC
28
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
DQM read latency=2
Y
X
X
X
0
X
Y
X
X
X
1
Y
A0-9
A10
A11
X
X
1
0
1
0
1
1
BA0,1
Q0
Q0 Q0
Q0
Q1 Q1
DQ
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
29
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRSC
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9
A10
M
X
X
X
0
Y
A11
BA0,1
DQ
0
0
D0
D0
D0
D0
Auto-Ref (last of 8 cycles)
Mode
ACT#0
WRITE#0
Register
Setting
Italic parameter indicates minimum case
12/May. /1999
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ELECTRIC
30
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Auto-Refresh
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9
A10
A11
X
X
X
0
Y
0
BA0,1
D0
D0
D0
D0
DQ
Auto-Refresh
Before Auto-Refresh,
all banks must be idle state.
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
12/May. /1999
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ELECTRIC
31
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
CLK can be stopped
tRC+1
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-9
A10
X
X
X
0
A11
BA0,1
DQ
Self-Refresh Entry
Self-Refresh Exit
ACT#0
Before Self-Refresh Entry,
all banks must be idle state.
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
32
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask
BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9
A10
A11
X
X
X
0
Y
Y
Y
BA0,1
0
0
0
masked
masked
DQ
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
33
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4, CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM read latency=2
DQM
A0-9
A10
A11
X
X
X
0
Y
Y
Y
BA0,1
0
0
0
masked
masked
DQ
Q0
Q0 Q0
Q0
Q0
Q0
Q0
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
34
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-9
A10
A11
X
X
X
0
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
35
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
CLK Suspend
BL=4,CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
CKE latency=1
CKE latency=1
DQM
A0-9
A10
A11
X
X
X
0
Y
Y
BA0,1
0
0
DQ
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
READ#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
12/May. /1999
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MITSUBISHI
ELECTRIC
36
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
128
SPD DATA(hex)
80
0
1
2
3
4
5
6
7
8
9
# of Serial PD Bytes Written during Production
Total # of Bytes in SPD device
Fundamental memory type
256 Bytes
SDRAM
A0-A11
A0-A9
1BANK
x64
08
04
0C
0A
01
40
00
01
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
0
Voltage interface standard of this assembly
LVTTL
SDRAM Cycletime at Max. Supported CAS Latency (CL).
7.5ns
75
54
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
10
5.4ns
non-parity
00
80
08
00
11
12
13
14
15
16
17
18
19
20
21
22
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
self refresh(15.625uS)
SDRAM width,Primary DRAM
x8
n/a
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
1
01
8F
1/2/4/8/Full page
# Banks on Each SDRAM device
CAS# Latency
4bank
3
04
04
0
01
01
00
0E
CS# Latency
Write Latency
0
unbuffered
SDRAM Module Attributes
SDRAM Device Attributes:General
Precharge All,Auto precharge
Write1/Read Burst
23
24
25
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
00
N/A
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
00
00
N/A
N/A
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
26
27
N/A
23ns(22.5ns)
00
17
28
29
Row Active to Row Active Min.
RAS to CAS Delay Min
15ns
23ns(22.5ns)
45ns
0F
17
2D
30
Active to Precharge Min
12/May. /1999
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MITSUBISHI
ELECTRIC
37
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31
32
33
34
35
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
128MByte
1.5ns
20
15
08
15
08
0.8ns
1.5ns
Data signal input hold time
0.8ns
36-61
62
Superset Information (may be used in future)
SPD Revision
option
00
02
JEDEC2
63
64-71
72
Checksum for bytes 0-62
Manufactures Jedec ID code per JEP-108E
Manufacturing location
A3
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
1CFFFFFFFFFFFFFF
01
02
03
Germany
04
4D4831365336345048422D36202020202020
73-90
91-92
Manufactures Part Number
Revision Code
MH16S64PHB-6
PCB revision
rrrr
93-94
95-98
Manufacturing date
year/week code
serial number
option
yyww
Assembly Serial Number
ssssssss
99-125
126
Manufacture Specific Data
Intetl specification frequency
00
64
127
Intel specification CAS# Latency support
CL=3,AP,CK0,2
open
AD
00
128+
Unused storage locations
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
38
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
133.35
3
8.89
1.27
6.35
6.35
11.43
36.83
42.18
54.61
24.495
127.35
3
34.925
3.9Max
1.27
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
39
MITSUBISHI LSIs
MH16S64PHB-6
1,073,741,824-BIT ( 16,777,216-WORD BY 64-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable,but there is always the possibility that trouble may occur with them.
Trouble with semiconductors consideration to safety when making your circuit designs,with
appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-
party's rights,originating in the use of any product data,diagrams,charts or circuit application examples
contained in these materials.
3.All information contained in these materials,including product data, diagrams and charts,represent
information on products at the time of publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubish
Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering
the use of a product contained herein for special applications,such as apparatus or systems for
transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or
in part these materials.
6.If these products or technologies are subject the Japanese export control restrictions,they must be
exported under a license from the Japanese government and cannot be imported into a country other than
the approved destination. Any diversion or reexport contrary to the export control laws and regulations of
Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
for further details on these materials or the products contained therein.
12/May. /1999
MIT-DS-0321-0.0
MITSUBISHI
ELECTRIC
40
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