MH16S72ABGA-7 [MITSUBISHI]
Synchronous DRAM Module, 16MX72, 6ns, CMOS, PBGA124, BGA-124;
| 型号： | MH16S72ABGA-7 |
| 厂家： | 
Mitsubishi Group |
| 描述： | Synchronous DRAM Module, 16MX72, 6ns, CMOS, PBGA124, BGA-124 时钟 动态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
PIN CONFIGURATION ( TOP VIEW )
A
M
DESCRIPTION
1
The MH16S72ABGA is an 16M word by 72-bit
Sy nchronous DRAM module.This consists of f iv e
industry standard 16M X 16 Sy nchronous DRAMs
in STSOP.
The ICs are mounted on both sides of Similar
FR-5 with BGA package.
FEATURES
CLK Access Time
Frequency
Type name
12
(Component SDRAM)
MH16S72ABGA-5
MH16S72ABGA-6
MH16S72ABGA-7
133MHz
133MHz
100MHz
5.4ns(CL=2)
5.4ns(CL=3)
6ns(CL=2)
L M
G H J K
C D E F
A B
1
2
Utilizes industry standard 16M X 16 Synchronous DRAMs in
STSOP package.
124 pin BGA (including 4 Dummy pins)
Single 3.3V +/- 0.3V supply
3
4
5
6
Clock frequency 100MHz, 133MHz
7
Fully synchronous operation reference to clock rising edge
Dual bank operation controlled by BA0,1(Bank Address)
/CAS latency - 2/3 (programmable)
Burst length - 1/2/4/8/Full Page (programmable)
Burst type - sequential / interleave (programmable)
Column access - random
8
9
10
11
12
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
8192 refresh cycle / 64ms
LVTTL Interface
APPLICATION
Main memory unit for computers, Microcomputer memory,
PDA, Refresh memory for CRT
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
Pin Configuration
A
B
C
D
E
F
G
H
J
K
L
M
1
2
NC
Vdd NC
NC
Vdd
A6
A5
A8
A4
Vss Vss
A3
A2
A1
NC
3 DQ24 DQ8 A9
A7 DQ67 DQ68 A0
A10 BA1 DQ39 DQ55
4 DQ25 DQ9 CKE A12 A11 DQ66 DQ69 BA0 /CS /RAS DQ38 DQ54
5 DQ26 DQ10 CLK DQM DQ23 DQ65 DQ70 DQ56 /CAS /WE DQ37 DQ53
6
Vdd DQ11 DQ6 DQ7 DQ22 Vss Vss DQ57 DQ40 DQ41 DQ36 Vdd
7 DQ27 DQ12 DQ4 DQ5 DQ21 DQ64 DQ71 DQ58 DQ42 DQ43 DQ35 DQ52
8 DQ28 DQ13 DQ2 DQ3 DQ19 DQ20 DQ59 DQ60 DQ44 DQ45 DQ34 DQ51
9 DQ29 DQ30 DQ14 DQ1 DQ17 DQ18 DQ61 DQ62 DQ46 DQ33 DQ49 DQ50
10 Vss DQ31 DQ15 DQ0 DQ16 Vdd Vdd DQ63 DQ47 DQ32 DQ48 Vss
11 NC
12 NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
Block Diagram
A<12..0>,BA<1..0>
/RAS
/CAS
/CS
/WE
CKE
CLK
DQM
UDQM
UDQM
UDQM
DQ0
DQ1
DQ2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ64
DQ65
DQ66
DQ67
DQ3
UDQ
DQ4
UDQ
UDQ
DQ5
DQ6
DQ7
LDQM
LDQM
LDQM
DQ8
DQ9
DQ10
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ68
DQ69
DQ70
DQ71
DQ11
LDQ
LDQ
LDQ
DQ12
DQ13
DQ14
DQ15
UDQM
DQ32
UDQM
DQ48
DQ33
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ34
DQ35
UDQ
DQ36
UDQ
DQ37
DQ38
DQ39
LDQM
LDQM
DQ40
DQ41
DQ42
DQ56
DQ57
DQ58
DQ43
LDQ
DQ59
DQ60
DQ61
DQ62
DQ63
LDQ
DQ44
DQ45
DQ46
DQ47
Vdd
0.1uF
C1 to C4
Gnd
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
CLK
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
CKE
Input
Chip Select: When /S is high,any command means
No Operation.
/CS
Input
Input
/RAS,/CAS,/WE
Combination of /RAS,/CAS,/WE defines basic commands.
A0-12 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-12.The Column
Address is specified by A0-8. A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
A0-12
BA0,1
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input
Input/Output
Input
Data In and Data out are referenced to the rising edge
of CK
DQ0-71
DQM
Din Mask/Output Disable: When DQM is high in burst
write. Din for the current cycle is masked. When DQM is high
in burst read , Dout is disabled at the next but one cycles.
Power Supply Power Supply for the memory mounted module.
Vdd,Vss
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S72ABGA provides basic functions,bank(row)activate,burst read / write8
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
Command
/RAS
/CAS
Command
Command
define basic commands
/WE
CKE
A10
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
BA0
0
BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
SW
0
0
LTMODE
BT
BL
/WE
BA0,1 A12-0
V
0
1
Burst Write
SW
BL
BT= 0
BT= 1
Single Write
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
2
CL
/CAS LATENCY
4
4
BURST
LENGTH
8
8
0 0 0
0 0 1
0 1 0
R
R
2
R
R
R
FP
R
R
R
R
LATENCY
MODE
3
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
R
R
0
1
SEQUENTIAL
BURST
TYPE
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
CK
Read
Y
Write
Y
Command
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D3
D2
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Supply Voltage
Input Voltage
Condition
Ratings
Unit
V
with respect to Vss
-0.5 ~ 4.6
VI
with respect to Vss -0.5 ~ Vdd+0.5
with respect to Vss -0.5 ~ Vdd+0.5
50
V
VO
IO
Output Voltage
Output Current
V
mA
W
Ta=25°C
Pd
Power Dissipation
Operating Temperature
5
Topr
0 ~ 70
°C
°C
Tstg
Storage Temperature
-40 ~ 100
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Vdd
Vss
VIH
VIL
Supply Voltage
Supply Voltage
V
V
V
V
0
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits(max.) Unit
Symbol
CI(A)
Parameter
Test Condition
pF
pF
28
Input Capacitance, address pin
/RAS,/CAS,/WE
VI = Vss
28
45
Input Capacitance
control pin
/CS,CKE
CI(C)
DQM
f=1MHz
CI(K) Input Capacitance, CK pin
pF
pF
24
12
Vi=25mVrms
CI/O
Input Capacitance, I/O pin
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
(max)
Parameter
Symbol
Test Condition
Unit Note
-5
-6
-7
operating current
one bank activ e (discrete)
mA
mA
1
2
tRC=min.tCLK=min, BL=1
600
500
450
Icc1
Icc2P
Idle stanby current
in power-down mode
CKE<VILmax,tCLK=min
CKE<VILmax,CLK=L,
10
5
150
30
7.5
5
125
30
5
5
100
30
mA
mA
mA
Icc2PS
2,3
2,4
Icc2N CKE>VIHmin,tCLK=min,/CS>VIH
Idle stanby current
in normal mode
Icc2NS
CKE>VIHmin,CLK=L
mA
mA
mA
3,5
4,5
5
175
75
150
75
125
75
active stanby current
in normal mode
CKE>VIHmin,/CS>VIHn
Icc3N
Icc3NS
Icc4
CKE>VIHmin,CLK=L
tCLK=min, BL=4, gapless data
750
600
500
850
15
burst current
auto-refresh current
tRFC=min, tCLK=min
CKE <0.2V
Icc5
1100 900
mA
mA
Icc6
15
15
self-refresh current
Note)
1:address are changed 3 times during tRC, only 1 bank is activ e & all other banks are idle
2.all banks are idle
3.input signals are changed one time during 3xtCLK
4.input signals are stable
5.all banks are activ e
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
IOH=-2mA
IOL=2mA
Unit
Min. Max.
2.4
VOH(DC)
VOL(DC)
IOZ
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
V
V
0.4
Q floating VO=0 ~ Vdd -10
uA
Off-stare Output Current
10
-50
Input Current
uA
VIH=0 ~ Vdd+0.3V
50
Ii
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Symbol Parameter
Limits
-6
Unit
-5
-7
Min. Max. Min. Max. Min. Max.
CL=2
7.5
10
10
ns
tCLK
CK cycle time
CL=3
7.5
2.5
7.5
2.5
10
3
ns
ns
tCH
CK High pulse width
tCL
tT
tIS
CK Low pilse width
Transition time of CK
Input Setup time(all inputs
2.5
1
1.5
2.5
1
1.5
3
1
2
ns
10 ns
ns
10
10
tIH
tRC
Input Hold time(all inp
Row cycle time
0.8
60
67.5
15
0.8
67.5
75
1
70
80
20
ns
ns
ns
ns
tRFC Refresh cycle time
tRCD Row to Column
tRAS Row Active tim
20
45 120K 45 120K 50 120K ns
tRP
tWR
tRRD
Row Precharge time
Write Recovery time
Act to Act Deley time
15
12
15
10
20
15
15
10
20
20
20
10
ns
ns
ns
tRSC Mode Register Set Cycle time
ns
tREF Average Refresh Interval time
7.8
7.8
7.8 us
Any AC timing is
1.4V
CK
referenced to the input
signal crossing
through 1.4V.
1.4V
Signal
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
-5
-6
-7
Symbol Parameter
Unit
ns
Min. Max. Min. Max. Min. Max.
tAC
Access time fr
CL=2
5.4
5.4
6
6
6
5.4
ns
ns
CL=3
CL=2
Outp
fr
tOH
3
3
3
3
3
3
CL=3
ns
time, output low
impedance from CK
Delay time, output high
impedance from CK
tOLZ
tOHZ
0
0
0
3
3
ns
ns
ns
CL=2
CL=3
3
3
5.4
5.4
3
3
6
6
6
5.4
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
2 In SSBGA lev el, the delay of trace (0.6ns) should be added to tAC.
Output Load Condition
CK
1.4V
VOUT
DQ
1.4V
50pF
Output Timing
Measurement
Reference Point
1.4V
1.4V
CK
tOLZ
tAC
DQ
tOHZ
tOH
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
OUTLINE
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Preliminary Spec.
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MH16S72ABGA-5,-6,-7
1207959552-BIT (166777216 - WORD BY 72-BIT)SynchronousDRAM
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MITSUBISHI
ELECTRIC
MIT-DS-0408-1.1
11.Jan.2002
( 13/ 13 )
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