MH16S64PHC-7 [MITSUBISHI]
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM; 1073741824位（ 16777216 - WORD 64位） SynchronousDRAM
| 型号： | MH16S64PHC-7 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM |
| 文件： | 总55页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64PHC is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
85pin
1pin
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
94pin
95pin
10pin
11pin
FEATURES
CLK Access Time
Frequency
(Component SDRAM)
-7
6.0ns(CL=3)
6.0ns(CL=3)
100MHz
100MHz
-8
100MHz
8.0ns(CL=3)
-10
124pin
125pin
40pin
41pin
Utilizes industry standard 8M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
168pin
84pin
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
APPLICATION
PC main memory
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
PIN NO.
PIN NAME
VSS
PIN NO.
PIN NAME
VSS
PIN NO.
PIN NAME
PIN NO.
PIN NAME
VSS
85
86
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
NC
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
2
DQ0
NC
CKE0
/S3
87
3
DQ1
/S2
88
4
DQ2
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
89
5
DQ3
90
6
VDD
91
7
DQ4
VDD
NC
VDD
NC
92
8
DQ5
93
9
DQ6
NC
NC
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ7
NC
NC
95
DQ8
NC
NC
VSS
96
VSS
VSS
97
DQ9
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
98
DQ10
DQ11
DQ12
DQ13
VDD
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ14
DQ15
NC
NC
NC
NC
NC
CKE1
VSS
VSS
NC
VSS
NC
DQ21
DQ22
DQ23
VSS
VSS
NC
DQ53
DQ54
DQ55
VSS
NC
NC
VDD
/WE0
VDD
/CAS
DQMB4
DQMB5
/S1
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
DQMB0
DQMB1
/S0
NC
/RAS
VSS
A1
VSS
A0
A2
A3
A4
A5
A6
A7
A8
A9
CK2
CK3
NC
NC
A10
BA1
VDD
VDD
CK0
BA0
SA0
SA1
SA2
VDD
WP
SDA
SCL
VDD
A11
VDD
CK1
NC
NC = No Connection
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S3
/S2
/S1
/S0
DQMB2
DQMB0
10W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D4
D6
D2
D0
DQMB6
DQMB4
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB3
DQMB1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
D3
D7
D1
D5
DQ15
DQMB7
DQMB5
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ63
10W
CK0
CK1
3SDRAMs+10pF
3SDRAMs+10pF
CK2
CK3
2SDRAMs+15pF
3.3V
2SDRAMs+15pF
D0 - D9
/RAS
10K
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
D0 - D9
D0 - D9
D0 - D9
D0 - D9
CKE1
CKE0
D5-D9
D0-D4
SERIAL PD
A0 A1 A2
SDA
SCL
WP
47K
Vss
D0 - D9
SA0 SA1 SA2
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
0
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
SPD enrty data
128
SPD DATA(hex)
80
08
04
0C
09
02
40
00
01
1
256 Bytes
SDRAM
A0-A11
A0-A8
2
3
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
4
5
2BANK
x64
6
Data Width of this assembly...
7
... Data Width continuation
0
8
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
LVTTL
9
-7,-8,-10
10ns
A0
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
-7,-8
-10
10
6ns
60
80
00
80
10
00
01
8F
04
06
8ns
11
12
13
14
15
16
17
18
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
non-parity
self refresh(15.625uS)
SDRAM width,Primary DRAM
Error Checking SDRAM data width
x16
N/A
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
1
1/2/4/8/Full page
4bank
# Banks on Each SDRAM device
CAS# Latency
2/3
19
20
21
22
23
CS# Latency
Write Latency
0
01
01
00
0E
0
SDRAM Module Attributes
SDRAM Device Attributes:General
non-buffered,non-registered
Precharge All,Auto precharge
10ns
-7
SDRAM Cycle time(2nd highest CAS latency)
A0
D0
F0
60
-8
-10
-7
Cycle time for CL=2
13ns
15ns
6ns
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
24
-8
7ns
8ns
70
80
00
00
14
1E
-10
25
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
N/A
N/A
26
27
-7,-8
-10
20ns
30ns
28
Row Active to Row Active Min.
-7,-8,-10
20ns
14
-7,-8
29
30
RAS to CAS Delay Min
Active to Precharge Min
20ns
14
-10
30ns
50ns
1E
32
-7,-8
-10
60ns
3C
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/ 55 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
Density of each bank on module
64MByte
2ns
10
20
00
Command and Address signal input setup time
-7,-8
-10
N/A
33
Command and Address signal input hold time
-7,-8
-10
1ns
N/A
10
00
20
00
34
35
Data signal input setup time
Data signal input hold time
-7,-8
-10
2ns
N/A
-7,-8
-10
1ns
10
00
00
12
01
N/A
36-61
62
Superset Information (may be used in future)
SPD Revision
option
rev 1.2A
rev 1
-7,-8
-10
63
Checksum for bytes 0-62
Check sum for -7
0E
4E
4B
Check sum for -8
Check sum for -10
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
Germany
73-90
Manufactures Part Number
4D4831365336345048432D37202020202020
4D4831365336345048432D38202020202020
MH16S64PHC-7
MH16S64PHC-8
4D4831365336345048432D31302020202020
MH16S64PHC-10
PCB revision
year/week code
serial number
option
91-92
93-94
95-98
99-125
126
Revision Code
rrrr
yyww
ssssssss
00
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
-7,-8
-10
100MHz
66MHz
64
66
FF
FD
06
-7
127
Intel specification CAS# Latency support
Unused storage locations
CL=2/3,AP,CK0-3
CL=3,AP,CK0-3
CL=2/3
-8
-10
128+
open
00
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
CK
Input
(CK0 ~ CK3)
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
CKE0
Input
Chip Select: When /S is high,any command means
No Operation.
/S
(/S0-3)
Input
Input
/RAS,/CAS,/WE
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
A0-11
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
BA0,1
Input
Data In and Data out are referenced to the rising edge of
CK
DQ0-63
Input/Output
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Vdd,Vss
Input
Power Supply Power Supply for the memory mounted module.
Input
Serial clock for serial PD
SCL
SDA
Output
Input
Serial data for serial PD
SA0-3
Address input for serial PD
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S64PHC provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
Command
/RAS
/CAS
Command
Command
define basic commands
/WE
CKE
A10
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
CKE CKE
/CAS
A11
A0-9
COMMAND
MNEMONIC
/RAS
/WE BA0,1
A10
/S
n-1
n
Deselect
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
No Operation
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
WRITEA
READ
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
L
V
V
V
V
X
X
X
X
L
V
V
V
V
Column Address Entry
& Write with Auto-
Precharge
L
H
L
Column Address Entry
& Read
H
H
Column Address Entry
& Read with Auto
Precharge
READA
H
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
L
L
REFSX
H
H
X
X
X
H
H
L
X
H
H
L
X
L
X
Burst Terminate
TERM
MRS
H
H
X
V*1
Mode Register Set
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Command
DESEL
NOP
Current State
IDLE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
NOP
L
BA
TBST
ILLEGAL*2
L
X
H
L
BA,CA,A10
BA,RA
READ/WRITE ILLEGAL*2
L
H
H
L
ACT
Bank Active,Latch RA
NOP*4
L
L
BA,A10
X
PRE/PREA
REFA
L
L
H
Auto-Refresh*5
Op-Code,
L
L
L
L
MRS
Mode Register Set*5
Mode-Add
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
NOP
TBST
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
Precharge/Precharge All
ILLEGAL
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
PRE/PREA
REFA
BA,A10
H
X
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
X
TBST
BA
Terminate Burst,Latch CA,
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
PRE/PREA
REFA
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
WRITE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
X
H
H
X
H
L
X
X
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
L
BA
TBST
Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
READ/READA
L
L
H
H
L
L
H
L
BA,CA,A10
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
PRE/PREA
REFA
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
H
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
BA
TBST
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
L
L
H
H
L
H
L
BA,RA
Bank Active/ILLEGAL*2
ILLEGAL*2
BA,A10
PRE/PREA
REFA
H
X
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
WRITE with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
TBST
BA
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
BA,RA
BA,A10
X
L
L
L
L
L
L
H
H
L
H
L
Bank Active/ILLEGAL*2
ILLEGAL*2
PRE/PREA
REFA
H
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
PRE -
/S
H
L
/RAS /CAS /WE
Address
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
X
H
H
H
L
X
H
H
L
X
H
L
X
X
CHARGING
L
BA
TBST
L
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
L
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
L
L
NOP*4(Idle after tRP)
ILLEGAL
L
L
H
Op-Code,
Mode-Add
X
L
L
L
L
MRS
ILLEGAL
ROW
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ACTIVATING
X
BA
TBST
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
WRITE RE-
COVERING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRC)
NOP(Idle after tRC)
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING
L
BA
TBST
ILLEGAL
L
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL
L
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
H
Op-Code,
Mode-Add
X
L
L
L
L
MRS
ILLEGAL
MODE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
REGISTER
SETTING
X
BA
TBST
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL
ILLEGAL
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CKE CKE
Action
Current State
/RAS /CAS /WE Add
/S
n-1
n
INVALID
SELF -
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
REFRESH*1
L
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
NOP(Maintain Self-Refresh)
INVALID
L
X
X
X
X
X
L
X
X
X
X
X
L
POWER
DOWN
H
L
X
H
L
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
ALL BANKS
IDLE*2
H
H
H
H
H
H
H
L
H
L
Enter Power Down
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
ILLEGAL
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
X
H
L
X
X
X
X
X
X
X
X
X
X
ANY STATE
other than
H
H
L
listed above
H
L
L
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
ACT
CKEL
CKEH
CLK
SUSPEND
POWER
DOWN
CKEL
CKEH
TBST(for Full Page)
WRITE
TBST(for Full Page)
READ
ROW
ACTIVE
READA
READ
WRITEA
CKEL
CKEH
CKEL
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
WRITE
CKEH
WRITEA
READA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
WRITEA
SUSPEND
READA
SUSPEND
PRE
WRITEA
READA
PRE
POWER
APPLIED
POWER
ON
PRE
CHARGE
PRE
Automatic Sequence
Command Sequence
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
CK
/S
/RAS
/CAS
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
WM
0
0
0
0
0
0
LTMODE
BT
BL
/WE
V
BA0,1 A11-0
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
2
CL
/CAS LATENCY
4
4
BURST
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
8
8
LENGTH
R
R
R
FP
R
R
R
R
LATENCY
MODE
3
R
R
R
R
0
1
SEQUENTIAL
BURST
TYPE
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
BURST
SINGLE BIT
0
1
WRITE
MODE
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
ACT
X
READ
Y
Command
Address
tRCD
CL=2
Q0
Q1
Q0
Q2
Q1
Q3
Q2
DQ
DQ
CL=2
CL=3
CL=3
Q3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
READ
ACT
X
Command
Y
Address
Q0
DQ
DQ
BL=1
BL=2
BL=4
BL=8
BL=FP
Q0 Q1
DQ
DQ
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
m=511
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CK
Read
Y
Write
Y
Command
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D3
D2
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2ACT command/tRCmin
tRCmin
Command
ACT
ACT READ
PRE
ACT
Xb
tRRD
tRP
tRAS
Xb
Y
0
Xa
A0-9
A10
tRCD
Xa
Xa
1
Xb
Xb
Xb
Xb
A11
BA0,1
DQ
00
01
00
01
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A8-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start at
BL after READA. The next ACT command can be issued after (BL + tRP) from the previous
READA.
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=3)
CK
Command
ACT
READ ACT
READ PRE
Y
tRCD
Y
0
Xa
Xa
Xa
Xb
Xb
Xb
A0-9
0
0
A10
A11
BA0,1
00
10
00
00
10
DQ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
/CAS latency
READ with Auto-Precharge (BL=4, CL=3)
CK
BL + tRP
Command
ACT
Xa
READ
ACT
Xa
tRCD
tRP
BL
Y
1
A0-9
A10
A11
Xa
Xa
Xa
Xa
00
BA0,1
DQ
00
00
Qa0 Qa1 Qa2 Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CK
Command
ACT
READ
BL
CL=3 DQ
CL=2 DQ
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data by interleaving the
multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be WRITE command is issued and the remaining burst length is
ignored.The read data burst length os unaffected while in this mode.
Multi Bank Interleaving WRITE (BL=4)
CK
Command
ACT
Write ACT
Write PRE
Y
PRE
tRCD
tRCD
Y
0
Xa
Xa
Xa
00
Xb
Xb
Xb
10
A0-9
A10
0
0
0
0
0
A11
BA0,1
10
00
00
10
DQ
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Write
ACT
tRCD
tRP
tWR
Xa
Xa
Xa
00
Xa
Xa
Xa
00
Y
1
A0-9
A10
A11
BA0,1
00
DQ
Da0 Da1 Da2 Da3
Internal precharge begins
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in
the same cycle as a write command set.(The latency of data input is 0.) The
burst length can be set to 1,2,4,8,and full-page,like burst read operations.
tRCD
CK
READ
ACT
X
Command
Y
Address
Q0
DQ
DQ
BL=1
BL=2
BL=4
BL=8
BL=FP
Q0 Q1
DQ
DQ
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
m=511
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1 at MRS.In a single write
operation,data is written only to the column address specified by the write
command set cycle without regard to the burst length setting.(The latency of data
input is 0.)
CK
READ
ACT
Command
tRCD
Y
X
Address
DQ
Q0
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of any bank. Random column access is
allowed. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
READ READ
READ
Yk
READ
Yi
0
Yj
0
Yl
0
A0-9
A10
0
A11
BA0,1
00
00
10
01
DQ
Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
A0-9
READ
Write
Yj
Yi
0
A10
A11
0
0
0
BA0,1
DQMB0-7
Q
Qai0
Daj0 Daj1 Daj2 Daj3
DQM control Write control
D
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Preliminary Spec.
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to
the /CAS Latency.As a result, READ to PRE interval determines valid data length to be
output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
READ
PRE
Q0
DQ
Q1
Q1
Q2
CL=3
Command
PRE
DQ
Q0
Q0
Command
READ PRE
DQ
Command
DQ
PRE
Q1
READ
Q0
Q2
CL=2
Command
READ
PRE
Q0
DQ
Q1
Command
READ PRE
DQ
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST is
mainly used to interrupt FP bursts.The figure below show examples, of how the output data
is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
Command
DQ
READ
TBST
Command
DQ
CL=3
Command
DQ
Command
DQ
Q0
Command
DQ
Q1
CL=2
Q2
Command
DQ
TBST
READ
Q0
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11/ Jan. /1999
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9
Write Write
Write
Yk
Write
Yl
Yi
0
Yj
0
0
0
A10
A11
BA0,1
00
00
10
00
DQ
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
Write READ
Write
READ
A0-9,11
A10
Yi
0
Yj
0
Yk
0
Yl
0
A11
BA0,1
00
00
10
00
DQMB0-7
DQ
Dai0
Qaj0 Qaj1
Qbl0
Dbk0 Dbk1
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from the
last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
Command
Write
PRE
ACT
tWR
tRP
Yi
0
Xb
Xb
Xb
00
A0-9,11
A10
0
A11
00
00
BA0,1
DQMB0-7
DQ
Dai0 Dai1
Dai2
[ Write Interrupt
A burst terminatn this case,
the write recoverase see the
waveforms below
CK
Command
A0-9
A10
BA0,1
DQMB0-7
DQ
Dai0 Dai1 Dai2
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11/ Jan. /1999
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycles within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on
4bank concurrentry. Before performing an auto-refresh, all banks must be in the idle
state. Auto-refresh to Auto-refresh interval is minimum tRC.Any command must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
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11/ Jan. /1999
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle
state and a new command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
tSRX
A0-11
BA0,1
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRC
+1 CLOCK
for recovery
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, A command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP NOP NOP NOP NOP
Active Power Down
CKE
Command
NOP NOP NOP NOP NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
Write
D0
READ
DQ
D1
D2
D3
Q0
Q1
Q2
Q3
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the output
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7
to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQMB0-7
READ
Write
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Supply Voltage
Input Voltage
Condition
Ratings
Unit
V
with respect to Vss
-0.5 ~ 4.6
VI
with respect to Vss
with respect to Vss
V
-0.5 ~ 4.6
-0.5 ~ 4.6
50
VO
IO
Output Voltage
Output Current
V
mA
W
8
Pd
Power Dissipation
Operating Temperature
Ta=25°C
Topr
0 ~ 70
°C
Tstg
Storage Temperature
-40 ~ 100
°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Vdd
Vss
VIH
VIL
Supply Voltage
Supply Voltage
V
V
V
V
0
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
Note:* VIH (max) = 5.5V for pulse width less than 10ns.
VIL (min) = -1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Parameter
CI(A) Input Capacitance, address pin
CI(C)
Test Condition Limits(max.)
Unit
Symbol
pF
pF
55
Input Capacitance, /RAS,/CAS,/WE
55
VI = Vss
25
CI(K) Input Capacitance, CK pin
CI(S) Input Capacitance, /CS pin
CI(E) Input Capacitance, CKE pin
pF
pF
pF
f=1MHz
25
35
22
22
Vi=25mVrms
CI(M) Input Capacitance, DQM pin
CI/O Input Capacitance, I/O pin
pF
pF
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
(max)
Parameter
Symbol
Test Condition
Unit Note
-10
-7, -8
operating current
one bank active (discrete)
mA
*1
Icc1
tRC=min.tCLK=min, BL=1, CL=3
700
580
*1
tCLK=15ns, CKE = H, VIH > Vcc - 0.2V, VIL < 0.2V
precharge stanby current
in non power-down
mode /CS>Vcc-0.2V
200
120
200
120
Icc2N
mA
*1
CLK=L & CKE=H, VIH > Vcc - 0.2V, VIL < 0.2V
all input signals are fixed.
mA
Icc2NS
tCLK = 15ns, CKE = L
mA
*1
16
8
16
8
Icc2P
precharge stanby current
in power-down mode
/CS>Vcc-0.2V
mA
CLK = L, CKE = L
Icc2PS
*1
mA
mA
*1
*1
*1
CKE=H, tCLK=15ns
320
280
320
280
Icc3N
active stanby current
CKE=H, CLK=L
tCLK=min, BL=4, CL=3 Aall banks active
Icc3NS
Icc4
Icc5
burst current
mA
mA
mA
mA
800
800
auto-refresh current
tRC=min, tCLK=min
*1
1600
1280
16
6.4
16
6.4
self-refresh current
Icc6
CKE <0.2V
*1,2
Note1:Icc(max) is specified at the output open condition.
Note2:Low Power version
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA
Low-Level Output Voltage(DC)
Parameter
Test Condition
Unit
Min. Max.
2.4
V
V
VOL(DC)
IOZOff-stareOutputCurrentQfloatingVO=0 ~ Vdd -10
IOL=2mA
0.4
10 uA
uA
Input Current
IiVIH=0~Vdd+0.3V
-80
80
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-8
Unit
Symbol Parameter
-7
-10
Min. Max. Min. Max. Min.
Max.
ns
ns
10
10
13
10
15
10
CL=2
CL=3
tCLK
CK cycle time
ns
ns
ns
ns
ns
tCH CK High pulse width
tCL CK Low pilse width
3
3
1
2
1
3
3
1
2
1
4
4
1
3
1
10
10
10
tT
tIS
tIH
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
20
50
20
20
20
20
10
10
70
20
90
30
tRC Row cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
100K
50 100K
60 100K
20
20
20
20
10
30
15
20
20
10
Self Refresh Exit time
Power Down Exit time
tSRX
tPDE
10
64
10
64
ms
64
tREF Refresh Interval time
1.4V
1.4V
Any AC timing is
CK
referenced to the input
signal crossing through
1.4V.
Signal
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
-8
Symbol Parameter
-7
-10
Unit
ns
Min. Max. Min. Max. Min. Max.
tAC
Access time from CK
CL=2
CL=3
6
6
7
6
8
8
ns
ns
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
3
0
3
3
0
3
3
0
3
tOH
tOLZ
tOHZ
ns
ns
6
6
8
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load
Condition
VTT=1.4V
CK
1.4V
50W
VREF=1.4V
DQ
1.4V
VOUT
50pF
Output Timing
Measurement
Reference Point
1.4V
1.4V
CK
DQ
tOHZ
tAC
tOH
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-8
A10
X
X
X
0
Y
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
0
D0
D0 D0
D0
D0 D0
WRITE#0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
X
X
1
A10
A9,11
0
1
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0
D0
D0 D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-8
DQM read latency =2
X
X
X
0
Y
X
X
X
0
Y
A10
A9,11
0
0
0
BA0,1
DQ
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE ³ BL allows full data out
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-8
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
Y
X
X
1
X
A10
A9,11
BA0,1
DQ
X
0
X
0
1
0
1
2
0
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0
ACT#0
READ#0
ACT#1
PRE#0
READ#1
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
X
X
X
0
Y
X
X
X
1
Y
X
X
1
A10
A9,11
0
1
0
1
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0 D0
D0
D0 D1
ACT#0
ACT#1
WRITE#0 with
AutoPrecharge
ACT#0
WRITE#0
ACT#1
WRITE#1 with
AutoPrecharge
WRITE#1
Italic parameter indicates minimum case
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39
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL+tRP
BL+tRP
CKE
DQM
A0-8
A10
DQM read latency =2
Y
X
X
X
0
X
Y
X
Y
X
X
X
Y
X
X
1
X
X
A9,11
BA0,1
DQ
0
1
0
0
1
1
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0 Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
ACT#0
READ#0
READ#1 with
Auto-Precharge
ACT#1
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
Y
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
0
1
0
D0
D0 D0
D0
D0 D0
D0
D0 D1
D1
D1 D1
D0
D0 D0
ACT#0
WRITE#0
ACT#1
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI
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41
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
Y
X
X
X
0
X
Y
Y
Y
X
X
1
A9,11
BA0,1
DQ
0
0
1
0
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
Q0
Q0 Q1
Q1
Q1 Q1
ACT#0
READ#0
ACT#1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tCCD
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
Y
Y
Y
X
X
1
A10
A9,11
BA0,1
0
0
0
1
0
CL=3
D0
D0 D0
D0
D0 D0
D1
D1
Q0
Q0
Q0 Q0
DQ
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
A9,11
BA0,1
DQ
0
0
0
1
0
0
Q0
Q0 Q0
Q0
Q0 Q0
Q1
Q1 Q0
D0 D0
WRITE#0
ACT#0
READ#0 READ#0 READ#0
ACT#1
READ#0
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
X
X
X
0
X
Y
Y
X
X
X
1
Y
X
X
1
A9,11
BA0,1
DQ
0
1
0
1
1
D0
D0 D0
D0
D1 D1
D1
D1 D1
ACT#0
WRITE#0
PRE#0
ACT#1
WRITE#1
PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by
Precharge of the other bank.
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
Y
X
X
X
0
X
Y
X
X
X
1
Y
X
X
1
A9,11
BA0,1
DQ
0
1
0
1
1
Q0
Q0 Q0
Q0
Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRSC
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
M
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
D0
D0
D0 D0
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
X
X
X
0
Y
A10
A9,11
BA0,1
DQ
0
D0
D0 D0
D0
Auto-Refresh
Before Auto-Refresh,
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
all banks must be idle state.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
CLK can be stopped
tRC
/RAS
/CAS
/WE
tSRX
CKE
DQM
A0-8
A10
CKE must be low to maintain Self-Refresh
X
X
X
0
A9,11
BA0,1
DQ
Self-Refresh Entry
Self-Refresh Exit
ACT#0
Before Self-Refresh Entry,
all banks must be idle state.
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
X
X
X
0
Y
Y
Y
A9,11
BA0,1
DQ
0
0
0
masked
masked
D0
D0 D0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
DQM read latency=2
X
X
X
0
Y
Y
Y
A0-8
A10
A9,11
BA0,1
0
0
0
masked
masked
Q0
Q0 Q0
READ#0
Q0
Q0
Q0
Q0
DQ
ACT#0
READ#0
READ#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-8
A10
CKE latency=1
X
X
X
0
A9,11
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
CKE latency=1
CKE latency=1
X
X
X
0
Y
Y
A9,11
BA0,1
DQ
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
CLK suspended
READ#0
CLK suspended
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
± 0 . 1 3 1 7 . 7 8
± 0 2 . 1 3
± 0 3 . 1 3
± 0 . 1 3 1 7 . 7 8
3 4 . 9 2 5
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
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11/ Jan. /1999
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