MT90823 [MITEL]
3V Large Digital Switch; 3V大型数字交换机
| 型号： | MT90823 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | 3V Large Digital Switch |
| 文件： | 总34页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT90823
3V Large Digital Switch
DS5064
ISSUE 3
January 2000
Features
•
•
•
•
2,048 × 2,048 channel non-blocking switching
at 8.192 Mb/s
Ordering Information
MT90823AP
84 Pin PLCC
100 Pin MQFP
100 Pin LQFP
120 Pin PBGA
Per-channel variable or constant throughput
delay
MT90823AL
MT90823AB
MT90823AG
Automatic identification of ST-BUS/GCI
interfaces
-40 to +85°C
Accept ST-BUS streams of 2.048, 4.096 or
8.192 Mb/s
Description
•
•
•
•
•
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
The MT90823 Large Digital Switch has
a
non-blocking switch capacity of: 2,048 x 2,048
channels at a serial bit rate of 8.192 Mb/s; 1,024 x
1,024 channels at 4.096 Mb/s; and 512 x 512
channels at 2.048 Mb/s. The device has many
features that are programmable on a per stream or
per channel basis, including message mode, input
offset delay and high impedance output control.
Control interface compatible to Motorola
non-multiplexed CPUs
•
•
Connection memory block programming
3.3V local I/O with 5V tolerant inputs and
TTL-compatible outputs
Per stream input delay control is particularly useful
for managing large multi-chip switches that transport
both voice channel and concatenated data channels.
•
IEEE-1149.1 (JTAG) Test Port
Applications
•
•
•
•
•
•
Medium and large switching platforms
In addition, the input stream can be individually
calibrated for input frame offset using a dedicated
pin.
CTI application
Voice/data multiplexer
Digital cross connects
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
V
V
SS
ODE
TMS
TDI TDO TCK TRST
IC
RESET
DD
Test Port
Loopback
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
STi0
STi1
STi2
Serial
to
Parallel
to
STi3
STi4
Output
MUX
STi5
Parallel
Multiple Buffer
Data Memory
STi6
Serial
STi7
Converter
STi8
Converter
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Connection
Memory
Internal
Registers
Timing
Unit
Microprocessor Interface
AS/ IM DS/
CLK F0i FE/ WFPS
HCLK
CS R/W
/WR
D15-D8/ CSTo
AD7-AD0
A7-A0 DTA
ALE
RD
Figure 1 - Functional Block Diagram
1
MT90823 CMOS
10
8
6
4
2
84
82
80
78
76
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
CSTo
DTA
D15
D14
D13
D12
D11
D10
D9
13
73
15
17
19
21
23
25
27
29
31
71
69
67
65
63
61
59
57
55
STi9
D8
84 PIN PLCC
STi10
STi11
STi12
STi13
STi14
STi15
F0i
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
FE/HCLK
VSS
CLK
VDD
34
36
38
40
42
44
46
48
50
52
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
DTA
D15
D14
D13
D12
D11
D10
D9
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
82
84
86
88
90
92
94
96
D8
100 PIN MQFP
(14mm x 20mm x 2.75mm)
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
98
99
FE/HCLK
VSS
CLK
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Figure 2 - PLCC and MQFP Pin Connections
2
CMOS MT90823
1
2
3
4
5
6
7
8
9
10
11
12
13
1
A
VSS VSS STo14 STo12STo10 STo9 STo7 STo5 STo4 STo2 STo0 VSS VSS
VSS VSS STo15 STo13STo11 STo8 VSS STo6 STo3 STo1 ODE VSS VSS
B
C
D
E
F
STi1 VSS VDD VSS VDD VSS VDD VSS VDD VSS DTA
STi0
CSTo
D15
D13
D11
D9
STi3 VDD
STi5 VSS
STi7 VDD
STi9 VSS
STi11 VDD
STi13 VSS
STi15 VDD
D14
VDD
STi2
VSS D12
VDD D10
VSS D8
STi4
TOP VIEW
PBGA
STi6
G
H
J
STi8
(23mm x 23mm x 2.13mm)
(Ball Pitch = 1.5mm)
VDD AD6
VSS AD4
VDD AD2
STi10
STi12
STi14
AD7
AD5
AD3
AD1
VSS
IM
K
L
FE/HCLKVSS VDD VSS VDD VSS VDD VSS VDD
AD0
F0i
VSS VSS TDI TCK IC
CLK TMS TDO TRST RESETA0
VSS
A6 R/W/RWAS/ALEVSS
A5 A7 DS/RD CS
M
N
WFPSA1
A2
A4
A3
1
- A1 corner is identified by metallized markings.
74
72
70
68
66
64
62
60
58
56
54
52
76
NC
50
NC
NC
NC
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
78
80
CSTo
DTA
D15
D14
D13
D12
D11
D10
D9
48
46
82
84
86
88
90
44
42
100 PIN LQFP
40
38
36
34
D8
STi9
(14mm x 14mm x 1.4mm)
(Pin Pitch = 0.50mm)
STi10
STi11
STi12
STi13
STi14
STi15
F0i
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
NC
92
94
32
30
28
26
FE/HCLK
VSS
96
CLK
VDD
NC
98
100
NC
NC
2
4
6
8
10
12
14
16
18
20
22
24
Figure 3 - PBGA and LQFP Pin Connections
3
MT90823 CMOS
Pin Description
Pin #
Name
Description
84
100
100
120
PLCC MQFP LQFP
BGA
1, 11, 31, 41,
30, 54 56, 66,
64, 75 76, 99
28,
38,
53,
63,
73,
96
A1,A2,A12,A13,
B1,B2,B7,B12,
B13,C3,C5,C7,
C9,C11,E3,E11
G3,G11,J3,J11,
L3,L5,L7,L9,L11,
M2,M12,M13,N1
VSS
Ground.
2, 32, 5, 40,
37,
C4,C6,C8,C10,
VDD
+3.3 Volt Power Supply.
63
67
64,98 D3,D11,F3,F11,
H3,H11,K3,K11,
L4,L6,L8,L10
3 - 10 68-75
65 -
72
B6,A6,A5,B5,A4, STo8 - 15 ST-BUS Output 8 to 15 (5V Tolerant Three-state
B4,A3,B3
Outputs): Serial data Output stream. These streams
may have data rates of 2.048, 4.096 or 8.192 Mb/s,
depending upon the value programmed at bits DR0 - 1
in the IMS register.
12 -
27
81-96
97
78 - C1,C2,D1,D2,E1, STi0 - 15 ST-BUS Input 0 to 15 (5V Tolerant Inputs): Serial
93
E2,F1,F2,G1,G2,
H1,H2,J1,J2,K1,
K2
data input stream. These streams may have data rates
of 2.048, 4.096 or 8.192 Mb/s, depending upon the
value programmed at bits DR0 - 1 in the IMS register.
28
94
L1
F0i
Frame Pulse (5V Tolerant Input): When the WFPS
pin is low, this input accepts and automatically
identifies frame synchronization signals formatted
according to ST-BUS and GCI specifications. When the
WFPS pin is high, this pin accepts a negative frame
pulse which conforms to WFPS formats.
29
31
98
95
97
L2
FE/HCLK Frame Evaluation / HCLK Clock (5V Tolerant Input):
When the WFPS pin is low, this pin is the frame
measurement input. When the WFPS pin is high, the
HCLK (4.096MHz clock) is required for frame alignment
in the wide frame pulse (WFP) mode.
100
N1
CLK
Clock (5V Tolerant Input): Serial clock for shifting data
in/out on the serial streams (STi/o 0 - 15). Depending
upon the value programmed at bits DR0 - 1 in the IMS
register, this input accepts a 4.096, 8.192 or 16.384
MHz clock.
33
34
35
6
7
8
3
4
5
N2
M3
N3
TMS
TDI
Test Mode Select (3.3V Input with internal pull-up):
JTAG signal that controls the TAP controller state
transitions.
Test Serial Data In (3.3V Tolerant Input with internal
pull-up): JTAG serial test instructions and data are
shifted in on this pin.
TDO
Test Serial Data Out (3.3V Output): JTAG serial data
is output on this pin on the falling edge of TCK. This pin
is held in high impedance state when JTAG scan is not
enabled.
4
CMOS MT90823
Pin Description (continued)
Pin #
Name
Description
84
100
100
120
PLCC MQFP LQFP
BGA
36
37
9
6
7
M4
TCK
Test Clock (5V Tolerant Input): Provides the clock to
the JTAG test logic.
10
N4
TRST
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should
be pulsed low on power-up, or held low, to ensure that
the MT90823 is in the normal functional mode.
38
39
11
12
8
9
M5
N5
IC
Internal Connection (3.3V Input with internal
pull-down): Connect to VSS for normal operation. This
pin must be low for the MT90823 to function normally
and to comply with IEEE 1149 (JTAG) boundary scan
requirements.
RESET Device Reset (5V Tolerant Input): This input (active
LOW) puts the MT90823 in its reset state to clear the
device internal counters, registers and bring STo0 - 15
and microport data outputs to a high impedance state.
The time constant for a power up reset circuit must be a
minimum of five times the rise time of the power supply.
In normal operation, the RESET pin must be held low
for a minimum of 100nsec to reset the device.
40
13
14-21
22
10
M6
WFPS
Wide Frame Pulse Select (5V Tolerant Input): When
1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in
ST-BUS/GCI mode.
41 -
48
11 -
18
N6,M7,N7,N8,
M8,N9,M9,N10
A0 - A7 Address 0 - 7 (5V Tolerant Input): When
non-multiplexed CPU bus operation is selected, these
lines provide the A0 - A7 address lines to the internal
memories.
49
19
N11
DS/RD Data Strobe / Read (5V Tolerant Input): For Motorola
multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable
the read and write operations.
For Motorola non-multiplexed CPU bus operation, this
input is DS. This active low input works in conjunction
with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This
active low input sets the data bus lines (AD0-AD7,
D8-D15) as outputs.
50
23
20
M10
R/W / WR Read/Write / Write (5V Tolerant Input): In the cases
of Motorola non-multiplexed and multiplexed bus
operations, this input is R/W. This input controls the
direction of the data bus lines (AD0 - AD7, D8-D15)
during a microprocessor access.
For multiplexed bus operation, this input is WR. This
active low input is used with RD to control the data bus
(AD0 - 7) lines as inputs.
5
MT90823 CMOS
Pin Description (continued)
Pin #
Name
Description
84
100
100
120
PLCC MQFP LQFP
BGA
51
52
24
25
21
22
N12
CS
Chip Select (5V Tolerant Input): Active low input used
by a microprocessor to activate the microprocessor
port of MT90823.
M11
AS/ALE Address Strobe or Latch Enable (5V Tolerant Input):
This input is used if multiplexed bus operation is
selected via the IM input pin. For Motorola
non-multiplexed bus operation, connect this pin to
ground.
53
26
23
N13
IM
CPU Interface Mode (5V Tolerant Input): When IM is
high, the microprocessor port is in the multiplexed
mode. When IM is low, the microprocessor port is in
non-multiplexed mode.
55 -
62
32-39
29 -
36
L12,L13,K12,
K13,J12,J13,
H12,H13
AD0 - 7 Address/Data Bus 0 to 7 (5V Tolerant I/O): These
pins are the eight least significant data bits of the
microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor
port.
65 -
72
42-49
50
39 -
46
G12,G13,F12,
F13,E12,E13,
D12,D13
D8 - 15 Data Bus 8-15 (5V Tolerant I/O): These pins are the
eight most significant data bits of the microprocessor
port.
73
47
C12
DTA
Data Transfer Acknowledgement (5V tolerant
Three-state Output): Indicates that a data bus transfer
is complete. When the bus cycle ends, this pin drives
HIGH and then tri-states, allowing for faster bus cycles
with a weaker pull-up resistor. A pull-up resistor is
required to hold a HIGH level when the pin is tri-stated.
74
76
55
57
48
54
C13
B11
CSTo
ODE
Control Output (5V Tolerant Output). This is a 4.096,
8.192 or 16.384 Mb/s output containing 512, 1024 or
2048 bits per frame respectively. The level of each bit is
determined by the CSTo bit in the connection memory.
See External Drive Control Section.
Output Drive Enable (5V Tolerant Input): This is the
output enable control for the STo0-15 serial outputs.
When ODE input is low and the OSB bit of the IMS
register is low, STo0-15 are in a high impedance state.
If this input is high, the STo0-15 output drivers are
enabled. However, each channel may still be put into a
high impedance state by using the per channel control
bit in the connection memory.
77 -
84
58-65
55 - A11,B10,A10,B9, STo0 - 7 Data Stream Output 0 to 7 (5V Tolerant Three-state
62
A9,A8,B8,A7
Outputs): Serial data Output stream. These streams
have selectable data rates of 2.048, 4.096 or 8.192 Mb/
s.
6
CMOS MT90823
Pin Description (continued)
Pin #
Name
Description
84
100
100
120
PLCC MQFP LQFP
BGA
-
1 - 4,
27 -
30,
1 - 2,
24 -
27,
NC
No connection.
51 -
54
49 -
52,
77 -
80
74 -
77,
99 -
100
Device Overview
Functional Description
The MT90823 Large Digital Switch is capable of
switching up to 2,048 × 2,048 channels. The
MT90823 is designed to switch 64 kb/s PCM or N x
64 kb/s data. The device maintains frame integrity in
data applications and minimum throughput delay for
voice applications on a per channel basis.
A functional Block Diagram of the MT90823 is shown
in Figure 1.
Data and Connection Memory
For all data rates, the received serial data is
converted
to
parallel
format
by
internal
The serial input streams of the MT90823 can have a
bit rate of 2.048, 4.096 or 8.192 Mbit/s and are
arranged in 125µs wide frames, which contain 32, 64
or 128 channels, respectively. The data rates on
input and output streams are identical.
serial-to-parallel converters and stored sequentially
in the data memory. Depending upon the selected
operation programmed in the interface mode select
(IMS) register, the useable data memory may be as
large as 2,048 bytes. The sequential addressing of
the data memory is performed by an internal counter,
which is reset by the input 8 kHz frame pulse (F0i) to
mark the frame boundaries of the incoming serial
data streams.
By using Mitel’s message mode capability, the
microprocessor can access input and output
time-slots on a per channel basis. This feature is
useful for transferring control and status information
for external circuits or other ST-BUS devices. The
MT90823 automatically identifies the polarity of the
frame synchronization input signal and configures its
serial streams to be compatible to either ST-BUS or
GCI formats.
Data to be output on the serial streams may come
from either the data memory or connection memory.
Locations in the connection memory are associated
with particular ST-BUS output channels. When a
channel is due to be transmitted on an ST-BUS
output, the data for this channel can be switched
either from an ST-BUS input in connection mode, or
from the lower half of the connection memory in
message mode. Data destined for a particular
channel on a serial output stream is read from the
data memory or connection memory during the
previous channel time-slot. This allows enough time
for memory access and parallel-to-serial conversion.
Two different microprocessor bus interfaces can be
selected through the Input Mode pin (IM):
Non-multiplexed or Multiplexed. These interfaces
provide compatibility with multiplexed and Motorola
multiplexed/non-multiplexed buses.
The frame offset calibration function allows users to
measure the frame offset delay using a frame
evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal
frame input offset registers, see Table 11.
Connection and Message Modes
In the connection mode, the addresses of the input
source data for all output channels are stored in the
connection memory. The connection memory is
mapped in such
corresponds to an output channel on the output
The internal loopback allows the ST-BUS output data
to be looped around to the ST-BUS inputs for
diagnostic purposes.
a
way that each location
7
MT90823 CMOS
streams. For details on the use of the source
address data (CAB and SAB bits), see Table 13 and
Table 14. Once the source address bits are
programmed by the microprocessor, the contents of
the data memory at the selected address are
transferred to the parallel-to-serial converters and
then onto an ST-BUS output stream.
The MT90823 provides two different interface timing
modes controlled by the WFPS pin. If the WFPS pin
is low, the MT90823 is in ST-BUS/GCI mode. If the
WFPS pin is high, the MT90823 is in the wide frame
pulse (WFP) frame alignment mode.
In ST-BUS/GCI mode, the input 8 kHz frame pulse
can be in either ST-BUS or GCI format. The
MT90823 automatically detects the presence of an
input frame pulse and identifies it as either ST-BUS
or GCI. In ST-BUS format, every second falling edge
of the master clock marks a bit boundary and the
data is clocked in on the rising edge of CLK, three
quarters of the way into the bit cell, see Figure 11. In
GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in
on the falling edge of CLK at three quarters of the
way into the bit cell, see Figure 12.
By having several output channels connected to the
same input source channel, data can be broadcasted
from one input channel to several output channels.
In message mode, the microprocessor writes data to
the connection memory locations corresponding to
the output stream and channel number. The lower
half (8 least significant bits) of the connection
memory content is transferred directly to the
parallel-to-serial converter. This data will be output
on the ST-BUS streams in every frame until the data
is changed by the microprocessor.
Wide Frame Pulse (WFP) Frame Alignment
Timing
The five most significant bits of the connection
memory controls the following for an output channel:
message or connection mode; constant or variable
delay; enables/tristate the ST-BUS output drivers;
and, enables/disable the loopback function. In ad-
dition, one of these bits allows the user to control the
CSTo output.
When the device is in WFP frame alignment mode,
the CLK input must be at 16.384 MHz, the FE/HCLK
input is 4.096 MHz and the 8 kHz frame pulse is in
ST-BUS format. The timing relationship between
CLK, HCLK and the frame pulse is defined in Figure
13.
If an output channel is set to a high-impedance state
through the connection memory, the ST-BUS output
When the WFPS pin is high, the frame alignment
evaluation feature is disabled, but the frame input
offset registers may still be programmed to
compensate for the varying frame delays on the
serial input streams.
will be in a high impedance state for the duration of
that channel. In addition to the per-channel control,
all channels on the ST-BUS outputs can be placed in
a high impedance state by either pulling the ODE
input pin low or programming the output standby
(OSB) bit in the interface mode selection register to
low. This action overrides the individual per-channel
programming by the connection memory bits.
Switching Configurations
The MT90823 maximum non-blocking switching
configurations is determined by the data rates
selected for the serial inputs and outputs. The
switching configuration is selected by two DR bits in
the IMS register. See Table 8 and Table 9.
The connection memory data can be accessed via
the microprocessor interface through the D0 to D15
pins. The addressing of the device internal registers,
data and connection memories is performed through
the address input pins and the Memory Select (MS)
bit of the control register. For details on device
addressing, see Software Control and Control
Register bits description (Tables 4, 6 and 7).
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the
device is configured with 16-input/16-output data
streams each having 32 64 kb/s channels. This
mode requires a CLK of 4.094 MHz and allows a
maximum non-blocking capacity of 512 x 512
channels.
Serial Data Interface Timing
The master clock frequency must always be twice
the data rate. The master clock (CLK) must be either
at 4.096, 8.192 or 16.384 MHz for serial data rate of
2.048, 4.096 or 8.192 Mb/s respectively. The input
and output stream data rates will always be identical.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the
device is configured with 16-input/16-output data
streams each having 64 64 kb/s channels. This
8
CMOS MT90823
mode requires a CLK of 8.192 MHz and allows a
maximum non-blocking capacity of 1,024 x 1,024
channels.
The SFE bit must be set to zero before starting a
new measurement cycle.
In ST-BUS mode, the falling edge of the frame
measurement signal (FE) is evaluated against the
falling edge of the ST-BUS frame pulse. In GCI
mode, the rising edge of FE is evaluated against the
rising edge of the GCI frame pulse. See Table 10 and
Figure 3 for the description of the frame alignment
register.
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the
device is configured with 16-input/16-output data
streams each having 128 64 kb/s channels. This
mode requires a CLK of 16.384 MHz and allows a
maximum non-blocking capacity of 2,048 x 2,048
channels. Table
1
summarizes the switching
configurations and the relationship between different
serial data rates and the master clock frequencies.
This feature is not available when the WFP Frame
Alignment mode is enabled (i.e., when the WFPS pin
is connected to VDD).
Serial
Interface
Data Rate
Master Clock
Required
(MHz)
Matrix
Channel
Capacity
Memory Block Programming
The MT90823 provides users with the capability of
initializing the entire connection memory block in two
frames. Bits 11 to 15 of every connection memory
location will be programmed with the pattern stored
in bits 5 to 9 of the IMS register.
2 Mb/s
4 Mb/s
8 Mb/s
4.096
8.192
512 x 512
1,024 x 1,024
2,048 x 2,048
16.384
Table 1- Switching Configuration
Input Frame Offset Selection
The block programming mode is enabled by setting
the memory block program (MBP) bit of the control
register high. When the block programming enable
(BPE) bit of the IMS register is set to high, the block
programming data will be loaded into the bits 11 to
15 of every connection memory location. The other
connection memory bits (bit 0 to bit 10) are loaded
with zeros. When the memory block programming is
complete, the device resets the BPE bit to zero.
Input frame offset selection allows the channel
alignment of individual input streams to be offset with
respect to the output stream channel alignment (i.e.
F0i). This feature is useful in compensating for
variable path delays caused by serial backplanes of
variable lengths, which may be implemented in large
centralized and distributed switching systems.
Loopback Control
Each input stream can have its own delay offset
value by programming the frame input offset (FOR)
registers. Possible adjustment can range up to +4
master clock (CLK) periods forward with resolution of
1/2 clock period. The output frame offset cannot be
offset or adjusted. See Figure 4, Table 11 and Table
12 for delay offset programming.
The loopback control (LPBK) bit of each connection
memory location allows the ST-BUS output data to
be looped backed internally to the ST-BUS input for
diagnostic purposes.
If the LPBK bit is high, the associated ST-BUS output
channel data is internally looped back to the ST-BUS
input channel (i.e., data from STo n channel m routes
to the STi n channel m internally); if the LPBK bit is
low, the loopback feature is disabled. For proper
per-channel loopback operation, the contents of
frame delay offset registers must be set to zero.
Serial Input Frame Alignment Evaluation
The MT90823 provides the frame evaluation (FE)
input to determine different data input delays with
respect to the frame pulse F0i.
Delay Through the MT90823
A measurement cycle is started by setting the start
frame evaluation (SFE) bit low for at least one frame.
Then the evaluation starts when the SFE bit in the
IMS register is changed from low to high. Two frames
later, the complete frame evaluation (CFE) bit of the
frame alignment register (FAR) changes from low to
high. This signals that a valid offset measurement is
ready to be read from bits 0 to 11 of the FAR register.
The switching of information from the input serial
streams to the output serial streams results in a
throughput delay. The device can be programmed to
perform time-slot interchange functions with different
throughput delay capabilities on a per-channel basis.
For voice application, select variable throughput
9
MT90823 CMOS
delay to ensure minimum delay between input and
output data. In wideband data applications, select
constant throughput delay to maintain the frame
integrity of the information through the switch.
In the MT90823, the minimum throughput delay
achievable in the constant delay mode is one frame.
For example, in 2 Mb/s mode, when input time-slot
31 is switched to output time-slot 0. The maximum
delay of 94 time-slots occurs when time-slot 0 in a
frame is switched to time-slot 31 in the frame. See
Table 3.
The delay through the device varies according to the
type of throughput delay selected in the V/C bit of the
connection memory.
Microprocessor Interface
Variable Delay Mode (V/C bit = 0)
The MT90823 provides a parallel microprocessor
interface for non-multiplexed or multiplexed bus
structures. This interface is compatible with Motorola
non-multiplexed and multiplexed buses.
The delay in this mode is dependent only on the
combination of source and destination channels. It is
independent of input and output streams. The
minimum delay achievable in the MT90823 is three
time-slots. When the input channel data is switched
to the same output channel (channel n, frame p), it
will be output in the following frame (channel n,
frame p+1). The same frame delay occurs if the input
channel n is switched to output channel n+1 or n+2.
When input channel n is switched to output channel
n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for
the MT90823 in the variable delay mode.
If the IM pin is low, the MT90823 microprocessor
interface assumes Motorola non-multiplexed bus
mode. If the IM pin is high, the device micro-
processor interface accepts two different timing
modes (mode1 and mode2) which allows direct
connection to multiplexed microprocessors.
The microprocessor interface automatically identifies
the type of microprocessor bus connected to the
MT90823. This circuit uses the level of the DS/RD
input pin at the rising edge of AS/ALE to identify the
appropriate bus timing connected to the MT90823. If
DS/RD is high at the falling edge of AS/ALE, then the
mode 1 multiplexed timing is selected. If DS/RD is
low at the falling edge of AS/ALE, then the mode 2
multiplexed bus timing is selected.
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all
switching configurations by using a multiple data
memory buffer. Input channel data written into the
data memory buffers during frame n will be read out
during frame n+2.
Delay for Variable Throughput Delay Mode
(m - output channel number)
(n - input channel number))
Input Rate
m < n
m = n, n+1, n+2
m > n+2
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32 - (n-m) time-slots
64 - (n-m) time-slots
128 - (n-m) time-slots
m-n + 32 time-slots
m-n + 64 time-slots
m-n + 128 time-slots
m-n time-slots
m-n time-slots
m-n time-slots
Table 2 - Variable Throughput Delay Value
Delay for Constant Throughput Delay Mode
(m - output channel number)
Input Rate
(n - input channel number))
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32 + (32 - n) + (m - 1) time-slots
64 + (64 - n) + (m- 1) time-slots
128 + (128 - n) + (m- 1) time-slots
Table 3 - Constant Throughput Delay Value
10
CMOS MT90823
For multiplexed operation, the 8-bit data and address
(AD0-AD7), 8-bit Data (D8-D15), Address strobe/
Address latch enable (AS/ALE), Data strobe/Read
(DS/RD), Read/Write /Write (R/W / WR), Chip select
(CS) and Data transfer acknowledge (DTA) signals
are required. See Figure 13 and Figure 14 for
multiplexed parallel microport timing.
an internal memory subsections corresponding to
input or output ST-BUS streams.
The data in the IMS register consists of block
programming bits (BPD0-BPD4), block programming
enable bit (BPE), output standby bit (OSB), start
frame evaluation bit (SFE) and data rate selection
bits (DR0, DR1). The block programming and the
block programming enable bits allows users to
program the entire connection memory, (see Memory
Block Programming section). If the ODE pin is low,
the OSB bit enables (if high) or disables (if low) all
ST-BUS output drivers. If the ODE pin is high, the
contents of the OSB bit is ignored and all ST-BUS
output drivers are enabled.
For the Motorola non-multiplexed bus, the 16-bit data
bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7)
and 4 control lines (CS, DS, R/W and DTA) signals
are required. See Figure 15 for Motorola non-
multiplexed microport timing.
The MT90823 microport provides access to the
internal registers, connection and data memories. All
locations provide read/write access except for the
data memory and the frame alignment register which
are read only.
Connection Memory Control
The contents of the CSTo bit of each connection
memory location are output on the CSTo pin once
every frame. The CSTo pin is a 4.096, 8.192 or
16.384 Mb/s output carrying 512, 1,024 or 2,048 bits
respectively. If the CSTo bit is set high, the
corresponding bit on the CSTo output is transmitted
high. If the CSTo bit is low, the corresponding bit on
the CSTo output is transmitted low. The contents of
the CSTo bits of the connection memory are
transmitted sequentially via the CSTo pin and are
synchronous with the data rates on the other ST-BUS
streams.
Memory Mapping
The address bus on the microprocessor interface
selects the MT90823 internal registers and memory.
If the A7 address input is low, then the control (CR),
interface mode selection (IMS), frame alignment
(FAR) and frame input offset (FOR) registers are
addressed by A6 to A0 as shown in Table 4.
If the A7 address input is high, then the remaining
address input lines are used to select up to 128
memory subsection locations. The number selected
corresponds to the maximum number of channels
per input or output stream. The address input lines
and the stream address bits (STA) of the control
register allow access to the entire data and
connection memories.
The CSTo bit is output one channel before the
corresponding channel on the ST-BUS. For example,
in 2Mb/s mode, the contents of the CSTo bit in
position 0 (STo0, CH0) of the connection memory is
output on the first clock cycle of channel 31 via CSTo
pin. The contents of the CSTo bit in position 32
(STo1, CH0) of the connection memory is output on
the second clock cycle of channel 31 via CSTo pin.
The control and IMS registers together control all the
major functions of the device. The IMS register
should be programmed immediately after system
power-up to establish the desired switching
configuration (see “Serial Data Interface Timing”
and “Switching Configurations” ).
When either the ODE pin or the OSB bit is high, the
OE bit of each connection memory location enables
(if high) or disables (if low) the output drivers for an
individual ST-BUS output stream and channel. Table
5 details this function.
The control register controls switching operations in
the MT90823. It selects the internal memory
locations that specify the input and output channels
selected for switching.
The connection memory message channel (MC) bit
(if high) enables message mode in the associated
ST-BUS output channel. When message mode is
enabled, only the lower half (8 least significant bits)
of the connection memory is transferred to the
ST-BUS outputs.
The data in the control register consists of the
memory block programming bit (MBP), the memory
select bit (MS) and the stream address bits (STA).
The memory block programming bit allows users to
program the entire connection memory block, (see
“Memory Block Programming” ). The memory select
bit controls the selection of the connection memory
or the data Memory. The stream address bits define
If the MC bit is low, the contents of the connection
memory stream address bit (SAB) and channel
address bit (CAB) defines the source information
(stream and channel) of the time-slot that will be
switched to the output.
11
MT90823 CMOS
Bit V/C (Variable/Constant Delay) of each connection
memory location allows the per-channel selection
between variable and constant throughput delay
modes.
back to the ST-BUS input channel (i.e., SToN
channel m data loops back to STi N channel m).
If the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation,
the contents of the frame delay offset registers must
be set to zero.
The loopback bit should be used for diagnostic
purpose only; this bit should be set to zero for normal
operation. If all LPBK bits are set high for all
connection memory locations, the associated
ST-BUS output channel data is internally looped
A7
A6
A5
A4
A3
A2
A1
A0
Location
Control Register, CR
(Note 1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Interface Mode Selection Register, IMS
Frame Alignment Register, FAR
Frame Input Offset Register 0, FOR0
Frame Input Offset Register 1, FOR1
Frame Input Offset Register 2, FOR2
Frame Input Offset Register 3, FOR3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 0
Ch 1
.
Ch 30
Ch 31
(Note 2)
(Note 3)
(Note 4)
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32
Ch 33
.
Ch 62
Ch 63
1
1
1
1
1
1
1
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 64
Ch 65
.
Ch 126
Ch 127
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8Mb/s mode.
Table 4 - Internal Register and Address Memory Mapping
OE bit in Connection
ODE pin
OSB bit in IMS register
ST-BUS Output Driver Status
Memory
0
Don’t Care
Don’t Care
Per Channel
High Impedance
1
1
1
0
0
1
0
1
High Impedance
Enable
Don’t care
Enable
Table 5 - Output High Impedance Control
12
CMOS MT90823
To prevent two ST-BUS outputs from driving the
same stream simultaneously, the microprocessor
should program the desired active paths through the
switch and put all other channels into a high
impedance state during the initialization routine by
using the block programming mode. In addition, the
loopback bits in the connection memory should be
cleared for normal operation.
Initialization of the MT90823
During power up, the TRST pin should be pulsed low,
or held low continuously, to ensure that the MT90863
is in the normal functional mode. A 5K pull-down
resistor can be connected to this pin so that the
device will not enter the JTAG test mode during
power up.
When this process is complete, the microprocessor
controlling the matrices can bring the ODE pin or
OSB bit high to relinquish the high impedance state
control to the OE bit in the connection memory.
Upon power up, the contents of the connection
memory can be in any state and the ODE pin should
be held low to keep all ST-BUS outputs in a high
impedance state until the microprocessor has
initialized the switching matrix.
Read/Write Address:
Reset Value:
00 ,
H
0000 .
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
MBP
MS STA3 STA2 STA1 STA0
Bit
Name
Description
15 - 6
5
Unused
MBP
Must be zero for normal operation.
Memory Block Program. When 1, the connection memory block programming
feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15.
When 0, this feature is disabled.
4
MS
Memory Select. When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
3 - 0
STA3-0
Stream Address Bits. The binary value expressed by these bits refers to the input or
output data stream, which corresponds to the subsection of memory made accessible
for subsequent operations. (STA3 = MSB, STA0 = LSB)
Table 6 - Control (CR) Register Bits
Input/Output
Data Rate
Valid Address Lines
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
A4, A3, A2, A1, A0
A5, A4, A3, A2, A1, A0
A6, A5, A4 A3, A2, A1, A0
Table 7 - Valid Address lines for Different Bit Rates
13
MT90823 CMOS
Read/Write Address:
Reset Value:
01 ,
H
0000 .
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BPD
3
BPD BPD
BPD
0
BPD
4
0
0
0
0
0
0
BPE OSB SFE
DR1
DR0
2
1
Bit
Name
Description
15-10
9-5
Unused
BPD4-0
Must be zero for normal operation.
Block Programming Data. These bits carry the value to be loaded into the
connection memory block whenever the memory block programming feature is
activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to
1, the contents of the bits BPD4- 0 are loaded into bit 15 to bit 11 of the connection
memory. Bit 10 to bit 0 of the connection memory are set to 0.
4
BPE
Begin Block programming Enable. A zero to one transition of this bit enables the
memory block programming function. The BPE and BPD4-0 bits in the IMS register
have to be defined in the same write operation. Once the BPE bit is set high, the
device requires two frames to complete the block programming. After the
programming function has finished, the BPE bit returns to zero to indicate the
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort
the programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames
to ensure proper operation.
3
2
OSB
SFE
Output standby. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15
are in high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0
to STo15 function normally. When ODE = 1, STo0 to STo15 output drivers function
normally.
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the
evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero
for at least one frame.
1 - 0
DR1-0
Data Rate Select. Input/Output data rate selection. See Table 9 for detailed
programming.
Table 8 - Interface Mode Selection (IMS) Register Bits
DR1
DR0
Data Rate Selected
Master Clock Required
0
0
1
1
0
1
0
1
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
4.096 MHz
8.192 MHz
16.384 MHz
Reserved
Table 9 - Serial Data Rate Selection (16 input x 16 output)
14
CMOS MT90823
Read Address:
Reset Value:
02 ,
H
0000 .
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CFE
FD11 FD10 FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
0
Bit
Name
Description
Must be zero for normal operation.
15 - 13
12
Unused
CFE
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and bits FD10 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to
0.
11
FD11
Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is
sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
(FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle.
10 - 0
FD10-0
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
Table 10 - Frame Alignment (FAR) Register Bits
ST-BUS Frame
CLK
Offset Value
FE Input
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
(FD[10:0] = 06 )
H
(FD11 = 0, sample at CLK low phase)
GCI Frame
CLK
Offset Value
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FE Input
(FD[10:0] = 09 )
H
(FD11 = 1, sample at CLK high phase)
Figure 4 - Example for Frame Alignment Measurement
15
MT90823 CMOS
Read/Write Address:
03 for FOR0 register,
H
04 for FOR1 register,
H
05 for FOR2 register,
H
06 for FOR3 register,
H
Reset value:
0000 for all FOR registers.
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32
OF31
OF30 DLE3 OF22
OF21 OF20
DLE2 OF12
OF11 OF10
DLE1 OF02
OF01 OF00
DLE0
FOR0 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72
OF71
OF70 DLE7 OF62
OF61 OF60
DLE6 OF52
OF51 OF50
DLE5 OF42
OF41 OF40
DLE4
FOR1 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92
OF91 OF90
DLE9 OF82
OF81 OF80
DLE8
FOR2 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR3 register
Name
Description
(Note 1)
OFn2, OFn1, OFn0
Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes
to recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input
frame offset can be selected to +4 clock periods from the point where the external
frame pulse input signal is applied to the F0i input of the device. See Figure 4.
DLEn
Data Latch Edge.
ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock falling edge is at the 3/4 of the bit cell.
GCI mode:
DLEn =0, if clock falling edge is at the 3/4 point of the bit cell.
DLEn =1, if when clock rising edge is at the 3/4 of the bit cell.
Note 1: n denotes an input stream number from 0 to 15.
Table 11 - Frame Input Offset (FOR) Register Bits
16
CMOS MT90823
Measurement Result from
Frame Delay Bits
Corresponding
Offset Bits
Input Stream
Offset
FD11
FD2
FD1
FD0
OFn2
OFn1
OFn0
DLEn
No clock period shift (Default)
+ 0.5 clock period shift
+1.0 clock period shift
+1.5 clock period shift
+2.0 clock period shift
+2.5 clock period shift
+3.0 clock period shift
+3.5 clock period shift
+4.0 clock period shift
+4.5 clock period shift
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) and Frame Delay Bits (FD11, FD2-0)
ST-BUS F0i
CLK
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
STi Stream
Bit 7
Bit 7
STi Stream
STi Stream
STi Stream
Bit 7
Bit 7
denotes the 3/4 point of the bit cell
GCI F0i
CLK
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
Bit 0
Input Stream
Bit 0
Input Stream
Input Stream
Input Stream
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
Figure 5 - Examples for Input Offset Delay Timing
17
MT90823 CMOS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V/C
MC CSTo
OE
SAB3 SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
LPBK
Bit
Name
Description
15
LPBK
Per Channel Loopback. This bit should be use for diagnostic purpose only.
Set this bit to zero for normal operation. When loopback bit is set for all
memory location, the STi n channel m data comes from STo n channel m. For
proper per channel loopback operations, set the delay offset register bits
OFn[2:0] to zero for the streams which are in the loopback mode.
14
13
V/C
MC
Variable /Constant Throughput Delay. This bit is used to select between
the variable (low) and the constant delay (high) modes on a per-channel
basis.
Message Channel. When 1, the contents of the connection memory are
output on the corresponding output channel and stream. Only the lower byte
(bit 7 - bit 0) will be output to the ST-BUS output pins. When 0, the contents of
the connection memory are the data memory address of the switched input
channel and stream.
12
11
CSTo
OE
Control ST-BUS output. This bit is output on the CSTo pin one channel early.
The CSTo bit for stream 0 is output first.
Output Enable. This bit enables the ST-BUS output drivers on a per-channel
basis.
When 1, the output driver functions normally. When 0, the output driver is in a
high-impedance state.
10 - 8,
7
(Note 1)
SAB3-0
CAB6-0
Source Stream Address Bits. The binary value is the number of the data
stream for the source of the connection.
6 - 0
Source Channel Address Bits. The binary value is the number of the
(Note 1)
channel for the source of the connection.
Note 1: If bit 13 (MC) of the corresponding connection memory location is 1 (device in message mode), then these entire 8 bits
(SAB0, CAB6 - CAB0) are output on the output channel and stream associated with this location.
Table 13 - Connection Memory Bits
Data Rate
CAB Bits Used to Determine the Source Channel of the Connection
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
CAB4 to CAB0 (32 channel/input stream)
CAB5 to CAB0 (64 channel/input stream)
CAB6 to CAB0 (128 channel/input stream)
Table 14 - CAB Bits Programming for Different Data Rates
18
CMOS MT90823
•
Test Reset (TRST)
Resets the JTAG scan structure. This pin is
internally pulled to VDD.
JTAG Support
The MT90823 JTAG interface conforms to the IEEE
1149.1
Boundary-Scan
standard
and
the
Instruction Register
Boundary-Scan Test (BST) design-for-testability
technique it specifies. The operation of the
boundary-scan circuitry is controlled by an external
test access port (TAP) Controller.
In accordance with the IEEE 1149.1 standard, the
MT90823 uses public instructions. The MT90823
JTAG Interface contains a two-bit instruction register.
Instructions are serially loaded into the instruction
register from the TDI when the TAP Controller is in
its shifted-IR state. Subsequently, the instructions
are decoded to achieve two basic functions: to select
the test data register that may operate while the
instruction is current, and to define the serial test
data register path, which is used to shift data
between TDI and DO during data register scanning.
Test Access Port (TAP)
The Test Access Port (TAP) provides access to the
many test functions of the MT90823. It consists of
three input pins and one output pin. The following
pins comprise the TAP.
•
Test Clock Input (TCK)
TCK provides the clock for the test logic. The
TCK does not interfere with any on-chip clock
and thus remains independent. The TCK
permits shifting of test data into or out of the
Boundary-Scan register cells concurrently with
the operation of the device and without
interfering with the on-chip logic.
Test Data Register
As specified in IEEE 1149.1, the MT90823 JTAG
Interface contains three test data registers:
•
The Boundary-Scan Register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to form
a scan path around the boundary of the
MT90823 core logic.
•
•
Test Mode Select Input (TMS)
The logic signals received at the TMS input are
interpreted by the TAP Controller to control the
test operations. The TMS signals are sampled
at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven
from an external source.
•
•
The Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from TDI to
its TDO.
Test Data Input (TDI)
Serial input data applied to this port is fed
either into the instruction register or into a test
data register, depending on the sequence
previously applied to the TMS input. Both
The Device Identification Register
The device identification register is a 32-bit
register with the register contain of:
registers are described in
a
subsequent
MSB
LSB
section. The received input data is sampled at
the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven
from an external source.
0000 0000 1000 0010 0011 0001 0100 1011
The LSB bit in the device identification register is
the first bit clocked out.
•
Test Data Output (TDO)
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or data register are serially
shifted out towards the TDO. The data out of
the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through
the boundary scan cells, the TDO driver is set
to a high impedance state.
The MT90823 boundary scan register contains 118
bits. Bit 0 in Table 15 Boundary Scan Register is the
first bit clocked out. All tristate enable bits are active
high.
19
MT90823 CMOS
Boundary Scan Bit 0 to Bit 117
Boundary Scan Bit 0 to Bit 117
Device Pin
Device Pin
Output
Scan
Cell
Input
Scan
Cell
Output
Scan
Cell
Input
Scan
Cell
Tristate
Control
Tristate
Control
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
0
2
4
6
8
10
12
14
1
3
5
7
9
11
13
15
A7
A6
A5
A4
A3
A2
A1
A0
73
74
75
76
77
78
79
80
ODE
CSTo
DTA
16
WFPS
RESET
CLK
81
82
83
84
85
17
18
19
D15
D14
D13
D12
D11
D10
D9
20
23
26
29
32
35
38
41
21
24
27
30
33
36
39
42
22
25
28
31
34
37
40
43
FE/HCLK
F0i
STi15
STi14
STi13
STi12
STi11
STi10
STi9
STi8
STi7
STi6
STi5
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
D8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
44
47
50
53
56
59
62
65
45
48
51
54
57
60
63
66
46
49
52
55
58
61
64
67
STi4
STi3
STi2
STi1
IM
AS/ALE
CS
68
69
70
71
72
STi0
STo15
STo14
STo13
STo12
STo11
STo10
STo9
102
104
106
108
110
112
114
116
103
105
107
109
111
113
115
117
R/W / WR
DS/RD
STo8
Table 15: Boundary Scan Register Bits
Table 15: Boundary Scan Register Bits
20
CMOS MT90823
Figure 6 illustrates how four MT90823 devices can
be used to form non-blocking switches for up to 4096
channels with data rate of 8.192 Mb/s.
Applications
Switch Matrix Architectures
Serial Input Frame Alignment Evaluation
The MT90823 is an ideal device for medium to large
size switch matrices where voice and grouped data
channels are transported within the same frame. In
such applications, the voice samples have to be time
interchanged with a minimum delay while maintain-
ing the integrity of grouped data. To ensure the
integrity of grouped data during switching and to
provide a minimum delay for voice connections, the
MT90823 provides per-channel selection between
variable and constant throughput delay. This can be
selected by the V/C bit of the Connection Memory.
The MT90823 is capable of performing frame
alignment evaluation. The frame pulse under
evaluation is connected to the FE (frame measure-
ment) pin. An external multiplexer is required to
select one of the frame pulses related to the different
input streams. The block diagram at Figure 7 shows
a switch matrix that performs frame alignment
evaluation for 16 frame pulses.
16 Streams
16 Streams
MT90823
#1
IN
OUT
16 Streams
16 Streams
MT90823
#2
MT90823
#3
Bit Rate
(IN/OUT)
Size of
Switch Matrix
2.048 Mb/s 1,024 - Channel Switch
4.096 Mb/s 2,048 - Channel Switch
8.192 Mb/s 4,096 - Channel Switch
MT90823
#4
Figure 6 - Switch Matrix with Serial Stream at Various Bit Rates
STi0
STi1
STi2
MT90823
Frame Alignment
Evaluation circuit
STo[0:15]
STi15
External
Mux
FE
input
CLK
FP
FP STi0
FP STi1
Central
Timing Source
FP STi2
FP STi15
Note:
1. Use the external mux to select one of the serial frame pulses.
2. To start a measurement cycle, set the Start Frame Evaluation (SFE) bit in the IMS register low for at least 1 frame.
3. Frame evaluation starts when the SFE bit is changed from low to high.
4. Two frames later, the Complete Frame Evaluation (CFE) bit of the Frame Alignment Register (FAR) changes from low to
high to signal the CPU that a valid offset measurement is ready to be read from bit [11:0] of the FAR register.
5. The SFE bit must be set to zero before a new measurement cycle started.
Figure 7 - Serial Input Frame Alignment Evaluation for Various Frame Pulses
21
MT90823 CMOS
Wide Frame Pulse (WFP) Frame Alignment
Mode
x 4,096 channel switch modules. Figure 6 shows the
implementation of the individual 4,096 x 4,096
channel switch modules from four MT90823 devices.
When the device is in the wide frame pulse mode
and if the input data streams are sampled at 3/4 bit
time, the device can operate in the HMVIP and
MVIP-90 environment. When input data streams are
sampled at half-bit time as specified in the HMVIP
and MVIP-90 standard, the device can only operate
with data rate of 2 Mb/s. Refer to the ST-BUS output
Figure 10 shows an eight-stream trunk card using
MT8986 Multi-rate Digital Switches to concentrate
32-channel 2.048 Mb/s ST-BUS (DSTi and DSTo)
streams at each E1/T1 trunk onto four 128-channel
8.192 Mb/s streams.
delay parameter, t
Electrical Characteristic table.
, as specified in the AC
SOD
The DACS switching matrix that formerly required
256 MT8986 devices in a square (16 x 16)
configuration can now be provided by 64 MT8986
and 16 MT90823 devices (see Figure 8).
The MT90823 is designed to accept a common
frame pulse F0i, the 4.096 MHz and 16.384 MHz
clocks required by the HMVIP standards. To enable
the Wide Frame Pulse Frame Alignment Mode, the
WFPS pin has to be set to HIGH and the DR1 and
DR0 bits set for 8.192Mb/s data rate operation.
Digital Access Cross-Connect System
Figure 8 illustrates the use of MT90823 devices to
construct a 256 E1/T1 Digital Access Cross- connect
System (DACS). The system consists of 32 trunk
cards each having eight E1 or T1 trunk interfaces for
a total of 256 trunks. Each trunk card uses two
MT8986 Multi-rate Digital Switches. The central
switching block uses 16 MT90823 devices.
The block diagram at Figure 9 shows how an 8,192 x
8,192 channel switch can be constructed from 4,096
Each line represents a stream
TC0
that consists of
E1
E1
128 channels at 8.192Mb/s
0
8 x E1/T1
Trunk Card
7
8,192 x 8,192 channel
Switch Matrix
TC1
E1
8
8 x E1/T1
Trunk Card
E1
15
Sixteen MT90823
(8 Mb/s mode)
64 input streams
x
64 output streams
(See Figure 9)
TC31
E1
E1
247
8 x E1/T1
Trunk Card
(Figure 10)
255
Figure 8 - 256 E1/T1 Digital Access Cross-Connect System (DACS)
22
CMOS MT90823
32 Streams
IN
4,096 x 4,096
Switch Matrix
(Figure 6)
4,096 x 4,096
Switch Matrix
(Figure 6)
32 Streams
OUT
32 Streams
4,096 x 4,096
Switch Matrix
(Figure 6)
4,096 x 4,096
Switch Matrix
(Figure 6)
32 Streams
Figure 9 - 8,192 x 8,192 Channel Switch Matrix
DSTo
DSTi
STi0
E1
E1
E1/T1 Trunk 0
MT8986
2 Mb/s
to
0
STi1
STo0
STo1
256-channel out
DSTo
DSTi
8 Mb/s
STi7
(8.192 Mb/s per channel)
E1/T1 Trunk 1
1
STo0
STo1
MT8986
8 Mb/s
to
STi0
STi1
256-channel in
DSTo
DSTi
E1
E1/T1 Trunk 7
2 Mb/s
7
STo7
(8.192 Mb/s per channel)
Figure 10 - Trunk Card Block Diagram
23
MT90823 CMOS
Absolute Maximum Ratings*
Parameter
Sym
Min
Max
Units
1
2
3
4
5
6
Supply Voltage
V
-0.3
5.0
V
V
DD
Voltage on any 3.3V Tolerant pin I/O (other than supply pins)
Voltage on any 5V Tolerant pin I/O (other than supply pins)
Continuous Current at digital outputs
V
VSS - 0.3
VSS - 0.3
V
+ 0.3
DD
I
V
5.5
20
V
I
I
mA
W
°C
o
Package power dissipation (PLCC & PQFP)
Storage temperature
P
T
1
D
- 65
+125
S
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Operating Temperature
Positive Supply
TOP
VDD
VIH
-40
3.0
+85
3.6
°C
V
Input High Voltage
0.7VDD
VDD
5.5
V
400mV noise margin
400mV noise margin
Input High Voltage on 5V Tolerant
Inputs
VIH
V
5
Input Low Voltage
VIL
VSS
0.3VDD
V
DC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Sym
Min
Typ
Max
Units Test Conditions
1
@ 2 Mb/s
12
20
45
15
26
70
mA
Supply Current
I
Output unloaded
DD
@ 4 Mb/s
@ 8 Mb/s
mA
mA
V
I
N
P
U
T
S
2
3
4
Input High Voltage
Input Low Voltage
V
0.7VDD
IH
V
0.3VDD
V
IL
Input Leakage (input pins)
Input Leakage (with pull-up or
pull-down)
I
I
15
50
µA
µA
IL
0≤<V≤V
See
DD
BL
Note 1
5
6
7
8
Input Pin Capacitance
Output High Voltage
Output Low Voltage
C
10
pF
V
I
V
0.8VDD
I
I
= -10mA
= 10mA
OH
OH
OL
O
U
T
P
U
T
V
0.4
5
V
OL
OZ
High Impedance Leakage
I
µA
0 < V < V
Note 1
See
DD
S
9
Output Pin Capacitance
C
10
pF
O
Note:
1. Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
CMOS Threshold
Sym
Level
Units
Conditions
1
2
3
V
0.5VDD
0.7VDD
0.3VDD
V
V
V
CT
Rise/Fall Threshold Voltage High
Rise/Fall Threshold Voltage Low
V
HM
V
LM
24
CMOS MT90823
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic
Sym
Min
Typ
Max
Units
Notes
tFPW
1
Frame pulse width (ST-BUS, GCI)
Bit rate = 2.048 Mb/s
26
26
26
295
145
80
ns
ns
ns
WFPS Pin = 0
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
tFPS
tFPH
tCP
2
3
4
Frame Pulse Setup time before
CLK falling (ST-BUS or GCI)
5
ns
WFPS Pin = 0
WFPS Pin = 0
Frame Pulse Hold Time from CLK
falling (ST-BUS or GCI)
10
ns
CLK Period
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
190
110
55
300
150
70
ns
ns
ns
WFPS Pin = 0
WFPS Pin = 0
WFPS Pin = 0
tCH
5
6
CLK Pulse Width High
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
85
50
20
150
75
40
ns
ns
ns
tCL
CLK Pulse Width Low
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
85
50
20
150
75
40
ns
ns
ns
tr, tf
7
8
Clock Rise/Fall Time
10
ns
ns
tHFPW
Wide frame pulse width
Bit rate = 8.192 Mb/s
195
5
295
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
WFPS Pin = 1
tHFPS
tHFPH
tHCP
9
Frame Pulse Setup Time before
HCLK falling
150
150
300
150
ns
ns
ns
ns
10 Frame Pulse Hold Time from
HCLK falling
10
190
85
11 HCLK (4.096MHz) Period
Bit rate = 8.192 Mb/s
tHCH
12 HCLK (4.096MHz) Pulse Width
High
Bit rate = 8.192 Mb/s
tHCL
13 HCLK (4.096MHz) Pulse Width
Low
85
150
ns
WFPS Pin = 1
Bit rate = 8.192 Mb/s
tHr, tHf
tDIF
14 HCLK Rise/Fall Time
10
10
ns
ns
15 Delay between falling edge of
HCLK and falling edge of CLK
-10
WFPS Pin = 0 or 1
25
MT90823 CMOS
AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes
Characteristic
Sti Set-up Time
Sym
tSIS
Min
Typ
Max
Units
Test Conditions
1
2
3
0
ns
ns
tSIH
Sti Hold Time
10
tSOD
Sto Delay - Active to Active
30
40
ns
ns
CL=30pF
CL=200pF
4
5
6
STo delay - Active to High-Z
Sto delay - High-Z to Active
t
t
32
32
32
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
RL=1K, CL=200pF, See Note 1
DZ
ZD
Output Driver Enable (ODE)
Delay
t
ns
ODE
7
CSTo Output Delay
t
30
40
ns
ns
CL=30pF
CL=200pF
XCD
Note:
1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
t
FPW
F0i
V
CT
t
t
CH
t
t
t
t
CP
FPS
r
FPH
CL
V
V
HM
TT
LM
CLK
V
t
t
SOD
f
Bit 0, Last Ch (Note1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
STo
V
CT
t
t
SIS
SIH
STi
Bit 0, Last Ch (Note1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
V
CT
Note 1:
2.048 Mb/s mode, last channel = ch 31,
4.196 Mb/s mode, last channel = ch 63,
8.192 Mb/s mode, last channel = ch 127.
Figure 11 - ST-BUS Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s
or 8.192 Mb/s, when WFPS pin = 0.
26
CMOS MT90823
t
FPW
F0i
V
CT
t
t
CH
t
t
t
CP
FPS
FPH
t
r
CL
V
V
V
HM
CT
LM
CLK
t
SOD
t
f
Bit 7, Last Ch (Note1)
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
Bit 2, Channel 0
STo
V
CT
CT
t
t
SIS
SIH
STi
Bit 7, Last Ch (Note1)
Bit 0, Channel 0
Bit 1, Channel 0
V
Note 1:
2Mb/s mode, last channel = ch 31,
4Mb/s mode, last channel = ch 63,
8Mb/s mode, last channel = ch 127
Figure 12 - GCI Timing at 2.048 Mb/s and High Speed Serial Interface
at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0
t
HFPW
t
t
HFPH
HFPS
V
CT
F0i
t
HCP
t
t
HCH
HCL
HCLK
V
V
V
HM
CT
LM
4.096MHz
t
t
DIF
Hf
t
CP
Hr
t
t
t
CL
t
r
CH
CLK
16.384MHz
V
CT
t
t
SOD
f
V
V
Bit 1, Ch 127
Bit 0, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
Bit 4, Ch 0
STo
STi
CT
t
SIS
t
SIH
Bit 1, Ch 127
Bit 0, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
Bit 4, Ch 0
CT
Figure 13 - WFP Bus Timing for High Speed Serial Interface (8.192Mb/s), when WFPS pin = 1
Note:
1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
27
MT90823 CMOS
CLK
V
V
CT
CT
(ST-BUS or)
(WFPS mode)
V
CT
ODE
STo
t
t
ODE
ODE
CLK
(GCI mode)
V
Valid Data
HiZ
HiZ
CT
t
DZ
V
HiZ
Valid Data
HiZ
STo
STo
CT
Figure 15 - Output Driver Enable (ODE)
t
ZD
V
Valid Data
CT
t
XCD
V
CSTo
CT
Figure 14 - Serial Output and External Control
28
CMOS MT90823
AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1)
Characteristics
ALE pulse width
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
t
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALW
Address setup from ALE falling
Address hold from ALE falling
RD active after ALE falling
Data setup from DTA Low on Read
CS hold after RD/WR
t
ADS
ADH
t
3
t
3
ALRD
t
5
C =150pF
L
DDR
t
5
CSRW
RD pulse width (fast read)
CS setup from RD
t
45
0
RW
t
CSR
DHR
Data hold after RD
t
10
20
C =150pF, R =1K,
L
L
Note 1.
10 WR pulse width (fast write)
11 WR delay after ALE falling
12 CS setup from WR
t
45
3
ns
ns
ns
ns
ns
ns
WW
t
ALWR
t
0
CSW
DSW
SWD
DHW
13 Data setup from WR (fast write)
14 Valid Data Delay on write (slow write)
15 Data hold after WR inactive
t
t
20
122
t
5
16 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory @ 2Mb/s
@ 4Mb/s
t
AKD
43/43
ns
ns
ns
ns
C =150pF
L
760/750
400/390
220/210
C =150pF
L
C =150pF
L
@ 8Mb/s
C =150pF
L
17 Acknowledgment Hold Time
t
22
ns
C =150pF, R =1K,
AKH
L
L
Note 1.
Note:
1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
t
ALW
V
V
CT
ALE
t
t
ADS
ADH
AD0-AD7
D8-D15
HiZ
HiZ
DATA
HiZ
ADDRESS
CT
t
t
ALRD
CSRW
CS
RD
V
CT
t
t
t
CSR
RW
V
CT
CT
t
DHR
WW
V
WR
t
CSW
t
DHW
t
SWD
t
DSW
t
t
ALWR
DDR
t
AKH
DTA
V
CT
t
AKD
Figure 16 - Multiplexed Bus Timing (Mode 1)
29
MT90823 CMOS
AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2)
Characteristics
AS pulse width
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
t
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ASW
Address setup from AS falling
Address hold from AS falling
Data setup from DTA Low on Read
CS hold after DS falling
t
ADS
ADH
DDR
t
3
t
5
C =150pF
L
t
0
CSH
CS setup from DS rising
t
0
CSS
Data hold after write
t
5
DHW
Data setup from DS -Write (fast
write)
t
20
DWS
9
Valid Data Delay on write (slow write)
t
t
122
20
ns
ns
ns
ns
SWD
RWS
RWH
10 R/W setup from DS rising
11 R/W hold after DS falling
12 Data hold after read
60
5
t
t
10
C =150pF, R =1K,
DHR
L
L
Note 1
13 DS delay after AS falling
t
10
ns
DSH
14 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory @ 2Mb/s
@ 4Mb/s
t
AKD
43/43
ns
ns
ns
ns
C =150pF
L
760/750
400/390
220/210
C =150pF
L
C =150pF
L
@ 8Mb/s
C =150pF
L
15 Acknowledgment Hold Time
t
22
ns
C =150pF, RL=1K,
AKH
L
Note 1
Note 1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
DS
V
CT
t
RWS
t
RWH
R/W
V
CT
t
t
DSH
ASW
V
CT
AS
t
t
t
ADS
t
DWS
ADH
DHW
t
SW
AD0-AD7
D8-D15
WR
DATA
V
HiZ
HiZ
HiZ
ADDRESS
CT
t
DHR
AD0-AD7
D8-D15
RD
DATA
V
HiZ
ADDRESS
CT
t
CSH
t
CSS
V
CS
CT
t
t
AKH
DDR
t
AKD
DTA
V
CT
Figure 17 - Multiplexed Bus Timing (Mode2)
30
CMOS MT90823
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
t
0
10
2
ns
ns
ns
ns
ns
ns
CSS
t
RWS
t
ADS
CSH
RWH
t
0
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
t
2
t
2
ADH
DDR
DHR
t
2
ns C =150pF
L
t
10
20
ns C =150pF, R =1K
L
L
Note 1
9
Data setup on write (fast write)
t
t
0
5
ns
ns
ns
DSW
SWD
DHW
10 Valid Data Delay on write (slow write)
11 Data hold on write
122
t
12 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory @ 2Mb/s
@ 4Mb/s
t
AKD
43/43
ns C =150pF
L
760/750
400/390
220/210
ns C =150pF
L
ns C =150pF
L
@ 8Mb/s
ns C =150pF
L
13 Acknowledgment Hold Time
t
22
ns C =150pF, RL=1K,
AKH
L
Note 1
Note:
1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
V
DS
CS
CT
t
t
CSH
CSS
V
CT
t
t
RWH
RWS
V
CT
R/W
t
t
ADS
ADH
V
VALID ADDRESS
CT
A0-A7
t
DHR
AD0-AD7
D8-D15
READ
V
VALID READ DATA
CT
t
t
DHW
DSW
t
SWD
AD0-AD7
D8-D15
WRITE
V
VALID WRITE DATA
CT
t
DDR
V
CT
DTA
t
AKD
t
AKH
Figure 18 - Motorola Non-Multiplexed Bus Timing
31
Package Outlines
Pin #1 Corner
Ø1.00(3X) REF.
1
2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
Ø
0.75 ± 0.15 (169X)
J
13 12 11 10 9
8
7
6
5 4 3 2 1
K
L
M
A
B
C
D
E
F
N
3.00*45 ° (4x)
20.00 REF
G
H
J
K
L
M
N
B
1.50
18.00
30 ° Typ.
A
23.00 ± 0.20
C
Seating Plane
Note: All governing dimensions are in millimetres for design purposes
Ball Gate Array
120-BGA
144-BGA
160-BGA
MT90823
MT90863
MT90826
Package Outlines
F
A
G
D
1
D
2
D
H
E
E
1
e: (lead coplanarity)
A
Notes:
1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
I
E
2
4) For D & E add for allowable Mold Protrusion 0.010"
20-Pin
28-Pin
44-Pin
68-Pin
84-Pin
Dim
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.200
(5.08)
0.165
(4.20)
0.200
(5.08)
A
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.130
(3.30)
0.090
(2.29)
0.130
(3.30)
A1
0.385
0.395
0.485
0.495
0.685
0.695
0.985
0.995
1.185
1.195
D/E
(9.78) (10.03) (12.32) (12.57) (17.40) (17.65) (25.02) (25.27) (30.10) (30.35)
0.350 0.356 0.450 0.456 0.650 0.656 0.950 0.958 1.150 1.158
(8.890) (9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413)
D1/E1
D2/E2
0.290
(7.37)
0.330
(8.38)
0.390
0.430
0.590
0.630
0.890
0.930
1.090
1.130
(9.91) (10.92) (14.99) (16.00) (22.61) (23.62) (27.69) (28.70)
0
0.004
0
0.004
0.032
0
0.004
0.032
0
0.004
0.032
0
0.004
0.032
e
F
0.026
0.032
0.026
0.026
0.026
0.026
(0.661) (0.812) (0.661) (0.812) (0.661) (0.812) (0.661) (0.812) (0.661) (0.812)
0.013 0.021 0.013 0.021 0.013 0.021 0.013 0.021 0.013 0.021
(0.331) (0.533) (0.331) (0.533) (0.331) (0.533) (0.331) (0.533) (0.331) (0.533)
G
H
I
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.020
(0.51)
0.020
(0.51)
0.020
(0.51)
0.020
(0.51)
Plastic J-Lead Chip Carrier - P-Suffix
General-10
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