MT90826 [ZARLINK]
Quad Digital Switch; 四数字开关
| 型号： | MT90826 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Quad Digital Switch |
| 文件： | 总46页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT90826
Quad Digital Switch
Data Sheet
August 2005
Features
•
•
•
•
•
4,096 × 4,096 channel non-blocking switching at
Ordering Information
MT90826AL 160 Pin MQFP
MT90826AG 160 Ball PBGA
8.192 or 16.384 Mbps
Trays
Trays
Trays
Per-channel variable or constant throughput
delay
MT90826AV
144 Ball LBGA
Accepts 32 ST-BUS streams of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps
MT90826AL1 160 Pin MQFP* Trays
*Pb Free Matte Tin
-40°C to +85°C
Split Rate mode provides a rate conversion option
to convert data from one rate to another rate
Applications
Automatic frame offset delay measurement for
ST-BUS input streams
Per-stream input delay programming
•
•
•
•
•
•
Medium switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
WAN access system
Wireless base stations
•
•
•
•
Per-stream output advancement programming
Per-channel high impedance output control
Bit Error Monitoring on selected ST-BUS input
and output channels.
•
•
•
•
Per-channel message mode
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
3.3 V local I/O with 5 V tolerant inputs and TTL
compatible outputs
V
V
ODE
TMS TDI TDO TCK TRST
Test Port
RESET
DD
SS
Parallel
to
Serial
to
STi0/FEi0
STo0
Output
MUX
STi1/FEi1
STo1
Multiple Buffer
Data Memory
•
•
Serial
•
Parallel
•
•
Converter
•
Converter
STi31/FEi31
STo31
Connection
Memory
Internal
Registers
Timing Unit
Microprocessor Interface
PLLV
PLLV
CLK F0i
SS
DS CS R/W A13-A0 DTA
D15-D0
DD
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT90826
Data Sheet
Description
The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,096 x 4,096 channels at a serial bit rate
of 8.192 Mbps or 16.384 Mbps, 2,048 x 2,048 channels at 4.096 Mbps and 1024 x 1024 channels at 2.048 Mbps.
The device has many features that are programmable on a per stream or per channel basis, including message
mode, input offset delay and high impedance output control.
The per stream input and output delay control is particularly useful for managing large multi-chip switches with a
distributed backplane.
Operating in Split Rate mode allows rate conversion for switching between two groups of bit rate streams.
2
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Table of Contents
1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Data and Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Connection and Message Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.0 Switching Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Serial Input Frame Alignment Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Input Frame Offset Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Output Advance Offset Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Bit Error Rate Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 Delay Through the MT90826 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Variable Delay Mode (TM1=0, TM0=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Constant Delay Mode (TM1=1, TM0=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.0 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.0 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.0 Connection Memory Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.0 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.0 Initialization of the MT90826 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - 160-Pin MQFP Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3 - 160 Ball PBGA Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 - 144 Ball LBGA Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5 - Example for Frame Alignment Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6 - Examples for Input Offset Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7 - Examples for Frame Output Offset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8 - ST-BUS Timing for Stream rate of 16.384 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 9 - ST-BUS Timing for Stream rate of 8.192 Mbps when CLK = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10 - ST-BUS Timing for Stream rate of 4.096 Mbps when CLK = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . 38
Figure 11 - ST-BUS Timing for Stream rate of 4.096 Mbps when CLK = 8.192 MHz. . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12 - ST-BUS Timing for Stream rate of 2.048 Mbps when CLK = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . 39
Figure 13 - -BUS Timing for Stream rate of 2.048 Mbps when CLK = 8.192 MHz. . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
List of Tables
Table 1 - Stream Usage under Various Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2 - Output High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6 - Serial Data Rate Selections and External Clock Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7 - Frame Alignment (FAR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8 - Frame Delay Offset Register (DOS) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10 - Frame Output Offset (FOR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11 - Output Offset Bits (FD9, FD2-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12 - Bit Error Input Selection (BISR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13 - Bit Error Count (BECR) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14 - Connection Memory Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15 - SAB and CAB Bits Programming for Various Interface Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Changes Summary
The following table captures the changes from the April 2005 issue.
Page
Item
Change
26
Figure 6 “Examples for Input Offset
Delay Timing”
Clarified the mid-point sampling of the 16Mbps input
data.
30
Section 9.0 Initialization of the
MT90826
Added the 600 µs waiting time needed for the APLL
module to be stabilized before starting the next
microprocessor port access cycle.
37
37
38
AC Electrical Characteristics - Serial
Streams for ST-BUS.
Clarified the 16, 8, 4 and 2 Mbps Input Data Sampling
timing.
Figure 8 “ST-BUS Timing for Stream
rate of 16.384 Mbps”
Clarified the input data sampling position at 16 Mbps
data rate.
Figure 9 “ST-BUS Timing for Stream
rate of 8.192 Mbps when CLK =
16.384 MHz”
Added the input data sampling position at 8 Mbps data
rate.
38
39
Figure 10 “ST-BUS Timing for Stream Added the input data sampling position at 4 Mbps data
rate of 4.096 Mbps when CLK =
16.384 MHz”
rate.
Figure 12 “ST-BUS Timing for Stream Added the input data sampling position at 2 Mbps data
rate of 2.048 Mbps when CLK =
16.384 MHz”
rate.
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
113
115
111 109 107
99
97
95
93
91
89
87
85
83
81
79
119 117
105 103
101
NC
STo22
STo23
VSS
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
NC
STi9/FEi9
STi8/FEi8
VDD
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
VDD
VSS
STi24/FEi24
STi25/FEi25
STI26/FEi26
STi27/FEi27
VSS
STo7
STo6
STo5
STo4
VSS
STo24
STo25
STo26
STo27
VSS
STi7/FEi7
STi6/FEi6
STi5/FEi5
STi4/FEi4
VDD
VDD
VSS
STi28/FEi28
STi29/FEi29
STi30/FEi30
STi31/FEi31
VSS
STo3
STo2
STo1
STo0
VSS
160 Pin MQFP
STo28
STo29
STo30
STo31
VSS
STi3/FEi3
STi2/FEi2
STi1/FEi1
STi0/FEi0
ODE
28 mm x 28 mm
Pin Pitch 0.65 mm
VDD
VDD
D0
VSS
D1
CLK
D2
PLLVDD
PLLGND
NC
D3
D4
D5
NC
D6
F0i
D7
IC3
VSS
VSS
VDD
IC2
D8
RESET
IC1
NC
NC
NC
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
Figure 2 - 160-Pin MQFP Pin Connections
7
Zarlink Semiconductor Inc.
MT90826
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
1
A
STi26 STi24 STo20 STi22 STi20 STi18 STi16 STo15 STo13 STo10 STo8 STi10
STi9
B
STi27 STi25 STo21 STi23 STi21 STi19 STi17 STo14 STo12 STo11 STo9 STi11 STi8
C
D
E
F
STo26 STo25 STo23 STo19 STo18 STo17 STo16 STi15 STi14 STi13 STi12
STo7 STo5
STo6 STo4
STo27 STo24 STo22 GND
VDD
GND
GND
GND
VDD
GND
VDD
GND
VDD
VDD
GND
VDD
VDD
VDD
STo3
STo2
STo1
STo0
STi30 STi28
STi31 STi29
STo28 STo29
STo30 STo31
NC
NC
D0
VDD
VDD
VDD
GND GND
GND
STi7
STi5
STi3
STi1
NC
STi6
STi4
STi2
STi0
ODE
CLK
G
H
J
TOP VIEW
GND
D2
D4
D7
VDD
VDD
GND
GND
GND
VDD
GND GND
NC
NC
D1
D5
D3
D6
GND
VDD
GND
VDD
GND GND VDD
K
L
NC
NC
A10
A7
PLLVDD PLLGND
F0i
D8
D9
A9
A3
A2
A12
A8
A13
A11
A6
NC
NC
DTA
R/W
NC
CS
DS
NC
A0
A1
IC1
TDI
IC2
IC3
M
N
D10
D11
D12
TRST RESET
D13
D14
D15
A4
A5
TMS
TDO
TCK
1
- A1 corner is identified by metallized markings.
23mm x 23mm
Ball Pitch 1.5mm
Figure 3 - 160 Ball PBGA Pin Connections
8
Zarlink Semiconductor Inc.
MT90826
Data Sheet
PINOUT DIAGRAM: (as viewed through top of package)
A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner
1
2
3
4
5
6
7
8
9
10
11
STi11
STI10
STo7
STo6
STi7
STi4
STi3
STi0
FOi
12
STi9
STi8
STo5
STo4
STi6
STi5
STi2
STi1
CLK
IC3
A
B
C
D
E
F
STo23 STo20 STi21
STo22 STo21 STi23
STi20
STi22
STi17
STi19
STi16 STo14 STo13 STo11
STi18 STo15 STo12 STo10
STo9
STo8
STi12
STo2
STo3
STo1
STi26
STi27
STi29
STi30
STi25 STo24 STo19 STo18 STo17 STo16 STi14
STi13
GND
VDD
VDD
STi24 STo25
GND
VDD
GND
GND
GND
GND
DS
VDD
GND
GND
GND
GND
VDD
A2
VDD
GND
GND
GND
GND
VDD
A5
STi15
GND
GND
STi28 STo27 STo26
STi31 STo28
VDD
VDD
VDD
GND
D13
G
H
J
STo30 STo31 STo29
GND PLLVDD STo0
GND PLLGND ODE
D1
D3
D2
D7
D0
D4
VDD
A8
NC
A9
NC
RESET
TCK
K
L
D5
D15
D8
D11
D9
CS
IC1
D6
R/W
DTA
A13
A0
A1
A4
A10
A7
A12
A11
TDO
TDI
IC2
M
D10
D12
D14
A3
A6
TMS
TRST
Figure 4 - 144 Ball LBGA Pin Connections
9
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Pin Description
Pin # MQFP
Pin # PBGA
Pin # LBGA
Name
Description
12,22,33,54, D5,D6,D7,D8,D9,
D5,D6,D7,E9,
F4,F9,G4,H4,
J6,J7,J8
VDD
+3.3 Volt Power Supply.
66,77,90,101,
112,125,136,
147,157
E4,E10,F4,
F10,G4,G10,
H4,J4,J10,K5,
K6,K7
11,21,32,45,
53,60,65,71,
76,84,89,95,
100,106,111,
117,124,130,
135,141,146,
156
D4,D10,E5,E6,
E7,E8,E9,F5,
F9,G5,G9,H5,
H9,H10,J5,J6,
J7,J8,J9,K4
D4,D9,E5,E6,
E7,E8,F5,F6,
F7,F8,G5,G6,
G7,G8,H5,H6,
H7,H8,J4
Vss
Ground.
34
35
36
N11
M11
N12
M10
M11
L11
TMS
TDI
Test Mode Select (3.3 V Input with
Internal pull-up). JTAG signal that
controls the state transitions of the TAP
controller. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data In (3.3 V Input with
Internal pull-up). JTAG serial test
instructions and data are shifted in on
this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
Test Serial Data Out (3.3 V Output).
JTAG serial data is output on this pin
on the falling edge of TCK. This pin is
held in high impedance state when
JTAG scan is not enabled.
37
38
N13
M12
L10
TCK
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test
logic.
M12
TRST
Test Reset (3.3 V Input with internal
pull-up). Asynchronously initializes the
JTAG TAP controller by putting it in the
Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not
driven. This pin should be pulsed low
on power-up, or held low, to ensure that
the device is in the normal functional
mode.
42
43
L11
K11
K10
IC1
Internal Connection 1 (3.3 V Input
with internal pull-down). Connect to
V
SS for normal operation.
M13
RESET
Device Reset (5 V Tolerant Input).
This input (active LOW) puts the device
in its reset state which clears the
device internal counters and registers.
10
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Pin Description (continued)
Pin # MQFP
Pin # PBGA
Pin # LBGA
Name
Description
44
L12
L12
K12
J11
IC2
Internal Connection 2 (3.3 V Input
with internal pull-down). Connect to
VSS for normal operation.
46
47
L13
K12
IC3
F0i
Internal Connection 3 (3.3 V Input
with internal pull-down). Connect to
VSS for normal operation.
Master Frame Pulse (5 V Tolerant
Input). This input accepts a 122 ns or
60 ns wide negative frame pulse. The
CPLL bit in the control register
determines the usage of the frame
pulse width. See Table 6 for details.
50
51
K10
K9
H9
G9
PLLGND
PLLVDD
Phase Lock Loop Ground.
Phase Lock Loop Power Supply.
3.3 V
52
K13
J12
CLK
Master Clock (5 V Tolerant Input).
Serial clock for shifting data in/out on
the serial streams. This pin accepts a
clock frequency of 8.192 MHz or
16.384 MHz. The CPLL bit in the
control register determines the usage
of the clock frequency. See Table 6 for
details.
55
J13
H10
ODE
Output Drive Enable (5 V Tolerant
Input). This is the output-enable
control pin for the STo0 to STo31 serial
outputs. See Table 2 for details.
56
57
H13
H12
H11
H12
STi0/FEi0,
STi1/FEi1
Serial Input Streams 0 to 31 and
Frame Evaluation Inputs 0 to 31 (5 V
Tolerant Inputs). Serial data input
streams. These streams may have
data rates of 2.048, 4.096, 8.192 or
16.384 Mbps, depending upon the
value programmed at bits DR0 - DR2 in
the control register. In the frame
evaluation mode, they are used as the
frame evaluation inputs.
58
G13
G12
STi2/FEi2
59
G12
G11
STi3/FEi3
67-70
78,79
82,83
91-94
102-105
113-116
126-129
137-140
F13,F12,E13,E12
B13,A13
F11,F12,E12,E11
B12,A12
STi4-7/FEi4-7
STi8-9/FEi8-9
A12,B12
B11,A11
STi10-11/FEi10-11
STi12-15/FEi12-15
STi16-19/FEi16-19
STi20-23/FEi20-23
STi24-27/FEi24-27
STi28-31/FEi28-31
C11,C10,C9,C8
A7,B7,A6,B6
A5,B5,A4,B4
A2,B2,A1,B1
E2,F2,E1,F1
C10,C9,C8,D8
A6,A5,B6,B5,
A4,A3,B4,B3
D2,C2,C1,D1
E2,E1,F1,F2
61-64
72-75
G11,F11,E11,D11
D13,C13,D12,C12
A11,B11,A10,B10
B9,A9,B8,A8
C7,C6,C5,C4
A3,B3
G10,F10,D10,E10
D12,C12,D11,C11
B10,A10,B9,A9
B8,A8,A7,B7
C7,C6,C5,C4
A2,B2
STo0 - 3
STo4 - 7
ST-BUS Output 0 to 31 (Three-state
Outputs). Serial data output streams.
These streams may have data rates of
2.048, 4.096, 8.192, or 16.384 Mbps,
depending upon the value programmed
at bits DR0 - DR2 in the control
register.
85-88
STo8 - 11
96-99
STo12 - 15
STo16 - 19
STo20, STo21
STo22, STo23
STo24 - 27
STo28 - 31
107-110
118,119
122,123
131-134
142-145
D3,C3
B1,A1
D2,C2,C1,D1
G1,G2,H1,H2
C3,D3,E4,E3
F3,G3,G1,G2
11
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Pin Description (continued)
Pin # MQFP
Pin # PBGA
Pin # LBGA
Name
Description
148 - 153
154,155
158
G3,J1,H3,J2,J3,K1, H3,H1,H2,J1,J3,K1
D0 - 5,
D6, D7
D8
D9 - 13
D14, D15
Data Bus 0 to 15 (5 V Tolerant I/O).
These pins form the 16-bit data bus of
the microprocessor port.
K2,K3
L1
L1,J2
L2
3 - 7
L2,M1,M2,M3,N1,
N2,N3
L3,M1,K3,M2,K4
M3,K2
8,9
10
M4
M4
DTA
Data Transfer Acknowledgment
(Three-state Output). This output
pulses low from tristate to indicate that
a databus transfer is complete. A pull-
up resistor is required to hold a HIGH
level when the pin is tristated.
15
14
13
N5
N4
M5
J5
L4
K5
DS
R/W
CS
Data Strobe (5 V Tolerant Input). This
active low input works in conjunction
with CS to enable the read and write
operations.
Read/Write (5 V Tolerant Input). This
input controls the direction of the data
bus lines (D0-D15) during a
microprocessor access.
Chip Select (5 V Tolerant Input).
Active low input used by a
microprocessor to activate the
microprocessor port.
16 - 20
23 - 31
M6,N6,N7,M7,N8
N9,N10,M8,M9,L7
L8,M10,L9,L10
M5,L6,K6,M6,L7,
K7,M7,M8,K8,K9,
L8,M9,L9,L5
A0 - A4
Address 0 to 13 (5 V Tolerant Input).
These lines provide the A0 - A13
address lines when accessing the
internal registers or memories.
A5 - A13
1,2,39,40,41,48, E3,F3,H11,J11,
J9,J10
NC
No Connect. These pins have to be
49,80,81,120,
121,159,160
J12,K8,K11,
L3,L4,L5,L6.
left unconnected.
1.0 Device Overview
The MT90826 Quad Digital Switch is capable of switching up to 4,096 × 4,096 channels. The MT90826 is designed
to switch 64 Kbps PCM or N x 64 Kbps data. The device maintains frame integrity in data applications and minimum
throughput delay for voice applications on a per channel basis.
The serial input streams of the MT90826 can have a bit rate of 2.048, 4.096, 8.192 or 16.384 Mbps and are
arranged in 125 µs wide frames, which contain 32, 64,128 or 256 channels, respectively. The data rates on input
and output streams match. All inputs and outputs may be programmed to 2.048, 4.096 or 8.192 Mbps. STi0-15 and
STo0-15 may be set to 16.384 Mbps. Combinations of two bit rates, N and 2N are provided. See Table 1.
By using Zarlink’s message mode capability, the microprocessor can access input and output timeslots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other ST-
BUS devices.
To correct for backplane delays, the MT90826 has a frame offset calibration function which allows users to measure
the frame delay on any of the input streams, This information can then be used to program the input offset dealy for
each individual stream. Refer to Table 7, 8, and 9 and Figure 6. In addition, the MT90826 allow users to advance
12
Zarlink Semiconductor Inc.
MT90826
Data Sheet
the output data position up to 45ns to compensate for the output delay caused by excessive output loading
conditions. See Figure 7 “Examples for Frame Output Offset Timing”.
Serial Interface Mode
Input Stream
Input Data Rate
Output Stream
Output Data Rate
8 Mbps
16 Mbps
STi0-31
STi0-15
STi0-15
STi15-31
STi0-11
STi12-19
STi0-31
STi0-15
STi16-31
STi0-31
8 Mbps
16 Mbps
4 Mbps
8 Mbps
16 Mbps
8 Mbps
4 Mbps
2 Mbps
4 Mbps
2 Mbps
STo0-31
STo0-15
STo0-15
STo16-31
STo0-11
STo12-19
STo0-31
STo0-15
STo16-31
STo0-31
8 Mbps
16 Mbps
4 Mbps
8 Mbps
16 Mbps
8 Mbps
4 Mbps
2 Mbps
4 Mbps
2 Mbps
4 Mbps and 8 Mbps
16 Mbps and 8 Mbps
4 Mbps
2 Mbps and 4 Mbps
2 Mbps
Table 1 - Stream Usage under Various Operation Modes
ODE pin
OSB bit in Control register
OE bit in Connection Memory
ST-BUS Output Driver
0
X
1
0
1
0
X
0
1
1
X
High-Z
Per Channel High-Z
Enable
0
1
1
Enable
1
Enable
Table 2 - Output High Impedance Control
The microport interface is compatible with Motorola non-multiplexed buses. Connection memory locations may be
directly written to or read from; data memory locations may be directly read from. A DTA signal is provided to hold
the bus until the asynchronous microport operation is queued into the device.
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Location
Control Register, CR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Frame Alignment Register, FAR
Input Offset Selection Register 0, DOS0
Input Offset Selection Register 1, DOS1
Input Offset Selection Register 2, DOS2
Input Offset Selection Register 3, DOS3
Input Offset Selection Register 4, DOS4
Table 3 - Address Map for Registers (A13 = 0)
13
Zarlink Semiconductor Inc.
MT90826
Data Sheet
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
Input Offset Selection Register 5, DOS5
Input Offset Selection Register 6, DOS6
Input Offset Selection Register 7, DOS7
Frame Output Offset Register, FOR0
Frame Output Offset Register, FOR1
Frame Output Offset Register, FOR2
Frame Output Offset Register, FOR3
Unused
Unused
Unused
Bit Error Input Selection Register, BISR
Bit Error Count Register, BECR
Table 3 - Address Map for Registers (A13 = 0) (continued)
2.0 Functional Description
A functional Block Diagram of the MT90826 is shown in Figure 1.
2.1 Data and Connection Memory
For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and
stored sequentially in the data memory. Depending upon the selected operation programmed in the control register,
the usable data memory may be as large as 4,096 bytes. The sequential addressing of the data memory is
performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries
of the incoming serial data streams.
Data to be output on the serial streams may come from either the data memory or connection memory. Locations in
the connection memory are associated with particular ST-BUS output channels. When a channel is due to be
transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in
connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular
channel on a serial output stream is read from the data memory or connection memory during the previous channel
timeslot. This allows enough time for memory access and parallel-to-serial conversion.
2.2 Connection and Message Modes
In the connection mode, the addresses of the input source data for all output channels are stored in the connection
memory. The connection memory is mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 14. Once the
source address bits are programmed by the microprocessor, the contents of the data memory at the selected
address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream.
By having several output channels connected to the same input source channel, data can be broadcast from one
input channel to several output channels.
In message mode, the microprocessor writes data to the connection memory locations corresponding to the output
stream and channel number. The lower half (8 least significant bits) of the connection memory content is
14
Zarlink Semiconductor Inc.
MT90826
Data Sheet
transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame
until the data is changed by the microprocessor.
The three most significant bits of the connection memory controls the following for an output channel: message or
connection mode, constant or variable delay mode, enables/tristate the ST-BUS output drivers and bit error test
pattern enable. If an output channel is set to a high-impedance state by setting the OE bit to zero in the connection
memory, the ST-BUS output will be in a high impedance state for the duration of that channel. In addition to the per-
channel control, all channels on the ST-BUS outputs can be placed in a high impedance state by pulling the ODE
input pin low and programming the output stand by (OSB) bit in the control register to low. This action overrides the
individual per-channel programming by the connection memory bits. See Table 2 for detail.
The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The
addressing of the device internal registers, data and connection memories is performed through the address input
pins and the Memory Select (MS) bit of the control register.
2.3 Clock Timing Requirements
The master clock (CLK) frequency must be either at 8.192 MHz or 16.384 MHz for serial data rate of 2.048, 4.096,
8.192 and 16.384 Mbps; see Table 6 for the selections of the master clock frequency.
3.0 Switching Configurations
The MT90826 maximum non-blocking switching configurations is determined by the data rates selected for the
serial inputs and outputs. The switching configuration is selected by three DR bits in the control register. See Table
5 and Table 6.
8 Mbps mode (DR2=0, DR1=0, DR0=0)
When the 8 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 128
64 Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. Table 1
summarizes the switching configurations and the relationship between different serial data rates and the master
clock frequencies.
16 Mbps mode (DR2=0, DR1=0, DR0 =1)
When the 16 Mbps mode is selected, the device is configured with 16-input/16-output data streams each having
256 64 Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels.
4 Mbps and 8 Mbps mode (DR2=0, DR1=1, DR0=0)
When the 4 Mbps and 8 Mbps mode is selected, the device is configured with 32-input/32-output data streams.
STi0-15/STo0-15 have a data rate of 4 Mbps and STi16-31/STo16-31 have a data rate of 8 Mbps. This mode allows
a maximum non-blocking capacity of 3,072 x 3,072 channels. The MT90826 is capable of rate conversion, allowing
4 Mbps input to be converted to 8 Mbps output and vice versa.
16 Mbps and 8 Mbps mode (DR2=0, DR1=1, DR0=1)
When the 16 Mbps and 8 Mbps mode is selected, the device is configured with 20-input/20-output data streams.
STi0-11/STo0-11 have a data rate of 16 Mbps and STi12-19/STo12-19 have a data rate of 8 Mbps. This mode
allows a maximum non-blocking capacity of 4,096 x 4,096 channels. The MT90826 is capable of rate conversion,
allowing 16 Mbps input to be converted to 8 Mbps output and vice versa.
4 Mbps mode (DR2=1, DR1=0, DR0=0)
When the 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 64
64 Kbps channels. This mode allows a maximum non-blocking capacity of 2,048 x 2,048 channels.
15
Zarlink Semiconductor Inc.
MT90826
Data Sheet
2 Mbps and 4 Mbps mode (DR2=1, DR1=0, DR0=1)
When the 2 Mbps and 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams.
STi0-15/STo0-15 have a data rate of 2 Mbps and STi16-31/STo16-31 have a data rate of 4 Mbps. This mode
allows a maximum non-blocking capacity of 1,536 x 1,536 channels. The MT90826 is capable of rate conversion,
allowing 2 Mbps input to be converted to 4 Mbps output and vice versa.
2 Mbps mode (DR2=1, DR1=1, DR0 =0)
When the 2 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 32
64 Kbps channels. This mode allows a maximum non-blocking capacity of 1,024 x 1,024 channels.
3.1 Serial Input Frame Alignment Evaluation
The MT90826 provides the frame evaluation inputs, FEi0 to FEi31, to determine different data input delays with
respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment
register (FAR), users can select one of the thirty-two frame evaluation inputs for the frame alignment measurement.
The internal master clock, which has a fixed relationship with the CLK and F0i depending upon the mode of
operation, is used as the reference timing signal to determine the input frame delays. See Figure 5 for the signal
alignments between the internal and the external master clocks.
A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the
evaluation starts when the SFE bit in the control register is changed from low to high. Two frames later, the
complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to signal that a valid
offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be set to zero before
a new measurement cycle started.
The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse
(F0i). See Table 7 for the description of the frame alignment register.
3.2 Input Frame Offset Selection
Input frame offset selection allows the channel alignment of individual input streams, which operate at 4.096 Mbps,
8.192 Mbps or 16.384 Mbps, to be shifted against the input frame pulse (F0i). The input offset selection is not
available for streams operated at 2.048 Mbps. This feature is useful in compensating for variable path delays
caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed
switching systems.
Each input stream has its own delay offset value programmed by the input delay offset registers. Each delay offset
register can control 4 input streams. There are eight delay offset registers (DOS0 to DOS7) to control 32 input
streams. Possible adjustment can range up to +4.5 internal master clock periods forward with resolution of 0.5
internal master clock period. See Table 8 and Table 9 for frame input delay offset programming.
3.3 Output Advance Offset Selection
The MT90826 allows users to advance individual output streams up to 45 ns with a resolution of 15 ns when the
device is in 8 Mbps, 16 Mbps, 4 and 8 Mbps or 16 and 8 Mbps mode. The output delay adjustment is useful in
compensating for variable output delays caused by various output loading conditions. The frame output offset
registers (FOR0 & FOR3) control the output offset delays for each output streams via the programming of the OFn
bits.
See Table 10 and Table 11 for the frame output offset programming.
16
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Stream Address (ST0-31)
Channel Address (Ch0-255)
Stream
Channel
Location
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Location
1
1
1
1
1
1
1
1
1
.
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
1
.
0
0
0
0
1
1
1
1
0
.
0
0
1
1
0
0
1
1
0
.
0
1
0
1
0
1
0
1
0
.
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 0
Ch 1
.
.
.
.
.
.
.
.
.
.
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
Ch 62
.
.
.
.
.
.
.
Ch 63 (Note 3)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Stream 22
Stream 23
Stream 24
Stream 25
Stream 26
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
Ch 64
Ch 65
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
Ch 126
Ch 127 (Note 4)
Ch 128
Ch 129
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Ch 254
Ch 255 (Note 5)
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mbps.
3. Channels 0 to 63 are used when serial stream is at 4Mbps
4. Channels 0 to 127 are used when serial stream is at 8Mbps
5. Channels 0 to 255 are used when serial stream is at 16Mbps
Table 4 - Address Map for Memory Locations (A13 = 1)
3.4 Memory Block Programming
The MT90826 provides users with the capability of initializing the entire connection memory block in two frames.
Bits 13 to 15 of every connection memory location will be programmed with the pattern stored in bits 13 to 15 of the
control register.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register
high. When the block programming enable (BPE) bit of the control register is set to high, the block programming
data will be loaded into the bits 13 to 15 of every connection memory location. The other connection memory bits
(bit 0 to 12) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit
to zero.
3.5 Bit Error Rate Monitoring
The MT90826 allows users to perform bit error rate monitoring by sending a pseudo random pattern to a selected
ST-BUS output channel and receiving the pattern from a selected ST-BUS input channel. The pseudo random
pattern is internally generated by the device with the polynomial of 215 -1.
Users can select the pseudo random pattern to be presented on a ST-BUS channel by programming the TM0 and
TM1 bits in the connection memory. When TM0 and TM1 bits are high, the pseudo random pattern is output to the
selected ST-BUS output channel. The pseudo random pattern is then received by a ST-BUS input channel which is
selected using the BSA and BCA bits in the bit error rate input selection register (BISR). An internal bit error counter
keeps track of the error counts which is then stored in the bit error count register (BECR).
The bit error test is enabled and disabled by the SBER bit in the control register. Setting the bit from zero to one
initiates the bit error test and enables the internal bit error counter. When the bit is programmed from one to zero,
17
Zarlink Semiconductor Inc.
MT90826
Data Sheet
the device stops the bit error rate test and the internal bit error counter and transfers the error counts to the bit error
count register.
In the control register, a zero to one transition of the CBER bit resets the bit error count register and the internal bit
error counter.
The MT90826 does not recognize an input of all 1s as an error. If all 1s are being fed into the input stream and
channel, the BERT on chip BECR does not increment. This test is performed by sending defined data through the
message mode to ensure there is proper connectivity, and then running the BER test normally.
4.0 Delay Through the MT90826
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected by the TM bits in the
connection memory.
4.1 Variable Delay Mode (TM1=0, TM0=0)
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The delay through the switch can vary from 3 channels to 1 frame + 3
channels. The Variable delay is only available for odd number output streams but not for the even number output
streams. Avoid programming the TM0 and TM1 bits to zero in the connection memory when the destination output
streams are STo0, 2, 4, ..., 28 and 30.
4.2 Constant Delay Mode (TM1=1, TM0=0)
In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory
buffer. The delay through the switch is always two frames. The constant delay mode is available for all output
streams.
5.0 Microprocessor Interface
The MT90826 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is
compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0-
D15), 14-bit address bus (A0-A13) and 4 control lines (CS, DS, R/W and DTA). See Figure 16 for Motorola non-
multiplexed microport timing.
The MT90826 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and BECR registers which are read only.
For data memory read operations, two consecutive microprocessor cycles are required. The read address (A0-A13)
should remain the same for the two consecutive read cycles. The data memory content from the first read cycle
should be ignored.
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Read/Write Address:
Reset Value:
0000H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
BPD2 BPD1 BPD0
CPLL CBER SBER SFE
0
BPE MBP
MS
OSB
0
Bit
Name
Description
15 - 13 BPD2-0
Block Programming Data. These bits carry the value to be loaded into the
connection memory block whenever the memory block programming feature is
activated. After the MBP bit is set to 1 and the BPE bit is set to 1, the contents of the
bits BPD2- 0 are loaded into bit 15 to bit 13 of the connection memory. Bit 12 to bit 0 of
the connection memory are set to 0.
12
11
Unused
Must be zero for normal operation.
CPLL
PLL Input Frequency Select. When zero or one, the CLK input is 16.384 MHz and
the F0i input is 60 ns wide. When one, the CLK input is 8.192 MHz and the F0i input is
122 ns wide. See Table 6 for the usage of the clock frequency.
10
9
CBER
SBER
Clear Bit Error Rate Register. A zero to one transition in this bit resets the internal
bit error counter and the bit error count register to zero.
Start Bit Error Rate Test. A zero to one transition in this bit starts the bit error rate
test. The bit error test result is kept in the bit error count register. A one to zero
transition stops the bit error rate test and the internal bit error counter.
8
SFE
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the frame alignement (FAR) register changes from
zero to one, the evaluation procedure stops. To start another frame evaluation cycle,
set this bit to zero.
7
6
Unused
BPE
Must be zero for normal operation.
Begin Block programming Enable. A zero to one transition of this bit enables the
memory block programming function. The BPE and BPD2-0 bits have to be defined in
the same write operation. Once the BPE bit is set high, the device requires two frames
to complete the block programming. After the programming function has finished, the
BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the
BPE or MBP can be set to 0 to abort the programming operation.
When BPE = 1, the other bits in the control register must not be changed for two
frames to ensure proper operation.
5
MBP
Memory Block Program. When 1, the connection memory block programming
feature is ready to program Bit13 to Bit15 of the connection memory. When 0, feature
is disabled.
Table 5 - Control Register Bits
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Read/Write Address:
Reset Value:
0000H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
BPD2 BPD1 BPD0
CPLL CBER SBER SFE
0
BPE MBP
MS
OSB
0
Bit
Name
Description
4
MS
Memory Select. When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
For data memory read operations, two consecutive microprocessor cycles are
required. The read address should remain the same for the two consecutive read
cycles. The data memory content from the first read cycle should be ignored. The
correct data memory content will be presented to the data bus on the second read
cycle.
3
OSB
Output Stand By. This bit controls the device output drivers.
OSB bit ODE pin OE bit STo0 - 31
0
1
1
0
X
1
0
1
1
1
X
0
Enable
Enable
1
Enable
0
High impedance state
Per-channel high impedance
X
2 - 0
DR2-0
Data Rate Select. Input/Output data rate selection. See next table (Table 6) for
detailed programming.
Table 5 - Control Register Bits (continued)
CLK
(CPLL=0)
CLK
(CPLL=1)
DR2
DR1
DR0
Serial Interface Mode
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
8 Mbps
16 Mbps
4 and 8 Mbps
16 and 8 Mbps
4 Mbps
16.384 MHz
16.384 MHz
16.384 MHz
8.192 MHz
2 and 4 Mbps
2 Mbps
16.384 MHz
8.192 MHz
Table 6 - Serial Data Rate Selections and External Clock Rates
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Read/Write Address:
Reset Value:
0001H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FE4
FE3
FE2 FE1
FE0
CFE
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
15 - 11
FE4-0
Frame Evaluation Input Select. The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
10
CFE
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
9
FD9
Frame Delay Bit 9. The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 5 for clock signal alignment.
Internal Master Clock
Operation Mode
2 Mbps
C8i
C16i
C32i
4 Mbps, 2&4 Mbps
8 Mbps, 16 Mbps, 4&8 Mbps, 16&8 Mbps
8 - 0
FD8-0
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
Table 7 - Frame Alignment (FAR) Register Bits
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Frame Boundary
F0i
CLK
(16.384 MHz)
Internal
master clock
at 32 MHz
Offset Value
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
FEi Input
(FD[8:0] = 06H, frame offset of six C32i clock cycles)
(FD9 = 0, sample at internal C32i low phase)
For 8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes
F0i
CLK
(16.384 MHz)
Internal
master clock
at 16 MHz
Offset Value
0
1
2
3
4
5
6
7
8
FEi Input
(FD[8:0] = 03H, frame offset of three C16i clock cycles)
(FD9 = 0, sample at internal C16i low phase)
For 4 Mbps and 2&4 Mbps modes
F0i
CLK
(16.384 MHz)
Internal
master clock
at 8 MHz
Offset Value
0
1
2
3
4
FEi Input
(FD[8:0] = 02H, frame offset of two C8i clock cycles)
(FD9 = 1, sample at internal C8i high phase)
For 2 Mbps mode
Figure 5 - Example for Frame Alignment Measurement
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Read/Write Address:
Reset value:
02H for DOS0 register,
03H for DOS1 register,
05H for DOS3 register,
07H for DOS5 register,
09H for DOS7 register,
04H for DOS2 register,
06H for DOS4 register,
08H for DOS6 register,
0000H for all DOS registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF33
IF32
IF31
IF30
IF22
IF21
IF20
IF12
IF11
IF10
IF02
IF01
IF41
IF81
IF00
IF23
IF13
IF03
DOS0 register
IF63
IF53
IF43
IF83
IF73
IF113
IF153
IF193
IF72
IF71
IF70
IF62
IF61
IF60
IF52
IF92
IF51
IF91
IF50
IF90
IF42
IF82
IF40
IF80
DOS1 register
IF112 IF111 IF110
IF152 IF151 IF150
IF192 IF191 IF190
IF103
IF102 IF101 IF100
IF93
DOS2 register
IF142 IF141 IF140 IF133
IF132 IF131 IF130 IF123
IF122 IF121 IF120
IF162 IF161 IF160
IF143
IF183
DOS3 register
IF173
IF163
IF182 IF181 IF180
IF172 IF171 IF170
DOS4 register
IF233 IF232 IF231 IF230 IF223
IF222 IF221 IF220 IF213 IF212 IF211 IF210 IF203 IF202 IF201 IF200
DOS5 register
IF272 IF271 IF270
IF262 IF261 IF260
IF252 IF251 IF250
IF242 IF241 IF240
IF273
IF263
IF253
IF243
DOS6 register
IF313 IF312 IF311 IF310 IF303 IF302 IF301 IF300 IF293 IF292 IF291 IF290 IF283 IF282 IF281 IF280
DOS7 register
Name (Note 1)
IFn3-0
Description
Input Offset Bits 3,2,1 & 0. These four bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STi pin: i.e., to start a new frame. The input
frame offset can be selected to +2.25 external clock periods (or 4.50 internal clock
cycles) from the point where the external frame pulse input signal is applied to the F0i
inputs of the device. See Table 9.
When the STi pin has a stream rate of 2.048 Mbps, the input offset cannot be adjusted
and the input offset bits have to be set to zero.
Table 8 - Frame Delay Offset Register (DOS) Bits
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Read/Write Address:
Reset value:
02H for DOS0 register,
03H for DOS1 register,
05H for DOS3 register,
07H for DOS5 register,
09H for DOS7 register,
04H for DOS2 register,
06H for DOS4 register,
08H for DOS6 register,
0000H for all DOS registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF33
IF32
IF31
IF30
IF22
IF21
IF20
IF12
IF11
IF10
IF02
IF01
IF41
IF81
IF00
IF23
IF13
IF03
DOS0 register
IF73
IF113
IF153
IF193
IF72
IF71
IF70
IF63
IF62
IF61
IF60
IF53
IF52
IF92
IF51
IF91
IF50
IF90
IF43
IF83
IF42
IF82
IF40
IF80
DOS1 register
IF112 IF111 IF110
IF152 IF151 IF150
IF192 IF191 IF190
IF103
IF143
IF183
IF102 IF101 IF100
IF93
DOS2 register
IF142 IF141 IF140 IF133
IF132 IF131 IF130 IF123
IF122 IF121 IF120
IF162 IF161 IF160
DOS3 register
IF173
IF163
IF182 IF181 IF180
IF172 IF171 IF170
DOS4 register
IF233 IF232 IF231 IF230 IF223
IF222 IF221 IF220 IF213 IF212 IF211 IF210 IF203 IF202 IF201 IF200
DOS5 register
IF272 IF271 IF270
IF262 IF261 IF260
IF252 IF251 IF250
IF242 IF241 IF240
IF273
IF263
IF253
IF243
DOS6 register
IF313 IF312 IF311 IF310 IF303 IF302 IF301 IF300 IF293 IF292 IF291 IF290 IF283 IF282 IF281 IF280
DOS7 register
Name (Note 1)
Description
Note 1: n denotes a STi stream number from 0 to 31.
Table 8 - Frame Delay Offset Register (DOS) Bits (continued)
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Measurement Result from
Frame Delay Bits
Corresponding Input Offset Bits
Input Stream
Offset
FD9
1
FD2
0
FD1
0
FD0
0
IFn3
0
IFn2
0
IFn1
0
IFn0
0
No internal master clock shift
(Default)
+ 0.5 internal master clock shift
+ 1.0 internal master clock shift
+ 1.5 internal master clock shift
+ 2.0 internal master clock shift
+ 2.5 internal master clock shift
+ 3.0 internal master clock shift
+ 3.5 internal master clock shift
+ 4.0 internal master clock shift
+ 4.5 internal master clock shift
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0)
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
F0i
CLK
(16.384 MHz)
Internal
master clock
at 32 MHz
IFn=0000
8Mbps STi Stream
Bit 7
IFn=0100
Bit 7
8Mbps STi Stream
denotes the 3/4 point of the 8M bps bit cell
F0i
CLK
(16.384 MHz)
Internal
master clock
at 32 MHz
IFn=0000
IFn=0010
16Mbps STi Stream
Bit 7
Bit 7
16Mbps STi Stream
denotes the 1/2 point of the 16M bps bit cell
Figure 6 - Examples for Input Offset Delay Timing
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Read/Write Address:
Reset value:
000AH for FOR0 register,
000BH for FOR1 register,
000CH for FOR2 register,
000DH for FOR3 register,
0000H for all FOR registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF71
OF70
OF61
OF60
OF51
OF50
OF41
OF40
OF31
OF30
OF21
OF20
OF11
OF10
OF01
OF00
FOR0 register
OF151 OF150 OF141 OF140 OF131 OF130 OF121 OF120 OF111 OF110 OF101 OF100 OF91
OF90
OF81
OF80
FOR1 register
OF231 OF230 OF221 OF220 OF211 OF210 OF201 OF200 OF191 OF190 OF181 OF180 O171
OF170 OF161 OF160
FOR2 register
OF311 OF310 OF301 OF300 OF291 OF290 OF281 OF280 OF271 OF270 OF261 OF260 OF251 OF250 OF241 OF240
FOR3 register
Name
Description
(Note 1)
OFn1, OFn0
(n = 0 to 31)
Output Offset Bits 1 - 0. These two bits define how soon the serial interface transmitter
output the bit 0 from the STo pin. The output stream offset can be selected to -45 ns
from the point where the external frame pulse input signal is applied to the F0i inputs of
the device. See Table 11 and Figure 6.
Table 10 - Frame Output Offset (FOR) Register Bits
Corresponding Output Offset Bits
Output Stream Offset for
8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes
(Not available for 2 Mbps, 4 Mbps and 2&4 Mbps modes)
OFn1
OFn0
0
0
1
1
0
1
0
1
0 ns
-15 ns
-30 ns
-45 ns
Table 11 - Output Offset Bits (FD9, FD2-0)
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
F0i
CLK
(16.384MHz)
STo Stream
Bit 7
offset=00, (0ns)
offset=01, (-15ns)
Bit 7
STo Stream
denotes the starting point of the bit cell
Figure 7 - Examples for Frame Output Offset Timing
Read/Write Address:
Reset value:
0011H for BISR register,
0000H
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
2
1
0
BSA4
BSA3
BSA2
BSA1
BSA0 BCA7
BCA6 BCA5 BCA4 BCA3 BCA2 BCA1 BCA0
Bit
Name
Description
12 - 8
BSA4 - BSA0
BER Input Stream Address Bits. The number expressed in binary notation on
these bits refers to the input data stream which receives the pseudo random
pattern.
7 - 0
BCA7 - BCA0
BER Input Channel Address Bits. The number expressed in binary notation
on these bits refers to the input channel which receives the pseudo random
pattern.
Table 12 - Bit Error Input Selection (BISR) Register Bits
Read Address:
0012H for BECR register,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER15 BER14 BER13 BER12 BER11 BER10 BER9 BER8 BER7
BER6 BER5 BER4 BER3 BER2 BER1 BER0
Bit
15 - 0
Name
Description
BER15 - BER0
Bit Error Rate Count Bits. The number expressed in binary notation on these
bits refers to the bit error counts. The register content can be cleared by
programming the CBER bit in the control register from zero to one.
Table 13 - Bit Error Count (BECR) Register Bits
The correct data memory content will be presented to the data bus (D0-D15) on the second read cycle.
28
Zarlink Semiconductor Inc.
MT90826
Data Sheet
6.0 Memory Mapping
The address bus on the microprocessor interface selects the internal registers and memories of the MT90826. If
the A13 address input is low, then the registers are addressed by A12 to A0 according to Table 3.
If the A13 is high, the remaining address input lines are used to select location in the data or connection memory
depending upon MS bit in the control register. For data memory reads, the serial inputs are selected. For
connection memory writes, the serial outputs are selected. The destination stream address bits and channel
address bits are defined by A12 to A8 and A7 to A0 respectively. See Table 4 for the memory address mapping.
The control register controls all the major functions of the device. It selects the internal memory locations that
specify the input and output channels selected for switching and should be programmed immediately after system
power-up to establish the desired switching configuration as explained in the Switching Configurations sections.
The data in the control register consists of the block programming (BPD0-2), the DPLL control (CPLL), the clear
BER test (CBER), the start BER test (SBER), the start frame evaluation (SFE), the block programming enable
(BPE), the memory block programming bit (MBP), the memory select bits (MS), the output stand by bit (OSB) and
the data rate selection (DR0-2) bits. See Table 5 for the description of the control register bits.
7.0 Connection Memory Control
The connection memory controls the switching configuration of the device. Locations of the connection memory are
associated with particular STo output streams.
The TM0 and TM1 bits of each connection memory location allows the selection of Variable throughput delay,
Constant throughput delay, Message or Bit error test mode for all STo channels.
When the variable or constant throughput delay mode is selected, (TM1=0/1, TM0=0), the contents of the stream
address bit (SAB) and the channel address bit (CAB) of the connection memory defines the source information
(stream and channel) of the timeslot that will be switched to the STo streams.
When the message mode is selected, (TM1=0, TM0=1) , only the lower half byte (8 least significant bits) of the
connection memory is transferred to the associated STo output channel.
When the bit error test mode is selected, (TM1=1, TM0=1), the pseudo random pattern will be output on the
associated STo output channel.
See Table 14 for the description of the connection memory bits.
8.0 DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic, to indicate to the CPU that a data bus transfer is complete. When the
read or write cycle ends, this pin changes to the high-impedance state.
29
Zarlink Semiconductor Inc.
MT90826
Data Sheet
9.0 Initialization of the MT90826
During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90826 is in
the normal functional mode. A 5 K pull-down resistor can be connected to the TRST pin so that the device will
not enter the JTAG test mode during power up.
An external RC network with a time constant of five times the power supply rise time should be connected to the
RESET pin to ensure that the device is properly reset after power up.
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching
matrix. This procedure prevents two serial outputs from driving the same stream simultaneously.
Wait for 600 µs for the APLL module to be stabilized before starting the microprocessor initialization routine.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch. Users can also consider using the memory block programming feature to quickly initialize the
OE, TM0 and TM1 bits in the connection memory. When this process is complete, the microprocessor controlling
the matrices can either bring the ODE pin high or enable the OSB bit in control register to relinquish the high
impedance state control.
10.0 JTAG Support
The MT90826 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.
10.1 Test Access Port (TAP)
The Test Access Port (TAP) provides access to the many test functions of the MT90826. It consists of three input
pins and one output pin. The following pins are from the TAP.
•
•
•
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
Vdd when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
•
•
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
Resets the JTAG scan structure. This pin is internally pulled to VDD.
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
10.2 Instruction Register
In accordance with the IEEE 1149.1 standard, the MT90826 uses public instructions. The JTAG Interface contains
a three-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the
TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions:
to select the test data register that may operate while the instruction is current, and to define the serial test data
register path, which is used to shift data between TDI and TDO during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT90826 JTAG Interface contains three test data registers:
•
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90826 core logic.
•
•
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
The Device Identification Register
The device identification register is a 32-bit register with the register contain of:
MSB
LSB
0000 0000 1000 0010 0110 0001 0100 1011
The LSB bit in the device identification register is the first bit clock out.
The MT90826 scan register contains 165 bits.
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Zarlink Semiconductor Inc.
MT90826
Data Sheet
Boundary Scan Bit 0 to Bit 165
Device Pin
Tri-state
Control
Output Scan
Cell
Input
Scan Cell
F0i
0
1
2
CLK
ODE
STi0
STi1
3
4
5
6
STi2
STi3
STo0
7
9
8
STo1
10
12
14
STo2
11
13
STo3
STi4
15
16
17
18
STi5
STi6
STi7
STo4
19
21
23
25
20
22
24
26
STo5
STo6
STo7
STi8
27
28
29
30
STi9
STi10
STi11
STo8
31
33
35
37
32
34
36
38
STo9
STo10
STo11
STi12
STi13
STi14
STi15
STo12
STo13
STo14
STo15
STi16
STi17
STi18
STi19
STo16
STo17
STo18
STo19
STi20
STi21
STi22
STi23
STo20
STo21
STo22
STo23
STi24
STi25
STi26
STi27
STo24
STo25
STo26
STo27
39
40
41
42
43
45
47
49
44
46
48
50
51
52
53
54
55
57
69
61
56
58
60
62
63
64
65
66
67
69
71
73
68
70
72
74
75
76
77
78
79
81
83
85
80
82
84
86
32
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Boundary Scan Bit 0 to Bit 165
Device Pin
Tri-state
Control
Output Scan
Cell
Input
Scan Cell
STi28
STi29
STi30
STi31
STo28
ST029
ST030
STo31
87
88
89
90
91
93
95
97
92
94
96
98
D0
D1
99
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
102
105
108
111
114
117
120
123
126
129
132
135
138
141
144
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DTA1
147
147
CS
148
149
150
R/W
DS
A0
A1
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
RESETb
Note 1: DTA is an open drain output and it requires a pull-up resistor. Safe for DTA = 0. DTA cell = 1 will produce active LOW.
33
Zarlink Semiconductor Inc.
MT90826
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAB
6
SAB
3
SAB
4
SAB
2
SAB
1
SAB
0
CAB
7
CAB
5
CAB
4
CAB
3
CAB
2
CAB
1
CAB
0
TM1 TM0
OE
Bit
15-14
Name
TM1-0
Description
Mode Select Bits.
TM1 TM0
Mode Selection
0
1
0
0
0
1
Variable Throughput Delay mode (Note 1)
Constant Throughput Delay mode (Note 2)
Message mode; the contents of the connection memory are
output on the corresponding output channel and stream. Only
the lower byte (bit 7 - bit 0) will be output to the ST-BUS output
pins.
1
1
Bit Error Test mode; the pseudo random test pattern will be
output on the output channel and stream associated with this
location.
13
OE
Output Enable. This bit enables the drivers of STo pins on a per-channel
basis. When 1, the STo output driver functions normally. When 0, the STo
output driver is in a high-impedance state.
12-8
7-0
SAB4-0
CAB7-0
Source Stream Address Bits. The binary value is the number of the data
stream for the source of the connection.
Source Channel Address Bits. The binary value is the number of the channel
for the source of the connection. When the message mode is enabled, these
entire 8 bits are output on the output channel and stream associated with this
location.
Note 1: The Variable delay is only available for odd number output streams but not for the even number output streams. Avoid
programming the TM0 and TM1 bits to zero in the connection memory when the destination output streams are STo0, 2, 4,
... , 28 and 30.
Note 2: The constant delay mode is available for all output streams.
Table 14 - Connection Memory Bits
SAB4 to SAB0 Bits Used to Determine
the Source Stream of the connection
CAB Bits Used to Determine the Source
Channel of the Connection
Data Rate
8 Mbps
16 Mbps
SAB4 to SAB0 (STi0 to STi31)
SAB3 to SAB0 (STi0 to STi15)
SAB4 to SAB0 (STi0 to STi31)
SAB4 to SAB0 (STi0 to STi19)
SAB4 to SAB0 (STi0 to STi31)
SAB4 to SAB0 (STi0 to STi31)
SAB4 to SAB0 (STi0 to STi31)
CAB6 to CAB0 (128 channel/frame)
CAB7 to CAB0 (256 channel/frame)
CAB6 to CAB0 (64 or 128 channel/frame)
CAB7 to CAB0 (128 or 256 channel/frame)
CAB5 to CAB0 (64 channel/frame)
4 Mbps & 8 Mbps
16 Mbps & 8 Mbps
4 Mbps
2 Mbps & 4 Mbps
2 Mbps
CAB5 to CAB0 (32 or 64 channel/frame)
CAB4 to CAB0 (32 channel/frame)
Table 15 - SAB and CAB Bits Programming for Various Interface Mode
34
Zarlink Semiconductor Inc.
MT90826
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
2
Supply Voltage
Voltage on any 3.3 V tolerant pin I/O (other than
supply pins)
VDD
VI
-0.3
VSS - 0.3
5.0
VDD + 0.3
V
V
3
Voltage on any 5 V tolerant pin I/O (other than sup-
ply pins)
VI
VSS - 0.3
5.0
V
4
5
6
Continuous Current at digital outputs
Package power dissipation
Storage temperature
Io
PD
TS
20
1
+125
mA
W
°C
- 65
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Operating Temperature
Positive Supply
Input High Voltage
Input High Voltage on 5 V Tolerant Inputs
Input Low Voltage
Sym.
Min.
Typ.
Max.
Units Test Conditions
1
2
3
4
5
TOP
VDD
VIH
VIH
VIL
-40
3.0
0.7VDD
+85
3.6
VDD
5.5
0.3VDD
°C
V
V
V
V
VSS
DC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Supply Current
Input High Voltage
Input Low Voltage
Input Leakage (input pins)
Input Leakage (with pull-up
or pull-down)
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
IDD
VIH
VIL
64
100
mA Output unloaded
V
V
0.7VDD
I
N
P
U
T
S
0.3VDD
15
50
IIL
µA
IBL
µA
0≤<V≤VDD See Note 1
5
6
7
8
9
Input Pin Capacitance
Output High Voltage
Output Low Voltage
High Impedance Leakage
Output Pin Capacitance
CI
VOH
VOL
IOZ
10
pF
V
V
µA
pF
O
U
T
0.8VDD
IOH = 10mA
IOL = 10mA
0 < V < VDD See Note 1
0.4
5
10
P
U
T
S
CO
Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
35
Zarlink Semiconductor Inc.
MT90826
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
Sym.
Level
Units
Conditions
1
2
3
CMOS Threshold Voltage
CMOS Rise/Fall Threshold Voltage High
CMOS Rise/Fall Threshold Voltage Low
VTT
VHM
VLM
0.5VDD
0.7VDD
0.3VDD
V
V
V
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic
Sym.
Min.
Typ.
Max.
Units
CLK
1
2
3
4
5
6
7
8
9
Frame pulse width
tFPW
tFPS
tFPH
tCP
55
5
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16.384 MHz
Frame Pulse Setup time before CLK falling
Frame Pulse Hold Time from CLK falling
CLK Period
10
55
20
20
115
5
10
110
50
50
0
70
40
40
CLK Pulse Width High
CLK Pulse Width Low
tCH
tCL
Frame pulse width
tFPW8
tFPS8
tFPH8
tCP8
tCH8
tCL8
tr, tf
145
8.192 MHz
Frame Pulse Setup time before CLK falling
Frame Pulse Hold Time from CLK falling
10 CLK Period
150
75
75
11 CLK Pulse Width High
12 CLK Pulse Width Low
13 Clock Rise/Fall Time
+10
36
Zarlink Semiconductor Inc.
MT90826
Data Sheet
AC Electrical Characteristics - Serial Streams for ST-BUS
Characteristic
Sym.
Min. Typ. Max. Units Test Conditions
1
2
3
4
Input Data Sample Point (Data rate of
16 Mbps)
Input Data Sample Point (Data rate of
8 Mbps)
Input Data Sample Point (Data rate of
4 Mbps)
Input Data Sample Point (Data rate of
2 Mbps)
tIDS_16
30
ns
ns
ns
ns
tIDS_8
tIDS_4
tIDS_2
91
183
366
5
6
7
8
STi Set-up Time (Data rate of 16 Mbps)
STi Hold Time (Date rate of 16 Mbps)
STi Set-up Time (Date rate of 2, 4 or 8 Mbps)
STi Hold Time (Date rate of 2, 4 or 8 Mbps)
tSIS_16
tSIH_16
tSIS
0
8
0
8
ns
ns
ns
ns
tSIH
9
STo Delay - Active to Active
tSOD
tODE
8
30
43
35
ns
ns
ns
CL=30pF
11
CL=200pF
10 Output Driver Enable (ODE) Delay
RL=1K, CL=200pF,
See Note 1
RL=1K, CL=200pF,
See Note 1
11 STo delay - Active to High-Z
- High-Z to Active
tDZ,
tZD
35
Note: 1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C
L
L
tFPW
F0i
VTT
tFPS
tFPH
t
IDS_16
tCP
tCH
tr
tCL
VHM
VTT
VLM
CLK
(16.384 MHz)
tf
tSOD
STo
Ch0
Bit6
Ch0
Bit5
Ch0
Bit3
Ch0
Bit2
Ch255
Bit1
Ch255
Bit0
Ch0
Bit7
Ch0
Ch0
VTT
Bit4
Bit1
(16 Mbps)
tSIH_16
tSIS_16
STi
Ch0
Bit6
Ch0
Bit5
Ch0
Bit3
Ch0
Bit2
Ch255
Bit1
Ch255
Ch0
Bit7
Ch0
Bit4
Ch0
Bit1
VTT
Bit0
(16 Mbps)
Figure 8 - ST-BUS Timing for Stream rate of 16.384 Mbps
37
Zarlink Semiconductor Inc.
MT90826
Data Sheet
tFPW
F0i
VTT
tFPS
tFPH
IDS_8
tCP
tCH
tr
tCL
t
VHM
VTT
VLM
CLK
(16.384 MHz)
tSOD
tf
Bit 0, Last Channel
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
VTT
STo
STi
tSIS
tSIH
Bit 0, Last Channel
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
VTT
Figure 9 - ST-BUS Timing for Stream rate of 8.192 Mbps when CLK = 16.384 MHz
tFPW
F0i
VTT
tCP
tCH
tFPS
tr
tFPH
tCL
VHM
VTT
VLM
CLK
(16.384 MHz)
t
IDS_4
tf
tSOD
STo
Ch63 Bit 0
Ch0 Bit 7
Ch0 Bit 6
VTT
(4 Mbps)
tSIS
tSIH
STi
Ch0 Bit 7
VTT
Ch63 Bit 0
Ch0 Bit 6
(4 Mbps)
Figure 10 - ST-BUS Timing for Stream rate of 4.096 Mbps when CLK = 16.384 MHz
tFPW8
F0i
VTT
tr
tCP8
tFPS8
tFPH8
tCL8
tCH8
VHM
VTT
VLM
CLK
(8.192 MHz)
tSOD
tf
STo
Ch63 Bit 0
Ch0 Bit 7
Ch0 Bit 6
VTT
(4 Mbps)
tSIS
tSIH
STi
Ch0 Bit 7
VTT
Ch63 Bit 0
Ch0 Bit 6
(4 Mbps)
Figure 11 - ST-BUS Timing for Stream rate of 4.096 Mbps when CLK = 8.192 MHz
38
Zarlink Semiconductor Inc.
MT90826
Data Sheet
tFPW
F0i
VTT
tCP
tCH
tFPS
tr
tFPH
tCL
VHM
VTT
VLM
CLK
(16.384 MHz)
t
tf
IDS_2
tSOD
STo
Ch0 Bit 6
Ch31 Bit 0
Ch0 Bit 7
V
(2 Mbps)
TT
tSIS
tSIH
STi
Ch0 Bit 7
Ch0 Bit 6
VTT
Ch31 Bit 0
(2 Mbps)
Figure 12 - ST-BUS Timing for Stream rate of 2.048 Mbps when CLK = 16.384 MHz
F0i
VTT
tCP8
tFPS8
tFPH8
tCL8
tCH8
VHM
VTT
VLM
CLK
(8.192 MHz)
tSOD
STo
Ch31 Bit 0
Ch0 Bit 7
Ch0 Bit 6
VTT
VTT
(2 Mbps)
tSIS
tSIH
STi
Ch0 Bit 7
Ch0 Bit 6
Ch31 Bit 0
(2 Mbps)
Figure 13 - -BUS Timing for Stream rate of 2.048 Mbps when CLK = 8.192 MHz
VTT
CLK
STo
STo
tDZ
VTT
VTT
HiZ
Valid Data
HiZ
tZD
Valid Data
Figure 14 - Serial Output and External Control
39
Zarlink Semiconductor Inc.
MT90826
Data Sheet
VTT
ODE
STo
tODE
tODE
VTT
Valid Data
HiZ
HiZ
Figure 15 - Output Driver Enable (ODE)
40
Zarlink Semiconductor Inc.
MT90826
Data Sheet
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
CS setup from DS falling
Sym. Min. Typ. Max. Units Test Conditions
1
2
3
4
5
6
7
8
tCSS
tRWS
tADS
tCSH
tRWH
tADH
tDDR
tDHR
0
10
2
ns
ns
ns
ns
ns
ns
ns
ns
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
0
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
2
10
27
12
CL=150pF
20
CL=150pF, RL=1K
Note 1
9
Data setup on write (register write2)
tDSW
tSWD
0
ns
10 Valid Data Delay on write (memory write3)
For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps
modes
50
85
ns
ns
ns
For 4 Mbps, 4&2 Mbps modes
For 2 Mbps mode
185
11 Data hold on write
tDHW
tAKD
13
ns
ns
12a Acknowledgment Delay: Register RD or WR
55
CL=150pF
CL=150pF
12b Acknowledgment Delay: Memory RD or WR
For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps
modes
tAKD
100
140
240
ns
ns
ns
For 4 Mbps, 4&2 Mbps modes
For 2 Mbps mode
13 Acknowledgment Hold Time
tAKH
24
ns
CL=150pF, RL=1K,
Note 1
Note:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
2. Register write timing refers to the rising edge of DS at the end of the write cycle.
3. Memory write timing refers to the falling edge of DS at the beginning of the write cycle.
41
Zarlink Semiconductor Inc.
MT90826
Data Sheet
VTT
VTT
DS
CS
tCSH
tCSS
tRWH
tRWS
VTT
VTT
VTT
VTT
R/W
tADS
tADH
Valid Address
A0-A7
tDHR
Valid Read Data
D0-D15
READ
tDHW
tDSW
tSWD
Valid Write Data
D0-D15
WRITE
tDDR
VTT
DTA
tAKD
tAKH
Figure 16 - Motorola Non-Multiplexed Bus Timing
42
Zarlink Semiconductor Inc.
Package Code
c
Zarlink Semiconductor 2002 All rights reserved.
2
Previous package codes
1
ISSUE
ACN
213834
213740
11Dec02
15Nov02
DATE
APPRD.
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