MT90826AG [MITEL]
Quad Digital Switch; 四数字开关
| 型号： | MT90826AG |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | Quad Digital Switch |
| 文件： | 总30页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT90826
Quad Digital Switch
Advanced Information
DS5197
ISSUE 2
June 1999
Features
•
•
•
•
•
4,096 × 4,096 channel non-blocking switching
at 8.192 or 16.384 Mb/s
Ordering Information
Per-channel variable or constant throughput
delay
MT90826AL
MT90826AG
160 Pin MQFP
160 Pin PBGA
Accept ST-BUS streams of 2.048Mb/s,
4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s
-40 to +85 C
Split Rate mode allows mix of two bit rates and
rate conversions
Automatic frame offset delay measurement for
ST-BUS input and output streams
Description
The MT90826 Quad Digital Switch has a non-
blocking switch capacity of 4,096 x 4,096 channels at
a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x
2,048 channels at 4.096Mb/s and 1024 x 1024
channels at 2.048Mb/s. The device has many
features that are programmable on a per stream or
per channel basis, including message mode, input
offset delay and high impedance output control.
•
•
•
Per-stream frame delay offset programming
Per-channel high impedance output control
Bit Error Monitoring on selected ST-BUS input
and output channels.
•
•
•
•
Per-channel message mode
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
3.3V local I/O with 5V tolerant inputs and TTL
compatible outputs
The per stream input and output delay control is
particularly useful for managing large multi-chip
switches with a distributed backplane.
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Operating in Split Rate mode allows for switching
between two groups of bit rate streams.
Voice/data multiplexer
Digital cross connects
WAN access system
Wireless base stations
V
V
SS
ODE
TMS TDI TDO TCK TRST IC1 RESET
DD
Test Port
Parallel
to
Serial
to
STi0/FEi0
STi1/FEi1
STo0
STo1
•
•
Output
MUX
Multiple Buffer
Data Memory
•
•
•
Serial
Parallel
Converter
•
Converter
STi31/FEi31
STo31
Connection
Internal
Registers
Memory
Timing
Unit
Microprocessor Interface
PLLV
DD
PLLV
CLK F0i IC2 IC3 DT1 AT1
DS CS R/W A13-A0 DTA
D15-D0
SS
Figure 1 - Functional Block Diagram
1
MT90826 CMOS
Advanced Information
113
115
111 109 107
99
97
95
93
91
89
87
85
83
81
119 117
105 103
101
NC
STo22
STo23
VSS
NC
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
STi9/FEi9
STi8/FEi8
VDD
VSS
STo7
STo6
STo5
STo4
VSS
STi7/FEi7
STi6/FEi6
STi5/FEi5
STi4/FEi4
VDD
VSS
STo3
STo2
STo1
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
VDD
STi24/FEi24
STi25/FEi25
STI26/FEi26
STi27/FEi27
VSS
STo24
STo25
STo26
STo27
VSS
VDD
STi28/FEi28
STi29/FEi29
STi30/FEi30
STi31/FEi31
VSS
STo0
VSS
160 Pin MQFP
28mm x 28mm
Pin Pitch 0.65mm
STo28
STo29
STo30
STo31
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
STi3/FEi3
STi2/FEi2
STi1/FEi1
STi0/FEi0
ODE
VDD
VSS
CLK
PLLVDD
PLLGND
DT1
AT1
F0i
IC3
VSS
IC2
RESET
IC1
NC
NC
XTM2
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
Figure 2 - 160-Pin MQFP Pin Connections
2
Advanced Information
CMOS MT90826
1
2
3
4
5
6
7
8
9
10
11
12
13
1
A
STi26 STi24 STo20 STi22 STi20 STi18 STi16 STo15 ST013 STo10 STo8 STi10
STi9
B
C
D
E
F
STi27 STi25 STo21 STi23 STi21 STi19 STi17 STo14 STo12 STo11 STo9 STi11 STi8
STo26 STo25 STo23 STo19 STo18 STo17 STo16 STi15 STi14 STi13 STi12 STo7 STo5
STo27 STo24 STo22 GND
VDD
GND
GND
GND
VDD
GND
VDD
GND
VDD
VDD
GND
VDD
VDD
VDD
STo3
STo2
STo1
STo0
STo6 STo4
STi30 STi28
STi31 STi29
STo28 STo29
STo30 STo31
NC
NC
D0
VDD
VDD
VDD
GND GND
GND
STi7
STi5
STi3
STi1
AT1
STi6
STi4
STi2
STi0
ODE
CLK
G
H
J
TOP VIEW
GND
D2
D4
D7
VDD
VDD
GND
GND
GND
VDD
GND GND
DT1
XTM2
D1
D5
D3
D6
GND
VDD
GND
VDD
GND GND VDD
K
L
XTM1
NC
A10
A7
PLLVDD PLLGND
F0i
D8
D9
A9
A3
A2
A12
A8
A13
A11
A6
NC
NC
DTA
R/W
NC
CS
DS
NC
A0
A1
IC1
TDI
IC2
IC3
M
N
D10
D11
D12
TRST RESET
D13
D14
D15
A4
A5
TMS
TDO
TCK
1
- A1 corner is identified by metallized markings.
23mm x 23mm
Ball Pitch 1.5mm
Figure 3 - 160-Pin PBGA Pin Connections
Pin Description
Pin # MQFP
Pin # PBGA
Name
Description
+3.3 Volt Power Supply
12,22,33,54, D5,D6,D7,D8,D9,
V
DD
66,77,90,101,
112,125,136,
147,157
E4,E10,F4,
F10,G4,G10,
H4,J4,J10,K5,
K6,K7
11,21,32,45, D4,D10,E5,E6,E7
53,60,65,71,
V
Ground
ss
,
76,84,89,95, E8,E9,F5,F9,G5,
100,106,111, G9,H5,H9,H10,J5
117,124,130,
135,141,146,
156
,
J6,J7,J8,J9,K4
3
MT90826 CMOS
Advanced Information
Pin Description (continued)
Pin # MQFP
Pin # PBGA
Name
Description
34
N11
TMS
Test Mode Select (3.3V Input with Internal pull-up):
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up
when not driven.
35
36
M11
N12
TDI
Test Serial Data In (3.3V Input with Internal pull-up):
JTAG serial test instructions and data are shifted in on
this pin. This pin is pulled high by an internal pull-up when
not driven.
TDO
Test Serial Data Out (3.3V Output): JTAG serial data is
output on this pin on the falling edge of TCK. This pin is
held in high impedance state when JTAG scan is not
enabled.
37
38
N13
M12
TCK
Test Clock (5V Tolerant Input): Provides the clock to the
JTAG test logic.
TRST
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be
pulsed low on power-up, or held low, to ensure that the
device is in the normal functional mode.
40
41
42
43
K11
J11
L11
M13
XTM1
XTM2
IC1
PLL Test Access 1 (3.3V Input): Use for PLL testing
only. No connect for normal operation.
PLL Test Access 1 (3.3V Input): Use for PLL testing
only. No connect for normal operation.
Internal Connection 1 (3.3V Input with internal pull-
down): Connect to VSS for normal operation.
RESET
Device Reset (5V Tolerant Input): This input (active
LOW) puts the device in its reset state which clears the
device internal counters and registers.
44
46
L12
L13
IC2
IC3
Internal Connection 2 (3.3V Input with internal pull-
down): Connect to VSS for normal operation.
When IC3 pin is tied to 3.3V, this pin is used as the PLL
bypass clock input for PLL testing only.
Internal Connection 3 (3.3V Input with internal pull-
down): Connect to VSS for normal operation.
When this pin is tied to 3.3V, it enables the PLL bypass
mode for PLL testing only.
47
48
49
K12
J12
H11
F0i
AT1
DT1
Master Frame Pulse (5V Tolerant Input): This input
accepts a 60ns wide negative frame pulse.
Analog Test Access (Bidirectional): Use for PLL testing
only. No connect for normal operation.
Digital Test Access Output (Output): Use for PLL
testing only. No connect for normal operation.
50
51
K10
K9
PLLGND
PLLVDD
Phase Lock Loop Ground.
Phase Lock Loop Power Supply: 3.3V
4
Advanced Information
CMOS MT90826
Pin Description (continued)
Pin # MQFP
Pin # PBGA
Name
Description
52
K13
CLK
Master Clock (5V Tolerant Input): Serial clock for
shifting data in/out on the serial streams. This pin accepts
a clock frequency of 8.192MHz or 16.384 MHz. The CPLL
bit in the control register determines the usage of the
clock frequency. See Table 6 for details.
55
J13
ODE
Output Drive Enable (5V Tolerant Input): This is the
output-enable control pin for the STo0 to STo31 serial
outputs. See Table 2 for details.
56
57
58
H13
H12
G13
STi0/FEi0,
STi1/FEi1
STi2/FEi2
Serial Input Streams 0 to 31 and Frame Evaluation
Inputs 0 to 31 (5V Tolerant Inputs): Serial data input
streams. These streams may have data rates of 2.048,
4.096, 8.192 or 16.384 Mb/s, depending upon the value
programmed at bits DR0 - DR2 in the control register. In
the frame evaluation mode, they are used as the frame
evaluation inputs.
59
G12
STi3/FEi3
67-70
78,79
82,83
91-94
102-105
113-116
126-129
137-140
F13,F12,E13,E12
B13,A13
A12,B12
STi4-7/FEi4-7
STi8-9/FEi8-9
STi10-11/FEi10-11
C11,C10,C9,C8 STi12-15/FEi12-15
A7,B7,A6,B6
A5,B5,A4,B4
A2,B2,A1,B1
E2,F2,E1,F1
STi16-19/FEi16-19
STi20-23/FEi20-23
STi24-27/FEi24-27
STi28-31/FEi28-31
61-64
72-75
85-88
G11,F11,E11,D11
D13,C13,D12,C12
A11,B11,A10,B10
B9,A9,B8,A8
C7,C6,C5,C4
A3,B3
D3,C3
D2,C2,C1,D1
G1,G2,H1,H2
STo0 - 3
STo4 - 7
STo8 - 11
STo12 - 15
STo16 - 19
STo20, STo21
STo22, STo23
STo24 - 27
STo28 - 31
ST-BUS Output 0 to 31 (Three-state Outputs). Serial
data output streams. These streams may have data rates
of 2.048, 4.096, 8.192, or 16.384 Mb/s, depending upon
the value programmed at bits DR0 - DR2 in the control
register.
96-99
107-110
118,119
122,123
131-134
142-145
148-153
154,155
158
G3,J1,H3,J2,J3,K1,
D0 - 5,
D6,D7
D8
Data Bus 0 -15 (5V Tolerant I/O): These pins form the
16-bit data bus of the microprocessor port.
K2,K3
L1
3-7
8,9
L2,M1,M2,M3,N1,
N2,N3
D9 - 13
D14,D15
10
M4
DTA
Data Transfer Acknowledgment (Three-state Output):
This output pulses low from tristate to indicate that a
databus transfer is complete. A pull-up resistor is required
to hold a HIGH level when the pin is tristated.
15
14
13
N5
N4
M5
DS
R/W
CS
Data Strobe (5V Tolerant Input): This active low input
works in conjunction with CS to enable the read and write
operations.
Read/Write (5V Tolerant Input): This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
Chip Select (5V Tolerant Input): Active low input used
by a microprocessor to activate the microprocessor port.
16-20
23-31
M6,N6,N7,M7,N8
N9,N10,M8,M9,L7
L8,M10,L9,A10
A0 - A4
A5-A13
Address 0 - 13 (5V Tolerant Input): These lines provide
the A0 - A13 address lines when accessing the internal
registers or memories.
1,2,39,80,81,120,
121,159,160
E3,F3,K8,
L3,L4,L5,L6
NC
No Connect
5
MT90826 CMOS
Advanced Information
The microport interface is compatible with Motorola
Device Overview
non-multiplexed
buses.
Connection
memory
locations may be directly written to or read from; data
memory locations may be directly read from. A DTA
signal is provided to hold the bus until the
asynchronous microport operation is queued into the
device. For applications that require no wait states,
indirect reading and writing may be used.
Intermediary registers are directly programmed with
the write data and address, or read address. The
data in the intermediary registers is internally
transferred synchronous with the operation of the
internal state machines. Completion of the operation
is indicated by a status register flag.
The MT90826 Quad Digital Switch is capable of
switching up to 4,096 × 4,096 channels. The
MT90826 is designed to switch 64 kbit/s PCM or N x
64k bit/s data. The device maintains frame integrity
in data applications and minimum throughput delay
for voice applications on a per channel basis.
The serial input streams of the MT90826 can have a
bit rate of 2.048, 4.096, 8.192 or 16.384 Mbit/s and
are arranged in 125µs wide frames, which contain
32, 64,128 or 256 channels, respectively. The data
rates on input and output streams match. All inputs
and outputs may be programmed to 2.048, 4.096 or
8.192 Mb/s. STi0-15 and STo0-15 may be set to
16.384 Mb/s. Combinations of two bit rates, N and
2N are provided. See Table 1.
Functional Description
A functional Block Diagram of the MT90826 is shown
in Figure 1.
By using Mitel’s message mode capability, the
microprocessor can access input and output
timeslots on a per channel basis. This feature is
useful for transferring control and status information
for external circuits or other ST-BUS devices.
Data and Connection Memory
For all data rates, the received serial data is
converted to parallel format by internal serial-to-
parallel converters and stored sequentially in the
data memory. Depending upon the selected
operation programmed in the control register, the
usable data memory may be as large as 4,096 bytes.
The sequential addressing of the data memory is
performed by an internal counter, which is reset by
the input 8 kHz frame pulse (F0i) to mark the frame
boundaries of the incoming serial data streams.
The frame offset calibration function allows users to
measure the frame offset delay for streams STi0 to
STi31. The offset calibration is activated by a frame
evaluation bit in the frame evaluation register. The
evaluation result is stored in the frame evaluation
registers and can be used to program the input offset
delay for individual streams using internal frame
input offset registers.
Data to be output on the serial streams may come
from either the data memory or connection memory.
Serial Interface Mode
Input Stream
Input Data Rate
Output Stream
Output Data Rate
8 Mb/s
16 Mb/s
STi0-31
STi0-15
STi0-15
STi15-31
STi0-11
STi12-19
STi0-31
STi0-15
STi16-31
STi0-31
8 Mb/s
16 Mb/s
4 Mbs/
8 Mb/s
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
4 Mb/s
2 Mb/s
STo0-31
STo0-15
STo0-15
STo16-31
STo0-11
STo12-19
STo0-31
STo0-15
STo16-31
STo0-31
8 Mb/s
16 Mb/s
4 Mb/s
8 Mb/s
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
4 Mb/s
2 Mb/s
4 Mb/s and 8 Mb/s
16 Mb/s and 8 Mb/s
4 Mb/s
2 Mb/s and 4 Mb/s
2 Mb/s
Table 1 - Stream Usage and External Clock Rates
6
Advanced Information
CMOS MT90826
Locations in the connection memory are associated
with particular ST-BUS output channels. When a
channel is due to be transmitted on an ST-BUS
output, the data for this channel can be switched
either from an ST-BUS input in connection mode, or
from the lower half of the connection memory in
message mode. Data destined for a particular
channel on a serial output stream is read from the
data memory or connection memory during the
previous channel timeslot. This allows enough time
for memory access and parallel-to-serial conversion.
drivers and bit error test pattern enable. If an output
channel is set to a high-impedance state by setting
the OE bit to zero in the connection memory, the ST-
BUS output will be in a high impedance state for the
duration of that channel. In addition to the per-
channel control, all channels on the ST-BUS outputs
can be placed in a high impedance state by pulling
the ODE input pin low and programming the output
stand by (OSB) bit in the control register to low. This
action overrides the individual per-channel
programming by the connection memory bits. See
Table 2 for detail.
Connection and Message Modes
The connection memory data can be accessed via
the microprocessor interface through the D0 to D15
pins. The addressing of the device internal registers,
data and connection memories is performed through
the address input pins and the Memory Select (MS)
bit of the control register.
In the connection mode, the addresses of the input
source data for all output channels are stored in the
connection memory. The connection memory is
mapped in such
a
way that each location
corresponds to an output channel on the output
streams. For details on the use of the source
address data (CAB and SAB bits), see Table 18.
Once the source address bits are programmed by
the microprocessor, the contents of the data memory
at the selected address are transferred to the
parallel-to-serial converters and then onto an ST-
BUS output stream.
Clock Timing Requirements
The master clock (CLK) frequency must be either at
8.192 or 16.384MHz for serial data rate of 2.048,
4.096, 8.192 and 16.384Mb/s; see Table 6 for the
selections of the master clock frequency.
By having several output channels connected to the
same input source channel, data can be broadcasted
from one input channel to several output channels.
Switching Configurations
The MT90826 maximum non-blocking switching
configurations is determined by the data rates
selected for the serial inputs and outputs. The
switching configuration is selected by three DR bits
in the control register. See Table 5 and Table 6.
In message mode, the microprocessor writes data to
the connection memory locations corresponding to
the output stream and channel number. The lower
half (8 least significant bits) of the connection
memory content is transferred directly to the parallel-
to-serial converter. This data will be output on the
ST-BUS streams in every frame until the data is
changed by the microprocessor.
8Mb/s mode (DR2=0, DR1=0, DR0=0)
When the 8Mb/s mode is selected, the device is
configured with 32-input/32-output data streams
each having 128 64Kbit/s channels. This mode
allows a maximum non-blocking capacity of 4,096 x
4,096 channels. Table 1 summarizes the switching
configurations and the relationship between different
serial data rates and the master clock frequencies.
The three most significant bits of the connection
memory controls the following for an output channel:
message or connection mode, constant or variable
delay mode, enables/tristate the ST-BUS output
ODE pin
OSB bit in Control register
OE bit in Connection Memory
ST-BUS Output Driver
0
X
1
0
1
0
X
0
1
1
X
0
1
1
1
High-Z
Per Channel High-Z
Enable
Enable
Enable
Table 2 - Output High Impedance Control
7
MT90826 CMOS
Advanced Information
16Mb/s mode (DR2=0, DR1=0, DR0 =1)
The internal master clock, which has a fixed
relationship with the CLK and F0i depending upon
the mode of operation, is used as the reference
timing signal to determine the input frame delays.
See Figure 4 for the signal alignments between the
internal and the external master clocks.
When the 16Mb/s mode is selected, the device is
configured with 16-input/16-output data streams
each having 256 64Kbit/s channels. This mode
allows a maximum non-blocking capacity of 4,096 x
4,096 channels.
A measurement cycle is started by setting the start
frame evaluation (SFE) bit low for at least one frame.
Then the evaluation starts when the SFE bit in the
control register is changed from low to high. Two
frames later, the complete frame evaluation (CFE) bit
of the frame alignment register changes from low to
high to signal that a valid offset measurement is
ready to be read from bits 0 to 9 of the FAR register.
The SFE bit must be set to zero before a new
measurement cycle started.
4Mb/s and 8Mb/s mode (DR2=0, DR1=1, DR0=0)
When the 4Mb/s and 8Mb/s mode is selected, the
device is configured with 32-input/32-output data
streams. STi0-15/STo0-15 have a data rate of 4Mb/s
and STi16-31/STo16-31 have a data rate of 8Mb/s.
This mode allows a maximum non-blocking capacity
of 3,072 x 3,072 channels.
16Mb/s and 8Mb/s mode (DR2=0, DR1=1, DR0=1)
When the 16Mb/s and 8Mb/s mode is selected, the
device is configured with 20-input/20-output data
streams. STi0-11/STo0-11 have a data rate of 16Mb/
s and STi12-19/STo12-19 have a data rate of 8Mb/s.
This mode allows a maximum non-blocking capacity
of 4,096 x 4,096 channels.
The falling edge of the frame measurement signal
(FEi) is evaluated against the falling edge of the
frame pulse (F0i). See Table 7 for the description of
the frame alignment register.
Input Frame Offset Selection
4Mb/s mode (DR2=1, DR1=0, DR0=0)
When the 4Mb/s mode is selected, the device is
configured with 32-input/32-output data streams
each having 64 64Kbit/s channels. This mode allows
a maximum non-blocking capacity of 2,048 x 2,048
channels.
Input frame offset selection allows the channel
alignment of individual input streams, which operate
at 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, to be
shifted against the input frame pulse (F0i). The input
offset selection is not available for streams operated
at 2.048Mb/s. This feature is useful in compensating
for variable path delays caused by serial backplanes
of variable lengths, which may be implemented in
large centralized and distributed switching systems.
2Mb/s and 4Mb/s mode (DR2=1, DR1=0, DR0=1)
When the 2Mb/s and 4Mb/s mode is selected, the
device is configured with 32-input/32-output data
streams. STi0-15/STo0-15 have a data rate of 2Mb/s
and STi16-31/STo16-31 have a data rate of 4Mb/s.
This mode allows a maximum non-blocking capacity
of 1,536 x 1,536 channels.
Each input stream has its own delay offset value
programmed by the input delay offset registers. Each
delay offset register can control 4 input streams.
There are eight delay offset registers (DOS0 to
DOS7) to control 32 input streams. Possible
adjustment can range up to +4.5 internal master
clock periods forward with resolution of 1/2 internal
master clock period. See Table 8 and Table 9 for
frame input delay offset programming.
2Mb/s mode (DR2=1, DR1=1, DR0 =0)
When the 2Mb/s mode is selected, the device is
configured with 32-input/32-output data streams
each having 32 64Kbit/s channels. This mode allows
a maximum non-blocking capacity of 1,024 x 1,024
channels.
Output Advance Offset Selection
Serial Input Frame Alignment Evaluation
The MT90826 allows users to advance individual
output streams up to 45ns with a resolution of 15ns
when the device is in 8Mb/s, 16Mb/s, 4 and 8 Mb/s or
16 and 8 Mb/s mode. The output delay adjustment is
useful in compensating for variable output delays
caused by various output loading conditions. The
frame output offset registers (FOR0 & FOR3) control
the output offset delays for each output streams via
the programming of the OFn bits.
The MT90826 provides the frame evaluation inputs,
FEi0 to FEi31, to determine different data input
delays with respect to the frame pulse F0i. By using
the frame evaluation input select bits (FE0 to FE4) of
the frame alignment register (FAR), users can select
one of the thirty-two frame evaluation inputs for the
frame alignment measurement.
8
Advanced Information
CMOS MT90826
See Table 10 and Table 11 for the frame output offset
programming.
Delay Through the MT90826
The switching of information from the input serial
streams to the output serial streams results in a
throughput delay. The device can be programmed to
perform timeslot interchange functions with different
throughput delay capabilities on the per-channel
basis. For voice application, select variable
throughput delay to ensure minimum delay between
input and output data. In wideband data applications,
select constant throughput delay to maintain the
frame integrity of the information through the switch.
Memory Block Programming
The MT90826 provides users with the capability of
initializing the entire connection memory block in two
frames. Bits 13 to 15 of every connection memory
location will be programmed with the pattern stored
in bits 13 to 15 of the control register.
The block programming mode is enabled by setting
the memory block program (MBP) bit of the control
register high. When the block programming enable
(BPE) bit of the control register is set to high, the
block programming data will be loaded into the bits
13 to 15 of every connection memory location. The
other connection memory bits (bit 0 to 12) are loaded
with zeros. When the memory block programming is
complete, the device resets the BPE bit to zero.
The delay through the device varies according to the
type of throughput delay selected by the TM bits in
the connection memory.
Variable Delay Mode (TM1=0, TM0=0)
The delay in this mode is dependent only on the
combination of source and destination channels and
is independent of input and output streams.
Bit Error Monitoring
The MT90826 allows users to perform bit error
monitoring by sending a pseudo random pattern to a
selected ST-BUS output channel and receiving the
pattern from a selected ST-BUS input channel. The
pseudo random pattern is internally generated by the
Constant Delay Mode (TM1=1, TM0=0)
In this mode, frame integrity is maintained in all
switching configurations by making use of a multiple
data memory buffer.
15
device with the polynomial of 2 -1.
Microprocessor Interface
Users can select the pseudo random pattern to be
presented on a ST-BUS channel by programming the
TM0 and TM1 bits in the connection memory. When
TM0 and TM1 bits are high, the pseudo random
pattern is output to the selected ST-BUS output
channel. The pseudo random pattern is then
received by a ST-BUS input channel which is
selected using the BSA and BCA bits in the bit error
rate input register (BISR). An internal bit error
counter keeps track of the error counts which is then
stored in the bit error count register (BECR).
The MT90826 provides a parallel microprocessor
interface for non-multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed
buses. The required microprocessor signals are the
16-bit data bus (D0-D15), 14-bit address bus (A0-
A13) and 4 control lines (CS, DS, R/W and DTA).
See Figure 14 for Motorola non-multiplexed
microport timing.
The MT90826 microport provides access to the
internal registers, connection and data memories. All
locations provide read/write access except for the
data memory, DRR and BECR registers which are
read only.
The bit error test is enabled and disabled by the
SBER bit in the control register. Setting the bit from
zero to one initiates the bit error test and enables the
internal bit error counter. When the bit is
programmed from one to zero, the internal bit error
counter transfers the error counts to the bit error
count register.
For data memory read operations, two consecutive
microprocessor cycles are required. The read
address (A0-A13) should remain the same for the
two consecutive read cycles. The data memory
content from the first read cycle should be ignored.
The correct data memory content will be presented
to the data bus (D0-D15) on the second read cycle.
In the control register, a zero to one transition of the
CBER bit resets the bit error count register and the
internal bit error counter.
9
MT90826 CMOS
Advanced Information
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Control Register, CR
Frame Alignment Register, FAR
Input Offset Selection Register 0, DOS0
Input Offset Selection Register 1, DOS1
Input Offset Selection Register 2, DOS2
Input Offset Selection Register 3, DOS3
Input Offset Selection Register 4, DOS4
Input Offset Selection Register 5, DOS5
Input Offset Selection Register 6, DOS6
Input Offset Selection Register 7, DOS7
Frame Output Offset Register, FOR0
Frame Output Offset Register, FOR1
Frame Output Offset Register, FOR2
Frame Output Offset Register, FOR3
Unused
Unused
Unused
Bit Error Input Selection Register, BISR
Bit Error Count Register, BECR
Table 3 - Address Map for Registers (A13 = 0)
Stream Address (ST0-31)
Channel Address (Ch0-255)
Stream
Location
Channel
Location
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
1
1
1
1
1
.
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
1
.
0
0
0
0
1
1
1
1
0
.
0
0
1
1
0
0
1
1
0
.
0
1
0
1
0
1
0
1
0
.
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
.
.
.
.
.
.
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
.
0
0
1
1
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
0
1
0
1
.
Ch 62
Ch 63 (Note 3)
Ch 64
Ch 65
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Stream 22
Stream 23
Stream 24
Stream 25
Stream 26
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
.
Ch 126
Ch 127 (Note 4)
Ch 128
Ch 129
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Ch 254
Ch 255 (Note 5)
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4Mb/s
4. Channels 0 to 127 are used when serial stream is at 8Mb/s
5. Channels 0 to 255 are used when serial stream is at 16Mb/s
Table 4 - Address Map for Memory Locations (A13 = 1)
10
Advanced Information
CMOS MT90826
Memory Mapping
When the message mode is selected, (TM1=0,
TM0=1) , only the lower half byte (8 least significant
bits) of the connection memory is transferred to the
associated STo output channel.
The address bus on the microprocessor interface
selects the internal registers and memories of the
MT90826. If the A13 address input is low, then the
registers are addressed by A12 to A0 according to
Table 3.
When the bit error test mode is selected, (TM1=1,
TM0=1), the pseudo random pattern will be output on
the associated STo output channel.
If the A13 is high, the remaining address input lines
are used to select location in the data or connection
memory depending upon MS bit in the control
register. For data memory reads, the serial inputs
are selected. For connection memory writes, the
serial outputs are selected. The destination stream
address bits and channel address bits are defined by
A12 to A8 and A7 to A0 respectively. See Table 4 for
the memory address mapping.
See Table 17 for the description of the connection
memory bits.
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic, to
indicate to the CPU that a data bus transfer is
complete. When the read or write cycle ends, this pin
changes to the high-impedance state.
The control register controls all the major functions
of the device. It selects the internal memory
locations that specify the input and output channels
selected for switching and should be programmed
immediately after system power-up to establish the
desired switching configuration as explained in the
Frame Alignment Timing & Switching Configurations
sections.
Initialization of the MT90826
During power up, the TRST pin should be pulsed low,
or held low continuously, to ensure that the MT90826
is in the normal functional mode. A 5K pull-down
resistor can be connected to the TRST pin so that
the device will not enter the JTAG test mode during
power up.
The data in the control register consists of the block
programming bits (BPD0-2), the block programming
enable bit (BPE), the memory block programming bit
(MBP), the memory select bits (MS), the start frame
evaluation bit (SFE), the output stand by bit (OSB),
the wide frame pulse control bit (WFP) and the data
rate selection bits (DR0-2). See Table 5 for the
description of the control register bits.
After power up, the contents of the connection
memory can be in any state. The ODE pin should be
held low after power up to keep all serial outputs in a
high impedance state until the microprocessor has
initialized the switching matrix. This procedure
prevents two serial outputs from driving the same
stream simultaneously.
Connection Memory Control
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the switch. Users can also consider
using the memory block programming feature to
quickly initialize the OE, TM0 and TM1 bits in the
connection memory. When this process is complete,
the microprocessor controlling the matrices can
either bring the ODE pin high or enable the OSB bit
in control register to relinquish the high impedance
state control.
The connection memory controls the switching
configuration of the device. Locations in the
connection memory are associated with particular
STo output streams.
The TM0 and TM1 bits of each connection memory
location allows the selection of the variable
throughput delay mode, the constant throughput
delay mode, the message mode or the bit error test
mode for all STo channels.
When the variable or constant throughput delay
mode is selected, (TM1=0/1, TM0=0), the contents of
the stream address bit (SAB) and the channel
address bit (CAB) of the connection memory defines
the source information (stream and channel) of the
timeslot that will be switched to the STo streams.
11
MT90826 CMOS
Advanced Information
Read/Write Address:
Reset Value:
0000 ,
H
0000 .
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
BPD2 BPD1 BPD0
CPLL CBER SBER SFE
0
BPE MBP
MS
OSB
0
Bit
Name
Description
15-13
BPD2-0
Block Programming Data. These bits carry the value to be loaded into the connection memory
block whenever the memory block programming feature is activated. After the MBP bit is set to 1
and the BPE bit is set to 1, the contents of the bits BPD2- 0 are loaded into bit 15 to bit 13 of the
connection memory. Bit 12 to bit 0 of the connection memory are set to 0.
12
11
Unused
CPLL
Must be zero for normal operation.
PLL Input Frequency Select. When zero, the CLK input is 16.384MHz. When 1, the CLK input
is 8.192MHz or 16.384MHz. See Table 6 for the usage of the clock frequency.
10
9
CBER
SBER
Clear Bit Error Rate Register. A zero to one transition in this bit resets the internal bit error
counter and the bit error count register to zero.
Start Bit Error Rate Test. A zero to one transition in this bit starts the bit error rate test. The bit
error test result is kept in the bit error count register. A one to zero transition stops the bit error
rate test and the internal bit error counter.
8
SFE
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the frame alignement (FAR) register changes from zero to one,
the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero.
7
6
Unused
BPE
Must be zero for normal operation.
Begin Block programming Enable. A zero to one transition of this bit enables the memory
block programming function. The BPE and BPD2-0 bits have to be defined in the same write
operation. Once the BPE bit is set high, the device requires two frames to complete the block
programming. After the programming function has finished, the BPE bit returns to zero to
indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort
the programming operation.
When BPE = 1, the other bits in the control register must not be changed for two frames to
ensure proper operation.
5
4
MBP
MS
Memory Block Program. When 1, the connection memory block programming feature is ready
to program Bit13 to Bit15 of the connection memory. When 0, feature is disabled.
Memory Select. When 0, connection memory is selected for read or write operations. When 1,
the data memory is selected for read operations and connection memory is selected for write
operations. (No microprocessor write operation is allowed for the data memory.)
For data memory read operations, two consecutive microprocessor cycles are required. The
read address should remain the same for the two consecutive read cycles. The data memory
content from the first read cycle should be ignored. The correct data memory content will be
presented to the data bus on the second read cycle.
3
OSB
Output Stand By. This bit controls the device output drivers.
OSB bit ODE pin OE bit STo0 - 31
0
1
1
0
X
1
0
1
0
X
1
1
1
X
0
Enable
Enable
Enable
High impedance state
Per-channel high impedance
2 - 0
DR2-0
Data Rate Select. Input/Output data rate selection. See next table (Table 6) for detailed
programming.
Table 5 - Control Register Bits
12
Advanced Information
CMOS MT90826
CLK
(CPLL=0)
CLK
(CPLL=1)
DR2
DR1
DR0
Serial Interface Mode
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
8 Mb/s
16 Mb/s
16.384MHz
16.384MHz
4 and 8 Mb/s
16 and 8 Mb/s
4 Mb/s
16.384MHz
16.384MHz
8.192MHz
8.192MHz
2 and 4 Mb/s
2 Mb/s
Table 6 - Serial Data Rate Selections and External Clock Rates
Read/Write Address:
Reset Value:
0001 ,
H
0000 .
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FE4
FE3
FE2 FE1
FE0
CFE
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
15-11
10
FE4-0
Frame Evaluation Input Select. The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
CFE
FD9
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
9
Frame Delay Bit 9. The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 4 for clock signal alignment.
Internal Master Clock
Operation Mode
2Mb/s
C8i
C16i
C32i
4Mb/s, 2&4Mb/s
8Mb/s, 16Mb/s, 4&8Mb/s, 16&8Mb/s
8-0
FD8-0
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
Table 7 - Frame Alignment (FAR) Register Bits
13
MT90826 CMOS
Advanced Information
Frame Boundary
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
Offset Value
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
FEi Input
(FD[8:0] = 06 , frame offset of six C32i clock cycles)
H
(FD9 = 0, sample at internal C32i low phase)
For 8Mb/s, 16Mb/s, 4&8Mb/s and 16&8Mb/s modes
F0i
CLK
(16.384MHz)
Internal
master clock
at 16 MHz
Offset Value
0
1
2
3
4
5
6
7
8
FEi Input
(FD[8:0] = 03 , frame offset of three C16i clock cycles)
H
(FD9 = 0, sample at internal C16i low phase)
For 4Mb/s and 2&4Mb/s modes
F0i
CLK
(16.384MHz)
Internal
master clock
at 8MHz
Offset Value
0
1
2
3
4
FEi Input
(FD[8:0] = 02 , frame offset of two C8i clock cycles)
H
(FD9 = 1, sample at internal C8i high phase)
For 2Mb/s mode
Figure 4 - Example for Frame Alignment Measurement
14
Advanced Information
CMOS MT90826
Read/Write Address:
02 for DOS0 register,
03 for DOS1 register,
H
H
04 for DOS2 register,
05 for DOS3 register,
H
H
06 for DOS4 register,
07 for DOS5 register,
H
H
08 for DOS6 register,
09 for DOS7 register,
H
H
Reset value:
0000 for all DOS registers.
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF33
IF32
IF31
IF30
IF22
IF21
IF20
IF12
IF11
IF10
IF02
IF01
IF00
IF23
IF13
IF03
DOS0 register
IF63
IF53
IF43
IF83
IF73
IF113
IF153
IF193
IF233
IF72
IF71
IF70
IF62
IF61
IF60
IF52
IF92
IF51
IF91
IF50
IF90
IF42
IF82
IF41
IF81
IF40
IF80
DOS1 register
IF112 IF111 IF110
IF152 IF151 IF150
IF192 IF191 IF190
IF103
IF143
IF183
IF102 IF101 IF100
IF93
DOS2 register
IF142 IF141 IF140 IF133
IF132 IF131 IF130 IF123
IF122 IF121 IF120
DOS3 register
IF173
IF163
IF182 IF181 IF180
IF172 IF171 IF170
IF162
IF202
IF161 IF160
DOS4 register
IF232
IF231
IF230 IF223
IF222
IF221
IF220 IF213
IF212
IF211
IF210 IF203
IF201
IF200
DOS5 register
IF272
IF312
IF271
IF311
IF270
IF262
IF302
IF261
IF301
IF260
IF252
IF292
IF251
IF291
IF250
IF242
IF282
IF241
IF281
IF240
IF280
IF273
IF313
IF263
IF253
IF243
DOS6 register
IF310 IF303
IF300 IF293
IF290 IF283
DOS7 register
Name
(Note 1)
Description
IFn3-0
Input Offset Bits 3,2,1 & 0. These four bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STi pin: i.e., to start a new frame. The input
frame offset can be selected to +2.25 clock periods from the point where the external
frame pulse input signal is applied to the F0i inputs of the device. See Table 9.
When the STi pin has a stream rate of 2.048Mb/s, the input offset can not be adjusted
and the input offset bits have to be set to zero.
Note 1: n denotes a STi stream number from 0 to 31.
Table 8 - Frame Delay Offset Register (DOS) Bits
15
MT90826 CMOS
Advanced Information
Measurement Result from
Frame Delay Bits
Corresponding Input Offset Bits
Input Stream
Offset
FD9
1
FD2
0
FD1
0
FD0
0
IFn3
0
IFn2
0
IFn1
0
IFn0
0
No internal master clock shift
(Default)
+ 1/4 internal master clock shift
+ 1/2 internal master clock shift
+ 3/4 internal master clock shift
+ 1.00 internal master clock shift
+ 1.25 internal master clock shift
+ 1.50 internal master clock shift
+ 1.75 internal master clock shift
+ 2.00 internal master clock shift
+ 2.25 internal master clock shift
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0)
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
IFn=0000
IFn=0100
8Mb/s STi Stream
8Mb/s STi Stream
Bit 7
Bit 7
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
IFn=0000
IFn=0100
16Mb/s STi Stream
Bit 7
Bit 7
16Mb/s STi Stream
denotes the 3/4 point of the bit cell
Figure 4 - Examples for Input Offset Delay Timing
16
Advanced Information
CMOS MT90826
Read/Write Address:
000AH for FOR0 register,
000BH for FOR1 register,
000CH for FOR2 register,
000DH for FOR3 register,
0000H for all FOR registers.
Reset value:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF71
OF70
OF61
OF60
OF51
OF50
OF41
OF40
OF31
OF30
OF21
OF20
OF11
OF10
OF01
OF00
FOR0 register
OF151 OF150 OF141 OF140 OF131 OF130 OF121 OF120 OF111 OF110 OF101 OF100 OF91
OF90
OF81
OF80
FOR1 register
OF231 OF230 OF221 OF220 OF211 OF210 OF201 OF200 OF191 OF190 OF181 OF180 O171
OF170 OF161 OF160
FOR2 register
OF311 OF310 OF301 OF300 OF291 OF290 OF281 OF280 OF271 OF270 OF261 OF260 OF251 OF250 OF241 OF240
FOR3 register
Name
Description
(Note 1)
OFn1, OFn0
(n = 0 to 31)
Output Offset Bits 1 - 0. These two bits define how soon the serial interface transmitter
output the bit 0 from the STo pin. The output stream offset can be selected to -45ns from
the point where the external frame pulse input signal is applied to the F0i inputs of the
device. See Table 11 and Figure 5
Table 10 - Frame Output Offset (FOR) Register Bits
Corresponding Output Offset Bits
Output Stream Offset for
8Mb/s, 16Mb/s, 4&8Mb/s and 16&8Mb/s modes
(Not available for 2Mb/s, 4Mb/s and 2&4 Mb/s modes)
OFn1
OFn0
0
0
1
1
0
1
0
1
0ns
-15ns
-30ns
-45ns
Table 11 - Output Offset Bits (FD9, FD2-0)
F0i
CLK
(16.384MHz)
STo Stream
Bit 7
offset=00, (0ns)
Bit 7
STo Stream
offset=01, (-15ns)
denotes the starting point of the bit cell
Figure 5 - Examples for Frame Output Offset Timing
17
MT90826 CMOS
Advanced Information
Read/Write Address:
Reset value:
0011 for BISR register,
H
0000
H
15
0
14
0
13
0
12
11
10
BSA2
9
8
7
6
5
4
3
2
1
0
BSA4 BSA3
BSA1 BSA0 BCA7
BCA6 BCA5 BCA4 BCA3 BCA2 BCA1 BCA0
Bit
Name
Description
12 - 8
BSA4 - BSA0
BER Input Stream Address Bits. The number expressed in binary notation on
these bits refers to the input data stream which receives the pseudo random
pattern.
7 - 0
BCA7 - BCA0
BER Input Channel Address Bits. The number expressed in binary notation
on these bits refers to the input channel which receives the pseudo random
pattern.
Table 12 - Bit Error Input Selection (BISR) Register Bits
Read Address:
Reset value:
0012 for BECR register,
H
0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER15 BER14 BER13 BER12 BER11 BER10 BER9 BER8 BER7
BER6 BER5 BER4 WR3
WR2
WR1
WR0
Bit
15 - 0
Name
Description
BER15 - BER0
Bit Error Rate Count Bits. The number expressed in binary notation on these
bits refers to the bit error counts. The register content can be cleared by
programming the CBER bit in the control register from zero to one.
Table 13 - Bit Error Count (BECR) Register Bits
18
Advanced Information
CMOS MT90826
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAB
6
SAB
3
SAB
4
SAB
2
SAB
1
SAB
0
CAB
7
CAB CAB CAB CAB CAB CAB
TM1 TM0
OE
5
4
3
2
1
0
Bit
15-14
Name
Description
TM1-0
Mode Select Bits.
TM1 TM0
Mode Selection
0
1
0
0
0
1
Variable Throughput Delay mode
Constant Throughput Delay mode
Message mode; the contents of the connection memory are
output on the corresponding output channel and stream. Only
the lower byte (bit 7 - bit 0) will be output to the ST-BUS output
pins.
1
1
Bit Error Test mode; the pseudo random test pattern will be
output on the output channel and stream associated with this
location.
13
OE
Output Enable. This bit enables the drivers of STo pins on a per-channel
basis. When 1, the STo output driver functions normally. When 0, the STo
output driver is in a high-impedance state.
12-8
7-0
SAB4-0
CAB7-0
Source Stream Address Bits. The binary value is the number of the data
stream for the source of the connection.
Source Channel Address Bits. The binary value is the number of the channel
for the source of the connection. When the message mode is enabled, these
entire 8 bits are output on the output channel and stream associated with this
location.
Table 14 - Connection Memory Bits
SAB4 to SAB0 Bits Used to Determine
the Source Stream of the connection
CAB Bits Used to Determine the Source
Channel of the Connection
Data Rate
8 Mb/s
16Mb/s
SAB4 to SAB0 (STi0 to STi31)
SAB3 to SAB0 (STi0 to STi15)
SAB4 to SAB0 (STi0 to STi31)
SAB3 to SAB0 (STi0 to STi19)
SAB4 to SAB0 (STi0 to STi31)
SAB4 to SAB0 (STi0 to STi31)
SAB4 to SAB0 (STi0 to STi31)
CAB6 to CAB0 (128 channel/frame)
CAB7 to CAB0 (256 channel/frame)
CAB6 to CAB0 (64 or 128 channel/frame)
CAB7 to CAB0 (128 or 256 channel/frame)
CAB5 to CAB0 (64 channel/frame)
4 Mb/s & 8 Mb/s
16 Mb/s & 8 Mb/s
4 Mb/s
2 Mb/s & 4 Mb/s
2 Mb/s
CAB5 to CAB0 (32 or 64 channel/frame)
CAB4 to CAB0 (32 channel/frame)
Table 15 - SAB and CAB Bits Programming for various interface mode
19
MT90826 CMOS
Advanced Information
•
Test Reset (TRST)
Resets the JTAG scan structure. This pin is
internally pulled to VDD.
JTAG Support
The MT90826 JTAG interface conforms to the
Boundary-Scan standard IEEE1149.1. This standard
specifies a design-for-testability technique called
Boundary-Scan test (BST). The operation of the
boundary-scan circuitry is controlled by an external
test access port (TAP) Controller.
Instruction Register
In accordance with the IEEE 1149.1 standard, the
MT90863 uses public instructions. The JTAG
Interface contains a two-bit instruction register.
Instructions are serially loaded into the instruction
register from the TDI when the TAP Controller is in
its shifted-IR state. Subsequently, the instructions
are decoded to achieve two basic functions: to select
the test data register that may operate while the
instruction is current, and to define the serial test
data register path, which is used to shift data
between TDI and DO during data register scanning.
Test Access Port (TAP)
The Test Access Port (TAP) provides access to the
many test functions of the MT90826. It consists of
three input pins and one output pin. The following
pins are from the TAP.
•
Test Clock Input (TCK)
TCK provides the clock for the test logic. The
TCK does not interfere with any on-chip clock
and thus remain independent. The TCK permits
shifting of test data into or out of the Boundary-
Scan register cells concurrently with the
operation of the device and without interfering
with the on-chip logic.
Test Data Register
As specified in IEEE 1149.1, the MT90826 JTAG
Interface contains three test data registers:
•
The Boundary-Scan register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to form
a scan path around the boundary of the
MT90863 core logic.
•
Test Mode Select Input (TMS)
The logic signals received at the TMS input are
interpreted by the TAP Controller to control the
test operations. The TMS signals are sampled
at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven
from an external source.
•
•
The Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from TDI to
its TDO.
•
Test Data Input (TDI)
The Device Identification Register
Serial input data applied to this port is fed
either into the instruction register or into a test
data register, depending on the sequence
previously applied to the TMS input. Both
registers are described in a subsequent
section. The received input data is sampled at
the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven
from an external source.
The device identification register is a 32-bit
register with the register contain of:
MSB
LSB
0000 0000 1000 0010 0110 0001 0100 1011
The LSB bit in the device identification register is
the first bit clock out.
•
Test Data Output (TDO)
The MT90826 scan register contains 165 bits.
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or data register are serially
shifted out towards the TDO. The data out of
the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through
the boundary scan cells, the TDO driver is set
to a high impedance state.
20
Advanced Information
CMOS MT90826
Boundary Scan Bit 0 to Bit 165
Boundary Scan Bit 0 to Bit 165
Device Pin
Device Pin
Tri-state
Control
Output
Scan Cell
Input
Scan Cell
Tri-state
Control
Output
Scan Cell
Input
Scan Cell
STi28
STi29
STi30
STi31
STo28
ST029
ST030
STo31
87
88
89
90
F0i
CLK
ODE
0
1
2
91
93
95
97
92
94
96
98
STi0
STi1
STi2
3
4
5
6
STi3
STo0
STo1
STo2
STo3
STi4
STi5
STi6
STi7
STo4
STo5
STo6
STo7
STi8
STi9
STi10
STi11
STo8
7
9
11
13
8
D0
D1
D2
D3
D4
D5
D6
D7
D8
99
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
10
12
14
102
105
108
111
114
117
120
123
126
129
132
135
138
141
144
15
16
17
18
19
21
23
25
20
22
24
26
D9
D10
D11
D12
D13
D14
D15
27
28
29
30
31
33
35
37
32
34
36
38
STo9
DTA
CS
R/W
DS
147
STo10
STo11
STi12
STi13
STi14
STi15
STo12
STo13
STo14
STo15
STi16
STi17
STi18
STi19
STo16
STo17
STo18
STo19
STi20
STi21
STi22
STi23
STo20
STo21
STo22
STo23
STi24
STi25
STi26
STi27
STo24
STo25
STo26
STo27
148
149
150
39
40
41
42
A0
A1
A2
A3
A4
A5
A6
A7
A8
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
43
45
47
49
44
46
48
50
51
52
53
54
A9
55
57
69
61
56
58
60
62
A10
A11
A12
A13
RESETb
63
64
65
66
67
69
71
73
68
70
72
74
75
76
77
78
79
81
83
85
80
82
84
86
21
MT90826 CMOS
Advanced Information
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
1
2
Supply Voltage
V
-0.3
5.0
V
V
DD
Voltage on any 3.3V tolerant pin I/O (other than sup-
ply pins)
V
VSS - 0.3
V
+ 0.3
DD
I
3
Voltage on any 5V tolerant pin I/O (other than sup-
ply pins)
V
VSS - 0.3
5.0
V
I
4
5
6
Continuous Current at digital outputs
Package power dissipation
Storage temperature
I
20
1
mA
W
o
P
T
D
- 65
+125
°C
S
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Operating Temperature
Sym
Min
Typ
Max
Units Test Conditions
1
2
3
4
5
TOP
VDD
VIH
VIH
VIL
-40
3.0
+85
3.6
°C
V
Positive Supply
Input High Voltage
0.7VDD
VDD
V
Input High Voltage on 5V Tolerant Inputs
Input Low Voltage
5.5
V
VSS
0.3VDD
V
DC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated.
ss
Characteristics
Supply Current
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
I
64
100
mA Output unloaded
DD
Input High Voltage
Input Low Voltage
V
0.7VDD
V
V
IH
I
N
P
U
T
S
V
0.3VDD
IL
Input Leakage (input pins)
Input Leakage (with pull-up
or pull-down)
I
15
50
µA
µA
IL
I
0≤<V≤V
See Note 1
DD
BL
5
6
7
8
Input Pin Capacitance
Output High Voltage
C
10
pF
V
I
O
U
T
P
U
T
V
0.8VDD
I
I
= 10mA
= 10mA
OH
OH
OL
Output Low Voltage
V
0.4
5
V
OL
OZ
High Impedance Leakage
Output Pin Capacitance
I
µA
pF
0 < V < V
See Note 1
DD
S
9
C
10
O
Note:
1. Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
Sym
Level
Units
Conditions
1
2
3
CMOS Threshold Voltage
V
0.5VDD
0.7VDD
0.3VDD
V
V
V
TT
CMOS Rise/Fall Threshold Voltage High
CMOS Rise/Fall Threshold Voltage Low
V
HM
V
LM
22
Advanced Information
CMOS MT90826
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic
Frame pulse width
Sym
Min
Typ
Max
Units
CLK
1
2
3
4
5
6
7
8
9
t
55
5
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FPW
16.384MHz
Frame Pulse Setup time before CLK falling
Frame Pulse Hold Time from CLK falling
CLK Period
t
FPS
t
10
55
20
20
115
5
FPH
t
70
40
CP
CLK Pulse Width High
t
CH
CLK Pulse Width Low
t
40
CL
Frame pulse width
t
145
8.192MHz
FPW8
Frame Pulse Setup time before CLK falling
Frame Pulse Hold Time from CLK falling
t
FPS8
t
10
110
50
50
-10
FPH8
10 CLK Period
t
150
75
CP8
11 CLK Pulse Width High
12 CLK Pulse Width Low
13 Clock Rise/Fall Time
t
CH8
t
75
CL8
t , t
+10
r
f
AC Electrical Characteristics - Serial Streams for ST-BUS
Characteristic
STi Set-up Time
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
t
0
8
ns
ns
ns
SIS
STi Hold Time
t
SIH
STo Delay - Active to Active
t
8
11
30
43
CL=30pF
CL=200pF
SOD
4
5
Output Driver Enable (ODE) Delay
t
35
ns
ns
RL=1K, CL=200pF, See
Note 1
ODE
STo delay - Active to High-Z
- High-Z to Active
t
35
RL=1K, CL=200pF, See
Note 1
ZD
Note:1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
t
FPW
F0i
V
TT
t
t
CH
t
t
t
t
CP
FPS
r
FPH
CL
V
V
V
CLK
(16.384MHz)
HM
TT
LM
t
t
SOD
f
STo
(16Mb/s)
Ch0
Bit6
Ch0
Bit5
Ch0
Bit3
Ch0
Bit2
Ch255
Bit1
Ch255
Bit0
Ch0
Bit7
Ch0
Bit4
Ch0
Bit1
V
TT
t
t
SIH
SIS
STi
(16Mb/s)
Ch0
Bit6
Ch0
Bit5
Ch0
Bit3
Ch0
Bit2
Ch255
Bit1
Ch255
Bit0
Ch0
Bit7
Ch0
Bit4
Ch0
Bit1
V
TT
Figure 6 - ST-BUS Timing for Stream rate of 16.384 Mb/s
23
MT90826 CMOS
Advanced Information
t
FPW
F0i
V
TT
t
t
CH
t
t
t
t
CP
FPS
r
FPH
CL
V
V
V
HM
TT
LM
CLK
(16.384MHz)
t
t
SOD
f
Bit 0, Last Channel
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
V
STo
STi
TT
t
t
SIS
SIH
Bit 0, Last Channel
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
V
TT
Figure 7 - ST-BUS Timing for Stream rate of 8.192 Mb/s
t
FPW
F0i
V
TT
t
t
t
t
t
t
CP
CH
FPS
r
FPH
CL
V
V
V
CLK
(16.384MHz)
HM
TT
LM
t
t
SOD
f
STo
Ch63 Bit 0
Ch63 Bit 0
Ch0 Bit 7
Ch0 Bit 6
V
TT
(4Mb/s)
t
t
SIS
SIH
STi
(4Mb/s)
Ch0 Bit 7
V
Ch0 Bit 6
TT
Figure 8 - ST-BUS Timing for Stream rate of 4.096 Mb/s when CLK = 16.384MHz
t
FPW8
F0i
V
TT
t
t
t
t
t
t
CH8
r
CP8
FPS8
FPH8
CL8
V
V
V
CLK
(8.192MHz)
HM
TT
LM
t
t
SOD
f
STo
Ch63 Bit 0
Ch63 Bit 0
Ch0 Bit 7
Ch0 Bit 6
V
TT
(4Mb/s)
t
t
SIS
SIH
STi
(4Mb/s)
Ch0 Bit 7
V
Ch0 Bit 6
TT
Figure 9 - ST-BUS Timing for Stream rate of 4.096 Mb/s when CLK = 8.192MHz
t
FPW
F0i
V
V
TT
t
t
CH
t
t
t
t
CP
FPS
r
FPH
CL
CLK
(16.384MHz)
HM
TT
V
V
LM
t
t
SOD
f
STo
Ch31 Bit 0
Ch31 Bit 0
Ch0 Bit 7
Ch0 Bit 6
V
TT
TT
(2Mb/s)
t
t
SIH
SIS
STi
(2Mb/s)
Ch0 Bit 7
Ch0 Bit 6
V
Figure 10 - ST-BUS Timing for Stream rate of 2.048 Mb/s when CLK = 16.384MHz
24
Advanced Information
CMOS MT90826
F0i
V
TT
t
t
t
t
t
CH8
CP8
FPS8
FPH8
CL8
V
V
V
CLK
(8.192MHz)
HM
TT
LM
t
SOD
STo
Ch31 Bit 0
(2Mb/s)
Ch0 Bit 7
Ch0 Bit 6
V
TT
TT
t
t
SIH
SIS
STi
Ch0 Bit 7
Ch0 Bit 6
V
Ch31 Bit 0
(2Mb/s)
Figure 11 - ST-BUS Timing for Stream rate of 2.048 Mb/s when CLK = 8.192MHzMHz
V
TT
CLK
STo
STo
V
TT
t
ODE
STo
DZ
t
t
ODE
ODE
V
Valid Data
HiZ
HiZ
TT
t
ZD
V
Valid Data
HiZ
HiZ
TT
V
Valid Data
TT
Figure 13 - Output Driver Enable (ODE)
Figure 12 - Serial Output and External Control
25
MT90826 CMOS
Advanced Information
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
CS setup from DS falling
Sym
Min
Typ
Max Units Test Conditions
1
2
3
4
5
6
7
8
t
0
10
2
ns
ns
ns
ns
ns
ns
CSS
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
t
RWS
t
ADS
CSH
RWH
t
0
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
t
2
t
10
27
12
ADH
DDR
DHR
t
ns
ns
C =150pF
L
t
20
55
C =150pF, R =1K
L
L
Note 1
9
Data setup on write (fast write)
t
t
0
ns
ns
DSW
SWD
10 Valid Data Delay on write (slow write)
50
85
185
11 Data hold on write
t
13
ns
ns
DHW
12a Acknowledgment Delay: Register RD or WR
t
C =150pF
L
AKD
12b Acknowledgment Delay: Memory RD or WR
16Mb/s, 16&8Mb/s, 8Mb/s, 4&8Mb/s
4Mb/s, 4&2Mb/s
t
AKD
100
140
240
ns
ns
ns
C =150pF
L
2Mb/s
13 Acknowledgment Hold Time
t
24
ns
C =150pF, RL=1K,
AKH
L
Note 1
Note:
1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
V
DS
CS
TT
t
t
CSH
CSS
V
TT
t
t
RWH
RWS
V
R/W
TT
t
t
ADS
ADH
V
Valid Address
TT
A0-A7
t
DHR
V
Valid Read Data
D0-D15
READ
TT
TT
t
t
DHW
DSW
t
SWD
V
Valid Write Data
D0-D15
WRITE
t
DDR
V
TT
DTA
t
AKD
t
AKH
Figure 14 - Motorola Non-Multiplexed Bus Timing
26
Package Outlines
Pin #1 Corner
Ø1.00(3X) REF.
1
2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
Ø
0.75 ± 0.15 (169X)
J
13 12 11 10 9
8
7
6
5 4 3 2 1
K
L
M
A
B
C
D
E
F
N
3.00*45 ° (4x)
20.00 REF
G
H
J
K
L
M
N
B
1.50
18.00
30 ° Typ.
A
23.00 ± 0.20
C
Seating Plane
Note: All governing dimensions are in millimetres for design purposes
Ball Gate Array
120-BGA
144-BGA
160-BGA
MT90823
MT90863
MT90826
Package Outlines
L1
A
A
2
L
A
1
e
b
D
D
1
Notes:
1)Not to scale
2) Top dimensions in inches
3) The governing controlling
dimensions are in millimeters
for design purposes ( )
E
E
1
Index
WARNING:
This package diagram does not apply to the MT90810AK
100 Pin Package. Please refer to the data sheet for
exact dimensions.
Pin 1
Metric Quad Flat Pack - L Suffix
44-Pin
64-Pin
100-Pin
128-Pin
Dim
Min
Max
Min
Max
Min
Max
Min
Max
A
A1
A2
b
-
0.096
(2.45)
-
0.134
(3.40)
-
0.134
(3.40)
-
0.154
(3.85)
0.01
(0.25)
-
0.01
(0.25)
-
0.01
(0.25)
-
0.00
0.01
(0.25)
0.077
(1.95)
0.083
(2.10)
0.1
(2.55)
0.12
(3.05)
0.1
(2.55)
0.12
(3.05)
0.125
(3.17)
0.144
(3.60)
0.01
(0.30)
0.018
(0.45)
0.013
(0.35)
0.02
(0.50)
0.009
(0.22)
0.015
(0.38)
0.019
(0.30)
0.018
(0.45)
D
0.547 BSC
0.941 BSC
0.941 BSC
1.23 BSC
(13.90 BSC)
(23.90 BSC)
(23.90 BSC)
(31.2 BSC)
D
0.394 BSC
(10.00 BSC)
0.787 BSC
(20.00 BSC)
0.787 BSC
(20.00 BSC)
1.102 BSC
(28.00 BSC)
1
E
0.547 BSC
(13.90 BSC)
0.705 BSC
(17.90 BSC)
0.705 BSC
(17.90 BSC)
1.23 BSC
(31.2 BSC)
E
0.394 BSC
(10.00 BSC)
0.551 BSC
(14.00 BSC)
0.551 BSC
(14.00 BSC)
1.102 BSC
(28.00 BSC)
1
e
0.031 BSC
(0.80 BSC)
0.039 BSC
(1.0 BSC)
0.256 BSC
(0.65 BSC)
0.031 BSC
(0.80 BSC)
L
0.029
(0.73)
0.04
(1.03)
0.029
(0.73)
0.04
(1.03)
0.029
(0.73)
0.04
(1.03)
0.029
(0.73)
0.04
(1.03)
L1
0.077 REF
(1.95 REF)
0.077 REF
(1.95 REF)
0.077 REF
(1.95 REF)
0.063 REF
(1.60 REF)
NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters.
Package Outlines
160-Pin
208-Pin
240-Pin
Dim
A
Min
Max
Min
Max
Min
Max
-
0.154
(3.92)
.161
(4.10)
-
0.161
(4.10)
A1
A2
b
0.01
(0.25)
0.01
(0.25)
0.02
(0.50)
0.01
(0.25)
0.02
(0.50)
0.125
(3.17)
0.144
(3.67)
.126
(3.20)
.142
(3.60)
0.126
(3.2)
0.142
(3.60)
0.009
(0.22)
0.015
(0.38)
.007
(0.17)
.011
(0.27)
0.007
(0.17)
0.010
(0.27)
D
1.23 BSC
(31.2 BSC)
1.204
(30.6)
1.360 BSC
(34.6 BSC)
D
1.102 BSC
(28.00 BSC)
1.102
(28.00)
1.26 BSC
(32.00 BSC)
1
E
1.23 BSC
(31.2 BSC)
1.204 BSC
(30.6 BSC)
1.360 BSC
(34.6 BSC)
E
1.102 BSC
(28.00 BSC)
1.102 BSC
(28.00 BSC)
1.26 BSC
(32.00 BSC)
1
e
0.025 BSC
(0.65 BSC)
0.020 BSC
(0.50 BSC)
0.0197 BSC
(0.50 BSC)
L
0.029
(0.73)
0.04
(1.03)
0.018
(0.45)
0.029
(0.75)
0.018
(0.45)
0.029
(0.75)
L1
0.063 REF
(1.60 REF)
0.051 REF
(1.30 REF)
0.051 REF
(1.30 REF)
NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters.
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相关型号：
MT90840AL1
Digital Time Switch, PQFP100, 14 X 20 MM, 2.80 MM HEIGHT, LEAD FREE, MO-112CC-1, MQFP-100
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