MT8940AE [MITEL]
ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL; ISO- CMOS ST- BUS⑩系列T1 / CEPT数字中继锁相环
| 型号： | MT8940AE |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| 文件： | 总19页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO-CMOS ST-BUS FAMILY
T1/CEPT Digital Trunk PLL
MT8940
ISSUE 8
March 1997
Features
Ordering Information
•
•
Provides T1 clock at 1.544 MHz locked to input
frame pulse
MT8940AE
24 Pin Plastic DIP (600 mil)
Sources CEPT (30+2) Digital Trunk/ST-BUS
clock and timing signals locked to internal or
external 8 kHz signal
-40°C to +85°C
•
•
•
•
TTL compatible logic inputs and outputs
Uncommitted 2-input NAND gate
Single 5 volt power supply
Description
The MT8940 is a dual digital phase-locked loop
providing the timing and synchronization signals for
the T1 or CEPT transmission links and the ST-BUS.
The first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
Low power ISO-CMOS technology
Applications
•
•
Synchronization and timing control for T1
and CEPT digital trunk transmission links
ST- BUS clock and frame pulse source
The MT8940 is fabricated in MITEL’s ISO-CMOS
technology.
CVb
F0i
Variable
DPLL #1
CV
Clock
Control
2:1 MUX
C12i
ENCV
MS0
Frame Pulse
Control
Mode
Selection
Logic
MS1
MS2
F0b
Input
Selector
MS3
C4b
4.096 MHz
Clock
Control
C8Kb
C4o
ENC4o
C16i
DPLL #2
C2o
Clock
Generator
2.048 MHz
Clock
Control
C2o
Ai
Bi
ENC2o
Yo
V
V
RST
DD
SS
Figure 1 - Functional Block Diagram
3-27
MT8940 ISO-CMOS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
ENVC
MS0
C12i
MS1
F0i
VDD
RST
CV
CVb
Yo
F0b
Bi
Ai
MS2
C16i
ENC4o
C8Kb
C4o
MS3
ENC2o
C2o
C2o
C4b
9
10
11
12
VSS
Figure 2 - Pin Connections
Pin Description
Pin #
Name
EN
Description
1
Variable clock enable (TTL compatible input) - This input (pulled internally to V ) directly
CV
DD
controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables
CV and when LOW, puts it in high impedance condition. It also controls the three states of
CVb signal (pin 21) if MS1 is LOW. When EN is HIGH, the pin CVb is an output and when
CV
LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.
2
MS0
Mode select ‘0’ input (TTL compatible) - This input (pulled internally to V ) in conjunction
SS
with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and
2).
3
4
C12i
MS1
Clock 12.355 MHz input (TTL compatible) - Master clock input at 12.355 MHz ±100ppm for
DPLL #1.
Mode select-1 input (TTL compatible) - This input (pulled internally to V ) in conjunction
SS
with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and
2)
5
6
F0i
Frame pulse input (TTL compatible) - This is the frame pulse input (pulled internally to
V
) at 8 kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544
DD
MHz) clock.
F0b
Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending
on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts
as an input (pulled internally to V ) to an external frame pulse.
DD
7
8
9
MS2
C16i
Mode select-2 input (TTL compatible) - This input (pulled internally to V ) in conjunction
with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.)
DD
Clock 16.388 MHz input (TTL compatible) - Master clock input at 16.388 MHz±32 ppm for
DPLL #2.
EN
Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally
C4o
to V ) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance
DD
condition.
3-28
ISO-CMOS MT8940
Pin Description (continued)
Pin #
Name
Description
Clock 8 kHz- Bidirectional (TTL compatible input and open drain output with 100K
10
C8Kb
internal resistor to V ) - This is the 8 kHz input signal on the rising edge of which DPLL #2
DD
locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs
an 8 kHz signal provided by DPLL #1, which is also connected internally to DPLL #2.
11
C4o
Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by EN
(pin 9).
C4o
12
13
V
Ground (0 Volt)
SS
C4b
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input (pulled
internally to V ) to an external clock at 4.096 MHz.
DD
14
15
16
C2o
C2o
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by EN
(pin 16).
C2o
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by EN
(pin 16).
C2o
EN
Enable 2.048 MHz clock (TTL compatible input) - This active high input (pulled internally
C2o
to V ) enables both C2o and C2o outputs (pins 14 and 15). When LOW, these outputs are
DD
in high impedance condition.
17
MS3
Mode select 3 input (TTL compatible) - This input (pulled internally to V ) in conjunction
DD
with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.)
18,19
Ai, Bi
Inputs A and B (TTL compatible) -These are the two inputs (pulled internally to V ) of the
SS
uncommitted NAND gate.
20
21
Y
Output Y (Totem pole output) - Output of the uncommitted NAND gate.
o
CVb
Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input (pulled internally to V ) to an external clock at 1.544 MHz or 2.048 MHz to provide the
DD
internal signal at 8 kHz to DPLL #2.
22
23
24
CV
Variable clock (Three state output) - This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled EN (pin 1).
CV
RST
Reset (Schmitt trigger input) -This input (active LOW) evokes reset condition for the
device.
V
V
(+5V) Power supply.
DD
DD
3-29
MT8940 ISO-CMOS
The phase sampling is done once in a frame (8 kHz)
and the divisions are set at 8 and 193 for DPLL #1,
which locks on to the falling edge of the input at 8
kHz to generate T1 (1.544 MHz) clock. Although the
phase sampling duration is the same for DPLL #2,
the divisions are set at 8 and 256 to provide the
CEPT/ST-BUS clock at 2.048 MHz synchronized to
the rising edge of the input signal (8 kHz). The
master clock source is specified to be at 12.355 MHz
±100 ppm for DPLL #1 and 16.388 MHz ±32 ppm for
DPLL #2 over the entire temperature range of
operation.
Functional Description
The MT8940 is a dual digital phase-locked loop
providing the timing and synchronization signals to
the interface circuits for T1 and CEPT (30+2)
Primary Multiplex Digital Transmission links. As
shown in Figure 1, it has two digital phase-locked
loops (DPLLs), associated output controls and the
mode selection logic circuits. The two DPLLs,
although similar in principle, operate independently
to provide T1 (1.544 MHz) and CEPT (2.048 MHz)
transmission clocks, and ST-BUS timing signals.
The inputs MS0 to MS3 are used to select the
operating mode of the MT8940, see Tables 1 to 4. All
the outputs are individually controlled to the high
impedance condition by their respective enable
controls. The uncommitted NAND gate is available
for use in applications involving MITEL’s
The principle of operation behind the two DPLLs is
shown in Figure 3. A master clock is divided down to
8 kHz where it is compared with the 8 kHz input, and
depending on the output of the phase comparison,
the master clock frequency is corrected. The
MT8940 achieves the frequency correction in both
directions by using the master clock at a slightly
higher frequency and dividing it unaltered or
stretching its period (at two discrete instants in a
frame) before the division depending on the phase
comparison output. When the input frequency is
MT8976/MH89760
(T1
interfaces)
and
MT8979/MH89790 (CEPT interfaces).
Modes of Operation
The operation of the MT8940 is categorized into
major and minor modes. The major modes are
defined for both DPLLs by the mode select pins MS0
and MS1. The minor modes are selected by MS2
and MS3, and are applicable only to DPLL #2. There
are no minor modes for DPLL #1.
Master Clock
Frequency
÷8
(12.355 MHz/
16.388 MHz)
Correction
Output
(1.544 MHz /
2.048 MHz)
Major modes of the DPLL #1
Input (8 kHz)
DPLL #1 can be operated in three major modes as
selected by MS0 and MS1 (Table 1). When MS1 is
LOW, it is in NORMAL mode, which provides a T1
(1.544 MHz) clock signal locked to the falling edge of
the input frame pulse F0i (8 kHz). DPLL#1 requires a
master clock input of 12.355 MHz±100 ppm (C12i).
In the second and third major modes (MS1 is HIGH),
DPLL #1 is set to DIVIDE an external 1.544 MHz or
2.048 MHz signal applied at CVb (pin 21). The
division can be set by MS0 to be either 193 (LOW) or
256 (HIGH). In these modes, the 8 kHz output is
connected internally to DPLL #2, which operates in
SINGLE CLOCK mode.
Phase
Comparison
÷193 /
÷256
Figure 3 - DPLL Principle
higher, the unchanged master clock is divided, thus
effectively speeding-up the locally generated clock
and eventually pulling it in synchronization with the
input. If the input frequency is lower than the divided
master clock, the period of the master clock is
stretched by half a cycle, at two discrete instants in a
phase sampling period. This introduces a total delay
of one master clock period over the sampling
duration, which is then divided to generate the local
signal synchronous with the input. Once the output is
phase-locked to the active edge of the input, the
circuit will maintain the locked condition as long as
the input frequency is within the lock-in range (±1.04
Hz) of the DPLLs. The lock-in range is wide enough
to meet the CCITT line rate specification (1.544
MHz±130ppm and 2.048 MHz ±50ppm) for the High
Capacity Terrestrial Digital Service.
Major modes of the DPLL #2
There are four major modes for DPLL #2 selectable
by MS0 and MS1, as shown in Table 2. In all these
modes DPLL #2 provides the CEPT PCM 30 timing,
and the ST-BUS clock and framing signals.
In NORMAL mode, DPLL #2 provides the CEPT and
ST-BUS compatible timing signals locked to the
rising edge of the 8 kHz input signal (C8Kb). These
3-30
ISO-CMOS MT8940
signals are the 4.096 MHz (C4o and C4b) and the
2.048 MHz (C2o and C2o) clocks, and the 8 kHz
Mode of
operation
MS0 MS1
Function
0
1
0
0
0
1
NORMAL Provides ST-BUS/CEPT
timing signals locked to the
rising edge of the 8kHz
Mode of
MS0 MS1
Function
operation
X
0
0
1
1
NORMAL
Provides the T1 (1.544
MHz) clock synchronized
to the falling edge of the
input frame pulse (F0i).
input signal at C8Kb.
FREE-RUN Provides ST-BUS timing
and framing signals with no
external inputs, except the
master clock.
DIVIDE-1
DIVIDE-2
DPLL #1 divides the CVb
input by 193. The divided
output is connected to
DPLL #2.
SINGLE
Provides the CEPT/ST-
CLOCK-1 BUS compatible timing
signals locked to the falling
edge of the 8kHz internal
signal provided by DPLL
#1.
1
DPLL #1 divides the CVb
input by 256. The divided
output is connected to
DPLL #2.
1
1
SINGLE
Provides CEPT/ST-BUS
Note:
X: indicates don’t care
CLOCK-2 timing signals locked to the
falling edge of the 8kHz
internal signal provided by
DPLL #1.
Table 1. Major Modes of the DPLL #1
frame pulse (F0b), which are derived from the 16.388
MHz master clock. This mode can also provide the
ST-BUS timing and framing signals with the input
(C8Kb) tied HIGH and the master clock set at 16.384
MHz. The DPLL makes no correction in this
configuration and provides the timing signals
compatible to the ST-BUS format without any jitter.
Table 2. Major Modes of the DPLL #2
When MS3 is HIGH, DPLL #2 operates in any of the
major modes as selected by MS0 and MS1.
When MS3 is LOW, it overrides the major mode
selected and DPLL #2 accepts an external clock of
4.096 MHz on C4b (pin 13) to provide the 2.048 MHz
clocks (C2o and C2o) and the 8 kHz frame pulse
(F0b) compatible with the ST-BUS format.
In FREE-RUN mode, DPLL #2 generates CEPT and
ST-BUS timing and framing signals with no external
inputs except the master clock set at 16.388 MHz.
Since the master clock source is set at a higher
frequency than the nominal value, the DPLL makes
the necessary corrections to deliver the averaged
timing signals compatible to the ST-BUS format.
The mode select bit MS2, controls the signal
direction of F0b (pin 6). When MS2 is LOW, F0b is an
input for an external frame pulse at 8 kHz. This
The operation of DPLL #2 in SINGLE CLOCK-1
mode is identical to SINGLE CLOCK-2 mode,
providing the CEPT and ST-BUS compatible timing
signals synchronized to the internal 8 kHz signal
obtained from DPLL#1 in DIVIDE mode. When
SINGLE CLOCK-1 mode is selected for DPLL #2, it
automatically selects the DIVIDE-1 mode for DPLL
#1, and thus, an external 1.544 MHz clock signal
applied at CVb (pin 21) is divided by DPLL #1 to
generate the internal signal at 8 kHz onto which
DPLL #2 locks. Similarly when SINGLE CLOCK-2
mode is selected, DPLL #1 is in DIVIDE-2 mode,
with an external signal of 2.048 MHz providing the
internal 8 kHz signal to DPLL #2. In both these
modes, this internal signal is available on C8Kb (pin
10) and DPLL #2 locks to its falling edge to provide
the CEPT and ST-BUS compatible timing signals.
This is in contrast to the Normal mode where these
timing signals are synchronized with the rising edge
of the 8 kHz signal on C8Kb.
MS2 MS3
Functional Description
Provides ST-BUS 4.096 MHz and 2.048
MHz clocks and 8kHz frame pulse
depending on the major mode selected.
Provides ST-BUS 4.096 MHz & 2.048 MHz
clocks depending on the major mode
selected while F0b acts as an input.
However, the input on F0b has no effect on
the operation of DPLL #2 unless it is in
FREE-RUN mode.
Overrides the major mode selected and
accepts properly phase related external
4.096 MHz clock and 8 kHz frame pulse to
provide the ST-BUS compatible clock at
2.048MHz.
1
1
0
1
0
1
0
0
Overrides the major mode selected and
accepts a 4.096 MHz external clock to
provide the ST-BUS clock and frame pulse
at 2.048 MHz and 8 kHz, respectively.
Table 3. Minor Modes of the DPLL #2
Minor modes of the DPLL #2
input is effective only if MS3 is also LOW and C4b is
accepting a 4.096 MHz external clock, which has a
proper phase relationship with the external input on
The minor modes for DPLL #2 depends upon the
status of the mode select bits MS2 and MS3 (pins 7
and 17).
3-31
MT8940 ISO-CMOS
F0b (refer to Figure 15). Otherwise, the input on pin
F0b will have no bearing on the operation of DPLL
#2, unless it is in FREE-RUN mode as selected by
MS0 and MS1. In FREE-RUN mode, the input on
F0b is treated the same way as the C8Kb input in
NORMAL mode. The frequency of the input signal on
F0b should be 16 kHz for DPLL #2 to provide the ST-
BUS compatible clocks at 4.096 MHz and 2.048
MHz.
When MS2 is HIGH, the F0b pin provides the ST-
BUS frame pulse output locked to the 8kHz internal
or external signal as determined by the other mode
select pins MS0, MS1 and MS3.
Table 4 summarizes the modes of the two DPLLs. It
should be noted that each of the major modes
selected for DPLL #2 can have any of the minor
modes, although some of the combinations are
functionally similar. The required operation of both
DPLL#1 and DPLL#2 must be considered when
determining MS0-MS3.
M
Operating Modes
DPLL #2
O
MS MS MS MS
D
E
#
0
1
2
3
DPLL #1
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
BUS clock at 2.048 MHz.
NORMAL MODE
NORMAL MODE
0
1
2
0
0
0
0
0
0
0
0
1
0
1
0
NORMAL MODE
F0b is an input but has no function in this mode.
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
NORMAL MODE
NORMAL MODE:
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the
input frame pulse (F0i).
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
3
0
0
1
1
DIVIDE-1 MODE
Same as mode ‘0’.
4
5
6
0
0
0
1
1
1
0
0
1
0
1
0
SINGLE CLOCK-1 MODE
F0b is an input, but has no function in this
mode.
DIVIDE-1 MODE
DIVIDE-1 MODE
DIVIDE-1 MODE:
Same as mode 2.
SINGLE CLOCK-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
7
0
1
1
1
NORMAL MODE
NORMAL MODE
Same as mode ‘0’.
8
9
1
1
1
0
0
0
0
0
1
0
1
0
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
NORMAL MODE
Same as mode 2.
10
NORMAL MODE
FREE-RUN MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of input frame external inputs except the master clock.
pulse (F0i).
Provides the ST-BUS timing signals with no
11
1
0
1
1
DIVIDE-2 MODE
DIVIDE-2 MODE
Same as mode ‘0’.
12
13
14
1
1
1
1
1
1
0
0
1
0
1
0
SINGLE CLOCK-2 MODE:
F0b is an input, but has no function in this
mode.
DIVIDE-2 MODE
Same as mode 2.
DIVIDE-2 MODE:
SINGLE CLOCK-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
15
1
1
1
1
Table 4. Summary of Modes of Operation - DPLL #1 and #2
3-32
ISO-CMOS MT8940
uncommitted NAND gate converts the received
signals, RxA and RxB of the MH89760 to a single
Return to Zero (RZ) input for the clock extraction
circuits of the MH89760. This is not required for the
MH89760B. The generated ST-BUS signals can be
used to synchronize the system and the switching
equipment at the master end.
Applications
The following figures illustrate how the MT8940 can
be used in a minimum component count approach to
providing the timing and synchronization signals for
the Mitel T1 and CEPT interfaces, and the ST-BUS.
The hardware selectable modes and the
independent control over each PLL adds flexibility to
the interface circuits. It can be easily reconfigured to
provide the timing and control signals for both at the
master and slave ends of the link.
At the slave end of the link (Figure 5) both the DPLLs
are in NORMAL mode with DPLL #2 providing the
ST-BUS timing signals locked to the 8 kHz frame
pulse (E8Ko) extracted from the received signal on
the T1 line. The regenerated frame pulse is looped
back to DPLL #1 to provide the T1 line clock as at
the master end. The 12.355 MHz and 16.388 MHz
crystal clock sources are necessary for DPLL #1 and
#2.
Synchronization and Timing Signals for the T1
Transmission Link
Figures 4 and 5 show examples of how to generate
the timing signals for the master and slave ends of a
T1 link.
Synchronization and Timing Signals for the
CEPT Transmission Link
At the master end of the link (Figure 4), DPLL #2 is
the source of the ST-BUS signals derived from the
4.096 MHz system clock. The frame pulse output is
looped back to DPLL #1 (in NORMAL mode), which
locks to it to generate the T1 line clock. The timing
relationship between the 1.544 MHz T1 clock and the
2.048 MHz ST-BUS clock meets the requirements of
the MH89760/760B. The crystal clock at 12.355 MHz
is used by DPLL #1 to generate the 1.544 MHz clock,
while DPLL #2 uses the 4.096 MHz system clock to
provide the ST-BUS timing signals. The ST-BUS
signals can also be obtained from DPLL #2 in FREE-
RUN mode, using a crystal clock at 16.388 MHz
instead of 4.096 MHz system clock. The
The MT8940 can be used to provide the timing and
synchronization signals for the MH89790/790B,
MITEL’s CEPT(30+2) digital trunk interface hybrid.
Since the operational frequencies of the ST-BUS and
the CEPT primary multiplex digital trunk are same,
only DPLL #2 is required to achieve synchronization
between the two.
Figures 6 and 7 show how the MT8940 can be used
to synchronize the ST-BUS and the CEPT
transmission link at the master and slave ends,
respectively.
MT8980/81
Crystal Clock
MT8940
(12.355 MHz
V
±100 ppm)
DD
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89760
CV
C1.5i
DSTi
C2i
F0i
DSTo
F0i
C12i
C4b
C2o
F0b
CSTi
EN
CV
CSTo
C8Kb
C16i
TxT
TxR
RxT
RxR
TRANSMIT
RECEIVE
T1
EN
RxA
C4o
4.096 MHz
System Clock
LINK
EN
C2o
RxB
RxD
(1.544 Mbps)
Ai
Bi
(ST-BUS
compatible)
Y
o
V
SS
RST
MODE OF OPERATION FOR THE MT8940
DPLL #1 - NORMAL (MS0 = X; MS1 = 0)
DPLL #2 - OVERRIDE THE MAJOR MODES (MS2 = 1; MS3 = 0)
Figure 4 - Synchronization at the Master End of the T1 Transmission Link
3-33
MT8940 ISO-CMOS
MT8980/81
Crystal Clock
MT8940
(12.355 MHz
± 100 ppm)
V
DD
MS0
MH89760
ST-BUS
SWITCH
MS1
MS2
MS3
CV
C1.5i
DSTi
C2i
F0i
DSTo
F0i
C12i
C4b
C2o
F0b
CSTi
EN
CV
CSTo
C8Kb
C16i
TxT
TxR
RxT
RxR
TRANSMIT
RECEIVE
T1
EN
RxA
C4o
LINK
EN
Ai
C2o
RxB
RxD
(1.544 Mbps)
Y
o
Bi
V
SS
Crystal Clock
RST
(16.388 MHz
± 32 ppm)
Mode of Operation for the MT8940
DPLL #1 - NORMAL (MS1=0)
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 5 - Synchronization at the Slave End of the T1 Transmission Link
MT8980/81
MT8940
V
DD
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89790
C4b
C2o
DSTi
C2i
F0i
DSTo
F0i
C12i
CSTi0
CSTi1
EN
4.096 MHz
System Clock
CV
C8Kb
C16i
CSTo
OUTA
OUTB
RxT
(ST-BUS
Compatible)
F0b
RxA
EN
EN
Ai
C4o
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
TRANSMIT
RECEIVE
C2o
RxB
RxD
Y
o
Bi
V
SS
RST
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - OVERRIDE MAJOR MODES (MS0=X; MS1=X
MS2=1; MS3=0)
Figure 6 - Synchronization at the Master End of the CEPT Digital Transmission Link
Generation of ST-BUS Timing Signals
mode with an oscillator input of 16.388 MHz. This
forces the DPLL to correct at a rate of 4 kHz to
maintain the ST-BUS clocks, which therefore, will be
jittered. In the other case, the oscillator input is
16.384 MHz (exactly eight times the output
frequency) and DPLL #2 operates in NORMAL mode
with C8Kb input tied HIGH. Since no corrections are
necessary, the output is free from jitter. DPLL #1 is
completely free in both cases and available for any
other purpose.
The MT8940 can source the properly formatted ST-
BUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.
Figure 8 shows two such applications using only
DPLL #2. In one case, the MT8940 is in FREE-RUN
3-34
ISO-CMOS MT8940
MT8940
MT8980/81
V
DD
MS0
MS1
MS2
MS3
MH89790
ST-BUS
SWITCH
C4b
C2o
DSTi
C2i
F0i
DSTo
F0i
C12i
CSTi0
CSTi1
EN
CV
C8Kb
C16i
Crystal Clock
CSTo
OUTA
OUTB
RxT
(16.388 MHz
± 32 ppm)
F0b
RxA
EN
EN
Ai
C4o
CEPT
TRANSMIT
C2o
RxB
RxD
PRIMARY
MULTIPLEX
DIGITAL
Y
o
Bi
LINK
RECEIVE
V
SS
RST
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 7 - Synchronization at the Slave End of the CEPT Digital Transmission Link
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
MT8940
MT8940
(MS0=0; MS1=0; MS2=1;
MS3=1)
V
V
DD
DD
MS0
MS1
MS2
MS3
MS0
MS1
MS2
MS3
C4o
C4b
C4o
C4b
ST-BUS
F0i
ST-BUS
F0i
C12i
C12i
EN
EN
CV
CV
TIMING
TIMING
C8Kb
C16i
C8Kb
C16i
EN
Crystal Clock
C2o
C2o
Crystal Clock
(16.388 MHz
± 32 ppm)
(16.388 MHz
± 32 ppm)
SIGNALS
EN
SIGNALS
C4o
C4o
C2o
C2o
F0b
C2o
F0b
EN
EN
Ai
C2o
Ai
Bi
Bi
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
V
V
SS
SS
RST
RST
MS2=1; MS3=1)
Figure 8 - Generation of the ST-BUS Timing Signals
3-35
MT8940 ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to ground (V ) unless otherwise stated.
SS
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
6
7
Supply Voltage
V
-0.3
7.0
V
DD
Voltage on any pin
V
V
-0.5
V +0.5
DD
V
I
SS
Input/Output Diode Current
Output Source or Sink Current
DC Supply or Ground Current
Storage Temperature
I
±10
mA
mA
mA
IK/OK
I
±25
±50
150
600
O
I
/I
DD SS
o
T
-65
C
ST
Package Power Dissipation
LCC
P
mW
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Characteristics
Supply Voltage
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
V
4.75
2.4
5.0
5.25
V
V
V
DD
Input HIGH Voltage
Input LOW Voltage
Operating Temperature
V
V
For 400 mV noise margin
For 400 mV noise margin
IH
DD
V
V
0.4
IL
SS
o
T
-40
25
85
C
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (V ) unless otherwise stated.
SS
V
=5.0 V±5%; V =0V; T =-40 to 85°C.
DD
SS
A
‡
Characteristics
Sym Min Typ
Max
Units
Test Conditions
Under clocked condition, with the
inputs tied to the same supply rail
as the corresponding pull-up /
down resistors.
S
U
P
I
8
15
100
mA
DD
I
1
Supply Current
DDS
2
3
4
5
6
7
Input HIGH voltage (For all the
inputs except pin 23)
V
2.0
2.8
V
V
IH
Positive-going threshold
voltage (For pin 23)
V
+
I
N
Input LOW voltage (For all the
inputs except pin 23)
V
0.8
1.5
V
IL
Negative-going threshold
voltage (For pin 23)
V
V
-
Output current HIGH (For all
the outputs except pin 10)
I
-9.5
4.5
2.0
mA
mA
V
=2.4 V
OH
OH
O
U
T
Output current LOW (For all the
outputs except pin 10)
I
I
V =0.4 V
OL
OL
OL
8
9
Output current LOW (pin 10)
mA
V
=0.4 V
OL
Leakage current on bidirect-
ional pins and all inputs except
C12i, C16i, RST
I
I
±150
±10
µA
V
=V or V
I/O SS DD
IZ/OZ
10
Leakage current on all outputs
and C12i, C16i, RST inputs
±1
µA
V
=V or V
I/O SS DD
IZ/OZ
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-36
ISO-CMOS MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 9)
SS
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
1
2
3
4
5
6
Frame pulse input (F0i) to CVb
output (1.544 MHz) delay
t
-40
75
15
ns
ns
ns
ns
ns
ns
F15H
CVb output (1.544 MHz) rise
time
t
10
12
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
r1.5
CVb output (1.544 MHz) fall
time
t
15
f1.5
P15
D
P
L
L
CVb output (1.544 MHz) clock
period
t
648
690
386
327
CVb output (1.544 MHz) clock
width (HIGH)
t
320
W15H
#1
CVb output (1.544 MHz) clock
width (LOW)
t
314
W15L
7
8
CV delay (HIGH to LOW)
t
5
30
10
ns
ns
15HL
15LH
CV delay (LOW to HIGH)
t
-12
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
V
V
IH
F0i
IL
t
F15H
t
P15
t
f1.5
t
W15H
V
V
OH
CVb
CV
OL
t
W15L
t
15HL
t
r1.5
t
15LH
V
V
OH
OL
Figure 9 - Timing Information for DPLL #1 in NORMAL Mode
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 10)
SS
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
1
2
3
4
5
C8Kb output (8kHz) delay
(HIGH to HIGH)
t
130
130
ns
ns
Test load circuit 2 (Fig. 17).
C8HH
C8Kb output (8 kHz) delay
(LOW to LOW)
t
50
Test load circuit 2 (Fig. 17).
D
P
L
L
C8LL
C8Kb output duty cycle
66
50
%
%
In Divide -1 Mode
In Divide - 2 Mode
Inverted clock output delay
(HIGH to LOW)
#1
t
40
35
75
60
ns
ns
ICHL
ICLH
Inverted clock output delay
(LOW to HIGH)
t
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-37
MT8940 ISO-CMOS
V
IH
CVb
V
IL
t
t
ICLH
ICHL
V
OH
CV
V
OL
t
t
C8LL
C8HH
V
OH
C8Kb
V
OL
Figure 10 - DPLL #1 in DIVIDE Mode
t
WFP
V
OH
F0b
V
OL
t
t
FPH
FPL
t
fC4
t
rC4
V
OH
C4b
C4o
V
OL
t
t
4oLH
4oHL
V
OH
V
OL
t
42LH
t
P2o
t
t
42HL
W2oH
t
rC2
t
fC2
V
OH
C2o
C2o
V
OL
t
W2oL
t
2oLH
t
2oHL
V
OH
V
OL
Figure 11 - Timing Information on DPLL #2 Outputs
3-38
ISO-CMOS MT8940
AC Electrical Characteristics†-Voltages are with respect to ground (V ) unless otherwise stated.(Ref. Figures 11&12)
SS
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
1
C4b output delay (HIGH to
LOW) from C8Kb input/output
Test load circuit 2 (Fig. 17)
on C8Kb.
t
-25
75
ns
84H
2
3
4
5
6
7
C4b output clock period
t
240
123
110
282
165
123
10
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 17).
P4o
C4b output clock width (HIGH)
C4b output clock width (LOW)
C4b output clock rise time
C4b clock output fall time
t
W4oH
t
W4oL
t
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
rC4
t
10
fC4
Frame pulse output delay
(HIGH to LOW) from C4b
t
50
40
ns
ns
FPL
8
Frame pulse output delay
(LOW to HIGH) from C4b
Test load circuit 1 (Fig. 17).
t
FPH
D
P
L
L
9
Frame pulse (F0b) width
C4o delay - LOW to HIGH
C4o delay - HIGH to LOW
t
200
-10
245
45
ns
ns
ns
WFP
4oLH
4oHL
10
11
12
t
t
45
#2
C4b to C2o delay (LOW to
HIGH)
t
t
+10
20
ns
ns
42LH
42HL
13
C4b to C2o delay (HIGH to
LOW)
14
15
16
17
18
19
20
C2o clock period
t
486
244
233
523
291
244
10
ns
ns
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 10).
P2o
C2o clock width (HIGH)
C2o clock width (LOW)
C2o clock rise time
t
W2oH
t
W2oL
t
Test load circuit 1 (Fig. 10).
Test load circuit 1 (Fig. 10).
rC2
C2o clock fall time
t
10
fC2
C2o delay - LOW to HIGH
t
20
2oLH
C2o delay - HIGH to LOW
t
-5
30
2oHL
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C8Kb
as
Output
V
OH
V
OL
C8Kb
as
V
IH
Input
V
IL
t
84H
t
W4oH
V
OH
C4b
F0b
V
OL
t
P4o
t
W4oL
t
t
FPH
FPL
V
OH
V
OL
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
3-39
MT8940 ISO-CMOS
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 13)
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
CV/CVb (1.544 MHz) Setup time
CV/CVb (1.544 MHz) Hold time
t
25
ns
ns
S15
t
110
H15
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
V
OH
Boundary between ST-BUS channel 2 bit 4 and
channel 2 bit 3
F0b
C2o
V
OL
20 CYCLES
V
OH
V
OL
t
H15
t
S15
V
OH
CV
V
OL
t
H15
t
S15
V
OH
CVb
V
OL
Figure 13 - F0b from DPLL #2 is Looped Back as Input to DPLL #1 (T1 Line synchronized to ST-BUS)
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 14)
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Master clocks input rise time
Master clocks input fall time
t
10
10
ns
ns
r
t
f
C
L
O
C
K
S
For DPLL #1, while operating to
provide the T1 clock signal.
Master clock period
(12.355MHz)
t
t
80.930 80.938 80.946
61.018 61.020 61.022
ns
ns
P12
P16
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
4
Master clock period
(16.388MHz)
5
6
Duty Cycle of master clocks
Lock-in Range (For each PLL)
45
50
55
%
With the Master clocks as shown
above.
-1.5
+1.04
Hz
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
t
f
r
2.4 V
1.5 V
0.4 V
Master clock
inputs
t
or t
P16
P12
Figure 14 - Master Clock Inputs
3-40
ISO-CMOS MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 15)
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
F0b input pulse width (LOW)
C4b input clock period
t
40
.080
25
ns
µs
ns
ns
WFP
t
50
P4o
Frame pulse (F0b) setup time
t
FS
Frame pulse (F0b) hold time
t
5
FH
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
WFP
V
IH
F0b
C4b
V
IL
t
FH
V
IH
V
IL
t
FS
t
P4o
Figure 15 - External Inputs on C4b and F0b for the DPLL #2
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 16)
SS
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
Delay from Enable to Output
(HIGH to THREE STATE)
t
15
65
55
40
50
ns
ns
ns
ns
Test load circuit 3 (Fig.17)
PHZ
O
U
T
P
U
T
Delay from Enable to Output
(LOW to THREE STATE)
t
10
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
PLZ
Delay from Enable to Output
(THREE STATE to HIGH)
t
PZH
Delay from Enable to Output
(THREE STATE to LOW)
t
PZL
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
6 ns
t
6 ns
f
r
3.0 V
2.7 V
1.3 V
0.3 V
Enable
Input
t
PZL
t
PLZ
Output
LOW to
OFF
1.3 V
10%
90%
t
PHZ
t
PZH
Output
HIGH
to OFF
1.3 V
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
Figure 16 - Three State Outputs and Enable Timings
3-41
MT8940 ISO-CMOS
AC Electrical Characteristics† - Uncommitted NAND Gate
Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
Propagation delay (LOW to
HIGH), input Ai or Bi to output
t
t
25
40
ns
Test load circuit 1 (Fig. 17)
PLH
Propagation delay (HIGH to
LOW), input Ai or Bi to output
20
40
ns
Test load circuit 1 (Fig. 17)
PHL
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
V
DD
V
DD
R =1kΩ
L
Test
point
A
B
R =1kΩ
From
L
From
From
Test
point
Test
point
output
output
output
under test
S
under test
under test
1
V
SS
C =50pF
L
C =50pF
C =50pF
Note: S is in position A
L
L
1
when measuring t
PLZ
and t and in position B
PZ
when measuring t
PZH
and
PHZ
t
Test load circuit- 1
Test load circuit- 2
Test load circuit- 3
Figure 17 - Test Load Circuits
3-42
Package Outlines
3
2
1
E
1
E
n-2 n-1 n
D
A
A
2
L
C
e
A
e
C
b
e
e
2
B
b
Notes:
D
1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
8-Pin
16-Pin
Plastic
18-Pin
Plastic
20-Pin
Plastic
DIM
A
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
0.210 (5.33)
0.195 (4.95)
0.210 (5.33)
0.195 (4.95)
0.210 (5.33)
0.195 (4.95)
0.210 (5.33)
0.195 (4.95)
0.115 (2.92)
0.115 (2.92)
0.115 (2.92)
0.115 (2.92)
A
2
0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
b
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
b
2
0.008
(0.203)
0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)
C
0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)
D
0.005 (0.13)
0.300 (7.62)
0.240 (6.10)
0.005 (0.13)
0.300 (7.62)
0.240 (6.10)
0.005 (0.13)
0.300 (7.62)
0.240 (6.10)
0.005 (0.13)
0.300 (7.62)
0.240 (6.10)
D
1
0.325 (8.26)
0.280 (7.11)
0.325 (8.26)
0.280 (7.11)
0.325 (8.26)
0.280 (7.11)
0.325 (8.26)
0.280 (7.11)
E
E
1
0.100 BSC (2.54)
0.300 BSC (7.62)
0.100 BSC (2.54)
0.300 BSC (7.62)
0.100 BSC (2.54)
0.300 BSC (7.62)
0.100 BSC (2.54)
0.300 BSC (7.62)
e
e
A
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
L
0.430 (10.92)
0.060 (1.52)
0.430 (10.92)
0.060 (1.52)
0.430 (10.92)
0.060 (1.52)
0.430 (10.92)
0.060 (1.52)
e
B
0
0
0
0
e
C
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
General-8
Package Outlines
3
2
1
E
1
E
n-2 n-1 n
D
α
A
A
2
L
C
e
A
b
e
e
2
B
b
Notes:
D
1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
22-Pin
Plastic
24-Pin
Plastic
28-Pin
Plastic
40-Pin
Plastic
DIM
A
Min
Max
Min
Max
Min
Max
Min
Max
0.210 (5.33)
0.195 (4.95)
0.250 (6.35)
0.195 (4.95)
0.250 (6.35)
0.195 (4.95)
0.250 (6.35)
0.195 (4.95)
0.125 (3.18)
0.125 (3.18)
0.125 (3.18)
0.125 (3.18)
A
2
0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)
0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)
b
b
2
C
1.050 (26.67) 1.120 (28.44) 1.150 (29.3)
0.005 (0.13) 0.005 (0.13)
1.290 (32.7)
1.380 (35.1)
0.005 (0.13)
1.565 (39.7)
1.980 (50.3)
0.005 (0.13)
2.095 (53.2)
D
D
1
0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)
0.290 (7.37) .330 (8.38)
0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)
0.246 (6.25) 0.254 (6.45)
0.100 BSC (2.54)
E
E
0.330 (8.39)
E
1
1
E
0.100 BSC (2.54)
0.400 BSC (10.16)
0.100 BSC (2.54)
0.600 BSC (15.24)
0.100 BSC (2.54)
0.600 BSC (15.24)
e
0.600 BSC (15.24)
0.300 BSC (7.62)
e
e
e
A
A
B
0.430 (10.92)
0.115 (2.93)
0.160 (4.06)
15°
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
15°
0.115 (2.93)
0.200 (5.08)
15°
L
15°
α
Shaded areas for 300 Mil Body Width 24 PDIP only
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