MT8940AE1 [ZARLINK]
Telecom Circuit, 1-Func, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24;
| 型号： | MT8940AE1 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Telecom Circuit, 1-Func, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24 电信 光电二极管 电信集成电路 |
| 文件： | 总23页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO-CMOS ST-BUSTM FAMILY MT8940
T1/CEPT Digital Trunk PLL
Data Sheet
September 2005
Features
•
Provides T1 clock at 1.544 MHz locked to input
frame pulse
Ordering Information
MT8940AE
MT8940AE1
24 Pin PDIP
24 Pin PDIP*
*Pb Free Matte Tin
Tubes
Tubes
•
Sources CEPT (30+2) Digital Trunk/ST-BUS clock
and timing signals locked to internal or external 8
kHz signal
-40°C to +85°C
•
•
•
•
TTL compatible logic inputs and outputs
Uncommitted 2-input NAND gate
Single 5 volt power supply
Description
The MT8940 is a dual digital phase-locked loop
providing the timing and synchronization signals for the
T1 or CEPT transmission links and the ST-BUS. The
first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
Low power ISO-CMOS technology
Applications
•
Synchronization and timing control for T1
and CEPT digital trunk transmission links
•
ST- BUS clock and frame pulse source
The MT8940 is fabricated in Zarlink’s ISO-CMOS
technology.
CVb
F0i
Variable
DPLL #1
CV
Clock
Control
2:1 MUX
C12i
ENCV
MS0
Frame Pulse
Control
Mode
Selection
Logic
MS1
MS2
F0b
Input
Selector
MS3
C4b
4.096 MHz
Clock
Control
C8Kb
C4o
ENC4o
C16i
DPLL #2
C2o
Clock
Generator
2.048 MHz
Clock
Control
C2o
Ai
Bi
ENC2o
Yo
VDD
VSS
RST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8940
Data Sheet
24
1
2
3
4
5
6
7
8
ENVC
MS0
C12i
MS1
F0i
VDD
RST
CV
CVb
Yo
23
22
21
20
19
18
17
16
15
14
13
F0b
Bi
Ai
MS2
C16i
ENC4o
C8Kb
C4o
MS3
ENC2o
C2o
C2o
C4b
9
10
11
12
VSS
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
ENCV
Variable clock enable (TTL compatible input) - This input (pulled internally to VDD) directly
controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables CV and
when LOW, puts it in high impedance condition. It also controls the three states of CVb signal (pin
21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high
impedance state. However, if MS1 is HIGH, CVb is always an input.
2
3
4
5
6
MS0
C12i
MS1
F0i
Mode select ‘0’ input (TTL compatible) - This input (pulled internally to VSS) in conjunction with
MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2).
Clock 12.355 MHz input (TTL compatible) - Master clock input at 12.355 MHz ±100 ppm for
DPLL #1.
Mode select-1 input (TTL compatible) - This input (pulled internally to VSS) in conjunction with
MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2)
Frame pulse input (TTL compatible) - This is the frame pulse input (pulled internally to VDD) at 8
kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544 MHz) clock.
F0b
Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending on the
minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts as an input
(pulled internally to VDD) to an external frame pulse.
7
8
MS2
C16i
Mode select-2 input (TTL compatible) - This input (pulled internally to VDD) in conjunction with
MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.)
Clock 16.388 MHz input (TTL compatible) - Master clock input at 16.388 MHz±32 ppm for DPLL
#2.
9
ENC4o
C8Kb
Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally to
V
DD) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance condition.
10
Clock 8 kHz- Bidirectional (TTL compatible input and open drain output with 100 K internal
resistor to VDD) - This is the 8 kHz input signal on the rising edge of which DPLL #2 locks during its
NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz signal
provided by DPLL #1, which is also connected internally to DPLL #2.
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
Pin Description (continued)
Pin #
Name
Description
11
C4o
Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin 13 (C4b)
at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high impedance state of this
output is controlled by ENC4o (pin 9).
12
13
VSS
C4b
Ground (0 Volt)
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When the
mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the falling edge in
the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input (pulled internally to VDD) to an
external clock at 4.096 MHz.
14
15
16
C2o
C2o
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a
falling edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by
ENC2o (pin 16).
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a
rising edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by
ENC2o (pin 16).
ENC2o
Enable 2.048 MHz clock (TTL compatible input) - This active high input (pulled internally to
VDD) enables both C2o and C2o outputs (pins 14 and 15). When LOW, these outputs are in high
impedance condition.
17
MS3
Mode select 3 input (TTL compatible) - This input (pulled internally to VDD) in conjunction with
MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.)
18,19
Ai, Bi
Inputs A and B (TTL compatible) -These are the two inputs (pulled internally to VSS) of the
uncommitted NAND gate.
20
21
Yo
Output Y (Totem pole output) - Output of the uncommitted NAND gate.
CVb
Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When acting as an
output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the 1.544 MHz clock
locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an input (pulled internally to
V
DD) to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz to DPLL
#2.
22
CV
Variable clock (Three state output) - This is the inverse output of the signal appearing on pin 21, the
high impedance state of which is controlled ENCV (pin 1).
23
24
RST
VDD
Reset (Schmitt trigger input) -This input (active LOW) evokes reset condition for the device.
VDD (+5 V) Power supply.
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
Functional Description
The MT8940 is a dual digital phase-locked loop providing the timing and synchronization signals to the interface
circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in Figure 1, it has two digital
phase-locked loops (DPLLs), associated output controls and the mode selection logic circuits. The two DPLLs,
although similar in principle, operate independently to provide T1 (1.544 MHz) and CEPT (2.048 MHz) transmission
clocks, and ST-BUS timing signals.
The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz
where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock
frequency is corrected. The MT8940 achieves the frequency correction in both directions by using the master clock
at a slightly higher frequency and dividing it unaltered or stretching its period (at two discrete instants in a frame)
before the division depending on the phase comparison output.
When the input frequency is higher, the
unchanged master clock is divided, thus effectively speeding-up the locally generated clock and eventually pulling it
in synchronization with the input. If the input frequency is lower than the divided master clock, the period of the
master clock is stretched by half a cycle, at two discrete instants in a phase sampling period. This introduces a total
delay of one master clock period over the sampling duration, which is then divided to generate the local signal
synchronous with the input. Once the output is phase-locked to the active edge of the input, the circuit will maintain
the locked condition as long as the input frequency is within the lock-in range (±1.04 Hz) of the DPLLs. The lock-in
range is wide enough to meet the CCITT line rate specification (1.544 MHz±130ppm and 2.048 MHz ±50ppm) for
the High Capacity Terrestrial Digital Service.
Master Clock
Frequency
÷8
(12.355 MHz/
16.388 MHz)
Correction
Output
(1.544 MHz /
2.048 MHz)
Input (8 kHz)
Phase
Comparison
÷193 /
÷256
Figure 3 - DPLL Principle
The phase sampling is done once in a frame (8 kHz) and the divisions are set at 8 and 193 for DPLL #1, which
locks on to the falling edge of the input at 8 kHz to generate T1 (1.544 MHz) clock. Although the phase sampling
duration is the same for DPLL #2, the divisions are set at 8 and 256 to provide the CEPT/ST-BUS clock at
2.048 MHz synchronized to the rising edge of the input signal (8 kHz). The master clock source is specified to be at
12.355 MHz ±100 ppm for DPLL #1 and 16.388 MHz ±32 ppm for DPLL #2 over the entire temperature range of
operation.
The inputs MS0 to MS3 are used to select the operating mode of the MT8940, see Tables 1 to 4. All the outputs are
individually controlled to the high impedance condition by their respective enable controls. The uncommitted NAND
gate is available for use in applications involving Zarlink’s MT8976/MH89760 (T1 interfaces) and
MT8979/MH89790 (CEPT interfaces).
Modes of Operation
The operation of the MT8940 is categorized into major and minor modes. The major modes are defined for both
DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by MS2 and MS3, and are applicable
only to DPLL #2. There are no minor modes for DPLL #1.
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
Major modes of the DPLL #1
DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in
NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse
F0i (8 kHz). DPLL#1 requires a master clock input of 12.355 MHz±100 ppm (C12i). In the second and third major
modes (MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin
21). The division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output is
connected internally to DPLL #2, which operates in SINGLE CLOCK mode.
Major modes of the DPLL #2
There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes
DPLL #2 provides the CEPT PCM 30 timing, and the ST-BUS clock and framing signals.
In NORMAL mode, DPLL #2 provides the CEPT and ST-BUS compatible timing signals locked to the rising edge of
the 8 kHz input signal (C8Kb). These signals are the 4.096 MHz (C4o and C4b) and the 2.048 MHz (C2o and C2o)
clocks, and the 8 kHz frame pulse (F0b), which are derived from the 16.388 MHz master clock. This mode can also
provide the ST-BUS timing and framing signals with the input (C8Kb) tied HIGH and the master clock set at 16.384 MHz.
The DPLL makes no correction in this configuration and provides the timing signals compatible to the ST-BUS format
without any jitter.
Mode of
operation
MS0 MS1
Function
X
0
1
1
NORMAL
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the
input frame pulse (F0i).
0
DIVIDE-1
DIVIDE-2
DPLL #1 divides the CVb input by
193. The divided output is connected
to DPLL #2.
1
DPLL #1 divides the CVb input by
256. The divided output is connected
to DPLL #2.
Note: X: indicates don’t care
Table 1 - Major Modes of the DPLL #1
In FREE-RUN mode, DPLL #2 generates CEPT and ST-BUS timing and framing signals with no external inputs
except the master clock set at 16.388 MHz. Since the master clock source is set at a higher frequency than the
nominal value, the DPLL makes the necessary corrections to deliver the averaged timing signals compatible to the
ST-BUS format.
The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT
and ST-BUS compatible timing signals synchronized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE
mode. When SINGLE CLOCK-1 mode is selected for DPLL #2, it automatically selects the DIVIDE-1 mode for
DPLL #1, and thus, an external 1.544 MHz clock signal applied at CVb (pin 21) is divided by DPLL #1 to generate
the internal signal at 8 kHz onto which DPLL #2 locks. Similarly when SINGLE CLOCK-2 mode is selected, DPLL
#1 is in DIVIDE-2 mode, with an external signal of 2.048 MHz providing the internal 8 kHz signal to DPLL #2. In
both these modes, this internal signal is available on C8Kb (pin 10) and DPLL #2 locks to its falling edge to provide
the CEPT and ST-BUS compatible timing signals. This is in contrast to the Normal mode where these timing signals
are synchronized with the rising edge of the 8 kHz signal on C8Kb.
Minor modes of the DPLL #2
The minor modes for DPLL #2 depends upon the status of the mode select bits MS2 and MS3 (pins 7 and 17).
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
Mode of
operation
MS0 MS1
Function
0
1
0
0
0
1
NORMAL Provides ST-BUS/CEPT timing signals
locked to the rising edge of the 8 kHz
input signal at C8Kb.
FREE-RUN Provides ST-BUS timing and framing
signals with no external inputs, except the
master clock.
SINGLE
Provides the CEPT/ST-BUS compatible
CLOCK-1 timing signals locked to the falling edge of
the 8 kHz internal signal provided by
DPLL #1.
1
1
SINGLE
Provides CEPT/ST-BUS timing signals
CLOCK-2 locked to the falling edge of the 8kHz
internal signal provided by DPLL #1.
Table 2 - Major Modes of the DPLL #2
When MS3 is HIGH, DPLL #2 operates in any of the major modes as selected by MS0 and MS1.
When MS3 is LOW, it overrides the major mode selected and DPLL #2 accepts an external clock of 4.096 MHz on
C4b (pin 13) to provide the 2.048 MHz clocks (C2o and C2o) and the 8 kHz frame pulse (F0b) compatible with the
ST-BUS format.
The mode select bit MS2, controls the signal direction of F0b (pin 6). When MS2 is LOW, F0b is an input for an
external frame pulse at 8 kHz. This input is effective only if MS3 is also LOW and C4b is accepting a 4.096 MHz
external clock, which has a proper phase relationship with the external input on F0b (refer to Figure 15). Otherwise, the
input on pin F0b will have no bearing on the operation of DPLL #2, unless it is in FREE-RUN mode as selected by MS0
and MS1. In FREE-RUN mode, the input on F0b is treated the same way as the C8Kb input in NORMAL mode. The
frequency of the input signal on F0b should be 16 kHz for DPLL #2 to provide the ST-BUS compatible clocks at 4.096
MHz and 2.048 MHz.
MS2 MS3
Functional Description
1
1
Provides ST-BUS 4.096 MHz and 2.048 MHz clocks and
8kHz frame pulse depending on the major mode selected.
Provides ST-BUS 4.096 MHz & 2.048 MHz clocks
depending on the major mode selected while F0b acts as
an input. However, the input on F0b has no effect on the
operation of DPLL #2 unless it is in FREE-RUN mode.
Overrides the major mode selected and accepts properly
phase related external 4.096 MHz clock and 8 kHz frame
pulse to provide the ST-BUS compatible clock at
2.048 MHz.
0
1
0
1
0
0
Overrides the major mode selected and accepts a 4.096
MHz external clock to provide the ST-BUS clock and
frame pulse at 2.048 MHz and 8 kHz, respectively.
Table 3 - Minor Modes of the DPLL #2
When MS2 is HIGH, the F0b pin provides the ST-BUS frame pulse output locked to the 8kHz internal or external
signal as determined by the other mode select pins MS0, MS1 and MS3.
Table 4 summarizes the modes of the two DPLLs. It should be noted that each of the major modes selected for
DPLL #2 can have any of the minor modes, although some of the combinations are functionally similar. The
required operation of both DPLL#1 and DPLL#2 must be considered when determining MS0-MS3.
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
M
O
D
E
#
Operating Modes
MS MS MS MS
0
1
2
3
DPLL #1
DPLL #2
Properly phase related External 4.096 MHz clock
and 8 kHz frame pulse provide the ST-BUS clock at
2.048 MHz.
NORMAL MODE
NORMAL MODE
0
0
0
0
0
NORMAL MODE
F0b is an input but has no function in this mode.
1
2
0
0
0
0
0
1
1
0
External 4.096 MHz provides the ST-BUS clock and
Frame Pulse at 2.048 MHz and 8 kHz, respectively.
NORMAL MODE
NORMAL MODE:
NORMAL MODE:
Provides the T1 (1.544 MHz) clock synchronized to Provides the CEPT/ST-BUS compatible timing
3
0
0
1
1
the falling edge of the
input frame pulse (F0i).
signals locked to the 8 kHz input signal (C8Kb).
DIVIDE-1 MODE
Same as mode ‘0’.
4
5
6
0
0
0
1
1
1
0
0
1
0
1
0
SINGLE CLOCK-1 MODE
F0b is an input, but has no function in this mode.
DIVIDE-1 MODE
DIVIDE-1 MODE
DIVIDE-1 MODE:
Same as mode 2.
SINGLE CLOCK-1 MODE:
Divides the CVb input by 193. The divided output is Provides the CEPT/ST-BUS compatible timing
7
0
1
1
1
connected to DPLL #2.
signals locked to the 8 kHz internal signal provided
by DPLL #1.
NORMAL MODE
NORMAL MODE
Same as mode ‘0’.
8
9
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
NORMAL MODE
NORMAL MODE
Same as mode 2.
10
11
FREE-RUN MODE:
Provides the T1 (1.544 MHz) clock synchronized to Provides the ST-BUS timing signals with no
the falling edge of input frame pulse (F0i).
external inputs except the master clock.
DIVIDE-2 MODE
Same as mode ‘0’.
12
13
14
1
1
1
1
1
1
0
0
1
0
1
0
DIVIDE-2 MODE
SINGLE CLOCK-2 MODE:
F0b is an input, but has no function in this mode.
DIVIDE-2 MODE
DIVIDE-2 MODE:
Same as mode 2.
SINGLE CLOCK-2 MODE:
Divides the CVb input by 256. The divided output is Provides the CEPT/ST-BUS compatible timing
15
1
1
1
1
connected to DPLL#2.
signals locked to the 8 kHz internal signal provided
by DPLL #1.
Table 4 - Summary of Modes of Operation - DPLL #1 and #2
Applications
The following figures illustrate how the MT8940 can be used in a minimum component count approach to providing
the timing and synchronization signals for the Zarlink T1 and CEPT interfaces, and the ST-BUS. The hardware
selectable modes and the independent control over each PLL adds flexibility to the interface circuits. It can be
easily reconfigured to provide the timing and control signals for both at the master and slave ends of the link.
Synchronization and Timing Signals for the T1 Transmission Link
Figures 4 and 5 show examples of how to generate the timing signals for the master and slave ends of a T1 link.
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
At the master end of the link (Figure 4), DPLL #2 is the source of the ST-BUS signals derived from the 4.096 MHz
system clock. The frame pulse output is looped back to DPLL #1 (in NORMAL mode), which locks to it to generate
the T1 line clock. The timing relationship between the 1.544 MHz T1 clock and the 2.048 MHz ST-BUS clock meets
the requirements of the MH89760/760B. The crystal clock at 12.355 MHz is used by DPLL #1 to generate the 1.544
MHz clock, while DPLL #2 uses the 4.096 MHz system clock to provide the ST-BUS timing signals. The ST-BUS
signals can also be obtained from DPLL #2 in FREE-RUN mode, using a crystal clock at 16.388 MHz instead of
4.096 MHz system clock. The uncommitted NAND gate converts the received signals, RxA and RxB of the
MH89760 to a single Return to Zero (RZ) input for the clock extraction circuits of the MH89760. This is not required
for the MH89760B. The generated ST-BUS signals can be used to synchronize the system and the switching
equipment at the master end.
At the slave end of the link (Figure 5) both the DPLLs are in NORMAL mode with DPLL #2 providing the ST-BUS
timing signals locked to the 8 kHz frame pulse (E8Ko) extracted from the received signal on the T1 line. The
regenerated frame pulse is looped back to DPLL #1 to provide the T1 line clock as at the master end. The 12.355
MHz and 16.388 MHz crystal clock sources are necessary for DPLL #1 and #2.
Synchronization and Timing Signals for the CEPT Transmission Link
The MT8940 can be used to provide the timing and synchronization signals for the MH89790/790B, Zarlink’s
CEPT(30+2) digital trunk interface hybrid. Since the operational frequencies of the ST-BUS and the CEPT primary
multiplex digital trunk are same, only DPLL #2 is required to achieve synchronization between the two.
Figures 6 and 7 show how the MT8940 can be used to synchronize the ST-BUS and the CEPT transmission link at
the master and slave ends, respectively.
MT8980/81
Crystal Clock
MT8940
(12.355 MHz
VDD
CV
±100 ppm)
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89760
C1.5i
DSTi
C2i
F0i
DSTo
F0i
C12i
C4b
C2o
CSTi
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
CSTo
TxT
TxR
RxT
RxR
TRANSMIT
RECEIVE
T1
RxA
4.096 MHz
System Clock
LINK
F0b
Yo
RxB
RxD
(1.544 Mbps)
(ST-BUS
compatible)
Bi
VSS
RST
MODE OF OPERATION FOR THE MT8940
DPLL #1 - NORMAL (MS0 = X; MS1 = 0)
DPLL #2 - OVERRIDE THE MAJOR MODES (MS2 = 1; MS3 = 0)
Figure 4 - Synchronization at the Master End of the T1 Transmission Link
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
MT8980/81
Crystal Clock
MT8940
(12.355 MHz
± 100 ppm)
VDD
CV
MS0
MS1
MS2
MS3
MH89760
ST-BUS
SWITCH
C1.5i
DSTi
C2i
F0i
DSTo
F0i
C12i
C4b
C2o
CSTi
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
CSTo
TxT
TxR
RxT
RxR
TRANSMIT
RECEIVE
T1
RxA
LINK
F0b
Yo
RxB
RxD
(1.544 Mbps)
Bi
VSS
Crystal Clock
RST
(16.388 MHz
± 32 ppm)
Mode of Operation for the MT8940
DPLL #1 - NORMAL (MS1=0)
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 5 - Synchronization at the Slave End of the T1 Transmission Link
MT8980/81
MT8940
VDD
C4b
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89790
DSTi
C2i
F0i
DSTo
F0i
C12i
CSTi0
CSTi1
C2o
F0b
Yo
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
4.096 MHz
System Clock
CSTo
OUTA
OUTB
RxT
(ST-BUS
Compatible)
RxA
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
TRANSMIT
RECEIVE
RxB
RxD
Bi
VSS
RST
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - OVERRIDE MAJOR MODES (MS0=X; MS1=X
MS2=1; MS3=0)
Figure 6 - Synchronization at the Master End of the CEPT Digital Transmission Link
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Zarlink Semiconductor Inc.
MT8940
Data Sheet
Generation of ST-BUS Timing Signals
The MT8940 can source the properly formatted ST-BUS timing and control signals with no external inputs except
the crystal clock. This can be used as the standard timing source for ST-BUS systems or any other system with
similar clock requirements. Figure 8 shows two such applications using only DPLL #2. In one case, the MT8940
is in FREE-RUN mode with an oscillator input of 16.388 MHz. This forces the DPLL to correct at a rate of 4 kHz to
maintain the ST-BUS clocks, which therefore, will be jittered. In the other case, the oscillator input is 16.384 MHz
(exactly eight times the output frequency) and DPLL #2 operates in NORMAL mode with C8Kb input tied HIGH.
Since no corrections are necessary, the output is free from jitter. DPLL #1 is completely free in both cases and
available for any other purpose.
MT8940
MT8980/81
VDD
MS0
MH89790
MS1
ST-BUS
MS2
SWITCH
C4b
C2o
DSTi
MS3
C2i
F0i
DSTo
F0i
C12i
CSTi0
CSTi1
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
Crystal Clock
CSTo
OUTA
OUTB
RxT
(16.388 MHz
± 32 ppm)
F0b
Yo
RxA
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
TRANSMIT
RECEIVE
RxB
RxD
Bi
VSS
RST
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 7 - Synchronization at the Slave End of the CEPT Digital Transmission Link
10
Zarlink Semiconductor Inc.
MT8940
Data Sheet
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0; MS2=1;
MS3=1)
MT8940
MT8940
VDD
VDD
MS0
MS1
MS2
MS3
MS0
MS1
MS2
MS3
C4o
C4b
C4o
C4b
ST-BUS
F0i
ST-BUS
F0i
C12i
C12i
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
TIMING
TIMING
Crystal Clock
C2o
C2o
Crystal Clock
(16.388 MHz
± 32 ppm)
(16.388 MHz
± 32 ppm)
SIGNALS
SIGNALS
C2o
F0b
C2o
F0b
Bi
Bi
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
VSS
VSS
RST
RST
MS2=1; MS3=1)
Figure 8 - Generation of the ST-BUS Timing Signals
11
Zarlink Semiconductor Inc.
MT8940
Data Sheet
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
2
3
4
5
6
7
Supply Voltage
VDD
VI
-0.3
7.0
V
Voltage on any pin
VSS-0.5
VDD+0.5
±10
V
Input/Output Diode Current
Output Source or Sink Current
DC Supply or Ground Current
Storage Temperature
IIK/OK
IO
IDD/ISS
TST
mA
mA
mA
oC
±25
±50
-65
150
Package Power Dissipation
LCC
PD
600
mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Supply Voltage
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
3
4
VDD
VIH
VIL
TA
4.75
2.4
5.0
5.25
VDD
0.4
V
V
Input HIGH Voltage
Input LOW Voltage
Operating Temperature
For 400 mV noise margin
For 400 mV noise margin
VSS
-40
V
25
85
oC
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
VDD=5.0 V±5%; VSS=0V; TA=-40 to 85°C.
Characteristics
Sym. Min. Typ.‡ Max.
Units
Test Conditions
S
U
P
IDD
IDDS
8
15
100
mA
Under clocked condition,
with the inputs tied to the
same supply rail as the
corresponding pull-up /
down resistors.
1
Supply Current
2
3
4
5
6
7
8
Input HIGH voltage (For all the
inputs except pin 23)
VIH
V+
2.0
2.8
V
V
Positive-going threshold voltage
(For pin 23)
I
N
Input LOW voltage (For all the
inputs except pin 23)
VIL
V-
0.8
1.5
V
Negative-going threshold voltage
(For pin 23)
V
Output current HIGH (For all the
outputs except pin 10)
IOH
IOL
IOL
-9.5
4.5
2.0
mA
mA
mA
VOH=2.4 V
VOL=0.4 V
VOL=0.4 V
O
U
T
Output current LOW (For all the
outputs except pin 10)
Output current LOW (pin 10)
12
Zarlink Semiconductor Inc.
MT8940
Data Sheet
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
VDD=5.0 V±5%; VSS=0V; TA=-40 to 85°C.
Characteristics
Sym. Min. Typ.‡ Max.
Units
Test Conditions
VI/O=VSS or VDD
9
Leakage current on bidirect-ional
pins and all inputs except C12i,
C16i, RST
IIZ/OZ
±150
µA
10
Leakage current on all outputs and IIZ/OZ
C12i, C16i, RST inputs
±1
±10
µA
VI/O=VSS or VDD
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 9)
Characteristics
Sym.
Min. Typ.‡ Max. Units
Test Conditions
1
Frame pulse input (F0i) to CVb
output (1.544 MHz) delay
tF15H
-40
75
ns
2
3
4
CVb output (1.544 MHz) rise time
CVb output (1.544 MHz) fall time
tr1.5
tf1.5
10
12
15
15
ns
ns
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
D
P
L
L
CVb output (1.544 MHz) clock
period
tP15
648
320
314
690
386
327
ns
ns
ns
5
6
CVb output (1.544 MHz) clock
width (HIGH)
tW15H
tW15L
#1
CVb output (1.544 MHz) clock
width (LOW)
7
8
CV delay (HIGH to LOW)
CV delay (LOW to HIGH)
t15HL
t15LH
5
30
10
ns
ns
-12
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VIH
F0i
VIL
tF15H
tP15
tf1.5
tW15H
VOH
CVb
VOL
tW15L
t15HL
tr1.5
t15LH
VOH
CV
VOL
Figure 9 - Timing Information for DPLL #1 in NORMAL Mode
13
Zarlink Semiconductor Inc.
MT8940
Data Sheet
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 10)
Min
.
Characteristics
Sym.
tC8HH
tC8LL
Typ.‡
Max. Units
Test Conditions
1
2
3
4
5
C8Kb output (8kHz) delay (HIGH
to HIGH)
130
130
ns
ns
Test load circuit 2 (Fig. 17).
Test load circuit 2 (Fig. 17).
C8Kb output (8 kHz) delay (LOW
to LOW)
50
D
P
L
L
C8Kb output duty cycle
66
50
%
%
In Divide -1 Mode
In Divide - 2 Mode
Inverted clock output delay
(HIGH to LOW)
#1
tICHL
tICLH
40
35
75
60
ns
ns
Inverted clock output delay (LOW
to HIGH)
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VIH
CVb
VIL
tICHL
tICLH
VOH
VOL
CV
tC8HH
tC8LL
VOH
VOL
C8Kb
Figure 10 - DPLL #1 in DIVIDE Mode
14
Zarlink Semiconductor Inc.
MT8940
Data Sheet
tWFP
VOH
VOL
F0b
tFPL
tFPH
tfC4
trC4
VOH
VOL
C4b
C4o
t4oLH
t4oHL
VOH
VOL
t42LH
tP2o
t42HL
tW2oH
trC2
tfC2
VOH
VOL
C2o
C2o
tW2oL
t2oLH
t2oHL
VOH
VOL
Figure 11 - Timing Information on DPLL #2 Outputs
15
Zarlink Semiconductor Inc.
MT8940
Data Sheet
AC Electrical Characteristics†-Voltages are with respect to ground (VSS) unless otherwise stated.(Ref. Figures 11&12)
Characteristics
Sym.
Min. Typ.‡ Max. Units
Test Conditions
1
C4b output delay (HIGH to
LOW) from C8Kb input/output
Test load circuit 2 (Fig. 17) on
C8Kb.
t84H
-25
75
ns
2
3
4
5
6
7
C4b output clock period
tP4o
tW4oH
tW4oL
trC4
240
123
110
282
165
123
10
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 17).
C4b output clock width (HIGH)
C4b output clock width (LOW)
C4b output clock rise time
C4b clock output fall time
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
tfC4
10
Frame pulse output delay (HIGH
to LOW) from C4b
tFPL
tFPH
50
40
ns
ns
8
Frame pulse output delay
(LOW to HIGH) from C4b
Test load circuit 1 (Fig. 17).
D
P
L
L
9
Frame pulse (F0b) width
C4o delay - LOW to HIGH
C4o delay - HIGH to LOW
tWFP
t4oLH
t4oHL
200
-10
245
45
ns
ns
ns
10
11
12
45
#2
C4b to C2o delay (LOW to
HIGH)
t42LH
t42HL
+10
20
ns
ns
13
C4b to C2o delay (HIGH to
LOW)
14
15
16
17
18
19
20
C2o clock period
tP2o
tW2oH
tW2oL
trC2
486
244
233
523
291
244
10
ns
ns
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 10).
C2o clock width (HIGH)
C2o clock width (LOW)
C2o clock rise time
Test load circuit 1 (Fig. 10).
Test load circuit 1 (Fig. 10).
C2o clock fall time
tfC2
10
C2o delay - LOW to HIGH
C2o delay - HIGH to LOW
t2oLH
t2oHL
20
-5
30
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
16
Zarlink Semiconductor Inc.
MT8940
Data Sheet
C8Kb
as
Output
VOH
VOL
C8Kb
as
VIH
VIL
Input
t84H
tW4oH
VOH
VOL
C4b
F0b
tP4o
tW4oL
tFPL
tFPH
VOH
VOL
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 13)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
CV/CVb (1.544 MHz) Setup time
CV/CVb (1.544 MHz) Hold time
tS15
tH15
25
ns
ns
110
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VOH
Boundary between ST-BUS channel 2 bit 4 and
F0b
C2o
VOL
channel 2 bit 3
20 CYCLES
VOH
VOL
tH15
tS15
VOH
VOL
CV
tH15
tS15
VOH
VOL
CVb
Figure 13 - F0b from DPLL #2 is Looped Back as Input to DPLL #1 (T1 Line synchronized to ST-
BUS)
17
Zarlink Semiconductor Inc.
MT8940
Data Sheet
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 14)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
3
Master clocks input rise time
Master clocks input fall time
Master clock period (12.355MHz)
tr
tf
10
10
ns
ns
For DPLL #1, while
operating to provide the T1
clock signal.
tP12
80.930
61.018
80.938
80.946
61.022
ns
ns
C
L
O
C
K
S
4
For DPLL #2, while
operating to provide the
CEPT and ST-BUS timing
signals.
Master clock period (16.388MHz) tP16
61.020
50
5
6
Duty Cycle of master clocks
Lock-in Range (For each PLL)
45
55
%
With the Master clocks as
shown above.
-1.5
+1.04
Hz
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tr
tf
2.4 V
1.5 V
0.4 V
Master clock
inputs
tP12 or tP16
Figure 14 - Master Clock Inputs
18
Zarlink Semiconductor Inc.
MT8940
Data Sheet
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 15)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
3
4
F0b input pulse width (LOW)
C4b input clock period
tWFP
tP4o
tFS
40
.080
25
ns
µs
ns
ns
50
Frame pulse (F0b) setup time
Frame pulse (F0b) hold time
tFH
5
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tWFP
VIH
F0b
VIL
tFH
VIH
C4b
VIL
tFS
tP4o
Figure 15 - External Inputs on C4b and F0b for the DPLL #2
19
Zarlink Semiconductor Inc.
MT8940
Data Sheet
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 16)
Characteristics
Sym.
Min.
Typ.‡
Max. Units
Test Conditions
1
2
3
4
Delay from Enable to Output
(HIGH to THREE STATE)
tPHZ
15
65
55
40
50
ns
ns
ns
ns
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
O
U
T
P
U
T
Delay from Enable to Output
(LOW to THREE STATE)
tPLZ
tPZH
tPZL
10
Delay from Enable to Output
(THREE STATE to HIGH)
Delay from Enable to Output
(THREE STATE to LOW)
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tf
6 ns
tr
6 ns
3.0 V
2.7 V
1.3 V
0.3 V
Enable
Input
tPZL
tPLZ
Output
LOW to
OFF
1.3 V
10%
90%
tPHZ
tPZH
Output
HIGH
to OFF
1.3 V
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
Figure 16 - Three State Outputs and Enable Timings
20
Zarlink Semiconductor Inc.
MT8940
Data Sheet
AC Electrical Characteristics† - Uncommitted NAND Gate - Voltages are with respect to ground (VSS) unless otherwise
stated.
Characteristics
Sym.
Min.
Typ.‡ Max.
Units
Test Conditions
1
2
Propagation delay (LOW to HIGH),
input Ai or Bi to output
tPLH
25
20
40
40
ns
Test load circuit 1 (Fig. 17)
Propagation delay (HIGH to LOW),
input Ai or Bi to output
tPHL
ns
Test load circuit 1 (Fig. 17)
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VDD
VDD
RL=1kΩ
Test
point
A
RL=1kΩ
From
From
From
Test
point
Test
point
output
output
output
under test
B
S1
under test
under test
VSS
CL=50pF
CL=50pF
CL=50pF
Note: S1 is in position A
when measuring tPLZ
and tPZ and in position B
when measuring tPHZ and
tPZH
Test load circuit- 1
Test load circuit- 2
Test load circuit- 3
Figure 17 - Test Load Circuits
21
Zarlink Semiconductor Inc.
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