MT8941AE [MITEL]
CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL; CMOS ST- BUS⑩家庭高级T1 / CEPT数字中继锁相环
| 型号： | MT8941AE |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
| 文件： | 总18页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS ST-BUS FAMILY MT8941
Advanced T1/CEPT Digital Trunk PLL
ISSUE 5
July 1993
Features
Ordering Information
•
•
Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)
MT8941AE
MT8941AP
24 Pin Plastic DIP
28 Pin PLCC
Provides CEPT clock at 2.048 MHz and ST-
BUS clock and timing signals locked to an
internal or external 8 kHz reference clock
-40°C to +85°C
•
•
Typical inherent output jitter (unfiltered)= 0.07
UI peak-to-peak
Description
Typical jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz ≥ 64 dB
The MT8941 is a dual digital phase-locked loop
providing the timing and synchronization signals for
the T1 or CEPT transmission links and the ST-BUS.
The first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to
an internal or an external 8 kHz frame pulse signal.
•
•
•
Jitter-free “FREE-RUN” mode
Uncommitted two-input NAND gate
Low power CMOS technology
Applications
The MT8941 offers improved jitter performance over
the MT8940. The two devices also have some
functional differences, which are listed in the section
on “Differences between MT8941 and MT8940”.
•
•
Synchronization and timing control for T1
and CEPT digital trunk transmission links
ST- BUS clock and frame pulse source
CVb
F0i
Variable
DPLL #1
CV
Clock
Control
2:1 MUX
C12i
ENCV
MS0
Frame Pulse
Control
Mode
Selection
Logic
MS1
MS2
F0b
Input
Selector
MS3
C4b
4.096 MHz
Clock
Control
C8Kb
C4o
ENC4o
C16i
DPLL #2
C2o
Clock
Generator
2.048 MHz
Clock
Control
C2o
Ai
Bi
ENC2o
Yo
VDD
VSS
RST
Figure 1 - Functional Block Diagram
3-43
MT8941 CMOS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
ENVC
MS0
C12i
MS1
F0i
VDD
RST
CV
CVb
Yo
•
NC
CVb
Yo
Bi
Ai
MS3
ENC2o
5
25
24
23
22
21
20
19
NC
MS1
6
F0i
7
F0b
Bi
Ai
8
F0b
MS2
C16i
MS2
C16i
ENC4o
C8Kb
C4o
9
MS3
ENC2o
C2o
C2o
C4b
10
11
ENC4o
VSS
24 PIN PDIP
28 PIN PLCC
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
DIP PLCC
1
1
EN
Variable clock enable (TTL compatible input) - This input directly controls the three states
of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts
it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1
is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high
impedance state. However, if MS1 is HIGH, CVb is always an input.
CV
2
2
MS0 Mode select ‘0’ input (TTL compatible) - This input in conjunction with MS1 (pin 4) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
3
4
3
6
C12i 12.352 MHz Clock input (TTL compatible) - Master clock input for DPLL #1.
MS1 Mode select-1 input (TTL compatible) - This input in conjunction with MS0 (pin 2) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
5
6
7
8
F0i
Frame pulse input (TTL compatible) - This is the frame pulse input at 8 kHz. DPLL #1
locks to the falling edge of this input to generate T1 (1.544 MHz) clock.
F0b Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending
on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as
an input to an external frame pulse.
7
9
MS2 Mode select-2 input (TTL compatible) - This input in conjunction with MS3 (pin 17) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
8
9
10
C16i 16.384 MHz Clock input (TTL compatible) - Master clock input for DPLL #2.
11 EN
Enable 4.096 MHz clock (TTL compatible input) - This active high input enables C4o (pin
C4o
11) output. When LOW, the output C4o is in high impedance condition.
10
12
C8Kb Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) - This is the 8
kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode.
When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal
provided by DPLL #1 which is also connected internally to DPLL #2.
11
13
14
C4o Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
12
V
Ground (0 Volt)
SS
3-44
CMOS MT8941
Pin Description (continued)
Pin #
Name
Description
DIP PLCC
13
15
C4b Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input to an
external clock at 4.096 MHz.
14
15
16
17
16
C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by EN
(pin 16).
C2o
17
C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by EN
(pin 16).
C2o
19 EN
Enable 2.048 MHz clock (TTL compatible input) - This active high input enables both C2o
and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance
condition.
C2o
20
MS3 Mode select 3 input (TTL compatible) - This input in conjunction with MS2 (pin 7) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
18, 21,
Ai, Bi Inputs A and B (TTL compatible) -These are the two inputs of the uncommitted NAND
19
20
21
22
23
24
gate.
Y
Output Y (Totem pole output) - Output of the uncommitted NAND gate.
o
CVb Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz
to DPLL #2.
22
23
26
27
CV
Variable clock (Three state output) - This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled by EN (pin 1).
CV
RST Reset (Schmitt trigger input) - This input (active LOW) puts the MT8941 in its reset state.
To guarantee proper operation, the device must be reset after power-up. The time constant
for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time
of the power supply. In normal operation, the RST pin must be held low for a minimum of
60nsec to reset the device.
24
28
V
V
(+5V) Power supply.
DD
DD
4,
5,
NC No Connection.
18,
25
3-45
MT8941 CMOS
Functional Description
C8Kb (DPLL #2)
or F0i (DPLL #1)
sampling edge
correction
The MT8941 is a dual digital phase-locked loop
providing the timing and synchronization signals to
the interface circuits for T1 and CEPT (30+2)
Primary Multiplex Digital Transmission links. As
shown in the functional block diagram (see Figure 1),
the MT8941 has two digital phase-locked loops
(DPLLs), associated output controls and the mode
selection logic circuits. The two DPLLs, although
similar in principle, operate independently to provide
T1 (1.544 MHz) and CEPT (2.048 MHz) transmission
clocks and ST-BUS timing signals.
Internal
8 kHz
correction
CS
speed-up
region
slow-down
region
tCS
F0b
tCSF
no-correction
(DPLL #2)
DPLL #1: tCS = 4 × TP12 ± 0.5 × TP12
DPLL #2: tCS = 512 × TP16 ± 0.5 × TP16
CSF = 766 × TP16
t
where, TP12 is the 12.352 MHz master clock oscillator period
for DPLL #1 and TP16 is the 16.384 MHz master clock period
for DPLL #2.
The principle of operation behind the two DPLLs is
shown in Figure 3. A master clock is divided down to
8 kHz where it is compared with the 8 kHz input, and
depending on the output of the phase comparison,
the master clock frequency is corrected.
Figure 4 - Phase Comparison
reference signal will be aligned with the falling edge
of CS if the reference signal is faster than the
internal 8 kHz signal.
Master clock
Frequency
(12.352 MHz /
16.384 MHz)
÷ 8
Correction
Input-to-Output Phase Relationship
Output
(1.544 MHz /
2.048 MHz)
The no-correction window size is 324 ns for DPLL #1
and 32 µs for DPLL #2. It is possible for the relative
phase of the reference signal to swing inside the no-
correction window depending on its jitter and the
relative drift of the master clock. As a result, the
phase relationship between the input signal and the
output clocks (and frame pulse in case of DPLL #2)
may vary up to a maximum of window size. This
situation is illustrated in Figure 4. The maximum
phase variation for DPLL #1 is 324 ns and for DPLL
#2 it is 32µs. However, this phase difference can be
absorbed by the input jitter buffer of Mitel’s T1/CEPT
devices.
Input (8 kHz)
÷ 193 /
÷ 256
Phase
Comparison
Figure 3 - DPLL Principle
The MT8941 achieves the frequency correction in
both directions by using three methods; speed-up,
slow-down and no-correction.
As shown in Figure 4, the falling edge of the 8 kHz
input signal (C8Kb for DPLL #2 or F0i for DPLL # 1)
is used to sample the internally generated 8 kHz
clock and the correction signal (CS) once in every
frame (125 µs). If the sampled CS is “1”, then the
DPLL makes a speed-up or slow-down correction
depending upon the sampled value of the internal 8
kHz signal. A sampled ”0” or “1” causes the
frequency correction circuit to respectively stretch or
shrink the master clock by half a period at one
instant in the frame. If the sampled CS is “0”, then
the DPLL makes no correction on the master clock
input. Note that since the internal 8 kHz signal and
the CS signal are derived from the master clock, a
correction will cause both clocks to stretch or shrink
simultaneously by an amount equal to half the period
of the master clock.
The no-correction window acts as a filter for low
frequency jitter and wander since the DPLL does not
track the reference signal inside it. The size of the
no-correction window is less than or equal to the size
of the input jitter buffer on the T1 and CEPT devices
to guarantee that no slip will occur in the received
T1/CEPT frame.
The circuit will remain in synchronization as long as
the input frequency is within the lock-in range of the
DPLLs (refer to the section on “Jitter Performance
and Lock-in Range” for further details). The lock-in
range is wide enough to meet the CCITT line rate
specification (1.544 MHz ±32 ppm and 2.048 MHz
±50 ppm) for the High Capacity Terrestrial Digital
Service.
Once in synchronization, the falling edge of the
reference signal (C8Kb or F0i) will be aligned with
either the falling or the rising edge of CS. It is aligned
with the rising edge of CS when the reference signal
is slower than the internal 8 kHz signal. On the other
hand, the falling edge of the
The phase sampling is done once in a frame (8 kHz)
for each DPLL. The divisions are set at 8 and 193 for
DPLL #1, which locks to the falling edge of the input
3-46
CMOS MT8941
at 8 kHz to generate T1 (1.544 MHz) clock. For
DPLL #2, the divisions are set at 8 and 256 to
provide the CEPT/ST-BUS clock at 2.048 MHz
synchronized to the falling edge of the input signal (8
kHz). The master clock source is specified to be
12.352 MHz for DPLL #1 and 16.384 MHz for DPLL
#2 over the entire temperature range of operation.
M
S
0
M
S
1
Mode of
Function
Operation
Provides the T1 (1.544 MHz) clock
X
0
0
1
1
NORMAL synchronized to the falling edge of
the input frame pulse (F0i).
DPLL #1 divides the CVb input by
DIVIDE-1 193. The divided output is
connected to DPLL #2.
The inputs MS0 to MS3 are used to select the
operating mode of the MT8941, see Tables 1 to 4.
All the outputs are controlled to the high impedance
condition by their respective enable controls. The
uncommitted NAND gate is available for use in
applications involving Mitel’s MT8976/ MH89760 (T1
DPLL #1 divides the CVb input by
DIVIDE-2 256. The divided output is
connected to DPLL #2.
1
Note:
X: indicates don’t care
Table 1. Major Modes of DPLL #1
Interfaces)
Interfaces).
and
MT8979/MH89790
(CEPT
M
S
0
M
S
1
Mode of
Function
Operation
Modes of Operation
Provides CEPT/ST-BUS timing
NORMAL signals locked to the falling edge of
the 8 kHz input signal at C8Kb.
0
1
0
0
The operation of the MT8941 is categorized into
major modes and minor modes. The major modes
are defined for both DPLLs by the mode select pins
MS0 and MS1. The minor modes are selected by
pins MS2 and MS3 and are applicable only to DPLL
#2. There are no minor modes for DPLL #1.
Provides CEPT/ST-BUS timing and
FREE-RUN framing signals with no external
inputs, except the master clock.
Provides CEPT/ST-BUS timing
SINGLE
signals locked to the falling edge of
0
1
1
1
CLOCK-1 the 8 kHz internal signal provided by
DPLL #1.
Major modes of DPLL #1
Provides CEPT/ST-BUS timing
SINGLE
signals locked to the falling edge of
DPLL #1 can be operated in three major modes as
selected by MS0 and MS1 (Table 1). When MS1 is
LOW, it is in NORMAL mode, which provides a T1
(1.544 MHz) clock signal locked to the falling edge
of the input frame pulse F0i (8 kHz). DPLL #1
requires a master clock input of 12.352 MHz (C12i).
In the second and third major modes (MS1 is HIGH),
DPLL #1 is set to DIVIDE an external 1.544 MHz or
2.048 MHz signal applied at CVb (pin 21). The
division can be set by MS0 to be either 193 (LOW) or
256 (HIGH). In these modes, the 8 kHz output at
C8Kb is connected internally to DPLL #2, which
operates in SINGLE CLOCK mode.
CLOCK-2 the 8 kHz internal signal provided by
DPLL #1.
Table 2. Major Modes of DPLL #2
M
S
2
M
S
3
Functional Description
Provides CEPT/ST-BUS 4.096 MHz and 2.048
MHz clocks and 8kHz frame pulse depending on
the major mode selected.
1
1
1
Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz
clocks depending on the major mode selected
while F0b acts as an input. However, the input on
F0b has no effect on the operation of DPLL #2
unless it is in FREE-RUN mode.
0
Major modes of DPLL #2
Overrides the major mode selected and accepts
properly phase related external 4.096 MHz clock
and 8 kHz frame pulse to provide the ST-BUS
compatible clock at 2.048 MHz.
0
1
0
0
There are four major modes for DPLL #2 selectable
by MS0 and MS1, as shown in Table 2. In all these
modes DPLL #2 provides the CEPT PCM30 timing,
and the ST-BUS clock and framing signals.
Overrides the major mode selected and accepts a
4.096 MHz external clock to provide the ST-BUS
clock and frame pulse at 2.048 MHz and 8 kHz,
respectively.
In NORMAL mode, DPLL #2 provides the CEPT/ST-
BUS compatible timing signals locked to the falling
edge of the 8 kHz input signal (C8Kb). These
signals are 4.096 MHz (C4o and C4b) and 2.048
MHz (C2o and C2o) clocks, and the 8 kHz frame
pulse (F0b) derived from the 16.384 MHz master
clock. This mode can be the same as the FREE-
Table 3. Minor Modes of DPLL #2
In FREE-RUN mode, DPLL #2 generates the stand-
alone CEPT and ST-BUS timing and framing signals
with no external inputs except the master clock set at
16.384 MHz. The DPLL makes no correction in this
configuration and provides the timing signals without
any jitter.
RUN mode if the C8Kb pin is tied to V or V
.
DD
SS
3-47
MT8941 CMOS
The operation of DPLL #2 in SINGLE CLOCK-1
mode is identical to SINGLE CLOCK-2 mode,
providing the CEPT and ST-BUS compatible timing
signals synchro-nized to the internal 8 kHz signal
obtained from DPLL#1 in DIVIDE mode. When
SINGLE CLOCK-1 mode is selected for DPLL #2, it
automatically selects the DIVIDE-1 mode for DPLL
#1, and thus, an external 1.544 MHz clock signal
applied at CVb (pin 21) is divided by DPLL #1 to
generate the internal signal at 8 kHz on to which
DPLL #2 locks. Similarly when SINGLE CLOCK-2
mode is selected, DPLL #1 is in DIVIDE-2 mode,
with an external signal of 2.048 MHz providing the
internal 8 kHz signal to DPLL #2. In both these
modes, this internal signal is available on C8Kb (pin
10) and DPLL #2 locks to the falling edge to provide
the CEPT and ST-BUS compatible timing signals.
This is in contrast to the Normal mode where these
timing signals are synchronized with the falling edge
of the 8 kHz signal on C8Kb.
Minor modes of DPLL #2
The minor modes for DPLL #2 depends upon the
status of the mode select bits MS2 and MS3 (pins 7
and 17).
Operating Modes
DPLL #2
M
S
0
M
S
1
M
S
2
M
S
3
Mode
#
DPLL #1
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
0
0
0
0
0
synchronized to the falling edge of the input
frame pulse (F0i).
BUS clock at 2.048 MHz.
NORMAL MODE:
F0b is an input but has no function in this mode.
1
2
0
0
0
0
0
1
1
0
NORMAL MODE
NORMAL MODE
NORMAL MODE
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
3
4
0
0
0
1
1
0
1
0
DIVIDE-1 MODE
Same as mode ‘0’.
SINGLE CLOCK-1 MODE
F0b is an input but has no function in this mode.
5
6
0
0
1
1
0
1
1
0
DIVIDE-1 MODE
DIVIDE-1 MODE
Same as mode 2.
DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
7
8
0
1
1
0
1
0
1
0
NORMAL MODE
NORMAL MODE
Same as mode ‘0’.
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
9
1
1
0
0
0
1
1
0
10
NORMAL MODE
NORMAL MODE
Same as mode 2.
FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.
11
12
1
1
0
1
1
0
1
0
DIVIDE-2 MODE
DIVIDE-2 MODE
Same as mode ‘0’.
SINGLE CLOCK-2 MODE:
F0b is an input but has no function in this mode.
13
14
1
1
1
1
0
1
1
0
DIVIDE-2 MODE
Same as mode 2.
DIVIDE-2 MODE:
SINGLE CLOCK-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
15
1
1
1
1
Table 4. Summary of Modes of Operation - DPLL #1 and #2
3-48
CMOS MT8941
When MS3 is HIGH, DPLL #2 operates in any of the
major modes selected by MS0 and MS1. When MS3
is LOW, it overrides the major mode selected and
DPLL#2 accepts an external clock of 4.096 MHz on
C4b (pin 13) to provide the 2.048 MHz clocks (C2o
and C2o) and the 8 kHz frame pulse (F0b)
compatible with the ST-BUS format. The mode select
bit MS2 controls the direction of the signal on F0b
(pin 6).
functionally similar. The required operation of both
DPLL #1 and DPLL #2 must be considered when
determining MS0-MS3.
The direction and frequency of each of the
bidirectional signals are listed in Table 5 for each of
the given modes in Table 4.
Jitter Performance and Lock-in Range
When MS2 is LOW, the F0b pin is an 8 kHz frame
pulse input. This input is effective only when MS3 is
also LOW and pin C4b is fed by a 4.096 MHz clock,
which has a proper phase relationship with the
signal on F0b (refer Figure 18). Otherwise, the input
on pin F0b will have no bearing on the operation of
DPLL #2, unless it is in FREE-RUN mode as
selected by MS0 and MS1. In FREE-RUN mode,
the input on F0b is treated the same way as the
C8Kb input is in NORMAL mode. The frequency of
the signal on F0b should be 16 kHz for DPLL #2 to
lock and generate the ST-BUS compatible clocks at
4.096 MHz and 2.048 MHz.
The output jitter of a DPLL is composed of the
intrinsic jitter, measured when no jitter is present at
the input, and the output jitter resulting from jitter on
the input signal. The spectrum of the intrinsic jitter
for both DPLLs of the MT8941 is shown in Figure 5.
The typical peak-to-peak value for this jitter is
0.07UI. The transfer function, which is the ratio of
the output jitter to the input jitter (both measured at a
particular frequency), is shown in Figure 6 for DPLL
#1 and Figure 7 for DPLL #2. The transfer function
is measured when the peak-to-peak amplitude of the
sinusoidal input jitter conforms to the following:
10 Hz - 100 Hz
100 Hz - 10 kHz : 20 dB / decade roll-off
> 10 kHz : 97.2 ns
: 13.6 µs
When MS2 is HIGH, the F0b pin provides the frame
pulse output compatible with the ST-BUS format and
locked to the internal or external input signal as
determined by the other mode select pins.
The ability of a DPLL to phase-lock the input signal
to the reference signal and to remain locked
depends upon its lock-in range. The lock-in range of
the DPLL is specified in terms of the maximum
frequency variation in the 8 kHz reference signal. It
is also directly affected by the oscillator frequency
tolerance. Table 6 lists different values for the lock-in
range and the corresponding oscillator frequency
tolerance for DPLL #1 and DPLL #2. The smaller
the tolerance value, the larger the lock-in range.
Table 4 summarizes the modes of the two DPLL. It
should be noted that each of the major modes
selected for DPLL #2 can have any of the minor
modes, although some of the combinations are
Mode
#
F0b
(kHz)
C4b
(MHz)
C8Kb
(kHz)
CVb
(MHz)
0
1
i:8
i:X
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:4.096
o:4.096
i:X
i:8
o:1.544
o:1.544
o:1.544
o:1.544
i:1.544
i:1.544
i:1.544
i:1.544
o:1.544
o:1.544
o:1.544
o:1.544
i:2.408
i:2.408
i:2.408
i:2.408
2
o:8
o:8
i:8
i:X
i:8
The T1 and CEPT standards specify that, for free
running equipment, the output clock tolerance must
be less than or equal to ±32ppm and ±50ppm
respectively. This requirement restricts the
3
4
i:X
o:8
i:X
o:8
i:X
i:X
i:X
i:X
i:X
o:8
i:X
o:8
5
i:X
6
o:8
o:8
i:8
Lock-in Range (±Hz)
Oscillator Clock*
7
Tolerance (±ppm)
8
DPLL #1
2.55
DPLL #2
1.91
1.87
1.79
1.69
1.55
1.15
.75
9
i:16
o:8
o:8
i:8
5
10
11
12
13
14
15
10
2.51
20
2.43
32
2.33
i:X
50
2.19
o:8
o:8
100
150
175
1.79
1.39
1.19
.55
Table 5. Functions of the Bidirectional Signals
in Each Mode
Table 6. Lock-in Range vs. Oscillator Frequency
Tolerance
* Please refer to the section on “Jitter Performance and Lock-in
Range” for recommended oscillator tolerances for DPLL #1 & #2.
Notes:
i
o
X
: Input
: Output
: “don’t care” input. Connect to VDD or VSS.
3-49
MT8941 CMOS
Fig. 5- The Spectrum of the Inherent Jitter for either PLL
Fig. 6 - The Jitter Transfer Function for PLL1
Fig. 7 - The Jitter Transfer Function for PLL2
3-50
CMOS MT8941
oscillators of DPLL #1 and DPLL #2 to have
maximum tolerances of ±32ppm and ±50ppm
respectively.
it is recommended to use a ±32 ppm oscillator for
DPLL #2 and a ±100 ppm oscillator for DPLL #1.
Differences between MT8941 and MT8940
However, if DPLL #1 and DPLL #2 are daisy-chained
as shown in Figures 9 and 10, the output clock
tolerance of DPLL #1 will be equal to that of the
DPLL #2 oscillator when DPLL #2 is free-running. In
this case, the oscillator tolerance of DPLL #1 has no
impact on its output clock tolerance. For this reason,
The MT8941 and MT8940 are pin and mode
compatible for most applications. However, the user
should take note of the following differences between
the two parts.
a) Distributed Timing
Data Bus
Line Card 1
8 kHz Reference Signal
MT8940
Clocks
M
U
X
Line Card n
8 kHz Reference Signal
MT8940
Clocks
b) Centralized Timing
Data Bus
Line Card 1
8 kHz Reference Signal
M
U
MT8941
X
Clocks
Line Card n
8 kHz Reference Signal
Figure 8 - Application Differences between the MT8940 and MT8941
3-51
MT8941 CMOS
Besides the improved jitter performance, the
MT8941 differs from the MT8940 in three other
areas:
Applications
The following figures illustrates how the MT8941 can
be used in a minimum component count approach in
providing the timing and synchro-nization signals for
the Mitel T1 or CEPT interfaces, and the ST-BUS.
The hardware selectable modes and the
independent control over each PLL adds flexibility to
the interface circuits. It can be easily reconfigured to
provide the timing and control signals for both the
master and slave ends of the link.
1. Input pins on the MT8941 do not incorporate
internal pull-up or pull-down resistors.
In
addition, the output configuration of the
bidirectional C8Kb pin has been converted from
an open drain output to a Totem-pole output.
2. The MT8941 includes a no-correction window to
filter out low frequency jitter and wander as
illustrated in Figure 4. Consequently, there is no
constant phase relationship between reference
signal F0i of DPLL # 1 or C8Kb of DPLL #2 and
the output clocks of DPLL #1 or DPLL #2.
Figure 4 shows the new phase relationship
between C8Kb and the DPLL #2 output clocks.
Figure 8 illustrates an application where the
MT8941 cannot replace the MT8940 and
suggests an alternative solution.
Synchronization and Timing Signals for the T1
Transmission Link
Figures 9 and 10 show examples of how to generate
the timing signals for the master and slave ends of a
T1 link. At the master end of the link (Figure 9),
DPLL #2 is the source of the ST-BUS signals derived
from the crystal clock. The frame pulse output is
looped back to DPLL #1 (in NORMAL mode), which
locks to it to generate the T1 line clock. The timing
relationship between the 1.544 MHz T1 clock and
3. The MT8941 must be reset after power-up in
order to guarantee proper operation, which is not
the case for the MT8940.
the 2.048 MHz ST-BUS clock
meets the
requirements of the MH89760/760B. The crystal
clock at 12.352 MHz is used by DPLL #1 to generate
the 1.544 MHz clock, while DPLL #2 (in FREE-RUN
mode) uses the 16.384 MHz crystal oscillator to
generate the ST-BUS clocks for system timing. The
generated ST-BUS signals can be used to
synchronize the system and the switching equipment
at the master end.
4. For the MT8941, DPLL #2 locks to the falling
edge of the C8Kb reference signal. DPLL#2 of
the MT8940 locks on to the rising edge of C8Kb.
5. While the MT8940 is available only in a 24 pin
plastic DIP, the MT8941 has an additional 28 pin
PLCC package option.
MT8980/81
Crystal Clock
MT8941
(12.352 MHz)
VDD
CVb
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89760B
C1.5i
DSTi
C2i
F0i
DSTo
F0i
C12i
C4b
C2o
F0b
CSTi
ENCV
C8Kb
C16i
CSTo
TxT
TxR
RxT
RxR
TRANSMIT
RECEIVE
T1
ENC4o
ENC2o
LINK
(1.544 Mbps)
Crystal Clock
(16.384 MHz)
VSS
RST
Mode of Operation for the MT8941
DPLL #1 - NORMAL (MS0 = X; MS1 = 0)
VDD
DPLL #2 - FREE-RUN (MS0=1; MS2=1; MS3=1)
R
C
Figure 9 - Synchronization at the Master End of the T1 Transmission Link
3-52
CMOS MT8941
MT8980/81
MT8941
Crystal Clock
(12.352 MHz)
VDD
CVb
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89760B
C1.5i
DSTi
C2i
F0i
DSTo
C12i
C4b
C2o
F0b
F0i
CSTi
ENCV
C8Kb
C16i
E8Ko
CSTo
TxT
TxR
RxT
RxR
TRANSMIT
ENC4o
ENC2o
T1
LINK
(1.544 Mbps)
RECEIVE
VSS
RST
Crystal Clock
(16.384 MHz)
Mode of Operation for the MT8941
DPLL #1 - NORMAL ( MS1=0)
R
C
VDD
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 10 - Synchronization at the Slave End of the T1 Transmission Link
MT8941
MT8980/81
VDD
C4b
MS0
MS1
MS2
MS3
MH89790B
ST-BUS
SWITCH
DSTi
C2i
F0i
DSTo
F0i
C12i
CSTi0
CSTi1
CSTo
OUTA
OUTB
RxT
C2o
F0b
Yo
ENCV
C8Kb
C16i
Crystal Clock
(16.384 MHz)
ENC4o
ENC2o
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
TRANSMIT
RECEIVE
VSS
RST
RxR
Mode of Operation for the MT8941
VDD
DPLL #1 - NOT USED
R
C
DPLL #2 - FREE-RUN (MS0=1; MS1=0; MS2=1; MS3=1)
Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link
At the slave end of the link (Figure 10) both the
DPLLs are in NORMAL mode, with DPLL #2
providing the ST-BUS timing signals locked to the 8
kHz frame pulse (E8Ko) extracted from the received
signal on the T1 line. The regenerated frame pulse
is looped back to DPLL #1 to provide the T1 line
clock, which is the same as the master end.
Synchronization and Timing Signals for the
CEPT Transmission Link
The MT8941 can be used to provide the timing and
synchronization signals for the MH89790/790B,
Mitel’s CEPT (30+2) Digital Trunk Interface Hybrid.
Since the operational frequencies of the ST-BUS and
the CEPT primary multiplex digital trunk are the
same, only DPLL #2 is required.
The 12.352 MHz and 16.384 MHz crystal clock
sources are necessary for DPLL #1 and #2,
respectively.
3-53
MT8941 CMOS
MT8980/81
MT8941
VDD
C4b
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89790B
DSTi
C2i
F0i
DSTo
C12i
F0i
C2o
F0b
Yo
CSTi0
CSTi1
CSTo
OUTA
OUTB
RxT
ENCV
C8Kb
C16i
E8Ko
Crystal Clock
(16.384 MHz)
ENC4o
ENC2o
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
TRANSMIT
RECEIVE
VSS
RST
RxR
Mode of Operation for the MT8941
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=1; MS1=0; MS2=1; MS3=1)
VDD
R
C
Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link
Figures 11 and 12 show how the MT8941 can be
used to synchronize the ST-BUS to the CEPT
transmission link at the master and slave ends.
Figure 13 shows two such applications using DPLL
#2. In one case, the MT8941 is in FREE-RUN
mode with an oscillator input of 16.384 MHz. In the
other case, it is in NORMAL mode with the C8Kb
input tied to V . For these applications, DPLL #2
DD
Generation of ST-BUS Timing Signals
does not make any corrections and therefore, the
output signals are free from jitter. DPLL #1 is
completely free.
The MT8941 can source the properly formatted ST-
BUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.
For prototyping purposes, Mitel offers the MT8941
Crystal Kit (MB6022) which contains 16.384 MHz
and 12.352 MHz clock oscillators.
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN MODE
(MS0=0; MS1=0;MS2=1;
MS3=1)
MT8941
MT8941
VDD
VDD
MS0
MS1
MS2
MS3
MS0
MS1
MS2
MS3
C4o
C4b
C4o
C4b
F0i
C12i
F0i
C12i
ST-BUS
ST-BUS
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
ENCV
C8Kb
C2o
C2o
TIMING
TIMING
Crystal Clock
(16.384 MHz)
Crystal Clock
(16.384 MHz)
C16i
ENC4o
ENC2o
Ai
C2o
F0b
C2o
F0b
SIGNALS
SIGNALS
Bi
Bi
VSS
VSS
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
RST
RST
MS2=1; MS3=1)
VDD
VDD
R
R
C
C
Figure 13 - Generation of the ST-BUS Timing Signals
3-54
CMOS MT8941
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
6
7
Supply Voltage
V
-0.3
7.0
V
DD
Voltage on any pin
V
V
-0.3
V +0.3
DD
V
I
SS
Input/Output Diode Current
Output Source or Sink Current
DC Supply or Ground Current
Storage Temperature
I
±10
mA
mA
mA
IK/OK
I
±25
±50
125
O
I
/I
DD SS
o
T
-55
C
ST
Package Power Dissipation
Plastic DIP
PLCC
P
P
1200
600
mW
mW
D
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Supply Voltage
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
V
4.5
2.0
5.0
5.5
V
V
V
DD
Input HIGH Voltage
Input LOW Voltage
Operating Temperature
V
V
DD
IH
V
V
0.8
IL
SS
o
T
-40
25
85
C
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
VDD=5.0V±5%; VSS=0V; TA=-40 to 85°C.
‡
Characteristics
Sym
Min Typ
Max
Units
Test Conditions
Under clocked condition, with the
inputs tied to the same supply
rail as the corresponding pull-up
/down resistors.
I
8
15
mA
DD
S
U
P
1
Supply Current
2
3
4
5
Input HIGH voltage (For all the
inputs except pin 23)
V
2.0
V
V
V
V
IH
Positive-going threshold
voltage (For pin 23)
V
3.0
1.5
4.0
0.8
+
I
N
Input LOW voltage (For all the
inputs except pin 23)
V
IL
Negative-going threshold
voltage (For pin 23)
V
1.0
-
O
U
T
6
7
8
Output current HIGH
Output current LOW
I
-4
4
mA
mA
µA
V
V
=2.4 V
OH
OH
I
=0.4 V
OL
OL
Leakage current on bidirect-
ional pins and all inputs except
C12i, C16i, RST, MS1, MS0
I
-100
-30
-8
V =V
IN SS
IL
9
Leakage current on pins MS1,
MS0
I
I
10
35
±1
120
+10
µA
µA
V =V
IN DD
IL
IL
10
Leakage current on all three-
state outputs and C12i, C16i,
RST inputs
-10
V
=V or V
I/O SS DD
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-55
MT8941 CMOS
AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 14)
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
85 pF Load
1
2
3
4
5
CVb output (1.544 MHz) rise
time
t
t
t
6
ns
r1.5
CVb output (1.544 MHz) fall
time
6
ns
85 pF Load
f1.5
D
P
L
CVb output (1.544 MHz) clock
period
607
318
277
648
689
324
363
ns
ns
ns
P15
L
CVb output (1.544 MHz) clock
width (HIGH)
t
W15H
#1
CVb output (1.544 MHz) clock
width (LOW)
t
W15L
6
7
CV delay (HIGH to LOW)
t
0
10
3
ns
ns
15HL
15LH
CV delay (LOW to HIGH)
t
-7
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tP15
tf1.5
tW15H
VOH
CVb
VOL
tW15L
t15HL
tr1.5
t15LH
VOH
CV
VOL
Figure 14 - Timing Information for DPLL #1 in NORMAL Mode
AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 15)
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
5
C8Kb output (8kHz) delay
(HIGH to HIGH)
t
0
10
25
34
ns
ns
85 pF Load
C8HH
C8Kb output (8 kHz) delay
(LOW to LOW )
t
2
13
85 pF Load
D
P
L
C8LL
C8Kb output duty cycle
66
50
%
%
In Divide -1 Mode
In Divide - 2 Mode
L
Inverted clock output delay
(HIGH to LOW )
#1
t
0
0
10
7
25
18
ns
ns
ICHL
Inverted clock output delay
(LOW to HIGH)
t
ICLH
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-56
CMOS MT8941
VIH
VIL
CVb
tICHL
tICLH
VOH
VOL
CV
tC8HH
tC8LL
VOH
VOL
C8Kb
Figure 15 - DPLL #1 in DIVIDE Mode
tWFP
VOH
VOL
F0b
tP4o
tFPL
tFPH
tfC4
tW4oH
trC4
VOH
VOL
C4b
C4o
tW4oL
t4oLH
t4oHL
VOH
VOL
t42LH
tP2o
t42HL
tW2oH
trC2
tfC2
VOH
VOL
C2o
C2o
tW2oL
t2oLH
t2oHL
VOH
VOL
Figure 16 - Timing Information on DPLL #2 Outputs
3-57
MT8941 CMOS
AC Electrical Characteristics†-Voltages are with respect to ground (VSS) unless otherwise stated.(Refer to Figure 16)
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
85 pF Load
1
2
3
4
5
6
C4b output clock period
t
213
85
244
275
159
122
ns
ns
ns
ns
ns
P4o
C4b output clock width (HIGH)
C4b output clock width (LOW)
C4b output clock rise time
C4b clock output fall time
t
W4oH
t
116
W4oL
t
6
6
85 pF Load
85 pF Load
85 pF Load
rC4
t
fC4
Frame pulse output delay
(HIGH to LOW) from C4b
t
0
0
13
8
ns
ns
FPL
7
Frame pulse output delay
(LOW to HIGH) from C4b
85 pF Load
t
FPH
8
9
Frame pulse (F0b) width
C4o delay - LOW to HIGH
C4o delay - HIGH to LOW
t
225
0
245
15
ns
ns
ns
WFP
D
P
L
t
4oLH
4oHL
10
11
t
t
0
20
L
C4b to C2o delay (LOW to
HIGH)
0
0
3
6
ns
ns
42LH
42HL
#2
12
C4b to C2o delay (HIGH to
LOW)
t
13
14
15
16
17
18
19
C2o clock period
t
457
207
238
488
519
280
244
ns
ns
ns
ns
ns
ns
ns
85 pF Load
P2o
C2o clock width ( HIGH )
C2o clock width ( LOW )
C2o clock rise time
t
W2oH
t
W2oL
t
t
6
6
85 pF Load
85 pF Load
rC2
fC2
C2o clock fall time
C2o delay - LOW to HIGH
C2o delay - HIGH to LOW
t
-5
0
2
7
2oLH
t
5
2oHL
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-58
CMOS MT8941
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 14)
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
Master clocks input rise time
Master clocks input fall time
t
10
10
ns
ns
r
t
f
For DPLL #1, while operating to
provide the T1 clock signal.
3 C Master clock period
t
t
80.943 80.958 80.974
61.023 61.035 61.046
ns
ns
P12
L (12.352MHz)*
O
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
4
Master clock period
C
P16
(16.384MHz)*
K
S
5
6
Duty Cycle of master clocks
45
50
55
%
With the Master frequency
tolerance at ±32 ppm.
Lock-in Range
DPLL #1
DPLL #2
-2.33
-1.69
+2.33
+1.69
Hz
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Please review the section on "Jitter Performance and Lock-in Range".
tr
tf
2.4 V
1.5 V
0.4 V
Master clock
inputs
tP12 or tP16
Figure 17 - Master Clock Inputs
AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 18)
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
F0b input pulse width (LOW)
C4b input clock period
t
244
244
50
ns
ns
ns
ns
WFP
t
P4o
Frame pulse (F0b) setup time
t
FS
Frame pulse (F0b) hold time
t
25
FH
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tWFP
VIH
F0b
VIL
tFH
VIH
C4b
VIL
tFS
tP4o
Figure 18 - External Inputs on C4b and F0b for the DPLL #2
3-59
MT8941 CMOS
AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 19)
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
Delay from Enable to Output
(HIGH to THREE STATE)
t
16
12
11
16
ns
ns
ns
ns
85 pF Load
PHZ
O
U
T
P
U
T
Delay from Enable to Output
(LOW to THREE STATE)
t
85 pF Load
85 pF Load
85 pF Load
PLZ
Delay from Enable to Output
(THREE STATE to HIGH)
t
PZH
Delay from Enable to Output
(THREE STATE to LOW)
t
50
PZL
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tf
6 ns
tr
6 ns
3.0 V
2.7 V
1.3 V
0.3 V
Enable
Input
tPZL
tPLZ
Output
LOW to
OFF
1.3 V
10%
90%
tPHZ
tPZH
Output
HIGH
to OFF
1.3 V
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
Figure 19 - Three State Outputs and Enable Timings
AC Electrical Characteristics† - Uncommitted NAND Gate
Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
85 pF Load
85 pF Load
1
2
Propagation delay (LOW to
HIGH), input Ai or Bi to output
t
t
11
ns
PLH
Propagation delay (HIGH to
LOW), input Ai or Bi to output
15
ns
PHL
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-60
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