LX1688CPW [MICROSEMI]
MULTIPLE LAMP CCFL CONTROLLER; 多灯CCFL控制器
| 型号： | LX1688CPW |
| 厂家： | 
Microsemi |
| 描述： | MULTIPLE LAMP CCFL CONTROLLER |
| 文件： | 总15页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
KEY FEATURES
DESCRIPTION
Provision to synchronize lamp
current & frequency with other
controllers
The LX1688 is a fixed frequency, generation technique.
dual current/voltage mode, switching
regulator that provides the control
function for Cold Cathode Fluorescent
Lighting (CCFL). This controller can
be used to drive a single lamp, but is
specifically designed for multiple lamp
LCD panels. The IC can be configured
as a master or slave and synchronize up
to 12 controllers.
Safety and reliability features
include a dual feedback control loop that
permits regulation of maximum lamp
strike voltage as well as lamp current.
Regulating maximum lamp voltage
permits the designer to provide for ample
worst-case lamp strike voltage while
conservatively limiting maximum open
circuit voltage. In addition the controller
Dimming with analog or digital
(PWM) methods (>20:1)
Programmable Fixed frequency
Adjustable Power-up reset
ENABLE/BRITE Polarity Selection
Voltage limiting on step-up
transformer secondary winding
Open lamp timeout circuitry
Switched VDD output (10mA)
Micro-Amp Sleep Mode
The LX1688 includes highly features include auto shutdown for an
integrated universal ‘PWM or DC’ open or broken lamp, and a lamp fault
dim input that allows either a PWM or detection with a status reporting output.
Operates with 3.3V to 5V Supply
100mA output drive capability
DC input to adjust brightness without
requiring external conditioning, since a
single external capacitor CPWM can
be used to integrate a PWM input.
Burst mode dimming is possible if the
user supplies a low frequency PWM
signal on the BRITE input and no
CPWM capacitor is used. The
controller utilizes Linfinity’s patented
direct drive fixed frequency topology
and patented resonant lamp strike
To improve design flexibility the IC
includes the ability to select the polarity
of both the chip enable and dim (BRITE)
inputs. Also included is a switched VDD
output of up to 10mA that will allow the
user to power other circuitry that can be
switched on and off with the inverters
enable input. This preserves the micro
power sleep mode with no additional
components.
APPLICATIONS/BENEFITS
Desktop LCD Monitors
Multiple lamp panels
Low Ambient Light Displays
High Efficiency
Lower Cost than Conventional
Buck/Royer Inverter Topologies
Improved Lamp Strike Capability
Improved Over-Voltage Control
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PRODUCT HIGHLIGHT
DIM M ING (BRITE)
ENABLE
LAM PS
IN PUT
CO NNECTO R
LX1688
M ASTER
STRIKE
STATUS
125 Hz 5% Duty cycle Burst
65KHz run frequency
FAULT
1
FAULT
FAULT
1
2
BRITE
ENABLE
LX1688
SLAVE
STRIKE
STATUS
VDD
FAULT
2
Ch3
Ch2
100µs
M
10.0mV Ω
10.0mV Ω
Simplified quad lamp inverter showing synchronized output waveforms
PACKAGE ORDER INFO
Plastic TSSOP
24-Pin
MIN VDD
MAX VDD
TJ (°C)
PW
0 to 70
-40 to 85
3.0V
3.0V
5.5V
5.5V
LX1688CPW
LX1688IPW
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 1
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Supply Voltage (VDD_P, VDD)....................................................................... 6.5V
Digital Inputs ..............................................................................-0.3V to VDD +0.5V
Analog Inputs............................................................................–0.1V to VDD +0.5V
Digital Outputs ..........................................................................-0.3V to VDD +0.5V
Analog Outputs .........................................................................-0.1V to VDD +0.5V
Operating Junction Temperature ..................................................................125°C
Storage Temperature....................................................................................150°C
Lead Temperature (Soldering, 10 Seconds) .................................................300°C
1
2
3
24
23
22
21
20
19
18
17
16
15
14
13
AOUT
VSS_P
VSS
BOUT
VDD_P
VDD
4
VDDSW
TRI_C
OLSNS
ISNS
BEPOL
5
6
7
8
BRITE
CPOR
ENABLE
I_R
ICOMP
VCOMP
VSNS
SLAVE
FAULT
9
CPWM1
CPWM2
RMP_RST
PHA_SYNC
10
11
12
Note 1: Exceeding these ratings could cause damage to the device. All voltages are with
PWPACKAGE
(Top View)
THERMAL DATA
Plastic TSSOP 24-Pin
PW
100°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
Junction Temperature Calculation: T = T + (P x θ ).
JC
J
A
D
The θJA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
Pin Name
AOUT
Description
Pin Name
BOUT
Description
Output Driver A
Output Driver B
Connects to dedicated GND for Aout and
Bout Drivers
Connects to dedicated VDD for Aout and
Bout Drivers
VSS_P
VSS
VDD_P
VDD
Connects to analog GND
Connects to analog VDD
Tri-mode input pin to control the polarity of
the ENABLE and BRITE signal
Analog/PWM input for brightness control
Connects an external capacitor CPOR to
VDD and is used for setting power-up reset
pulse width.
Switchable VDD output controlled by
ENABLE
BEPOL
BRITE
VDDSW
TRI_C
Connects to external capacitor CTRI
Analog input to detect open-lamp condition
CPOR
OLSNS
Analog input from lamp current, has built-in
300mv offset
Used to enable or disable the chip
ENABLE
I_R
ISNS
Connects to external resistor RI; for bias
current setting for internal oscillator
Connects to external capacitor CPWM, used
for integrating an external digital PWM
signal for analog dimming
Connects to external capacitor CPWM, used
for integrating an external digital PWM
signal for analog dimming.
Current error Amp’s output; connects to
external capacitor CICOMP
ICOMP
Voltage error Amp’s output; connects to
external capacitor CVCOMP, can be used for
soft-start
CPWM1
CPWM2
VCOMP
VSNS
Analog input from transformer output
voltage
If SLAVE = “0”, RMP_RST is a CMOS
output; if SLAVE = “1”, it is a CMOS input
that locks the ramp oscillation frequency to
the master clock
Input control pin for setting the IC either in
Master or Slave mode; “1” for slave mode
and “0” for master mode.
RMP_RST
PHA_SYNC
SLAVE
FAULT
If SLAVE= “0”, PHA_SYNC is a CMOS
output; if SLAVE = “1”, it is a CMOS input
Digital output to indicate maximum number
of lamp striking attempts has occurred
without lamp ignition.
that
make
the
AOUT/BOUT
phase
synchronous with the master
Copyright 2001
Microsemi
Page 2
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
RECOMMENDED OPERATING CONDITIONS
LX1688
Typ
Parameter
Units
Min
Max
Supply Voltage (VDD ,VDDP
BRITE Linear DC Voltage Range
BRITE PWM Logic Signal Voltage Range
Digital Inputs (SLAVE, PHA_SYNC, RMP_RST, BEPOL, ENABLE )
)
3
1
0
0
5.5
2.5
VDD
VDD
V
V
V
V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, specifications apply over the range: TA=-40 to 85OC, VDD (For LX1688IWP) & TA= 0 to 70OC, VDD (For LX1688CWP),
VDD_P = 3.0 to 5.5V. RI = 80Kohms, CTRI = 0.083µF
LX1688
Parameter
Symbol
Test Conditions
Units
Min
Typ.
Max
Dimmer
VBRITE_MAX
VBRITE_MIN
VBRITE_MAX
VBRITE_MIN
VBRT_FULL
VBRT_DARK
VTH_IAMP
VBEPOL = VDD
2.6
0.4
2.5
0.5
0.5
2.5
2.0
0
Conventional¹ Dimming
BRITE Input Voltage
V
V
VBEPOL = VDD
VBEPOL = VSS or float
VBEPOL = VSS or float
VBEPOL = VSS, VBRITE = 0.4V
VBEPOL = VSS, VBRITE = 2.6V
TA= 0 to 70OC
0.4
Reverse Dimming
BRITE Input Voltage
2.6
Max Brightness VBRT Voltage
Full-darkness VBRT voltage
1.90
2.05
0.05
450
550
V
V
ISNS input threshold voltage
ISNS input threshold voltage
BRITE-to-ICOMP propagation delay
Strike and Ramp Generator
Max. number of strike before fault
150
150
300
300
2
mV
mV
µS
VTH_IAMP
TA=-40 to 85OC
TD_BRITE
NFAULT
VP_TRI
63
Triangular Wave Generator Analog Output
2.3
2.5
0.3
2.6
0.40
13
V
V
Peak Voltage
Triangular Wave Generator Analog Output
Valley Voltage
VV_TRI
0.15
Triangular Wave Generator Oscillation
F_TRI
FMAX_STK
FLAMP
7
10
195
65
Hz
Frequency
Max. Lamp Strike Frequency
Lamp Run Frequency
FMAX_STK = FLAMP X ~2.5
150
60
KHz
KHz
VOLSNS > 0.65V; VDD=5V
70
70
TA= 0 to 70OC
VOLSNS > 0.65V; VDD=5V
TA=-40 to 85OC
Lamp Run Frequency
FLAMP
57
65
KHz
Lamp Run Frequency regulation over VDD
OLSNS threshold voltage
FLAMP_REG
VTH_OLSNS
VH_OLSNS
TD_OLSNS
VOLSNS > 0.65V
4
800
400
6
% /V
‘mV
‘mV
us
650
300
840
500
1
OLSNS hysteresis
OLSNS-to-ICOMP propagation delay
GBNT ²
Fault, PHA_SYNC, RMP_RST, logic high
VH
VDD – 0.5
V
threshold
Fault, PHA_SYNC, RMP_RST, logic low
threshold
Minimum Fault-pin output current
VL
0.7
15
1
V
I_FAULT
10
‘mA
¹Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage
² Guaranteed but not production tested
Copyright 2001
Microsemi
Page 3
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1688
Typ.
Parameter
Symbol
Test Conditions
Units
Min
Max
Strike and Ramp Generator (continued)
Minimum PHA_SYNC-pin output current
Minimum RMP_RST-pin output current
Minimum A_SYNC output pulse duty-cycle
Minimum A_SYNC input pulse duty-cycle
Minimum RMP_RST output pulse duty-cycle
Minimum RMP_RST input pulse duty-cycle
Output Buffer
I_PHA_SYNC
I_RMP_RST
DO_ASYNC
DI_ASYNC
DO_RST
VSLAVE = 0V
10
10
49
48
10
5
‘mA
mA
%
%
%
VSLAVE = 0V
VSLAVE = 0V
VSLAVE = VDD
VSLAVE = 0V
VSLAVE = VDD
50
50
17
DI_RST
%
VAOUT
VDD = 5.5V
VAOUT BOUT = 4.5V
VDD = 5.5V
, BOUT = 1V
Output Sink Current
ISK_OUTBUF
IS_OUTBUF
100
100
‘mA
‘mA
,
Output Source Current
Output Sink Current
Output Source Current
Output Sink Current
ISK_OUTBUF
IS_OUTBUF
ISK_OUTBUF
VAOUT
VAOUT
VAOUT
,
,
,
BOUT = 1V, VDD = 3V
BOUT = 2V, VDD = 3V
BOUT = 1V, VDD = 5.5V
50
50
100
‘mA
‘mA
‘mA
PWM
V
‘mA
µmho
µA
VSNS threshold voltage
VCOMP Discharge Current
IAMP transconductance
VAMP, IAMP output source current
VAMP, IAMP output sink current
ICOMP discharge current
VAMP transconductance
ICOMP-to-output propagation delay
BIAS
VTH_VSNS
ID_VCOMP
GM_IAMP
IS_IAMP
ISK_IAMP
ID_ICOMP
GM_ICMP
TD_ICOMP
1.2
1.25
4
200
75
75
10
1.3
∆ISNS = 0.2V
VCOMP, ICOMP = 0
VCOMP, ICOMP =VDD
100
500
µA
‘mA
µmho
nS
∆VSNS = 0.1V
200
0.95
10
500
1100
800
V
µA
mS
‘mA
µA
Voltage at Pin I_R
V_IR
IMAX_IR
TPOR
1.05
Pin I_R max. source current
Power-on Reset Pulse Width
Minimum VDDSW sourcing Current
50
31
25
CPOR =.1uF
(VDD – VDDSW) < 0.2V
IMIN_VDDSW
VENABLE = 0.8V, VBEPOL = VDD
V
DDSW Off Current
IOFF_VDDSW
1
15
VDDSW = 0V
General
mA
mA
Operating Current
IDD
VDD = VDD_P = 5V
5.5
2
8
4
VOLSNS = VDD = VDD_P = 5V,
Output buffer operating current
IDD_P
CA = CB = 1000pF
V
V
ENABLE logic threshold
ENABLE threshold hysteresis
VTH_EN
VTH_EN
0.8
1.7
0.2
2.4
VENABLE = 0.8V
IDD_SLEEP
IDD_SLEEP
IDD_SLEEP
IDD_SLEEP
20
20
20
20
50
50
Sleep-mode current (see table-1 for Pin
ENABLE polarity)
(VBEPOL = VDD or float)
VENABLE = 2.5V
(VBEPOL = VDD or float)
VENABLE = 0.8V
µA
300
(VBEPOL = VSS
)
VDD_P Leakage in Sleep Mode
VENABLE = 2.5V
300
2.9
(VBEPOL = VSS
)
V
mV
UVLO threshold
UVLO hysteresis
VTH_UVLO
VH_UVLO
Rising turn-on threshold
Falling turn-off hysteresis
2.6
2.8
190
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 4
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
CHARACTERISTIC CURVES
Typical Operating Current (VDD) ISNS Input Threshold Voltage Vs Temperature
6
5.5
5
380
360
340
320
300
280
260
240
220
200
180
VDD=5.5V
VDD=3V
VDD=5.5V
VDD=3V
4.5
4
3.5
3
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Output Frequency Vs Temperature
Under Voltage Lockout Vs Temperature
70
68
66
64
62
60
58
56
2.9
2.85
2.8
Turn On
VDD=5V
2.75
2.7
VDD=3V
2.65
2.6
Turn Off
2.55
2.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
I_R Voltage Vs Temperature VDD=V
Power-on-Reset Pulse Width Vs Temperature VDD=5V
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
40
35
30
25
20
15
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Copyright 2001
Microsemi
Page 5
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
TABLE 1
Pin BEPOL
VDD
FLOAT
VSS
ENABLE POLARITY
DIMMING POLARITY*
CONVENTIONAL
REVERSE
+ (HI = CHIP_ON, LOW = CHIP_OFF
+ (HI = CHIP_ON, LOW = CHIP_OFF)
- (LOW = CHIP_ON, HI = CHIP_OFF)
REVERSE
* Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin.
Reverse polarity means that brightness decreases with increasing voltage
OPERATIONAL MODES
Controller
Mode
Controller
Operation
Input Pin:
OLSNS
Input Pin:
SLAVE
Output Pin:
FAULT
Lamp
Frequency
Pin: RMP_RST
Output: FINT
Pin: A_SYNC
Output: FINT / 2
Output: FINT / 2
Run
> 0.6V
< 0.2V
VSS
VSS
L
L
FINT / 2
Ramping up /
Master
Slave
Striking
Output: FINT
down
Fault
Run
X
VSS
VDD
H
L
Output: FINT
Input: FEXT
Output: FINT / 2
Input: FEXT / 2
Off
FEXT / 2
> 0.6V
Ramping up /
Striking
Fault
< 0.2V
X
VDD
VDD
L
Input: FEXT
Input: FEXT
Input: FEXT / 2
Input: FEXT / 2
down
H
Off
BLOCK DIAGRAM
VCOMP ICOMP
VSNS
ISNS
FEXT/2
VDD_P
VOLTAGE
ERROR AMP
COMPARATOR
TFF R
PWR_ GD
Q
A OUT
1.25V
VAMP
PHA_SYNC
Q
PWR_ BD
T
OUTPUT
PWR_ GD
FAULT
STEERING
LOGIC
RAMP RUN
GENERATOR
FINT
PWR_BD
FAULT
SLAVE
Q
B OUT
VSS_P
STRIKE
GENERATOR
RMP_RST
FEXT
300mV
CURRENT
IAMP
COMPARATOR
1V
1V
+
-
+
200K
-
BRT
2.5V
800mV
600mV
100K
100K
100K
100K
BRITE
0-2V
+
IGNITE
-
OLSNS
TRI_C
0.5V
CPW 1
CPW 2
BEPOL
TRI WAVE
GEN
6 BIT
COUNTER
PWR_ BD
1M
VDD
POLARITY
DECODE
BIAS GEN
UVLO
PWR_GD
1M
TTL
FAULT
BUF
FAULT
PWR_BD
TTL
BUF
ENABLE
VDDSW
INTERNAL VDD
VSS
VSS
VDD
CPOR
I_R
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 6
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
DETAILED DESCRIPTION
The LX1688 is a backlight controller specifically
and Slave Input/Output are used.
RMP_RST and
designed with a special feature set needed in multiple
lamp desktop monitors, and other multiple lamp displays.
While utilizing the same architecture as Linfinity’s
LX1686 controller it eliminates the synchronized digital
dimming and adds, lamp ‘strike’ count out timer, lamp
fault status output, and external clock input/output that
permits multiple controllers to synchronize their output
current both in frequency and phase.
PHA_SYNC should be connected between all the
controllers. The master controller should have its SLAVE
pin connected to VSS (GND) and the slave controllers
SLAVE input to VDD (High).
BEPOL Input
The BEPOL pin is a tri-mode input that controls the
polarity of the ENABLE and BRITE input signals.
Depending on the state of this pin (VDD, floating, or VSS)
the controller can be set to allow active high enable with
active high full brightness or active high or low enable with
active low full brightness (see Table 1).
Operation From 3.3V and/or 5.0V Input Supply
The LX1688 is designed to operate and meet all
specifications at 3.3V ±10% to 5.0V ±10%. The under
voltage lockout is set at nominally 2.8V with a 190mV
hysteresis.
BRITE Input (Dimming Input)
The BRITE input is capable of accepting either a DC
voltage (≥.5V to ≤2.5V) or a PWM digital signal that is
clamped on chip (<.5V or >2.5V). A digital signal can
either be passed unfiltered to effect pulse ‘digital’ dimming
or filtered with a capacitor to effect analog dimming with a
digital PWM signal.
Master/Slave Clock Synchronization
One or more controllers (up to 11) may be designated
as slave controllers and receive ramp reset and phase
synchronization from the designated master controller.
This will allow up to 12 lamps (24 with two lamps in
series/controller design) to all operate in phase and
frequency synchronization. This is important to prevent
Analog Dimming Methods:
• Mechanical or digital potentiometer set to provide 1V
to 2.5V on the wiper output. A filter cap from BRITE
to signal ground is recommended.
random
interference
between
lamps
through
unpredictably changing electric and magnetic fields that
will inevitably link them.
• D/A converter output directly connected to BRITE
input. A R/C filter using a capacitor from the CPW1
input to ground for applications where the ADC
output may contain noise sufficient to modulate the
BRITE input.
• A high frequency PWM digital logic pulse connected
directly to the BRITE input. The Brightness (BRT,
internal node) output will be sensitive only to the
PWM duty cycle, and not to the PWM signal
amplitude, so long as the amplitude exceeds 2.6V for
a logic high (1) and is less than .4V for a logic (0).
This pulse frequency will typically be between 1KHz
and 100KHz and will not be synchronized with the
LCD video frame rate. A capacitor (CPWM) between
CPW1 and CPW2 will integrate the PWM signal for
use by the controller.
The LX1688 has two independent oscillators, one for
lamp strike and one for the lamp run frequency. The
strike oscillator ramps the operating frequency slowly up
and down when the open lamp sense input (OLSNS)
indicates the lamp is not ignited. During this lamp strike
condition the operating frequency of each IC will vary up
and down as needed to strike its lamp. The controller is
so designed that the master controller clock remains at the
pre-selected frequency for fully ignited lamps even while
striking. Likewise the designated slave controller will not
alter the frequency or phase of the master clock during its
strike phase. Thus each controller will vary its frequency
as needed to strike its lamp then it will synchronize to the
master clock frequency and phase.
The TRI_C wave generator (see Block Diagram) sets
the rate of operating frequency variation during lamp
strike. The TRI_C generator is connected to a 6-bit
counter that times out after 63 cycles and then latches the
FAULT output high if the OLSNS input indicates no
lamp current is flowing. Even in the case of timeout fault
the master controller clock will continue to provide
synchronization to the slave controllers.
Digital Dimming Methods:
• Low frequency PWM digital logic pulses connected
directly to the BRITE input. As above the Brightness
(BRT internal) will be sensitive only to the PWM
duty cycle, and not to the PWM signal amplitude, so
long as the amplitude exceeds 2.6V for a logic high
(1) and is less than .4V for a logic (0). This pulse
frequency will typically be in the range of 90-320Hz
When synchronizing more than one controller the
Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC),
Copyright 2001
Microsemi
Page 7
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
DETAILED DESCRIPTION (CO N T I N U E D )
and may or may not be externally synchronized to the
can thus be adjusted by varying the value of RI-R, the typical
LCD video frame rate. It will directly gate the signal
range from about 50K to 100K. Since there is some
variation in the frequency due to change in the input supply
(VDD) it is recommended that the value of RI-R be selected
at the nominal input voltage.
BRT. CPWM should not be used in this case.
Fault Pin
The fault pin is a digital output that indicates that the
maximum numbers of strike attempts has occurred
without lamp ignition. In this condition the FAULT pin
will go active high with typically 20mA drive capability.
Holding the OLSNS pin low (<200mV) will also force
timeout and activate the FAULT pin. When used as a
master, fault condition true does not inhibit master clock
outputs PHA_SYNC and RMP_RST.
Sleep Mode (ENABLE Signal) and Switched VDD
(VDDSW)
Since the LX1688 can be used in portable battery
operated systems, a very low power sleep mode is included.
The IC will consume less than 10µA quiescent current from
both the VDD and VDD_P pins combined, when the
ENABLE pin is deactivated. The polarity of the ENABLE
pin is programmable by the BEPOL input (see table 1). In
addition the controller provides a switched supply pin
VDDSW this output supplies at least 10mA at VDD ─ .2V
for external circuitry. This output can be used to power
additional circuitry that can be enabled with the controller.
I_R Pin
The run mode frequency of the output is one half the
internal ramp frequency, which is proportional to a bias
current set by resistor RI of 80.6K. The output frequency
BIAS & TIMING EQUATIONS
Formula 1:
Formula 2:
Triangular Wave Generator Frequency, FTRI
Lamp Frequency (AOUT’s switching frequency), FLAMP
1
1
FTRI
=
[Hz]
FLAMP
=
[Hz]
I
(25× R
I
×CTRI
)
200e-12× R
Formula 3:
Formula 4:
Minimum Current Error Amp Bandwidth, BWIEA_MIN
Minimum Voltage Error Amp Bandwidth, BWVEA_MIN
0.000048
0.000048
BWIEA_MIN
=
[Hz]
BWVEA_MIN
=
[Hz]
C
ICOMP
C
VCOMP
Formula 5:
Softstart time, TSS
Formula 6:
Minimum Power-on Reset Pulse Width, TMIN_POR
MIN_POR = 2.3e6×CPOR [sec]
T
SS = 4,500,000 ×CVCOMP [sec]
T
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 8
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
TYPICAL APPLICATION
CN1
VIN
VIN
GND
GND
1
2
3
4
5
6
7
C1
10%
470nF 16V
U2
SI9945AEY
VBRITE
RMP_RST
PHA_SYNC
C13
8
T1
CN2
0.1uF 50V
1:75
RMP_RST
PHA_SYNC
1 HV1
R4 39
7
6
5
4
3
2
4
8
9
2
LV1
2
1
ENABLE
2.2PF
PCB
C14
VDDP
VDDP
BC847ALT1
Q2
5
VDDSW
10
39
R5
C12
BC847ALT1
Q1
+
220µ
25V
1
3
R8
C15
100K
2
1
2.2nF
50V 5%
COG
R6
82
D1
R7
3
BAW56
1
24
C2
10K
AOUT
VSS_P
VSS
BEPOL
BRITE
CPOR
ENABLE
I_R
CPWM1
BOUT
VDD_P
VDD
VDD_SW
TRI_C
OLSNS
ISNS
ICOMP
VCOMP
VSNS
16V 10%
470nF
R2 47
2
3
23
22
VDD
Analog Ground must
connect to power
ground at this point
only
C4
C5
VDDSW
220nF
4
220nF
VDD
VDD
16V
10%
D2
16V 10%
C6
20
5
6
7
1
2
82nF
3
16V 10%
C7
19
18
R9
1K
16V 10%
10nF 16V
10% C3
BAW56
C16
100nF
C8
R12
2.74K
1%
3.3nF
2.2nF
3
COG
D3
16V 5%
C9
R10
1M
R1
8
9
17
16
50V 5%
BAV99
4.7nF
2
1
C10 16V 10%
80.6K 1%
10nF
16V 10%
R11
2.74K
1%
C11
10
11
12
15
14
13
10nF
CPWM2
RMP_RST SLAVE
PHA_SYNC FAULT
16V 10%
RMP_RST
PHA_SYNC
R3
220
LED1
OPTION
Figure 1- Schematic for LX1688 Inverter Module configured as a Master
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 9
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
APPLICATION INFORMATION
Application example with LX1688
Setting Master/Slave configuration
This section will highlight the features of LX1688
controller by showing a practical example. Three
identical inverter modules are connected to each other
and each module drives a single lamp. One module
configured as a master and two others configured as
slaves.
Simply connecting pin 14 to the ground for a master and
to the VDD for a slave will do master and slave
configuration. As shown in figure 2, module (A) configured
as master and modules (B) and (C) configured as slaves.
Synchronization of Frequency and Phase
To synchronize the Lamp frequency and phase of all
modules, it is required to connect the RMP_RST pin of all
the modules together and connect PHA_SYNC pin of all the
modules together.
A complete schematic hooked up a a master is given in
Figure 1, the schematic provides all necessary functions
such as high voltage feedback for regulation the peak
lamp voltage, short-circuit protection, open lamp sensing
and lamp current regulation needed for a typical
application. The section follows with measurement
waveforms and list of material of the actual modules. For
more detail design procedure and circuit description
please refer to application note (AN-13), which is
available in Microsemi’s web site.
Layout consideration
By designing the layout in a proper way we can reduce the
overall noise and EMI for the module.
The gate drivers for MOSFETs should have an
independent loop that doesn’t interface with the more
sensitive analog control function, therefore LX1688
provides two power inputs with separate ground pins
(analog/signal), VDD feeds all analog signals and VDD_P
feeds only the output drivers, as shown in figure1 these two
pins (pin 23, 24) are separated and filtered by R14, C2 and
C7. The connection of two ground pins should be at only
one point as shown in figure1.
Input Voltage
The LX1688 controller can operate at 3.3 to 5.0V
±10%, in this application all modules were driven by the
same power voltage (a constant 5.0V), which provides
VDD for controllers, and input voltage for the power
section. Notice that VDD feeds all analog signals and
VDD_P feeds only the output driver stage, these two
signals should be filtered separately (Figure 1).
The power traces should be short and wide as possible and
all periphery components such capacitors should be located
as closed as possible to the controller.
Setting lamp frequency
Oscilloscope Waveforms Pictures
The value of R1 determines magnitude of internal
The following oscilloscope waveform pictures are taken
from the actual circuits and will show the operation of the
modules in different modes when three identical modules
are synchronized, one as a master, and two others as slaves.
current sources that set timing parameters. Equation (2)
gives the relationship between Lamp frequency (FLAMP
)
and (RI_R), R1 in schematic. For this application we
choose R6=80.6 Kohm, which results to a lamp
frequency at 62.0 KHz.
Dimming
The LX1688 includes highly integrated universal
‘PWM or DC’ dim input that allows either a PWM or DC
input without requiring external conditioning.
In this application we choose Digital Dimming by
applying a PWM signal to BRITE pin.
All modules were driven by the same PWM signals,
but notice that it is possible to dim each module quite
separately.
BEPOL pin has three different modes (see table 1), in
this application it is connected to VDD which means
active high enable with active high full brightness.
The PWM signal can be varied in frequency between
48-320 HZ. No capacitor between CPWM1 and CPWM2
is necessary.
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 10
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
TYPICAL SLAVE APPLICATIONS
VDDP
CN
1
C1
470nF 16V
10%
VIN
1
VIN
2
3
GND
GND
C2
4
5
1
2
3
24
23
22
AOU
T
BOU
T
470nF 16V
10%
VBRITE
6
7
8
RMP_RST
VDD
R2
47
VSS_P
VSS
VDD_P
VDD
PHA_SYNC
ENABLE
VDDSW
9
C4
VDDSW
VDD
10
4
5
6
7
8
21
220nF
16v 10%
C5
BEPOL
VDD_SW
VBRITE
20
19
C6
TRI_
C
BRITE
CPOR
C7
C8
Power
Output
Section
OLSNS
C3 10nF
16V 10%
18
17
ENABLE
I_R
ISNS
ICOMP
VCOMP
VSNS
C9
R1
80.6K 1% 9
16
15
C10
CPWM1
CPWM2
10
C11
11
12
14
13
RMP_RST
PHA-SYNC
RMP_RST
SLAVE
FAUL
T
PHA_SYNC
R3
220
LED1
C5 : 220nF 16V 10%
C6 : 82nF 16V 10%
C7 : 100nF 16V 10%
C8 : 2.2nF 50V 5%
C9 : 4.7nF 16V 10%
C10-11 : 10nF 16V 10%
Master
VDDP
VDDP
C1a
470nF 16V
10%
C1b
470nF 16V
10%
CN1
CN1
VIN
VIN
1
1
2
3
VIN
VIN
2
GND
GND
3
GND
GND
4
C2a
470nF 16V
10%
C2b
470nF 16V
10%
4
5
1
24
23
22
1
24
23
22
AOU
T
BOU
T
AOU
T
BOU
T
5
VBRITE
VBRITE
6
6
7
8
2
3
2
3
RMP_RST
RMP_RST
7
VDD
VDD
R2a
47
R2b
47
VSS_P
VSS
VDD_P
VSS_P
VSS
VDD_P
VDD
PHA_SYNC
PHA_SYNC
8
ENABLE
VDDSW
ENABLE
9
VDD
9
C4a
C4b
VDDSW
10
VDDSW
VDDSW
VDD
VDD
10
4
5
6
7
8
21
220nF
4
5
6
7
8
21
220nF
16v 10%
C5a
C5b
16v 10%
BEPOL
VDD_SW
BEPOL
VDD_SW
VBRITE
VBRITE
20
19
20
19
TRI_
C
C6a
TRI_
C
C6b
BRITE
CPOR
BRITE
CPOR
C7a
C8a
C7b
C8b
Power
Output
Section
Power
Output
Section
OLSNS
OLSNS
C3b 10nF
16V 10%
C3a 10nF
16V 10%
18
17
18
17
ENABLE
I_R
ISNS
ENABLE
I_R
ISNS
ICOMP
VCOMP
VSNS
ICOMP
VCOMP
VSNS
C9a
C9b
R1a
R1b
80.6K 1% 9
80.6K 1% 9
16
15
C10a
16
15
C10b
CPWM1
CPWM2
CPWM1
CPWM2
10
10
C11a
C11b
11
12
14
13
11
12
14
13
RMP_RST
PHA-SYNC
RMP_RST
PHA-SYNC
RMP_RST
SLAVE
RMP_RST
SLAVE
FAUL
T
FAUL
T
PHA_SYNC
PHA_SYNC
R3a
220
R3b
220
VDDSW
VDDSW
R13a
100K
R13b
100K
Slave 1
Slave 2
LED1a
LED1b
C5a: 220nF 16V 10%
C6a: 82nF 16V 10%
C7a: 100nF 16V 10%
C8a: 2.2nF 50V 5%
C9a: 4.7nF 16V 10%
C10-11a: 10nF 16V 10%
C5b: 220nF 16V 10%
C6b: 82nF 16V 10%
C7b: 100nF 16V 10%
C8b: 2.2nF 50V 5%
C9b: 4.7nF 16V 10%
C10-11b: 10nF 16V 10%
Figure 2- Schematic modules connected as a Master and Slaves
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 11
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
APPLICATION INFORMATION (CONTINUED)
Multiple Lamp Sync
Strike Mode
The figure 3 shows the sync signals (PHA_SYNC and
RMP_RST) timing relationship to Gate signal AOUT,
for the master module. AOUT and PHA_SYNC running
at the same frequency and RMP_RST signal has the
twice frequency.
Every IC includes a separate strike controller that operates
from the primary oscillator; therefore the strike controller is
independent of the sync signals. The following oscilloscope
waveform picture is taken when the master module is on
striking mode and the salves are on running mode.
Figure 3- Sync signals-Timing relationship to AOUT
CH2= AOUT(Master), CH3=PHA_SYNC,
CH4=RMP_RST
Figure 5- Master is in striking mode while slaves are in
running mode CH2= AOUT(Master),
CH3=AOUT(Slave1), CH4=AOUT(Slave2)
Output Drivers
The figure 4 shows the gate signals of the modules,
which are operating, in running mode during digital
dimming with 95% duty cycle. As shown all signals are
synchronized. The difference between each signal’s duty
cycles is because each lamp has an independent control
loop.
Figure 4- Output drivers of both Master
and Slaves.
CH2=AOUT(Master),
CH3=AOUT(Slave1),
CH4=AOUT(Slave2)
Copyright 2001
Microsemi
Page 12
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
APPLICATION INFORMATION (CONTINUED)
Digital Dimming
The following oscilloscope waveforms are showing gate
signals of Master and slaves during digital dimming at 50%
and 5% duty cycle.
Figure 7- Gate signals during digital dimming with 5% duty
Figure 6- Gate signals during digital dimming with 50%
duty cycle CH2= AOUT(Master),
cycle CH2= AOUT(Master), CH3=AOUT(Slave1),
CH4=AOUT(Slave2)
CH3=AOUT(Slave1), CH4=AOUT(Slave2)
Output currents
Figure 8 shows the output current of master and slaves
during digital dimming with 5% duty cycle. The lamp currents
are operating in phase and frequency synchronization. This
prevents random interface between controllers and reduces
EMI.
Figure 8- Output current during
digital dimming with 5%
duty cycle R1= out(Master)
R2=Iout(Slave1)
R3=Iout(Slave2)
Lamp Current at 10mA/Div
Copyright 2001
Microsemi
Page 13
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
LX1688 MODULE BOARD LIST OF MATERIAL
Reference
Designator
U1
Part Description
Manufacture
Part Number
Backlight Controller
Dual N-Channel MOSFET
NPN Transistor
Dual Diode
LX1688
Si9945AEY
BC847ALT1
BAW56
Microsemi
Siliconix
Motorola
Motorola
Philips
U2
Q1, Q2
D1, D2
D3
LED1
R1
Dual Diode
BAV99
LED
80.6 K 1% 1/16 W
47 ohm 5% 1/8 W
220 ohm 5% 1/8 W
R2
R3
39 ohm 5% 1/16 W
82 ohm 5% 1/16 W
10 K 5% 1/16 W
100 K 5% 1/16 W
1 K 5% 1/16 W
R4, R5
R6
R7
R8
R9
1 M 5% 1/16 W
R10
2.74 K 1% 1/16 W
R11, R12
470 nF 16V 10% X7R 1206
10 nF 16V 10% 0805
220 nF 16V 10% X7R 1206
220 nF 16V 20% 0805
82 nF 16V 10% X7R 0603
100 nF 16V 20% X7R
2.2 nF 50V 10%
C1, C2
C3
C4
C5
C6
C7
C8
C9
C10, C11
C12
C13
C14
C15
C16
T1
NOVACAP
0805YC224MAT2A
0603YC823KAT2A
0603YC104MAT2A
0603B22K500NT
0603YC472KAT2A
0603YC103KAT2A
AVX
AVX
AVX
NOVACAP
AVX
AVX
AVX
NOVACAP
4.7 nF 16V 10% X7R
10 nF 16V 10% X7R
220 uF Tantalum 7343
220 pF 2KV 5% COG
2.2 pF PCB
1206N221J202NT
2.2nF 50V 5% COG
3.3 nF 50V 5% COG
08055A222JAT2A
0805N332J500NT
SGE2645-1
AVX
NOVACAP
Microsemi
Low profile, High voltage xfmr,
turns ratio 1:75
CN1
CN2
Connector, 10 pin
53261-1090
Molex
Molex
Connector, 2 pin
Table 2- List of material for LX1688 inverter module
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Page 14
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
I N T E G R A T E D P R O D U C T S
MULTIPLE LAMP CCFL CONTROLLER
PHYSICAL DIMENSIONS
PW
24-PIN THIN SMALL SHRINK OUTLINE (TSSOP)
3 2 1
P
E
F
D
E
A
H
L
SEATING PLANE
B
C
G
M
MILLIMETERS
INCHES
Dim
MIN
0.85
0.19
0.09
7.70
4.30
MAX
0.95
0.30
0.20
7.90
4.50
MIN
MAX
0.037
0.012
A
B
0.033
0.007
C
0.0035 0.008
D
0.303
0.169
0.311
0.177
E
F
0.65 BSC
0.025 BSC
G
H
0.05
–
0.15
1.10
0.75
8°
0.002
–
0.005
.0433
0.030
8°
L
0.50
0°
0.020
0°
M
P
6.4 BSC
0.252 BSC
*LC
–
0.10
–
0.004
Note:
1. Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm(.006”) on any side.
Lead dimension shall not include solder coverage
PRODUCTION DATA – Information contained in this document is proprietary to Microsemi
and is current as of publication date. This document may not be modified in any way without
the express written consent of Microsemi. Product processing does not necessarily include
testing of all parameters. Microsemi reserves the right to change the configuration and
performance of the product and to discontinue product at any time.
Copyright 2001
Microsemi
Page 15
Rev. 1.1a, 2003-03-21
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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