LX1688IPW-TR [MICROSEMI]
Multiple Lamp CCFL Controller; 多灯CCFL控制器
| 型号： | LX1688IPW-TR |
| 厂家： | 
Microsemi |
| 描述： | Multiple Lamp CCFL Controller |
| 文件： | 总16页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
KEY FEATURES
DESCRIPTION
Provision to Synchronize Lamp
Current & Frequency With Other
Controllers
Dimming With Analog or Digital
(PWM) Methods (>20:1)
Programmable Fixed Frequency
Adjustable Power-up Reset
ENABLE/BRITE Polarity Selection
Voltage Limiting on Step-up
Transformer Secondary Winding
Open Lamp Timeout Circuitry
Switched VDD Output (10mA)
Micro-Amp Sleep Mode
The LX1688 is a fixed frequency, dual
current/voltage mode, switching regulator dual feedback control loop that permits
that provides the control function for Cold regulation of maximum lamp strike voltage
Safety and reliability features include a
Cathode Fluorescent Lighting (CCFL). as well as lamp current.
Regulating
This controller can be used to drive a maximum lamp voltage permits the designer
single lamp, but is specifically designed to provide for ample worst-case lamp strike
for multiple lamp LCD panels. The IC can voltage while conservatively limiting
be configured as a master or slave and maximum open circuit voltage. In addition
synchronize up to 12 controllers.
the controller features include auto
The LX1688 includes highly integrated shutdown for an open or broken lamp, and a
universal ‘PWM or DC’ dim input that lamp fault detection with a status reporting
allows either a PWM or DC input to adjust output.
Operates With 3.3V to 5V Supply
100mA Output Drive Capability
brightness without requiring external
To improve design flexibility the IC
conditioning, since single external includes the ability to select the polarity of
a
capacitor CPWM can be used to integrate both the chip enable and dim (BRITE)
a PWM input. Burst mode dimming is inputs. Also included is a switched VDD
A P P L I C A T I O N S / B E N E F I T S
possible if the user supplies
a low output of up to 10mA that will allow the
Desktop LCD Monitors
Multiple Lamp Panels
frequency PWM signal on the BRITE user to power other circuitry that can be
input and no CPWM capacitor is used. The switched on and off with the inverters
controller utilizes Microsemi’s patented enable input. This preserves the micro
direct drive fixed frequency topology and power sleep mode with no additional
patented resonant lamp strike generation components.
Low Ambient Light Displays
High Efficiency
Lower Cost than Conventional
Buck/Royer Inverter Topologies
Improved Lamp Strike Capability
Improved Over-Voltage Control
technique.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
Protected by U.S. Patents 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending
PRODUCT HIGHLIGHT
DIMMING (BRITE)
ENABLE
LAMPS
INPUT
CONNECTOR
LX1688
MASTER
STRIKE
STATUS
125 Hz 5% Duty cycle Burst
65KHz run frequency
FAULT 1
FAULT 1
FAULT 2
BRITE
ENABLE
LX1688
SLAVE
STRIKE
STATUS
VDD
FAULT 2
Ch3
100µs
M
10.0mV Ω
Ch2
10.0mV Ω
Simplified Quad Lamp Inverter Showing Synchronized Output Waveforms
PACKAGE ORDER INFO
Plastic TSSOP
24-Pin
PW
MIN VDD
MAX VDD
TJ (°C)
RoHS compliant / Pb-free Transition DC: 0442
0 to 70
-40 to 85
3.0V
3.0V
5.5V
5.5V
LX1688CPW
LX1688IPW
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1688CPW-TR)
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 1
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Supply Voltage (VDD_P, VDD)................................................................................ 6.5V
Digital Inputs ................................................................................... -0.3V to VDD +0.5V
Analog Inputs.................................................................................. –0.1V to VDD +0.5V
Digital Outputs................................................................................. -0.3V to VDD +0.5V
Analog Outputs................................................................................ -0.1V to VDD +0.5V
Maximum Operating Junction Temperature ............................................................150°C
Storage Temperature................................................................................. -65°C to 150°C
Peak Package Solder Reflow Temp. (40 seconds max. exposure) ................260°C(+0.-5)
1
2
24
23
22
21
20
19
18
17
16
15
14
13
BOUT
AOUT
VSS_P
VDD_P
VDD
VDDSW
TRI_C
OLSNS
ISNS
3
VSS
BEPOL
BRITE
CPOR
ENABLE
I_R
CPWM1
CPWM2
RMP_RST
PHA_SYNC
4
5
6
7
8
ICOMP
VCOMP
VSNS
SLAVE
FAULT
9
10
11
12
PW PACKAGE
Note 1: Exceeding these ratings could cause damage to the device. All voltages are with
respect to Ground. Currents are positive into, negative out of the specified terminal.
(Top View)
RoHS / Pb-free 100% matte Tin Lead Finish
THERMAL DATA
Plastic TSSOP 24-Pin
PW
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
100°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the
above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
Pin Name
AOUT
Description
Pin Name
Description
Output Driver A
BOUT
Output Driver B
Connects to dedicated GND for Aout and Bout
Drivers
Connects to analog GND
Connects to dedicated VDD for Aout and Bout
Drivers
Connects to analog VDD
VSS_P
VSS
VDD_P
VDD
Tri-mode input pin to control the polarity of the
ENABLE and BRITE signal
Analog/PWM input for brightness control
Connects an external capacitor CPOR to VDD and
is used for setting power-up reset pulse width.
BEPOL
BRITE
CPOR
VDDSW
TRI_C
OLSNS
Switchable VDD output controlled by ENABLE
Connects to external capacitor CTRI
Analog input to detect open-lamp condition
Analog input from lamp current, has built-in 300mv
offset
Current error Amp’s output; connects to external
capacitor CICOMP
ENABLE
I_R
Used to enable or disable the chip
ISNS
Connects to external resistor RI; for bias current
setting for internal oscillator
ICOMP
Connects to external capacitor CPWM, used for
integrating an external digital PWM signal for
analog dimming
Voltage error Amp’s output; connects to external
capacitor CVCOMP, can be used for soft-start
CPWM1
CPWM2
VCOMP
VSNS
Connects to external capacitor CPWM, used for
integrating an external digital PWM signal for
analog dimming.
Analog input from transformer output voltage
If SLAVE = “0”, RMP_RST is a CMOS output; if
SLAVE = “1”, it is a CMOS input that locks the
ramp oscillation frequency to the master clock
Input control pin for setting the IC either in Master
or Slave mode; “1” for slave mode and “0” for
master mode.
RMP_RST
SLAVE
FAULT
If SLAVE= “0”, PHA_SYNC is a CMOS output; if
SLAVE = “1”, it is a CMOS input that make the
AOUT/BOUT phase synchronous with the master
Digital output to indicate maximum number of lamp
striking attempts has occurred without lamp
ignition.
PHA_SYNC
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 2
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
RECOMMENDED OPERATING CONDITIONS
LX1688
Typ
Parameter
Units
Min
Max
Supply Voltage (VDD ,VDDP
BRITE Linear DC Voltage Range
BRITE PWM Logic Signal Voltage Range
Digital Inputs (SLAVE, PHA_SYNC, RMP_RST, BEPOL, ENABLE )
)
3
1
0
0
5.5
2.5
VDD
VDD
V
V
V
V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, specifications apply over the range: TA=-40 to 85OC, VDD (For LX1688IWP) & TA= 0 to 70OC, VDD (For
LX1688CWP), VDD_P = 3.0 to 5.5V. RI = 80Kohms, CTRI = 0.083µF
LX1688
Parameter
Symbol
Test Conditions
Units
Min
Typ.
Max
DIMMER
VBRITE_MAX
VBRITE_MIN
VBRITE_MAX
VBRITE_MIN
VBRT_FULL
VBRT_DARK
VTH_IAMP
VBEPOL = VDD
2.6
0.4
2.5
0.5
0.5
2.5
2.0
0
Conventional¹ Dimming
BRITE Input Voltage
V
V
VBEPOL = VDD
VBEPOL = VSS or float
VBEPOL = VSS or float
VBEPOL = VSS, VBRITE = 0.4V
VBEPOL = VSS, VBRITE = 2.6V
TA= 0 to 70OC
0.4
Reverse Dimming
BRITE Input Voltage
2.6
Max Brightness VBRT Voltage
Full-darkness VBRT voltage
1.90
2.05
0.05
450
550
V
V
ISNS input threshold voltage
ISNS input threshold voltage
BRITE-to-ICOMP propagation delay
STRIKE AND RAMP GENERATOR
Max. number of strike before fault
150
150
300
300
2
mV
mV
µS
VTH_IAMP
TA= -40 to 85OC
TD_BRITE
NFAULT
VP_TRI
63
Triangular Wave Generator Analog Output
Peak Voltage
Triangular Wave Generator Analog Output
Valley Voltage
Triangular Wave Generator Oscillation
Frequency
2.3
2.5
0.3
2.6
0.40
13
V
V
VV_TRI
0.15
F_TRI
FMAX_STK
FLAMP
7
10
195
65
Hz
Max. Lamp Strike Frequency
FMAX_STK = FLAMP X ~2.5
150
60
KHz
KHz
VOLSNS > 0.65V; VDD=5V
Lamp Run Frequency
70
70
TA= 0 to 70OC
VOLSNS > 0.65V; VDD=5V
TA=-40 to 85OC
Lamp Run Frequency
FLAMP
57
65
KHz
Lamp Run Frequency regulation over VDD
OLSNS threshold voltage
FLAMP_REG
VTH_OLSNS
VH_OLSNS
TD_OLSNS
VOLSNS > 0.65V
4
6
840
640
1
% /V
‘mV
‘mV
us
740
540
790
590
OLSNS hysteresis
OLSNS-to-ICOMP propagation delay
GBNT ²
Fault, PHA_SYNC, RMP_RST, logic high
threshold
VH
VDD – 0.5
V
Fault, PHA_SYNC, RMP_RST, logic low
threshold
VL
0.7
15
1
V
Minimum Fault-pin output current
I_FAULT
10
‘mA
¹Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing
voltage
² Guaranteed but not production tested
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 3
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1688
Typ.
Parameter
Symbol
Test Conditions
Units
Min
Max
STRIKE AND RAMP GENERATOR (CONTINUED)
Minimum PHA_SYNC-pin output current
Minimum RMP_RST-pin output current
Minimum A_SYNC output pulse duty-cycle
Minimum A_SYNC input pulse duty-cycle
Minimum RMP_RST output pulse duty-cycle
Minimum RMP_RST input pulse duty-cycle
OUTPUT BUFFER
I_PHA_SYNC
VSLAVE = 0V
10
10
49
48
10
5
‘mA
mA
%
I_RMP_RST
DO_ASYNC
DI_ASYNC
DO_RST
VSLAVE = 0V
VSLAVE = 0V
VSLAVE = VDD
VSLAVE = 0V
VSLAVE = VDD
50
50
17
%
%
DI_RST
%
VAOUT
VDD = 5.5V
VAOUT BOUT = 4.5V
VDD = 5.5V
, BOUT = 1V
Output Sink Current
ISK_OUTBUF
IS_OUTBUF
100
100
‘mA
‘mA
,
Output Source Current
Output Sink Current
ISK_OUTBUF
IS_OUTBUF
ISK_OUTBUF
VAOUT
VAOUT
VAOUT
,
,
,
BOUT = 1V, VDD = 3V
BOUT = 2V, VDD = 3V
BOUT = 1V, VDD = 5.5V
50
50
‘mA
‘mA
‘mA
Output Source Current
Output Sink Current
100
PWM
VSNS threshold voltage
VCOMP Discharge Current
IAMP transconductance
VAMP, IAMP output source current
VAMP, IAMP output sink current
ICOMP discharge current
VAMP transconductance
ICOMP-to-output propagation delay
BIAS
VTH_VSNS
ID_VCOMP
GM_IAMP
IS_IAMP
1.2
1.25
4
1.3
V
‘mA
µmho
µA
ΔISNS = 0.2V
100
200
75
500
VCOMP, ICOMP = 0
VCOMP, ICOMP =VDD
ISK_IAMP
ID_ICOMP
GM_ICMP
TD_ICOMP
75
µA
10
‘mA
µmho
nS
ΔVSNS = 0.1V
200
0.95
10
500
1100
800
Voltage at Pin I_R
V_IR
IMAX_IR
1.05
V
Pin I_R max. source current
Power-on Reset Pulse Width
Minimum VDDSW sourcing Current
50
31
25
µA
TPOR
CPOR =.1uF
mS
‘mA
IMIN_VDDSW
(VDD – VDDSW) < 0.2V
VENABLE = 0.8V, VBEPOL = VDD
VDDSW = 0V
VDDSW Off Current
IOFF_VDDSW
1
15
µA
GENERAL
Operating Current
IDD
VDD = VDD_P = 5V
5.5
2
8
4
mA
mA
VOLSNS = VDD = VDD_P = 5V,
CA = CB = 1000pF
Output buffer operating current
IDD_P
V
V
ENABLE logic threshold
VTH_EN
VTH_EN
0.8
1.7
0.2
2.4
ENABLE threshold hysteresis
VENABLE = 0.8V
(VBEPOL = VDD or float)
VENABLE = 2.5V
(VBEPOL = VDD or float)
VENABLE = 0.8V
IDD_SLEEP
IDD_SLEEP
IDD_SLEEP
IDD_SLEEP
20
20
20
20
50
50
Sleep-mode current (see table-1 for Pin
ENABLE polarity)
µA
300
(VBEPOL = VSS
VENABLE = 2.5V
(VBEPOL = VSS
)
VDD_P Leakage in Sleep Mode
300
2.9
)
UVLO threshold
UVLO hysteresis
VTH_UVLO
VH_UVLO
Rising turn-on threshold
Falling turn-off hysteresis
2.6
2.8
V
190
mV
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 4
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
RESPONSE VS WAVELENGTH
IS N K STEP RESPONSE
ISNS Input Threshold Voltage Vs Temperature
Typical Operating Current (VDD)
6
380
360
340
5.5
VDD=5.5V
320
5
VDD=5.5V
300
4.5
280
260
VDD=3V
4
3.5
3
240
VDD=3V
220
200
180
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Output Frequency Vs Temperature
Under Voltage Lockout Vs Temperature
70
68
66
64
62
60
58
56
2.9
2.85
2.8
Turn On
VDD=5V
2.75
2.7
VDD=3V
2.65
2.6
Turn Off
2.55
2.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
I_R Voltage Vs Temperature VDD=V
Power-on-Reset Pulse Width Vs Temperature VDD=5V
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
40
35
30
25
20
15
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 5
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
TABLE 1
Pin BEPOL
VDD
ENABLE POLARITY
DIMMING POLARITY*
CONVENTIONAL
REVERSE
+ (HI = CHIP_ON, LOW = CHIP_OFF
+ (HI = CHIP_ON, LOW = CHIP_OFF)
- (LOW = CHIP_ON, HI = CHIP_OFF)
FLOAT
VSS
REVERSE
* Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin.
Reverse polarity means that brightness decreases with increasing voltage
OPERATIONAL MODES
Controller
Mode
Controller
Operation
Input Pin:
OLSNS
Input Pin:
SLAVE
Output Pin:
FAULT
Lamp
Frequency
Pin: RMP_RST
Output: FINT
Pin: A_SYNC
Output: FINT / 2
Output: FINT / 2
Run
> 0.6V
VSS
L
FINT / 2
Ramping up /
down
Master
Slave
Striking
< 0.2V
VSS
L
Output: FINT
Fault
Run
X
VSS
VDD
H
L
Output: FINT
Input: FEXT
Output: FINT / 2
Input: FEXT / 2
Off
> 0.6V
FEXT / 2
Ramping up /
down
Striking
Fault
< 0.2V
X
VDD
VDD
L
Input: FEXT
Input: FEXT
Input: FEXT / 2
Input: FEXT / 2
H
Off
SIMPLIFIED BLOCK DIAGRAM
VCOMP ICOMP
VSNS
ISNS
FEXT/2
VDD_P
VOLTAGE
COMPARATOR
ERROR AMP
TFF R
T
PWR_ GD
Q
A OUT
1.25V
VAMP
PHA_SYNC
SLAVE
Q
PWR_ BD
OUTPUT
PWR_ GD
FAULT
STEERING
LOGIC
RAMP RUN
FINT
PWR_BD
FAULT
GENERATOR
Q
B OUT
VSS_P
STRIKE
RMP_RST
FEXT
GENERATOR
300mV
CURRENT
COMPARATOR
IAMP
1V
1V
+
-
+
-
200K
BRT
2.5
V
800mV
600mV
BRITE
100K
100K
100K
100K
0-2V
+
IGNITE
6 BIT
-
OLSNS
0.5
V
CPW 1
CPW 2
BEPOL
TRI WAVE
GEN
TRI_C
COUNTER
PWR_ BD
1M
VDD
POLARITY
DECODE
BIAS GEN
UVLO
PWR_GD
PWR_BD
1M
TTL
BUF
FAULT
FAULT
TTL
BUF
ENABLE
VDDSW
INTERNAL VDD
VSS
LX1688
VSS
VDD
CPOR
I_R
Figure – Simplified Block Diagram
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 6
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
DETAILED DESCRIPTION
The LX1688 is a backlight controller specifically
designed with a special feature set needed in multiple lamp
desktop monitors, and other multiple lamp displays. While
utilizing the same architecture as Microsemi’s LX1686
controller it eliminates the synchronized digital dimming
and adds, lamp ‘strike’ count out timer, lamp fault status
output, and external clock input/output that permits multiple
controllers to synchronize their output current both in
frequency and phase.
and Slave Input/Output are used. RMP_RST and
PHA_SYNC should be connected between all the
controllers. The master controller should have its SLAVE
pin connected to VSS (GND) and the slave controllers
SLAVE input to VDD (High).
BEPOL INPUT
The BEPOL pin is a tri-mode input that controls the
polarity of the ENABLE and BRITE input signals.
Depending on the state of this pin (VDD, floating, or VSS)
the controller can be set to allow active high enable with
active high full brightness or active high or low enable
with active low full brightness (see Table 1).
OPERATION FROM 3.3V AND/OR 5.0V INPUT SUPPLY
The LX1688 is designed to operate and meet all
specifications at 3.3V ±10% to 5.0V ±10%. The under
voltage lockout is set at nominally 2.8V with a 190mV
hysteresis.
BRITE INPUT (DIMMING INPUT)
The BRITE input is capable of accepting either a DC
voltage (> .5V to < 2.5V) or a PWM digital signal that is
clamped on chip (< .5V or > 2.5V). A digital signal can
either be passed unfiltered to effect pulse ‘digital’ dimming
or filtered with a capacitor to effect analog dimming with a
digital PWM signal.
MASTER/SLAVE CLOCK SYNCHRONIZATION
One or more controllers (up to 11) may be designated as
slave controllers and receive ramp reset and phase
synchronization from the designated master controller.
This will allow up to 12 lamps (24 with two lamps in
series/controller design) to all operate in phase and
frequency synchronization. This is important to prevent
random interference between lamps through unpredictably
changing electric and magnetic fields that will inevitably
link them.
The LX1688 has two independent oscillators, one for
lamp strike and one for the lamp run frequency. The strike
oscillator ramps the operating frequency slowly up and
down when the open lamp sense input (OLSNS) indicates
the lamp is not ignited. During this lamp strike condition
the operating frequency of each IC will vary up and down
as needed to strike its lamp. The controller is so designed
that the master controller clock remains at the pre-selected
frequency for fully ignited lamps even while striking.
Likewise the designated slave controller will not alter the
frequency or phase of the master clock during its strike
phase. Thus each controller will vary its frequency as
needed to strike its lamp then it will synchronize to the
master clock frequency and phase.
Analog Dimming Methods:
• Mechanical or digital potentiometer set to provide 1V
to 2.5V on the wiper output. A filter cap from BRITE
to signal ground is recommended.
• D/A converter output directly connected to BRITE
input. A R/C filter using a capacitor from the CPW1
input to ground for applications where the ADC output
may contain noise sufficient to modulate the BRITE
input.
• A high frequency PWM digital logic pulse connected
directly to the BRITE input. The Brightness (BRT,
internal node) output will be sensitive only to the
PWM duty cycle, and not to the PWM signal
amplitude, so long as the amplitude exceeds 2.6V for a
logic high (1) and is less than .4V for a logic (0). This
pulse frequency will typically be between 1KHz and
100KHz and will not be synchronized with the LCD
video frame rate. A capacitor (CPWM) between
CPW1 and CPW2 will integrate the PWM signal for
use by the controller.
The TRI_C wave generator (see Block Diagram) sets the
rate of operating frequency variation during lamp strike.
The TRI_C generator is connected to a 6-bit counter that
times out after 63 cycles and then latches the FAULT
output high if the OLSNS input indicates no lamp current is
flowing. Even in the case of timeout fault the master
controller clock will continue to provide synchronization to
the slave controllers.
Digital Dimming Methods:
• Low frequency PWM digital logic pulses connected
directly to the BRITE input. As above the Brightness
(BRT internal) will be sensitive only to the PWM duty
cycle, and not to the PWM signal amplitude, so long
as the amplitude exceeds 2.6V for a logic high (1) and
is less than .4V for a logic (0). This pulse frequency
will typically be in the range of 90-320Hz.
When synchronizing more than one controller the Ramp
Reset (RMP_RST), Phase Sync (PHA_SYNC),
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 7
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
DETAILED DESCRIPTION
and may or may not be externally synchronized to the LCD
video frame rate. It will directly gate the signal BRT.
CPWM should not be used in this case.
RMP_RST AND PHA_SYNC PIN TIMING REQUIREMENT
WITH SLAVE MODE OPERATION
When the LX1688 is configured for slave mode
operation, and RMP_RST and PHA_SYNC is supplied
from an external source, the signal timing should be met as
outlined below.
FAULT PIN
The fault pin is a digital output that indicates that the
maximum numbers of strike attempts has occurred without
lamp ignition. In this condition the FAULT pin will go
active high with typically 20mA drive capability. Holding
the OLSNS pin low (<200mV) will also force timeout and
activate the FAULT pin. When used as a master, fault
condition true does not inhibit master clock outputs
PHA_SYNC and RMP_RST.
RMP_RST should be 2 times frequency of lamp
frequency and duty should be 10 to 13%, and PHA_SYNC
should be generated by divide by 2 of RMP_RST signal.
Phase of these signals should be met the as shown, note the
delay between the RMP_RST and PHA_SYNC signals:
I_R PIN
The run mode frequency of the output is one half the
internal ramp frequency, which is proportional to a bias
current set by resistor RI of 80.6K. The output frequency
can thus be adjusted by varying the value of RI-R, the
typical range from about 50K to 100K. Since there is some
variation in the frequency due to change in the input supply
(VDD) it is recommended that the value of RI-R be selected
at the nominal input voltage.
Min
150
10
Typ
Max
Unit
nsec
%
T1
T2
250
13
51
T3
49
50
%
Tr, Tf
100
nsec
T3 duty is 50% of operating frequency.
SLEEP MODE (ENABLE SIGNAL) AND SWITCHED VDD
(VDDSW)
Since the LX1688 can be used in portable battery
operated systems, a very low power sleep mode is included.
The IC will consume less than 10µA quiescent current from
both the VDD and VDD_P pins combined, when the
ENABLE pin is deactivated. The polarity of the ENABLE
pin is programmable by the BEPOL input (see table 1). In
addition the controller provides a switched supply pin
VDDSW this output supplies at least 10mA at VDD ─ .2V
for external circuitry. This output can be used to power
additional circuitry that can be enabled with the controller.
T2
T3
T1
BIAS & TIMING EQUATIONS
Formula 1:
Formula 2:
Triangular Wave Generator Frequency, FTRI
Lamp Frequency (AOUT’s switching frequency), FLAMP
1
1
FTRI
=
[Hz]
F
LAMP
=
[Hz]
(25× R
I
×CTRI
)
200e-12× R
I
Formula 3:
Formula 4:
Minimum Current Error Amp Bandwidth, BWIEA_MIN
Minimum Voltage Error Amp Bandwidth, BWVEA_MIN
0.000048
0.000048
B
WIEA_MIN
=
[Hz]
B
WVEA_MIN
=
[Hz]
C
ICOMP
C
VCOMP
Formula 5:
Softstart time, TSS
Formula 6:
Minimum Power-on Reset Pulse Width, TMIN_POR
MIN_POR = 2.3e6×CPOR [sec]
T
SS = 4,500,000 × CVCOMP [sec]
T
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 8
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
APPLICATION CIRCUITS
CN1
VIN
VIN
1
2
C1
10%
470nF 16V
GND
GND
3
4
5
6
U2
SI9945AEY
8
VBRITE
C13
0.1uF 50V
T1
CN2
1 HV1
2
LV1
RMP_RST
PHA_SYNC
1:75
3
7
RMP_RST
PHA_SYNC
R4 39
7
5
2
8
2
1
6
4
ENABLE
VDDSW
2.2PF
PCB
C14
VDDP
VDDP
9
Q2
5
BC847ALT1
Q1
10
R5 39
C12
4
BC847ALT1
+
220µ
25V
1
3
R8
C15
100K
2
1
2.2nF
50V 5%
COG
R6
82
D1
BAW56
R7
10K
3
1
24
C2
AOUT
VSS_P
VSS
BOUT
VDD_P
VDD
16V 10%
470nF
R2 47
2
3
23
22
VDD
Analog Ground must
connect to power
ground at this point
only
C4
220nF
C5
VDDSW
4
220nF
VDD
VDD
BEPOL
VDD_SW
TRI_C
16V
D2
3
16V 10%
C6
20
5
6
7
1
2
10%
82nF
BRITE
16V 10%
C7
19
18
R9
1K
16V 10%
10nF 16V
10%
C3
BAW56
CPOR
OLSNS
ISNS
C16
100nF
C8
2.2nF
16V 5%
R12
2.74K
1%
3.3nF
ENABLE
3
COG
50V 5%
D3
BAV99
C9
4.7nF
R10
1M
R1
8
9
17
16
ICOMP
VCOMP
VSNS
I_R
2
1
C10 16V 10%
10nF
16V 10%
80.6K 1%
CPWM1
R11
2.74K
1%
C11
10nF
10
11
12
15
14
13
CPWM2
16V 10%
RMP_RST
RMP_RST SLAVE
PHA_SYNC FAULT
PHA_SYNC
R3
220
LED1
OPTION
Figure 1 – Schematic for LX1688 Inverter Module Configured as Master
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 9
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
APPLICATION INFORMATION
SETTING MASTER/SLAVE CONFIGURATION
APPLICATION EXAMPLE WITH LX1688
This section will highlight the features of LX1688
controller by showing a practical example. Three identical
inverter modules are connected to each other and each
module drives a single lamp. One module configured as a
master and two others configured as slaves.
Simply connecting pin 14 to the ground for a master
and to the VDD for a slave will do master and slave
configuration. As shown in figure 2, module (A)
configured as master and modules (B) and (C) configured
as slaves.
A complete schematic hooked up a a master is given in
Figure 1, the schematic provides all necessary functions
such as high voltage feedback for regulation the peak lamp
voltage, short-circuit protection, open lamp sensing and
lamp current regulation needed for a typical application.
The section follows with measurement waveforms and list
of material of the actual modules. For more detail design
procedure and circuit description please refer to application
note (AN-13), which is available in Microsemi’s web site.
INPUT VOLTAGE
The LX1688 controller can operate at 3.3 to 5.0V
±10%, in this application all modules were driven by the
same power voltage (a constant 5.0V), which provides
VDD for controllers, and input voltage for the power
section. Notice that VDD feeds all analog signals and
VDD_P feeds only the output driver stage, these two
signals should be filtered separately (Figure 1).
SETTING LAMP FREQUENCY
SYNCHRONIZATION OF FREQUENCY AND PHASE
To synchronize the Lamp frequency and phase of all
modules, it is required to connect the RMP_RST pin of all
the modules together and connect PHA_SYNC pin of all
the modules together.
LAYOUT CONSIDERATION
By designing the layout in a proper way we can reduce
the overall noise and EMI for the module.
The gate drivers for MOSFETs should have an
independent loop that doesn’t interface with the more
sensitive analog control function, therefore LX1688
provides two power inputs with separate ground pins
(analog/signal), VDD feeds all analog signals and VDD_P
feeds only the output drivers, as shown in figure1 these
two pins (pin 23, 24) are separated and filtered by R14, C2
and C7. The connection of two ground pins should be at
only one point as shown in figure1.
The power traces should be short and wide as possible
and all periphery components such capacitors should be
located as closed as possible to the controller.
The value of R1 determines magnitude of internal
current sources that set timing parameters. Equation (2)
gives the relationship between Lamp frequency (FLAMP)
and (RI_R), R1 in schematic. For this application we
choose R6=80.6 KΩ, which results to a lamp frequency at
62.0 KHz.
OSCILLOSCOPE WAVEFORMS PICTURES
The following oscilloscope waveform pictures are
taken from the actual circuits and will show the operation
of the modules in different modes when three identical
modules are synchronized, one as a master, and two others
as slaves.
DIMMING
The LX1688 includes highly integrated universal ‘PWM
or DC’ dim input that allows either a PWM or DC input
without requiring external conditioning.
In this application we choose Digital Dimming by
applying a PWM signal to BRITE pin.
All modules were driven by the same PWM signals, but
notice that it is possible to dim each module quite
separately.
BEPOL pin has three different modes (see table 1), in
this application it is connected to VDD which means active
high enable with active high full brightness.
The PWM signal can be varied in frequency between
48-320 HZ. No capacitor between CPWM1 and CPWM2 is
necessary.
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 10
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
TYPICAL SLAVE APPLICATIONS
VDDP
CN
1
C1
470nF 16V
10%
VIN
1
VIN
2
3
GND
GND
C2
470nF 16V
10%
4
5
1
2
3
24
23
22
AOUT
VSS_P
VSS
BOUT
VDD_P
VDD
VBRITE
6
7
8
RMP_RST
VDD
R2
47
PHA_SYNC
ENABLE
VDDSW
9
C4
1
0
VDDSW
VDD
4
5
6
7
21
220nF
16v 10%
C5
BEPOL VDD_SW
VBRITE
20
19
C6
BRITE
CPOR
TRI_C
C7
C8
Power
Output
Section
OLSNS
C3 10nF
16V 10%
18
17
ENABLE
I_R
ISNS
ICOMP
VCOMP
VSNS
8
9
C9
R1
80.6K 1%
16
15
C10
CPWM1
CPWM2
10
C11
11
12
14
13
RMP_RST
PHA-SYNC
RMP_RST SLAVE
PHA_SYNC
FAULT
R3
220
LED1
C5 : 220nF 16V 10%
C6 : 82nF 16V 10%
C7 : 100nF 16V 10%
C8 : 2.2nF 50V 5%
C9 : 4.7nF 16V 10%
C10-11 : 10nF 16V 10%
Master
VDDP
C1a
470nF 16V
10%
CN1
VDDP
C1b
470nF 16V
10%
CN1
VIN
1
2
3
VIN
VIN
1
2
3
VIN
GND
GND
GND
GND
C2a
470nF 16V
10%
4
5
1
24
23
22
C2b
470nF 16V
10%
4
5
6
7
8
1
24
23
22
AOUT
VSS_P
VSS
BOUT
AOUT
VSS_P
BOUT
VDD_P
VDD
VBRITE
6
7
8
VBRITE
2
3
RMP_RST
2
3
VDD
R2a
47
VDD_P
VDD
RMP_RST
VDD
R2b
47
PHA_SYNC
PHA_SYNC
ENABLE
VDDSW
9
ENABLE
VDDSW
VSS
9
C4a
220nF
16v 10%
VDDSW
C4b
220nF
16v 10%
VDD
10
4
5
6
7
21
VDDSW
21
VDD
10
C5a
4
5
6
7
C5b
BEPOL
VDD_SW
BEPOL
VDD_SW
VBRITE
VBRITE
20
19
C6a
20
19
C6b
BRITE
CPOR
TRI_C
BRITE
CPOR
TRI_C
C7a
C8a
Power
Output
Section
C7b
C8b
OLSNS
Power
Output
Section
OLSNS
C3a 10nF
16V 10%
C3b 10nF
16V 10%
18
17
18
17
ENABLE
I_R
ISNS
ICOMP
VCOMP
VSNS
ENABLE
I_R
ISNS
ICOMP
VCOMP
VSNS
8
9
8
9
C9a
C9b
R1a
80.6K 1%
R1b
80.6K 1%
16
15
C10a
16
15
C10b
CPWM1
CPWM2
CPWM1
CPWM2
10
10
C11a
C11b
11
12
14
13
11
12
14
13
RMP_RST
PHA-SYNC
RMP_RST SLAVE
PHA_SYNC FAULT
RMP_RST
RMP_RST SLAVE
PHA_SYNC FAULT
PHA-SYNC
R3a
220
VDDSW
R3b
220
VDDSW
R13a
100K
R13b
100K
Slave 1
Slave 2
LED1a
LED1b
C5a: 220nF 16V 10%
C6a: 82nF 16V 10%
C7a: 100nF 16V 10%
C8a: 2.2nF 50V 5%
C9a: 4.7nF 16V 10%
C10-11a: 10nF 16V 10%
C5b: 220nF 16V 10%
C6b: 82nF 16V 10%
C7b: 100nF 16V 10%
C8b: 2.2nF 50V 5%
C9b: 4.7nF 16V 10%
C10-11b: 10nF 16V 10%
Figure 2 – Schematic Modules Connected as a Master and Slave
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 11
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION
Multiple Lamp Sync
Strike Mode
The figure 3 shows the sync signals (PHA_SYNC
and RMP_RST) timing relationship to Gate signal
AOUT, for the master module. AOUT and
PHA_SYNC running at the same frequency and
RMP_RST signal has the twice frequency.
Every IC includes a separate strike controller that
operates from the primary oscillator; therefore the strike
controller is independent of the sync signals. The
following oscilloscope waveform picture is taken when
the master module is on striking mode and the salves are
on running mode.
Figure 3- Sync signals-Timing relationship to AOUT
CH2= AOUT(Master), CH3=PHA_SYNC,
CH4=RMP_RST
Figure 5- Master is in striking mode while slaves
are in running mode CH2=
AOUT(Master), CH3=AOUT(Slave1),
CH4=AOUT(Slave2)
Output Drivers
The figure 4 shows the gate signals of the modules, which are operating, in running mode during digital dimming with 95%
duty cycle. As shown all signals are synchronized. The difference between each signal’s duty cycles is because each lamp has
an independent control loop.
Figure 4- Output drivers of both Master
and Slaves.
CH2=AOUT(Master),
CH3=AOUT(Slave1),
CH4=AOUT(Slave2)
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 12
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
THEORY OF OPERATION
Digital Dimming
The following oscilloscope waveforms are showing
gate signals of Master and slaves during digital dimming at
50% and 5% duty cycle.
Figure 7- Gate signals during digital dimming with
Figure 6- Gate signals during digital dimming with
50% duty cycle CH2= AOUT(Master),
5% duty cycle CH2= AOUT(Master),
CH3=AOUT(Slave1), CH4=AOUT(Slave2)
CH3=AOUT(Slave1), CH4=AOUT(Slave2)
Output currents
Figure 8 shows the output current of master and slaves during digital dimming with 5% duty cycle. The lamp currents are
operating in phase and frequency synchronization. This prevents random interface between controllers and reduces EMI.
Figure 8- Output current during
digital dimming with 5%
duty cycle R1= out(Master)
R2=Iout(Slave1)
R3=Iout(Slave2)
Lamp Current at 10mA/Div
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 13
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
LX1688 MODULE BOARD LIST OF MATERIAL
Reference
Designator
U1
Part Description
Manufacture
Part Number
Backlight Controller
Dual N-Channel MOSFET
NPN Transistor
Dual Diode
Microsemi
Siliconix
Motorola
Motorola
Philips
LX1688
Si9945AEY
BC847ALT1
BAW56
U2
Q1, Q2
D1, D2
D3
Dual Diode
BAV99
LED1
R1
R2
LED
80.6K 1% 1/16 W
47 ohm 5% 1/8 W
220 ohm 5% 1/8 W
R3
R4, R5
R6
39 ohm 5% 1/16 W
82 ohm 5% 1/16 W
10K 5% 1/16 W
100K 5% 1/16 W
1K 5% 1/16 W
R7
R8
R9
R10
1 M 5% 1/16 W
2.74K 1% 1/16 W
R11, R12
C1, C2
C3
C4
C5
C6
C7
C8
C9
C10, C11
C12
C13
C14
C15
C16
T1
470nF 16V 10% X7R 1206
10nF 16V 10% 0805
220nF 16V 10% X7R 1206
220nF 16V 20% 0805
82nF 16V 10% X7R 0603
100nF 16V 20% X7R
2.2nF 50V 10%
NOVACAP
AVX
AVX
AVX
0805YC224MAT2A
0603YC823KAT2A
0603YC104MAT2A
0603B22K500NT
0603YC472KAT2A
0603YC103KAT2A
NOVACAP
AVX
AVX
AVX
NOVACAP
4.7nF 16V 10% X7R
10nF 16V 10% X7R
220µF Tantalum 7343
220pF 2KV 5% COG
2.2pF PCB
1206N221J202NT
2.2nF 50V 5% COG
3.3nF 50V 5% COG
Low profile, High voltage xfmr,
turns ratio 1:75
AVX
NOVACAP
Microsemi
08055A222JAT2A
0805N332J500NT
SGE2645-1
CN1
CN2
Connector, 10 pin
Connector, 2 pin
Molex
Molex
53261-1090
Table 2- List of material for LX1688 inverter module
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Page 14
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
PACKAGE DIMENSIONS
24-Pin Thin Small Shrink Outline (TSSOP) Package
PW
3 2 1
P
E
F
D
A
H
L
SEATING PLANE
B
C
G
M
MILLIMETERS
INCHES
Dim
MIN
0.85
0.19
0.09
7.70
4.30
MAX
0.95
0.30
0.20
7.90
4.50
MIN
0.033
0.007
MAX
0.037
0.012
A
B
C
D
E
0.0035 0.008
0.303
0.169
0.311
0.177
F
0.65 BSC
0.025 BSC
G
H
L
M
P
*LC
0.05
–
0.50
0°
6.25
–
0.15
1.10
0.75
8°
6.55
0.10
0.002
–
0.020
0°
0.246
–
0.005
.0433
0.030
8°
0.258
0.004
* Lead Coplanarity
Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall
not include solder coverage.
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 15
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
RangeMAX™
LX1688
®
Multiple Lamp CCFL Controller
TM
PRODUCTION DATA SHEET
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright © 2001
Rev. 1.2, 2006-03-09
Microsemi
Integrated Products Division
Page 16
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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