LX1689 [MICROSEMI]
Third Generation CCFL Controller; 第三代CCFL控制器
| 型号： | LX1689 |
| 厂家： | 
Microsemi |
| 描述： | Third Generation CCFL Controller |
| 文件： | 总15页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
KEY FEATURES
DESCRIPTION
The LX1689 is the latest generation
The brightness control input allows the
3 to 28 Volt Single Fixed (±20%)
Supply Operating Range
Selectable Analog/Digital
Dimming Modes
Direct Drive CCFL (Cold Cathode use of either a DC voltage or a PWM
Fluorescent Lamp) Controller. It uses input to simplify design. Programmable
new circuit design techniques (patents polarity brightness control is retained,
pending) and combines digital and linear except in the case of externally clocked
circuits with an advanced BiCMOS digital dimming. Two onboard LDO
process to create a more complete regulators extend the input voltage range
controller in a small package.
When compared to the original external circuitry as was required with our
LX1686 design, identical module previous controllers. The LX1689
Digital Dimming Can Synch to
External Or Internal Clocks
User Programmable Digital
Dimming Burst Frequency
252 mS Power On Delay
Flexible Lamp Current
of the IC up to 28 Volts without using
Compensation Input
Open Lamp Shutdown and Fault
Output Indicator
applications use from 12 to 30 less includes a new lamp strike detection
components. New functions and scheme that saves a package pin and three
enhancements have been added to make external components. Internal circuits
“On Chip” Full Wave Lamp
Current & Voltage Rectifiers
20 Pin TSSOP Package
the LX1689 even easier to use.
monitor lamp current pulses at the I_SNS
The on-chip PLL circuit used to input to determine if the lamp strikes and
synchronize the digital dimming burst if it stays ignited once operational.
BENEFITS
frequency to the video frame rate, as
Integrating full wave rectifiers for
Low Component Count /
Module Cost / Size
used in the LX1686, is replaced with a each of three lamp inputs has significantly
programmable counter. This counter can reduced the lamp feedback component
divide the video controller horizontal count. In addition the controller features
sync pulse, other external clock source include auto shutdown for open or broken
or the internal chip clock source to lamps, and a lamp fault detection with a
High “Nits/Watt” Efficiency
Operates Directly From 1 to 6
Li_Ion Cells
Lamp Current Compensation
Input Makes Indoor/Outdoor
And Wide Temperature Range
Applications Easy to Design
generate the burst frequency.
status reporting output.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PRODUCT HIGHLIGHT
LX1689 CCFL Inverter Layouts Examples*
2.64in. (67mm)
Bill of Materials
.397 in.
1
1
LX1689CPW
Transformer
Dual FET
Actual Inverter Size
OR
1
1.38in. (35mm)
2
7
Connectors
Resistors
.870 in.
(22mm)
9
21
Capacitors
Total Count
Actual Inverter Size
*As Shown in Figure 1 (Typical Application)
PACKAGE ORDER INFO
Plastic TSSOP
20-PIN
MIN VDD
MAX VDD
TJ (°C)
PW
0 to 70
3V
3V
28V
28V
LX1689CPW
LX1689IPW
-40 to 85
Note: Available in Tape & Reel.
Append the letter “T” to the part number. (i.e. LX1689CPWT)
Copyright 2000
Microsemi
Page 1
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
ABSOLUTE MAXIMUM RATINGS
PACKAGE PIN OUT
Supply Voltage (V_BATT)................................................................................................. 30V
Digital Input (ENABLE).....................................................................................-0.3V to 7V
Analog Inputs Transient Peak (I_SNS, OC_SNS, OV_SNS)..............................-25V to +25V
Analog Inputs (BRITE_IN, EA_IN)..................................................................-0.3V to 5.5V
Digital Inputs (DIM_CLK,DIM_MODE, DIV_248) .........................................-0.3V to 5.5V
Digital Output (AOUT, BOUT).................................................................-0.3V to VDD_P +0.5V
Analog Outputs (BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT)...-0.3V to VDD_A_ +0.5V
Operating Temperature Range ..................................................................... -45°C – 100°C
Maximum Junction Temperature ...............................................................................125°C
1
2
3
4
5
6
20
19
18
17
16
15
14
13
GND
AOUT
BOUT
VDD_P
VDD_A
V_BATT
OC_SNS
OV_SNS
DIM_CLK
DIM_MODE
DIV_248
I_SNS
BRITE_C
BRITE_R
BRITE_IN
7
8
BRITE_OUT
EA_OUT
EA_IN
9
12
11
10
ENABLE
I_R
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
PW PACKAGE
(Top View)
THERMAL DATA
Plastic TSSOP 20-Pin
PW
144°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
Junction Temperature Calculation: T = T + (P x θ ).
JA
J
A
D
The θJA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
PIN NAME
DESCRIPTION
GND
Ground
Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_P LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 5.3V
and is used only to drive the output buffers at AOUT and BOUT. The external capacitor will be a 100 to 1000nF
ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be
reduced if the combination of output current and input voltage exceeds power dissipation capability of the die.
VDD_P
AOUT
A buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_A LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally
2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is
6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the
combination of output current and input voltage exceeds power dissipation capability of the die. The external
capacitor will be a 100 to 1000nF ceramic dielectric type.
VDD_A
BOUT
B buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
Voltage Input, 3 to 28V input range. V_BATT is switched (see ENABLE) to remove power from chip. Two LDO
regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care
must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to
the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type.
V_BATT
Copyright 2000
Microsemi
Integrated Products
Page 2
Rev. 1.0b, 2003-03-31
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
FUNCTIONAL PIN DESCRIPTION (CONTINUED)
PIN NAME
DESCRIPTION
Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for
external Digital Dimming. This input can be any clock signal up to 200KHz. This pin is also used to control the
dimming polarity when operating in the analog or internal digital mode. If DIM_MODE is in the open condition
(Analog Dimming Mode) the DIM_CLK input should be connected to VDD_A for conventional dimming polarity
or set to Ground for reverse polarity. Conventional polarity means that lamp brightness increases with
increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing
voltage.
DIM_CLK
Over Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high
voltage transformer secondary winding current. The OC_SNS input is full wave rectified, then applied to a digital
comparator with a 2V reference to cause peak voltages greater than 2V to digitally reset the PWM logic on a
pulse by pulse basis.
OC_SNS
Frequency range of the input signal is 10kHz to 500KHz. Normal operating voltage levels should be under
max ±1.8VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault
conditions. Transients under fault conditions can reach ± 25VPK.
Dimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming
Mode, or external Digital Dimming Mode. If the input is left open or forced to VDD_A / 2 Analog mode is
selected.
DIM_MODE
If connected to VDD_A, Digital Dimming with a external clock source applied to the DIM_CLK input is
selected to the burst timing generator. If connected to Ground, Digital Dimming with a internal clock is selected.
The internal clock is equivalent to the frequency at AOUT divided by two, both the internal or external clock
frequency can be divided down by setting the DIV_248 pin. (see DIV_248)
Over Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp
voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to
cause peak voltage greaten than 2V to digitally reset the PWM logic on a pulse by pulse basis.
Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage levels should be under
±1.8VPK, and abnormal voltage can operate continuously as high as ±10V peak under load fault conditions.
Transients under fault conditions can reach ± 25VPK.
OV_SNS
DIV_248
The input has a 10K pull down resistor that serves as a DC restorer to the external capacitor that divides
down lamp voltage.
Divide Digital Dimming clock by 2, 4, or 8. This three state input pin causes the internal or external digital
dimming clock source to be divided by one of the three values, 2, 4, or 8. Its purpose is to allow a selection of
three possible burst rates for any given external or internal clock source. A high (VDD_A) selects divide by 2,
open selects divide by 4, and ground selects divided by 8. We advise keeping burst above 95Hz and below
about 400HZ. This will minimize visible flicker and possible audible noise from the power supply components.
Current Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current.
The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error
amplifier through a 100K resistor.
Frequency range of the input signal is 10KHz to 500KHz. Normal operating voltage levels will be in the range
of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault
conditions. Transient under fault conditions can reach ± 25VPK. We strongly recommend a 10K resistor be
placed in series with the pin to limit current from voltage spikes that can occur by intermittent lamp connectors,
or arcing from a faulty high voltage transformer. This resistor will eliminate the possibility of IC damage under
these fault conditions.
I_SNS
The open lamp fault logic monitors the I_SNS pin voltage and number of lamp current cycles. If the number
of lamp current cycles with amplitude below fault threshold are less than 8 in a given fault checking period then
the strike latch will not be reset and a fault is declared, which shuts down the A/B outputs. In the strike mode, if
no lamp current is detected after 15 attempts a fault is likewise declared. ( See further LX1689 operation
section)
Copyright 2000
Microsemi
Integrated Products
Page 3
Rev. 1.0b, 2003-03-31
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
FUNCTIONAL PIN DESCRIPTION (CONTINUED)
PIN NAME
DESCRIPTION
BRITE Filter Capacitor and FAULT Output. Used to convert higher frequency digital PWM inputs to proportional
DC currents at the BRITE_OUT pin. The capacitor forms a low pass filter with an internal 200K resistor. This
pin will be driven to VDD_A if a lamp fault is detected by the LX1689. If no fault is present the voltage at this pin
will vary from 50mV to 1.05V as BRITE_IN varies from 0 to 2V. A CMOS gate may be connected to this pin to
sense the fault condition. TTL gates or other low impedance (less than 20 megohm) must not be connected to
this node as their DC resistance will load the internal 200K resistor and create error in the BRITE_OUT current
level.
BRITE_C
Error Amp Inverting Input. Frequency Compensation input for the Error Amplifier. See EA_OUT below. A
100K, negative TC on chip resistor connected between the inverting input of the error amplifier and the output of
the I_SNS full wave rectifier is the resistor in an R/C loop compensation network.
EA_IN
BRITE_R
Dedicated Bias resistor for BRITE_OUT current source.
Error Amp Output. Error amplifier is a GM type and does not require a external capacitor for stability. An
external capacitor is connected from this pin to EA_IN to adjust the loop response of the inverter module. This
capacitor value can vary from 100pF to 5000pF in various applications. This capacitor may also be connected
from the EA_OUT to ground.
EA_OUT
Brightness Control Input. The input signal can be a DC voltage, a low frequency pulse width modulated digital
signal, or a high frequency pulse width modulated digital signal. Active DC voltage range is 0.5 to 2.0V. Signals
above 2V are clipped and signals below 0.5V make output current from the BRITE_OUT pin near zero. Low
frequency digital PWM signals up to 500Hz can be applied to affect Digital Dimming. Higher frequency PWM
signals, up to 100KHz are filtered to an equivalent DC current at the BRITE_OUT pin by adding a capacitor at
the BRITE_C pin. On chip signal conditioning amplifiers clip inputs above 2V so that lamp current amplitude is
not sensitive to the voltage level variations of a digital PWM input signal.
BRITE_IN
Brightness Reference Current Output. This variable current source is the mirror of BRITE_R current multiplied
by the voltage at BRITE_C (0 to 1.0V) when analog dimming is selected, or by 1.0V when digital dimming is
selected. It becomes the reference voltage to the lamp current error amplifier when applied to an external
precision resistor connected from the BRITE_OUT pin to ground. BRITE_OUT current:
IBRITE_OUT = IBRITE_R ×1.0 (DigitalDimmingMode)
IBRITE_OUT = IBRITE_R × VBRITE_C (AnalogDimming Mode)
VBRITE_OUT = IBRITE_R × RBRITE_OUT
1.00V
BRITE_OUT
IBRITE_R
=
RBRITE_R
Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the
V_BATT pin, disabling all functions. Logic threshold is about 1.2V. Maximum current into V_BATT when
ENABLE < 0.3V, V_BATT <28V, is 28 µA. ENABLE may be connected to V_BATT through a series resistor if
the disable function is not used. Resistor tolerance is ± 10%; and R value is:
ENABLE
I_R
[V_BATTMIN − 1.5V]
R =
30x10−6 Amp
The Enable pin can be connected directly to 3.3/5V logic.
Current Reference Resistor Input. Connects to an external resistor that determines the magnitude of internal
bias currents. The nominal lamp frequency can be adjusted by varying this resistor value in the range of 10K to
150K Ohms.
1.00V
II_R
=
RI_R
Copyright 2000
Microsemi
Page 4
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
RECOMMENDED OPERATING CONDITIONS
LX1689
Typ
Parameter
Units
Min
Max
Supply Voltage (V_BATT
Digital Input (ENABLE)
Analog Inputs (I_SNS, OC_SNS, OV_SNS)
BRITE_IN Linear DC Voltage Range
BRITE_IN PWM Logic Signal Voltage Range
Digital Inputs (DIM_MODE, DIV_248,DIM_CLK)
)
3
0
-3
0.5
0
28
6.5
3
2
5
V
V
VPK
V
V
V
0
5.5
20
Maximum Output Gate Charge (AOUT, BOUT
)
10
nC
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature: LX1689CPW: 0°C ≤ TA ≤ 70°C,
LX1689IPW: -40°C ≤ TA ≤ 85°C, except where otherwise noted.
Test conditions: V_BATT =3.3 to 28 VDC, I_R =80.6KΩ, BRITE_R = BRITE_OUT = 10KΩ, BRITE_C =open, ICOMP =100pf
LX1689
Typ
Parameter
Symbol
Test Conditions
Units
Min
5.05
2.75
Max
5.55
3.15
POWER
`
Regulator Output Voltage
VDD_P Drop Out Voltage
Regulator Output Voltage
VDD_A Dropout Voltage
VBATT Static Current
VBATT Dynamic Current
Sleep Mode Current
Sleep Mode Current
ENABLE INPUT
VDD_P
∆VDD_P
VDD_A
∆VDD_A
IBATT
V_BATT = 6 to 28 V, I Load = 0 – 5mADC
∆VDD_P = -1% , I Load = 5mADC; TA = 25°C
V_BATT = 3.5 to 28V, I Load = 0 – 5mADC
∆VDD_A = -1% , I Load = 5mADC; TA = 25°C
5.3
50
2.95
100
5.5
10
V
mV
V
mV
mA
mA
µA
µA
9
17
5
IBATT
CAOUT = CBOUT = 1000pF
IBATT_SLEEP VENABLE ≤ 0.4V; VBATT = 5V
IBATT_SLEEP VENABLE ≤ 0.4V; VBATT = 28V
2.8
22
35
`
`
Run Threshold
Shutdown Threshold
Input High Current
Input High Current
Input Low Current
VTH_ENRUN
VTL_ENSHDN
IIH_ENABLE
IIH_ENABLE
IIL_ENABLE
1.1
1.1
2
35
0
1.4
V
V
µA
µA
µA
0.4
-1
ENABLE = 2V
ENABLE = 5V
ENABLE = 0V
12
80
1
UNDER VOLTAGE LOCKOUT
Startup Threshold
UVLO Threshold
UVLO Hysteresis
Run Mode
Shutdown Mode
2.55
2.35
200
2.8
V
V
mV
VT_UVLO
VH_UVLO
2.1
Copyright 2000
Microsemi
Page 5
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1689
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
RAMP GENERATOR
`
Max Strike / Run Frequency Ratio
Maximum Lamp Run Frequency
Lamp Run Frequency
FRAMP_STK Ratio to run frequency, I_SNS = OV_SNS = 0V
FRAMP_RUNMAX Lamp is ignited; I_R=10K
4
250
63
5
450
65
6
KHz
KHz
KHz
FLAMP_RUN
67
69
Lamp is ignited ;TA = 25°C
Lamp Run Frequency
FLAMP_RUN Lamp is ignited
61
65
Lamp Run Frequency Regulation over
FLAMP_REG 3.3 < VBATT < 28V
0.1
%
V_BATT
DIV_248 = VDD_A, DIM_MODE = 0V
DIV_248 = Floating, DIM_MODE = 0V
DIV_248 = Gnd, DIM_MODE = 0V
254
127
63.5
Hz
Hz
Hz
Internal Digital Dimming
Burst Frequency
FBURST
BIAS BLOCK
`
`
Voltage at Pin I_R
V_IR
VBATT = 2.8V to 28V, IOUT = 0 to 100uA, TA = 25°C
I_R = 0V
0.95
100
1.0
1.05
2.01
V
Pin I_R Max Source Current
IMAX_IR
700
µA
Voltage Reference Voltage
V2P0
TA = 25°C, reference use only
1.99
2
V
(Internal node)
PWM BLOCK
Error Amp Transconductance
Error Amp Output Source Current
Error Amp Output Sink Current
Error Amp Output High Voltage
Error Amp Output Low Voltage
Error Amp Input Offset Voltage
Max Duty Cycle
GM_EAMP
IS_EAMP
ISK_EAMP
VH_EAMP
VL_EAMP
VOS_EAMP
DCMAX
RVV
90
5
5
180
12
12
2.9
0.015
µmho
µA
µA
V
V
mV
%
BRITE_OUT – EA_IN = 50mV
EA_IN – BRITE_OUT = 50mV
2.5
0.5
70
44
200
1.95
Ramp Valley Voltage
Ramp Peak Voltage
mV
V
RPV
OUTPUT BUFFER BLOCK
`
`
Output Sink Current
Output Source Current
Output Rise Time
Output Fall Time
DIM_CLK INPUT
ISK_OUTBUF VAOUT, VBOUT = VDD_P
100
100
25
mA
mA
nS
IS_OUTBUF
TR
VAOUT, VBOUT = 0V
COUT = 1000pF
COUT = 1000pF
200
200
TF
25
nS
Pull-up Resistance
To VDDA
50
0.9
0.9
45
KΩ
V
V
µA
µA
Input High Threshold
Input Low Threshold
Input High Current
VTH_DIM_CLK Conventional Dimming
VTL_DIM_CLK Reverse Dimming
IIH_DIM_CLK DIM_CLK = 5V
1.4
0.4
70
-100
Input Low Current
IIL_DIM_CLK DIM_CLK = 0V
-65
TRI-STATE LOGIC INPUTS (DIM_MODE,DIV_248)
`
Low State
VTL_TRI_
VTF_TRI
VTH_TRI
IIH_TRI
0.4
1.2
0.6
1.35
2.1
70
V
V
Floating State
High State
1.8
2.8
120
-50
V
Input High Current
Input Low Current
DIM_MODE = DIV_248 = 5V
DIM_MODE = DIV_248 = 0V
µA
µA
IIL_TRI
-25
Copyright 2000
Microsemi
Page 6
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1689
Typ
Parameter
Symbol
Test Conditions
Units
Min
Max
ANALOG DIMMER BLOCK
`
BRITE_IN Input Current
BRITE_IN II BRITE_IN = 0 to 5V
BRITE_IN < 0.45V
-1
1
µA
mV
V
20
52
100
1.12
1.14
1.14
1.16
120
Conventional Dimming
BRITE_OUT
BRITE_IN > 2.05V; TA = 25°C
0.96
0.94
0.98
0.96
10
1.04
1.04
1.06
1.06
62
BRITE_IN > 2.05V
V
BRITE_IN < 0.45V; TA = 25°C
BRITE_ IN < 0.45V
V
Reverse Dimming
BRITE_OUT
V
BRITE_IN > 2.05V
mV
DIGITAL DIMMER BLOCK
`
Minimum Duty Cycle; BRITE_IN ≤ 0.55V
Maximum Duty Cycle; BRITE_IN =1.90V
Maximum Duty Cycle; BRITE_IN ≥ 1.95V
Maximum Duty Cycle; BRITE_IN ≤ 0.55V
Maximum Duty Cycle; BRITE_IN = 0.6V
Minimum Duty Cycle; BRITE_IN ≥ 1.95V
2
85
100
100
85
2
10
92
15
100
%
%
%
%
%
%
Conventional Dimming
Duty Cycle
Reverse Dimming
Duty Cycle
92
10
100
15
TIMING GENERATOR BLOCK
`
Number of Lamp Return Current
Cycles before Run Mode
NIGNITE
To switch to Run Mode
8
Cycles
I_SNS Run Mode Checking Interval
Fault Comparator Threshold Voltage
Lamp return current cycles, 8192 x 1 /fO
I_ SNS Open Lamp Fault Detect, TA =25°C
126
305
mS
mVPK
250
350
Number of Strike sweep Attempts
Before Fault Shutdown
Power On Delay Before Strike
NSTRK_FAULT FLAMP Sweep Cycles, I_SNS = 0V_SNS = 0V
15
TD_PWRON
16384 X Lamp Run Period
252
ms
Number of Sweeping Strike Frequency
1024
Steps
Steps per Attempt
Number of Output Pulses per Striking
Step
16
Cycles
LAMP FEEDBACK CONDITIONING BLOCK
`
I_SNS =10V
I_SNS = -10V
80
-200
± 2
± 2
260
-320
± 2
± 2
45
-110
0.31
2
0.3
1.9
150
-350
± 2.2
µA
µA
VPK
VPK
µA
µA
VPK
VPK
µA
µA
V
I_SNS Input Current
I_SNSIIN
OV_SNS Input High Threshold
OV_SNS Input Low Threshold
VTH_OV_SNS Active Over Voltage Protection
VTL_OV_SNS Inactive Over Voltage Protection
OV_SNS = 10V
OV_SNS = -10V
VTH_OC_SNS Active Over Current Protection
VTL_OC_SNS Inactive Over Voltage Protection
± 1.8
± 1.8
400
-450
± 2.2
OV_SNS Input Current
OV_SNSIIN
OC_SNS Input High Threshold
OC_SNS Input Low Threshold
OC_SNS = 10V
OC_SNS = -10V
I_SNS = 0.3VDC, TA = 25°C
I_SNS = 2.0VDC, TA = 25°C
I_SNS = -0.3VDC, TA = 25°C
I_SNS = -2.0VDC, TA = 25°C
80
OC_SNS Input Current
OC_SNSIIN
-180
0.35
2.05
0.36
2.05
0.27
1.95
0.24
1.75
V
V
V
Full Wave Rectifiers RMS Transfer
I_SNSRMS
Copyright 2000
Microsemi
Page 7
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
BLOCK DIAGRAM
V_BATT
PWM CONTROL
BLOCK
ENABLE & BIAS
GENERATOR
BLOCK
OUTPUT DRIVERS BLOCK
AOUT
RAMP_D
FAULT
ENABLE
SLEEP
SHUTDOW N
OUTPUT
STEERING
LOGIC
VDD_A
VDD_P
BOUT
EA_OUT
EA_IN
5.3V
DUAL LDO
UVLO BIAS
2.95V
RAMP_C
+
-
2.0V
REF
BRITE_OUT
+
-
PWR_GD
ERROR
AMP
DIM CLOCK
IGNITE
I_R
DIGITAL DIM
+
-
0.5V
50K
DDIM
LAMP FEEDBACK
CONDITIONING BLOCK
F EXT
BRITE_IN
2.0V
+
I_SNS
-
75K
-
+
50K
LSNS
0.5V
RECTIFIER
VDD_A
2.0V
OC_SNS
-
+
FAULT
VDD_A
-
+
BRITE_C
OC_SNS
RECTIFIER
0.5V
200K
ANADIM
OV_SNS
GND
-
+
BRITE_OUT
BRITE_R
OV_SNS
RECTIFIER
1V
I1
-
RESET
+
-
+
200K
-
+
300mV
I1
6BIT
VDAC
RUN MODE
FAULT DET
DIM_CLK
STRIKE
DETECTION
BLOCK
6 BIT
COUNTER
MUX
&
DIV
STRIKE MODE
FAULT DET
FAULT
DIM_ MODE
DIV_248
IGNITE
EXT
3 STATE
ANLG
N
DECODER
INT
20 BIT
R
10 BIT
REGISTER
10 BIT
IDAC
COUNTER &
POW ER ON
D
Q
Q
S
RS
Q
3 STATE
DECODER
R
RESET LOGIC
DIGITAL DIM
ANALOG DIM
RAMP_C
RAMP
GENERATOR
TIMMING
GENERATOR
BLOCK
DIMMING
CONTROL
BLOCK
FIGURE 1 – Simplified Block Diagram
Copyright 2000
Microsemi
Page 8
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
TYPICAL APPLICATION
3.0V < VBATT < 5V
Nominal 3.2V to 4.2V
T1 SGE2697-1
MICROSEMI
U2 FDC6305N
FAIRCHILD
Lamp
Lamp
C1
6
1
6
100nF 16V
C8
100nF
50V
VBATT
GND
2
275VRMS
±
BRITE
4,5
ENABLE
IOUT = 3.5m
100kHz
1
3
1:53
C9*
2pF
LMT1410
BRITE Input Control Range
(Linear DC)
C4
100nF 16V
4
VDD_A
Min. Brite 'LO' <= 0.50V
Max. Brite 'HI' >= 2.00V
C6
+
100µF
10V 20%
TANT
C3
100nF 16V
3
(2.5V to 3.3V Logic PWM)
Min. Brite Pos Duty <= 1.6%
Max. Brite Pos Duty >= 92%
PWM freq 7.5Khz to 100Khz
2,5
R5
10
GND
VDD_P
C11
Burst Rate Freq: 195Hz ± 4%
AOUT
BOUT
DIM_CLK
DIM_MODE
VDD_A
VBATT
OC_SNS
OV_SNS
1.0uF 10V
10%
VDD_A
N.C.
Alternate Maximum Lamp Current Table
Lamp current
|
R1 value
|
R7 Value
DIV_248
BRITE_C
BRITE_R
BRITE_IN
I_SNS
BRITE_OUT
EA_OUT
R4
10K
R6
4.0mArms | 6.65K 1% | 221 1%
3.5mArms | 6.65K 1% | 255 1%
3.0mArms | 6.65K 1% | 294 1%
2.5mArms | 11.8K 1% | 200 1%
2.0mArms | 11.8K 1% | 249 1%
1.5mArms | 11.8K 1% | 332 1%
C7
120
C10
1.5nF
25V 5%
COG
C2
1nF
16V
R7
100nF 16V
255Ω 1%
R1
C5
R3
6.65K 1%
470pF 16V
4.99K 1%
EA_IN
I_R
ENABLE
Enable input
R2
51.1K
1%
Logic Level: 2.5V to 3.3V
ON: Logic 'HI' = >1.5V
*C9 PCB CAPACITOR COPPER AREAS TO EQUAL
APPROXIMATELY 342MM FOR 0.80MM THICK PCB
PCB CAP AREA FORMULA (K TYPICIALLY = 5.35)
LX1689CPW
OFF: Logic 'LOW' =< 0.8V
+9
AREA(MM²) = D(mm) x C x 113097 E / K
FIGURE 2 – LX1689 Typical 1W Application
DIMMING TABLE
DIM_MODE
DIM_CLK
DIMMING MODE
DIMMING POLARITY*
External Burst
Dimming from divided
DIM_CLK input
VDD_A
External Clock Source
Conventional
Floating or VDD_A/2
VDD_A
GND
Analog Dimming
Conventional
Reverse
Floating or VDD_A/2
Analog Dimming
Internal Burst
Dimming from divided
Run Frequency
GND
GND
VDD_A
GND
Conventional
Reverse
Internal Burst
Dimming from Divided
Run Frequency
* Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE_IN pin.
Reverse polarity means that brightness decreases with increasing voltage.
Copyright 2000
Rev. 1.0b, 2003-03-31
Microsemi
Integrated Products
Page 9
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
APPLICATION
+
+
-
-
x
x
FIGURE 3 – Typical Dual 4 Watt Application
Copyright 2000
Microsemi
Page 10
Rev. 1.0b, 2003-03-31
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
DESCRIPTION
F E A T U R E R E V I E W
On-Chip LDO Regulators
Lamp Current Compensation
The BRITE_OUT pin outputs a precision current that is
to 28 Volts without using external circuitry as was required with proportional to the BRITE_IN signal. This current can be applied to
Two LDO regulators extend the input voltage range of the IC up
our previous controllers.
a precision resistor to develop the brightness control voltage at the
error amplifiers non-inverting input. Since the output is constant
current, designers can easily compensate lamp current with respect
to temperature, input voltage, ambient or lamp light output, and
combinations of these conditions by using various temperature or
light sensitive components in combination with resistors. This
capability is very useful in automotive and outdoor applications
where operating temperatures and ambient light vary over wide
ranges. See functional pin description for details.
Under Voltage Lockout
If the battery input voltage is too low for the controller to
function properly, it will turn itself off, preventing spurious
operation. If the battery voltage falls to less than 1V where UVLO
is no longer guaranteed, 10K pull down resistors on the AOUT and
BOUT pins insure the external power FETs cannot be biased on.
Power On Delay
A
power up reset delays AOUT and BOUT turn on for
Strike Voltage Generation
approximately 16384 x 1/fO milliseconds after power is applied.
This gives extra time for the BRITE_IN source voltage to stabilize
so the lamp is not inadvertently powered up at high brightness and
then suddenly lowered, creating an undesirable light flash.
Improved strike voltage generation circuits ramp strike voltage to
5X fO and repeats it’s cycle unless excessive high voltage is sensed
at OV_SNS. If OV_SNS is detected during strike, strike voltage
will not ramp and will hold the current voltage until total strikes
lamp cycles numbers reach 245,760. Strike potential is removed
immediately when the lamp strikes or if the time limit is reached.
Enhanced BRITE Conditioning Circuitry
The BRITE_IN input is now enhanced to accept either DC
voltage or logic PWM signals. When PWM signals are input, their
levels are clipped at 2V and 0.5V so lamp current will not be
affected by variations in logic signal level. In addition, the
BRITE_C pin permits filtering DC inputs and converting high
frequency PWM inputs to DC voltages with the addition of only a
single external capacitor. A low frequency (less than 500Hz)
PWM signal can be used to directly modulate the duty cycle of the
lamp current. In this case the capacitor at BRITE_C is not
installed.
Strike Detection
The LX1689 includes a new lamp strike detection scheme that
saves a package pin and three external components. Internal circuits
monitor lamp current pulses at the I_SNS input to determine if the
lamp strikes and if it stays ignited once operational.
Fault Time Out
If the lamp fails to ignite with in approximately 1.6 seconds
(depending on Run Frequency) at maximum strike potential, or if it
extinguishes while enabled, or the external clock frequency at the
DIM_CLK pin terminates, the output drive is shut down and the
BRITE_C pin is driven high. This pin can be monitored with a
CMOS gate to obtain a logical indication that a lamp fault has
occurred. It is especially useful in multiple lamp applications or for
system diagnostic input.
Digital or Analog Dimming Modes
A DIM_MODE input pin selects either Analog or Digital mode.
In Analog mode DC voltage at BRITE_IN controls lamp current
amplitude. In Digital mode it controls digital dimming duty cycle
with amplitude fixed at a value set by the external current scaling
resistor (BRITE_R). When in Digital mode, the dimming burst
frequency can be synchronous to lamp current by selecting internal
The voltage on pin BRITE_C will vary directly with BRITE
clocking, or to an external clock that may be a multiple of the input voltage, but does not exceed 1.2V unless a fault condition
video vertical frame rate. With an external clock source, three burst occurs.
rate selections are available by programming the DIV_248 input to
On Chip Rectifier
divide the source clock by 2,4, or 8. This clock source is further
Integrating full wave rectifiers for each of three lamp inputs has
divided by 64 generating the internal burst ramp waveform. Using
significantly reduced lamp feedback component count. Current
the internal clock as source the DIV_248 input changes to divide
Sense (I_SNS), Over Current Sense (OC_SNS) and Over Voltage
by 4, 8, or 16. This feature allows the designer to set a burst
Sense (OV_SNS) signals are now detected using only one external
frequency in the range of 100 to 500Hz. The external clock source
scaling resistor or capacitor each. Rectification accuracy is
must not be interrupted unless the BRITE_IN is set > 2V or the
improved with high performance on chip rectifiers to provide better
lamp current and voltage regulation.
lamp will extinguish.
Brightness Polarity Control
Complete Fault Protection
In Analog dimming mode or internal Digital Dimming, the IC
In addition to the faulty lamp time out, lamp open, lamp shorted,
can be programmed to either increase or decrease lamp current
and either lamp terminal shorted to ground are detected. Open
amplitude as a function of increasing signal at the BRITE_IN pin
circuit voltage can never go higher than the preset maximum strike
by simply connecting the DIM_CLK input to ground or VDD_A
potential and total current from the circuit is safely limited with a
or open(see Dimming Table). If External Digital dimming mode is
scaling resistor. UL safety specifications can now be easily met in
used, lamp current amplitude is constant and its duty cycle is
any application.
always directly proportional to DC input voltage and / or PWM
duty cycle at the BRITE_IN pin.
Copyright 2000
Rev. 1.0b, 2003-03-31
Microsemi
Integrated Products
Page 11
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
DESCRIPTION (CONTINUED)
Since strike frequency is held constant once the LX1689 senses
maximum safe output voltage, maximum strike potential is
continuously impressed across the lamp for the entire strike period.
LX1689 OPERATION
Four operating modes: Power On Delay, Strike, Run, and Fault
modes are employed by the LX1689. Upon power up or ENABLE
going true, Power On Delay is automatically invoked.
Immediately after termination of Power On Delay, or ENABLE
going true, strike mode is entered. After a successful strike, e.g.
lamp is ignited, run mode is entered. If ignition is unsuccessful, or
if the lamp extinguishes while running, Fault mode is entered.
Lamp ignition is determined by monitoring the lamp current
feedback voltage at pin I_SNS. Lamp current cycles are counted
from the beginning of Strike mode. If 8 or more complete cycles
occur the lamp is declared ignited. If less than 8, the lamp is
considered not ignited and Strike mode continues until ignition is
detected or strike time out is reached.
Because strike frequency is ramped up rather than simply
stepped, the entire range of possible self-resonant frequencies is
covered. Transformer manufacturing is simplified and parasitic
panel capacitance values are no longer critical. The 5:1 strike
frequency range easily covers the self-resonant frequency of all
practical lamp assembly and transformer combinations.
The only way to re-initiate the strike process is to either cycle
V_BATT or ENABLE off and on.
If ignition is successful, ramp frequency immediately returns to
its normal run value.
Run Mode
After run mode is entered lamp current cycles are sampled every
8192 x 1/fO to determine that the lamp has not inadvertently
extinguished. If at least 8 lamp current pulses are counted in each
sample, Run mode is maintained. Otherwise, Fault mode is
entered. Strike mode can be entered only once for each on/off cycle
Entered only by detection of a successful Strike. Ramp generator
frequency control is immediately switched from DAC output to a
fixed reference that sets the normal run frequency. During Run
mode, the Fault Detect Counter is reset approximately every 8192 x
1/fO. The lamp current cycle counter is monitored to insure at least
8 current cycles received during each period. If less than 8, the
lamp is considered extinguished and the Fault Mode is entered.
of either V_BATT or ENABLE.
This insures that even
intermittent lamp failures cannot cause the module to continuously
output maximum strike voltage.
Fault Mode
Power ON Delay Mode
Fault Mode may be entered from either Strike or Run Mode as
described above. In Fault Mode, the A & B output drivers are
forced low and the BRITE_C pin is driven to VDD_A to indicate
the fault condition. Fault mode may be cleared by cycling
ENABLE off then on, or by removing and applying V_BATT.
External load on the BRITE_C pin is limited to a filter capacitor and
single CMOS gate input.
All functions are activated except that AOUT and BOUT are
inhibited. Delay is 16384 x 1/fO determined by counting Ramp
clocks. The first of 16 sweeps is decoded as the power on delay
period. The subsequent 15 sweeps are used for controlling the
Ramp generator during Strike Mode. Power on delay is activated
at every V_BATT power up sequence and ENABLE sequence.
Strike Mode
DESIGN PROCEDURE
Entered from Power On Delay, or upon an ENABLE sequence.
Control of the Ramp Generator frequency is switched to a DAC
output. Frequency is increased in a saw tooth fashion from normal
run value to as high as five times that value, for up to 15 sweeps.
If while strike frequency is ramping up, the over voltage set point
at OV_SNS is detected, strike frequency will freeze at that value
until either the lamp strikes or the timeout is reached. Strike Mode
is terminated by reaching 15 sweep counts or by detecting lamp
ignition. If strike is successful, Run Mode is entered. If
unsuccessful, Fault mode is entered, a fault is declared and the A &
B outputs are shut off.
Selecting the I_R resistor value
This resistor determines the frequency of the on chip oscillator.
The output of the oscillator, RAMP_C, controls all timing functions.
It must be chosen first, and will be in the range of 10K to 150K
ohms. The output frequency approximated by the following
formula : RI_R = 5.24E9 / FLAMPOUT(Hz)
RAMP_C frequency is twice lamp output current frequency.
Driving the BRITE_IN Input
BRITE_IN can be a DC voltage, a low frequency PWM signal
that produces direct digital dimming, or a higher frequency PWM
signal that is converted to a proportional DC level by adding a filter
capacitor at the BRITE_C pin. 100% duty cycle corresponds to 1.1
volt, and 0% duty cycle corresponds to zero volts at the BRITE_C
pin. Maximum BRITE_IN input frequency for PWM inputs is 100
KHz, but when converting frequencies above 25 KHz to DC, some
accuracy is lost. The BRITE_IN input circuitry includes on-chip
active voltage clamps that ignore input voltage greater than 2.0V
and less than 0.5V. This allows the use of digital PWM input
signals where brightness is dependent only on duty cycle, with no
contribution
The purpose of sweeping lamp frequency up during strike is to
operate at the unloaded resonant frequency of the transformer and
lamp load. This generates the high lamp striking voltage required,
since at resonance, output voltage from the transformer will
increase to any value needed to cause ignition. A capacitive
voltage divider provides output voltage feedback to the OV_SNS
pin, which freezes Strike Frequency to limit maximum output
voltage to a safe value.
Copyright 2000
Rev. 1.0b, 2003-03-31
Microsemi
Page 12
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
DESCRIPTION (CONTINUED)
due to varying input signal amplitude. Input impedance is very
Because the BRITE_OUT output is a linear current source, you
high so BRITE_IN can also be driven from a 100K potentiometer can place other components, such as a thermistor or photo resistor,
with no offset error.
at this pin to generate complex functions for controlling brightness.
For example; use a PWM input at the BRITE_IN pin to control
dimming, and boost analog lamp current amplitude at cold lamp
temperature with a thermistor at the BRITE_OUT pin. This will
help warm the lamp faster at start up so final brightness is reached
sooner.
BRITE_R and BRITE_OUT Resistor values.
The BRITE_OUT pin is the output from the BRITE_IN signal
processor. It is a linear current source that varies from 0 to the
current value established at pin BRITE_R multiplied by the DC
voltage at pin BRITE_C. The optimum value for BRITE_R is
usually 10K ohms. The BRITE_OUT voltage range can be scaled
from 300mV to 2.0V. However, it is recommended that the
SETTING THE OUTPUT CURRENT.
Referring to the application examples figures 2 and 3. The
scaling of BRITE_OUT (including Analog mode BRITE_IN current setting resistor(s) are R7, and R19 and R20 respectively.
range) be within 400mV to 1.2V. Maximum voltage correlates to The value these resistor(s) are in the range of 200 to 400ohms. The
full brightness settings. It is the ratio of the two resistors following formula can be used to determine the current setting
multiplied by the voltage at BRITE_C:
resistor value. Use 1180 for Digital mode and 1260 for analog dim.
V BRITE_OUT = V BRITE_C (RBRITE_OUT / RBRITE_R_
)
RSNS = 1180 or 1260 x RBRITE_OUT / IOUT(mARMS) x RBRITE_R
In some applications, a precision 10K resistor is connected from In the 1W burst dimming application example shown in figure 2 the
BRITE_OUT and BRITE_R to ground to develop 1.0V to output current is set for nominally 3.5mA. RSNS is calculated
represent maximum lamp brightness. In Analog mode the using the formula above as follows:
BRITE_OUT voltage potential is proportional to BRITE_IN. The
RSNS = 1180 x 4990 / 3.5 x 6550 = 256.8 ohms
minimum brightness setting at BRITE_IN corresponds to the
A standard value of 255 ohms was chosen. It is recommended to
minimum voltage at BRITE_OUT. In digital mode, BRITE_IN
keep the value of the sense resistor in the range of 200 to 400 ohms
has no effect on BRITE_OUT.
as stated above. If calculated value exceeds 400 ohms its best to
increase the value of the RBRITE_R resistor.
MECHANICAL DRAWING
20-Pin Thin Small Shrink Outline (TSSOP)
PW
MILLIMETERS
INCHES
Dim
3 2 1
MIN
0.80
0.19
0.09
6.40
4.30
MAX
1.05
0.30
MIN
MAX
0.041
0.012
A
B
0.032
P
E
0.007
C
0.180 0.0035 0.0071
D
6.60
4.48
0.252
0.169
0.260
0.176
F
E
F
0.65 BSC
0.025 BSC
D
G
H
0.05
–
0.15
1.10
0.70
8°
0.002
–
0.005
0.0433
0.028
8°
A
H
L
SEATING PLANE
B
C
G
L
0.50
0°
0.020
0°
M
M
P
6.25
–
6.50
0.10
0.246
–
0.256
0.004
*LC
Note:
1. Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm(.006”) on any side.
Lead dimension shall not include solder coverage.
Copyright 2000
Rev. 1.0b, 2003-03-31
Microsemi
Page 13
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
LX1689
Third Generation CCFL Controller
I N T E G R A T E D P R O D U C T S
PRODUCTION DATA SHEET
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
Copyright 2000
Microsemi
Integrated Products
Page 14
Rev. 1.0b, 2003-03-31
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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