LE7942BDJC [MICROSEMI]

SLIC, PQCC32, GREEN, PLASTIC, MS-016, LCC-32;


型号：	LE7942BDJC
厂家：	Microsemi
描述：	SLIC, PQCC32, GREEN, PLASTIC, MS-016, LCC-32 电池电信电信集成电路
文件：	总19页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

™

Le7942B

Subscriber Line Interface Circuit

VE580 Series

Voice Solution

DISTINCTIVE CHARACTERISTICS

Programmable constant-current feed

Receive current gain = 500

Compatible with Le7942 Device

Tip Open state for ground-start lines

–19 V to –58 V battery operation

Ideal for PBX and KTS applications

On-chip switching regulator for low-power

dissipation

Programmable loop-detect threshold

Low standby power

Performs polarity reversal

Ground-key detector

Pin for external ground-key noise filter capacitor

Test relay driver option

Can be used with or without the on-chip switching

regulator

On-hook transmission

BLOCK DIAGRAM

TESTOUT

RINGOUT

Test Relay Driver

Ring Relay Driver

A(TIP)

Ground-Key

Input Decoder

and Control

Detector

HPA

HPB

DET

Two-Wire

Interface

GKFIL

RSN

VTX

Signal

Transmission

Off-Hook

Detector

B(RING)

RDC

CAS

Power-Feed

Controller

Ring-Trip

Detector

VREG

Switching

Regulator

VBAT

BGND

VCC

VEE

AGND/DGND

CHS

CHCLK

QBAT

15474A-001

Document ID# 081195 Date:

Sep 19, 2007

NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and

technology of Legerity Holdings.

Rev:

Version:

Distribution:

Public Document

Le7942B

Data Sheet

ORDERING INFORMATION

Standard Products

Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the elements below.

Le7942B

C = Commercial (0°C to 70°C)*

PLCC package

PACKAGING MATERIAL

Blank= Standard package

D= Green package (see note)

PERFORMANCE GRADE

Blank = Standard specification

–1 = Performance Grading

–2 = Performance Grading

DEVICE NUMBER/DESCRIPTION

Le7942B

Subscriber Line Interface Circuit

Note: The green package meets RoHS Directive 2002/95/EC of the European

Council to minimize the environmental impact of electrical equipment.

Valid Combinations

Valid Combinations lists configurations planned

to be supported in volume for this device. Consult

the local Legerity sales office to confirm

availability of specific valid combinations, to

check on newly released combinations, and to

obtain additional data on Legerity’s standard

military–grade products.

Valid Combinations

Green Package

Le7942BDJC

Le7942B–1DJC

Le7942B–2DJC

Non-Green Package

Le7942BJC

Le7942B-1JC

Le7942B-2JC

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

CONNECTION DIAGRAMS

Top View

32 31 30

TESTOUT

32-Pin PLCC

VBAT

HPB

HPA

QBAT

CHS

VTX

VBREF

CHCLK

RSN

AGND/DGND

14 15 16 17 18 19 20

Notes:

1. Pin 1 is marked for orientation.

2. TP is a thermal conduction pin tied to substrate (QBAT).

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

PIN DESCRIPTIONS

Pin Names

AGND/DGND

A (TIP)

Type

Gnd

Description

Analog and Digital ground.

Output of A(TIP) power amplifier.

Battery (power) ground.

Output

Gnd

BGND

B (RING)

C3–C1

Output

Input

Output of B(RING) power amplifier.

Decoder. TTL compatible. C3 is MSB and C1 is LSB.

Input

Test Relay Driver Command. TTL compatible. A logic Low enables the driver.

CAS

Capacitor

Anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation

region.

CHCLK

Input

Chopper Clock. Input to switching regulator (TTL compatible). Freq = 256 kHz (typ).

(See Note 1).

CHS

Input

Output

Chopper Stabilization. (See Note 1) Connection for external chopper stabilizing components.

Ring-trip negative. Negative input to ring-trip comparator.

Ring-trip positive. Positive input to ring-trip comparator.

Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The

detector is selected by the logic inputs (C3–C1, E1). The output is open-collector with a built-in

15 kΩ pull-up resistor.

DET

Input

Ground-Key Enable. E1 = High connects the ground-key detector to DET. E1 = Low connects the

off-hook or ring-trip detector to DET.

GKFIL

HPA

HPB

—

Connection for external ground-key, noise-filter capacitor. (See Note 2.)

High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.

High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.

Switching Regulator Power Transistor. Connection point for filter inductor and anode of Switching

Regulator Power Transistor. Connection point for filter inductor and anode of catch diode. Has up

to 60 V of pulse waveform on it and must be isolated from sensitive circuits. Keep the diode

connections short because of the high currents and high di/dt.

Capacitor

Output

(See Note 1)

QBAT

RDC

Battery

Resistor

Quiet Battery. (See Note 1). Filtered battery supply for the signal processing circuits.

Detector resistor. Detector threshold set and filter pin. May be connected to ground or -5V.

DC feed resistor. Connection point for the DC feed current programming network. The other end

of the network connects to the receiver summing node (RSN).

RINGOUT

RSN

Output

Input

Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.

(See Note 3)

Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal

to 500 x the current into this pin. The networks that program receive gain, two-wire impedance,

and feed current all connect to this node.

TESTOUT

Output

Test Relay Driver. Open collector driver with emitter internally connected to BGND.

(See Note 3)

Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as

open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper

on the board to enhance heat dissipation.

Thermal

VBAT

VCC

VBREF

VREG

Battery

Power

Input

Battery supply.

+5 V power supply.

Reference voltage. No current on the pin. May be connected to QBAT or –5 V.

Regulated Voltage. (See Note 1.) Provides negative power supply for power amplifiers.

Connection point for inductor, filter capacitor, and chopper stabilization.

VTX

Output

Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage.

VTX also sources the two-wire input impedance programming network.

Notes:

1. All pins, except CHCLK, connect to VBAT when using SLIC without a switching regulator. CHCLK is connected to AGND/

DGND.

2. To prevent noise pickup by the detection circuits when using Ground-Key Detect state (E1 = logical 1), a 3300 pF minimum

bypass capacitor is recommended between the GKFIL pin and ground.

3. Each relay driver has a zener clamp to BGND.

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Storage temperature . . . . . . . . . . . . –55°C to +150°C

OPERATING RANGES

Commercial (C) Devices

_CCwith respect to AGND/DGND . . .–0.4 V to +7.0 V

_EEwith respect to AGND/DGND . . . +0.4 V to QBAT

_BATwith respect to AGND/DGND. . . +0.4 V to –70 V

Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C*

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V

V_EE. . . . . . . . . . . . . . . . . . . . . . . . . .–4.75 V to QBAT

Note: Rise time of V_BAT(dv/dt) must be limited to 27 V/µs or

_BAT. . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to –58 V**

less when Q_BATbypass = 0.33 µF.

AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V

BGND with respect to

BGND with respect to AGND/DGND .+1.0 V to –3.0 V

A(TIP) or B(RING) to BGND:

AGND/DGND. . . . . . . . . . . . –100 mV to +100 mV

Continuous . . . . . . . . . . . . . . . . . . –70 V to +1.0 V

10 ms (f = 0.1 Hz) . . . . . . . . . . . . . –70 V to +5.0 V

1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . .–90 V to +10 V

250 ns (f = 0.1 Hz) . . . . . . . . . . . .–120 V to +15 V

Load Resistance on VTX to ground . . . . . . 10 kΩ min

The Operating Ranges define those limits between which the

functionality of the device is guaranteed.

Current from A(TIP) or B(RING). . . . . . . . . . . .±150 mA

Voltage on RINGOUT, TESTOUT . . . .BGND to + 7 V

*Legerity guarantees the performance of this device over

commercial (0 to 70°C) and industrial (-40 to 85 °C)

temperature ranges by conducting electrical characterization

over each range and by conducting a production test with

single insertion coupled to periodic sampling. These

characterization and test procedures comply with section

4.6.2 of Bellcore TR-TSY-000357 Component Reliability

Assurance Requirements for Telecommunications

Equipment.

Voltage on RINGOUT, TESTOUT (transient)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGND to +10 V

Current through relay drivers . . . . . . . . . . . . . . 60 mA

Voltage on ring-trip inputs

(DA and DB) . . . . . . . . . . . . . . . . . . . . . V_BATto 0 V

Current into ring-trip inputs . . . . . . . . . . . . . . . . .±10 mA

**Can be used without switching regulator components in this

range of battery voltages, provided maximum power

dissipation specifications are not exceeded.

Peak current into regulator

switch (L pin). . . . . . . . . . . . . . . . . . . . . . . 150 mA

Package Assembly

Switcher transient peak off

The non-green package devices are assembled with

industry-standard mold compounds, and the leads

possess a tin/lead (Sn/Pb) plating. These packages

are compatible with conventional SnPb eutectic solder

board assembly processes. The peak soldering

temperature should not exceed 225°C during printed

circuit board assembly.

voltage on L pin. . . . . . . . . . . . . . . . . . . . . . +1.0 V

C4–C1, E1, CHCLK to

AGND/DGND . . . . . . . . . . . .–0.4 V to V_CC+ 0.4 V

Maximum power dissipation, T (see note) . . . . .70°C

In 32-pin PLCC package. . . . . . . . . . . . . . . 1.74 W

Note: Thermal limiting circuitry on chip will shut down the

circuit at a junction temperature of about 165°C. The device

should never be exposed to this temperature. Operation

above 145°C junction temperature may degrade device

reliability. See the SLIC Packaging Considerations for more

information.

The green package devices are assembled with

enhanced environmental compatible lead-free,

halogen-free, and antimony-free materials. The leads

possess a matte-tin plating which is compatible with

conventional board assembly processes or newer

lead-free board assembly processes. The peak

soldering temperature should not exceed 245°C during

printed circuit board assembly.

Stresses above those listed under Absolute Maximum Ratings

cancause permanent device failure. Functionality at or above

these limits is not implied. Exposure to Absolute Maximum

Ratings for extended periods may affect device reliability.

Refer to IPC/JEDEC J-Std-020B Table 5-2 for the

recommended solder reflow temperature profile

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

ELECTRICAL CHARACTERISTICS

Description

Test Conditions (See Note 1) Grade

Min

Typ

Max

Unit

Note

Analog (V_TX) output impedance

all

—

Ω

–35

–30

+35

+30

–1

Analog (V_TX) output offset

0°C to +70°C

—

–2

–40

–35

+40

+35

–1

–2

–40°C to +85°C

Analog (RSN) input impedance 300 Hz to 3.4 kHz

all

—

Ω

Longitudinal impedance at A or

—

Overload level

4-wire

2-wire

all

–2.5

—

+2.5

—

Vpk

Transmission Performance, 2-Wire Impedance (See Test Circuit D)

2-wire return loss 300 to 3400 Hz all

Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C); R_L= 600 Ω

4, 10

200 Hz to 1 kHz

–1

–2

1, 2

1, 2, 4

1, 2

normal polarity 0°C to +70°C

normal polarity –40°C to +85°C

reverse polarity

—

Longitudinal to metallic L-T, L-4

1 kHz to 3.4 kHz

–1

–2

normal polarity 0°C to +70°C

normal polarity –40°C to +85°C

reverse polarity

1, 2

1, 2, 4

1, 2

—

Longitudinal signal generation

4-L

300 Hz to 800 Hz

Reverse polarity

–1

–2

—

Longitudinal current capability

per wire

Active state

OHT state

all

—

mArms

Insertion Loss (4- to 2-Wire, See Test Circuit B)

BAT = –48 V, R_LDC= R_LAC= 600 Ω; BAT = –24 V, R_LDC= 300 Ω, R_LAC= 600 Ω

–0.15

+0.15

+0.10

0 dBm, 1 kHz

–1

–2

–0.15

–0.10

—

0°C to +70°C

Gain accuracy

–0.20

–0.15

+0.20

+0.15

0 dBm, 1 kHz

–40°C to +85°C

–1

–2

300 Hz to 3400 Hz

Relative to 1 kHz

0°C to +70°C

–0.15

–0.10

+0.15

+0.10

–1

–2

Variation with frequency

300 Hz to 3400 Hz

Relative to 1 kHz

–40°C to +85°C

–0.20

–0.15

+0.20

+0.15

–1

–2

Zarlink Semiconductor Inc.

Le7942B

ELECTRICAL CHARACTERISTICS (continued)

Data Sheet

Description

Test Conditions (See Note 1) Grade

Min

Typ

Max

Unit

Note

0°C to +70°C

+7 dBm to –55 dBm

Reference: –0 dBm

all

–0.10

—

+0.10

Gain tracking

–40°C to +85°C

+7 dBm to –55 dBm

Reference: –0 dBm

all

–0.15

—

+0.15

Insertion Loss and Balance Return Signal (2- to 4-Wire and 4- to 4-Wire, See Test Circuits A and B)

BAT = –48 V, R_LDC= R_LAC= 600 Ω; BAT = –24 V, R_LDC= 300 Ω, R_LAC= 600 Ω

–6.17

–6.12

–5.87

–5.92

0 dBm, 1 kHz

–1

–2

–6.02

0°C to +70°C

Gain accuracy

–6.22

–6.17

–5.82

–5.87

3, 4

0 dBm, 1 kHz

–40°C to +85°C

–1

–2

300 Hz to 3400 Hz

Relative to 1 kHz

0°C to +70°C

all

–0.10

–0.15

–0.10

–0.15

+0.10

+0.15

+0.10

–0.15

3, 4

Variation with frequency

300 Hz to 3400 Hz

Relative to 1 kHz

–40°C to +85°C

0°C to +70°C

+3 dBm to –55 dBm

Reference: 0 dBm

Gain tracking

Group delay

–40°C to +85°C

+3 dBm to –55 dBm

Reference: 0 dBm

all

3, 4

f = 1 kHz

5.3

µs

4, 12

Total Harmonic Distortion (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B)

BAT = –48 V, R_LDC= R_LAC= 600 Ω

Harmonic distortion

300 Hz to 3400 Hz

Idle Channel Noise

0 dBm

all

–64

–55

–50

–40

+7 dBm

BAT = –48 V, R_LDC= R_LAC= 600 Ω; BAT = –24 V, R_LDC= 300 Ω, R_LAC= 600 Ω

2-wire, 0°C to +70°C

+10

+12

C-message weighted noise

Psophometric weighted noise

all

dBmc

dBmp

2-wire, –40°C to +85°C

2-wire, 0°C to +70°C

2-wire, –40°C to +85°C

–83

–80

–78

—

Single Frequency Out-of-Band Noise (See Test Circuit E)

Metallic

4 kHz to 9 kHz

–76

–63

9 kHz to 1 MHz

all

4, 5, 8

4, 5

256 kHz and harmonics**

dBm

Longitudinal

1 kHz to 15 kHz

–70

–85

–57

Above 15 kHz

4, 5, 8

4, 5

256 kHz and harmonics**

Note:

**Applies only when switching regulator is used.

Zarlink Semiconductor Inc.

Le7942B

ELECTRICAL CHARACTERISTICS (continued)

Data Sheet

Description

Test Conditions (See Note 1) Grade

Min

Typ

Max

Unit

Note

Line Characteristics (See Figures 1a, 1b, 1c)

Short loops, Active state

Long loops, Active state

V_BAT= –24 V, R_LDC= 300 Ω

V_BAT= –43 V, R_LDC= 600 Ω

_BAT= –48 V, R_LDC= 600 Ω

4, 9

all

31.8

34.4

37.0

—

V_BAT= –24 V, R_LDC= 640 Ω

V_BAT= –43 V, R_LDC= 1300 Ω

20.0

23.0

18.0

4, 9

—

all

V_BAT= –48 V, R_LDC= 1900 Ω

OHT state

_BAT= –24 V, R_LDC= 300 Ω

_BAT= –48 V, R_LDC= 600 Ω

4, 9

—

31.4

34.4

37.4

Loop current

Tip Open state, R_L= 0 Ω

Disconnect state, R_L= 0 Ω

all

1.0

I_LLIM (I_Tipand I_Ring

)

Tip and ring shorted to GND

120

Power Dissipation Battery, Normal Loop Polarity

On-hook Open Circuit state

V_BAT= –24 V, w/o switching reg.

_BAT= –48 V, with switching reg.

all

100

—

On-hook OHT state

V_BAT= –24 V, w/o switching reg.

V_BAT= –48 V, with switching reg.

130

—

225

On-hook Active state

V_BAT= –24 V, w/o switching reg.

V_BAT= –48 V, with switching reg.

130

225

300

—

Off-hook OHT state

R_L= 50 Ω

_BAT= –24 V, w/o switching reg.

500

400

950

750

—

V_BAT= –48 V, with switching reg.

Off-hook Active state

R_L= 50 Ω

_BAT= –24 V, w/o switching reg.

800

450

1100

1000

—

V_BAT= –48 V, with switching reg.

Supply Currents, Battery = –24 V or –48 V

V_CCon-hook supply current

Open Circuit state

2.5

4.5

OHT state

all

10.0

12.0

Active state

V_BREFon-hook supply current

Open Circuit state

OHT state

Active state

V_BATon-hook supply current

Open Circuit state

OHT state

Active state

0.6

2.3

1.0

5.0

6.0

Power Supply Rejection Ratio (V_RIPPLE= 50 mVrms)

V_CC

50 Hz to 3.4 kHz

3.4 kHz to 50 kHz

all

V_BAT

50 Hz to 3.4 kHz

3.4 kHz to 50 kHz

all

Effective int. resistance

CAS to GND

170

255

+20

kΩ

Off-Hook Detector

I_DET= 365/R_DIf R_Dto gnd

Current threshold

all

–20

_DET= 1825/R_DIf R_Dto –5V

Zarlink Semiconductor Inc.

Le7942B

ELECTRICAL CHARACTERISTICS (continued)

Data Sheet

Description

Test Conditions (See Note 1) Grade

Min

Typ

Max

Unit

Note

Ground-Key Detector Thresholds, Active State

Ground-key resistance

threshold

V_BAT= –24 V, B(RING) to GND

V_BAT= –48 V, B(RING) to GND

1.0

2.0

2.2

5.0

4.5

10.0

—

all

kΩ

Ground-key current threshold

B(RING) to GND

Midpoint to GND

all

Effective internal resistance

Ring-Trip Detector Input

Bias current

GKFIL to AGND/DGND

kΩ

all

–5

–0.05

µA

Offset voltage

Source resistance = 0 to 2 MΩ

–50

+50

Logic Inputs (C4–C1, E1, and CHCLK)

Input High voltage

all

2.0

Input Low voltage

0.8

Input High current

Input Low current

Logic Output (DET)

Output Low voltage

Output High voltage

All inputs except E1

Input E1

–75

–0.4

µA

_OUT= 0.3 mA

all

0.4

I_OUT= –0.1 mA

2.4

Relay Driver Outputs (RINGOUT, TESTOUT)

On voltage

25 mA sink

V_OH= 5 V

I_L= 100 µA

I_L= 30 mA

all

0.3

+1.5

100

Off leakage

µA

Zener break-over

Zener on voltage

7.2

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

RELAY DRIVER SCHEMATICS

RINGOUT

TESTOUT

BGND

SWITCHING CHARACTERISTICS

Symbol

Parameter

Test Conditions

Temperature

Range

Min Typ Max Unit Note

tgkde

E1 Low to DET High (E0 = 1)

E1 Low to DET Low (E0 = 1)

E1 High to DET Low (E0 = 1)

E1 High to DET High (E0 = 1)

0°C to +70°C

3.8

4.0

Ground-Key Detect state

R_Lopen, R_Gconnected

–40°C to +85°C

0°C to +70°C

1.1

1.6

(See Figure H)

–40°C to +85°C

µs

tshde

0°C to +70°C

1.2

1.7

Switchhook Detect state

–40°C to +85°C

R_L= 600 Ω, R_Gopen

0°C to +70°C

3.8

4.0

(See Figure G)

–40°C to +85°C

SWITCHING WAVEFORMS

E1 to DET

DET

tgkde

tshde

tgkde

tshde

Note:

All delays measured at 1.4 V levels.

15474A-003

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

Notes:

1. Unless otherwise noted, test conditions are BAT = –48 V, V_CC= +5 V, R_L= 600 Ω, C_HP= 0.33 µF,

R_DC1= R_DC2= 9.09 kΩ, C_DC= 0.39 µF, R_D= 35.4 kΩ when R_Dis connected to ground and R_D= 177 kΩ when Rd is con-

nected to -5V. C_CAS= 0.47 µF, no fuse resistors, R_T=150 kΩ, and R_RX= 150 kΩ. Switching regulator components: L = 1 mH,

C_FIL= 0.47 µF (see Application Circuit).

2. Overload level is defined when THD = 1%.

3. Balance return signal is the signal generated at V_TXby V_RX. This specification assumes the two-wire AC load impedance

matches the programmed impedance.

4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.

5. For frequencies below 12 kHz, these tests are performed with a longitudinal impedance of 90 Ω and metallic impedance of

300 Ω. For frequencies greater than 12 kHz, a longitudinal impedance of 90 Ω and a metallic impedance of 135 Ω is used.

These tests are extremely sensitive to circuit board layout. Please refer to application notes for details.

6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.

7. “Midpoint” is defined as the connection point between two 300 Ω series resistors connected between A(TIP) and B(RING).

8. Fundamental and harmonics from 256 kHz switch regulator chopper are not included.

9. For –24 V battery, switching regulator is disabled. L, CHS, and VREG pins connected to VBAT pin; CHCLK pin connected to

AGND/DGND.

10. Assumes the following Z_Tnetwork:

VTX

RSN

75 kΩ

120 pF

11. Tested with 0 Ω source impedance. 2 MΩ is specified for system design purposes only.

12. Group delay can be considerably reduced by using a Z_Tnetwork such as that shown in Note 10 above. The network reduces

the group delay to less than 2 µs. The effect of group delay on linecard performance may be compensated for by using the

QSLAC™ or DSLAC™ device.

Table 1. SLIC Device Decoding

DET Output

State

C3 C2 C1

Two-Wire Status

Open Circuit

E1 = 0

Ring trip

E1 = 1

Ring trip

Ringing

Ring trip

Ground key

—

Active

Loop detector

On-Hook TX (OHT)

Tip Open

Reserved

—

Active Polarity Reversal

OHT Polarity Reversal

Ground key

Table 2. User-Programmable Components

∗

Z_T= 250(Z_2WIN– 2R_F

)

Z_Tis connected between the VTX and RSN pins. The fuse re-

sistors are R_F, and Z_2WINis the desired 2-wire AC input im-

pedance. When computing Z_T, the internal current amplifier

pole and any external stray capacitance between VTX and

RSN must be taken into account.

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

Table 2. User-Programmable Components

Z_RXis connected from V_RXto the R_SN. Z_Tis defined above,

and G_42Lis the desired receive gain.

Z_L

500Z_T

------------ -------------------------------------------------

Z_RX

•

G42_LZ_T+ 250(Z_L+ 2R_F)

R_DC1, R_DC2, and C_DCform the network connected to the

RDC pin. R_DC1and R_DC2are approximately equal. I_LOOPis

the desired loop current in the constant-current region.

625

R_DC1+ R_DC2= -------------

I_LOOP

R_DC1+ R_DC2

-------------------------------

R_DC1R_DC2

C_DC= 1.5 ms •

R_Dand C_Dform a network connected from RD to either

ground or –5 V, and I_Tis the threshold current between on

hook and off hook.

365

R_D= -------- If R_Dis connected to ground.

I_T

1825

R_D= ----------- If R_Dis connected to -5V.

I_T

0.5 ms

C_D= ----------------

R_D

_CASis the regulator filter capacitor, and f_cis the desired filter

C_CAS= -----------------------------

cut-off frequency.

3.4 • 10⁵πf_c

Note:

*R_FUSE= 20 – 50 Ω, user selectable.

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

DC FEED CHARACTERISTICS

VAB vesus Iloop, BAT =-48V

7942B

7942 (active)

7942 (OHT)

Iloop

R_DC1+ R_DC2= R_DC= 18.18 kΩ

Active state

OHT state

Notes:

1. Constant-current region:

625

R_DC

Active state:

I_L= ----------

625

R_DC

OHT state:

I_L= ---------

2. Anti-saturation 2 region:

Active state:

and

R_DC





----------

210

V_AB= BAT – 7.9 – I

^L



OHT state:

a. V_A–V_B(V_AB) Voltage vs. Loop Current (Typical)

Zarlink Semiconductor Inc.

Le7942B

DC FEED CHARACTERISTICS (continued)

Data Sheet

Iloop vesus Loop Resistance, BAT = -48V

45000

40000

35000

30000

25000

20000

15000

10000

5000

7942B

7942 (active)

Iloop

R_DC1+ R_DC2= R_DC= 18.18 kΩ

b. Loop Current vs. Load Resistance (Typical)

RSN

RDC

R_DC1

SLIC

I_L

R_L

R_DC2

C_DC

Feed current programmed by R_DC1and R_DC2

c. Feed Programming

15474A-004

Figure 1. DC Feed Characteristics

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

TEST CIRCUITS

(TIP)

VTX

(TIP)

R_L

R_T

SLIC

V_L

V_AB

R_T

V_AB

R_L

AGND

R_L

R_RX

V_RX

RSN

(RING)

I_L4-2= –20 log (V_AB/ V_RX

)

I_L2-4= –20 log (V_TX/ V_AB

)

BRS = 20 log (V_TX/ V_RX

)

A. Two- to Four-Wire Insertion Loss

B. Four- to Two-Wire Insertion Loss and Balance Return Signal

Z_D

(TIP)

VTX

(TIP)

1/ωC << R_L

R_L

R_T

SLIC

AGND

V_L

R_T

V_M

AGND

V_S

SLIC

V_L

Z_IN

R_L

R_RX

VRX

RSN

B(RING)

RSN

(RING)

R_RX

S2 Open, S1 Closed:

L-T Long. Bal. = 20 log (V_AB/ V_L)

L-4 Long. Bal. = 20 log (V_TX/ V_L)

Note:

Z_Dis the desired impedance (e.g., the characteristic

impedance of the line).

S2 Closed, S1 Open:

4-L Long. Sig. Gen. = 20 log (V_L/ V_RX

R_L= –20 log (2 V_M/ V_S)

)

C. Longitudinal Balance

D. Two-Wire Return Loss Test Circuit

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

TEST CIRCUITS (continued)

R_L

A(TIP)

68 Ω

S_M

R_L

R_E

56 Ω

IDC

V_N

SLIC

B(RING)

68 Ω

B(RING)

S_E

Current Feed or Ground Key

1/ωC << 90 Ω

E. Single-Frequency Noise

F. Ground-Key Detection Center Point Test

6.2 kΩ

A(TIP)

DET

15 pF

R_L= 600 Ω

B(RING)

R_G

B(RING)

R_G: 2 kΩ at V_BAT= –48 V

1 kΩ at V_BAT= –24 V

H. Ground-Key Switching

G. Loop-Detector Switching

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

PHYSICAL DIMENSIONS

32-Pin PLCC

NOTES:

Dimensioning and tolerancing conform to ASME Y14,5M-1994.

32-Pin PLCC

JEDEC # MS-016

To be measured at seating plan - C - contact point.

Min

Nom

Max

0.140

0.095

0.495

0.453

Symbol

0.125

0.075

0.485

0.447

Dimensions “D1” and “E1” do not include mold protrusion.

Allowable mold protrusion is 0.010 inch per side. Dimensions

“D” and “E” include mold mismatch and determined at the

parting line; that is “D1” and “E1” are measured at the extreme

material condition at the upper or lower parting line.

0.090

0.490

0.450

0.205 REF

0.590

0.550

0.255 REF

0.585

0.547

0.595

0.553

Exact shape of this feature is optional.

Details of pin 1 identifier are optional but must be located

within the zone indicated.

0 deg

10 deg

Sum of DAM bar protrusions to be 0.007 max per lead.

Controlling dimension : Inch.

Reference document : JEDEC MS-016

32-Pin PLCC

Note:

Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the

device. Markings will vary with the mold tool used in manufacturing.

Zarlink Semiconductor Inc.

Le7942B

Data Sheet

REVISION HISTORY

Revision A1 to B1

•

Page 12, modified ZRX equation.

Revision B1 to C1

•

Page 8, Line characteristics, OHT State, V_BAT= –24 V, R_LDC= 600 Ω to R_LDC= 300 Ω.

Page 8, Power Dissipation, Off-hook OHT state R_L= 50 Ω, V_BAT= –24 V, w/o switching reg., max 800mW to 950mW.

Revision C1 to D1

•

Page 8, Line characteristics, I LIM (I and I

), changed Max value from 105 to 120.

Ring

Tip

Revision D1 to E1

•

Added green package OPN

Added Package Assembly section

Revision E1 to E2

•

Enhanced format of package drawing in Physical Dimensions section

Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007

Zarlink Semiconductor Inc.

™

For more information about all Zarlink products

visit our Web Site at:

www.zarlink.com

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application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

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